Low Power Wideband Fractional RF
Synthesizer / PLL
8V97053
Datasheet
Description
Features
The 8V97053 is a high-performance Wideband RF Synthesizer /
PLL optimized for use as the local oscillator (LO) in Multi-Carrier,
Multi-mode FDD, and TDD Base Station radio card. It is offered in
a compact 5 5, 32-VFQFPN.
▪ Dual Differential Outputs
▪ Output frequency range: 34.375MHz to 4400MHz (continuous
The 8V97053 Wideband RF Synthesizer / PLL offers a default
Fractional Mode with the option to use it with an Integer mode. It
requires an external loop filter.
▪ Open Drain Outputs (see Output Clock Distribution)
▪ Fractional-N synthesizer (also supports Integer-N mode)
▪ 16-bit integer and 12-bit fractional
range)
▪ RF Output Divide by 1, 2, 4, 8, 16, 32, 64
The 8V97053 with integrated Voltage Controlled Oscillator (VCO)
supports output frequencies from 34.375MHz to 4400MHz, and
maintains superior phase noise and spurious performance.
(16-bit fractional when using the register 7)
▪
▪
▪
▪
RF_OUT[A:B] output drivers have independently programmable
output power ranging from –4dBm to +7dBm. The RF_OUT
outputs can be muted. The mute function is accessible via a SPI
command or mute pin.
3- or 4-wire SPI interface (compatible with 3.3V and 1.8V)
Single 3.3V supply
Logic compatibility: 1.8V
Programmable output power level: -4dBm to +5dBm
(up to +7 when using register 6)
▪ Mute function
The operation of the 8V97053 is controlled by writing to registers
through a 3-wire SPI interface. The 8V97053 has an additional
option that allows users to read back values from registers by
configuring the MUX_OUT pin as a SDO for the SPI interface. The
SPI interface is compatible with 1.8V logic and is tolerant to 3.3V.
▪ Ultra low PN for 1.65GHz LO: -142.08dBc/Hz at 1MHz Offset,
(typical)
▪
▪
▪
▪
▪
▪
In multi-service base stations, very low noise oscillators are
required to generate a large variety of frequencies to the mixers
while maintaining excellent phase noise performance and low
power. The 8V97053 offers a large tuning range capable of
providing multi-band local oscillator (LO) frequency synthesis in
multi-mode base stations, thus limiting the use of multiple narrow
band RF Synthesizers and reducing the BOM complexity and
cost. The device can operate over -40°C to +85°C industrial
temperature range.
Lock Detect Indicators
Input reference frequency: 5MHz to 310MHz
Automatic VCO band selection (Autocal feature)
-40°C to +85°C ambient operating temperature
Supports case temperature ≤ 105°C operations
Lead-free (RoHS 6), 32-VFQFPN, 5 5 mm package
Typical Applications
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Wireless infrastructure
Test equipment
CATV equipment
Military and aerospace
Wireless LAN
Clock generation
©2018 Integrated Device Technology, Inc.
1
September 22, 2018
8V97053 Datasheet
Block Diagram
SDO
MUX_OUT
Lock
Detect
REF_IN
SCLK
SDI
CSB
R
2
2
PFD
LD
CP_OUT
Charge
Pump
External
Loop Filter
16/12 or 16/
16-bit Frac-N
Divider
VTUNE
SPI
FLSW
M0
CE
RF_OUT A
nRF_OUT A
Logic and Registers
RF_OUT B
nRF_OUT B
MUTE
©2018 Integrated Device Technology, Inc.
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September 22, 2018
8V97053 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Phase Noise (Open-Loop) at 730MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Phase Noise Performance (Open-Loop) at 1.1GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Phase Noise Performance (Open-Loop) at 1.65GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Phase Noise Performance (Open-Loop) at 2.3GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Phase Noise Performance (Open-Loop) at 3.8GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Phase Noise Performance (Open-Loop) at 4.4GHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Synthesizer Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reference Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reference Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Feedback Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Phase and Frequency Detector (PFD) and Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PFD Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
External Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Phase Detector Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Charge Pump High-Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Integrated Low Noise VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Band Selection Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Phase Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Phase Resync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Fast Lock Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RF Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MUX_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Default Power-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Program Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3- or 4-Wire SPI Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
©2018 Integrated Device Technology, Inc.
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September 22, 2018
8V97053 Datasheet
Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Filter Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2nd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3rd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
©2018 Integrated Device Technology, Inc.
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September 22, 2018
8V97053 Datasheet
Pin Assignments
VDD_SD
GND_SD
MUX_OUT
REF_IN
VDDD
GNDD
MUTE
LD
Figure 1. Pin Assignments for 32-VFQFPN, 5 x5 Package – Top View
32
31
30
29
28
27
26
25
SCLK
1
24
VREF
SDI
2
23
VCOM
CSB
3
22
RCP
CE
4
21
GNDA_VCO
FLSW
5
20
VTUNE
V_CP
6
19
VBIAS
CP_OUT
7
18
GNDA_VCO
GND_CP
8
17
VVCO
9
10
11
12
13
14
15
16
GNDA
VDDA
GNDA_VCO
RF_OUTA
nRF_OUTA
RF_OUTB
nRF_OUTB
VVCO
8V97053
Pin Descriptions
Table 1. Pin Description[a]
Pin
Name
Type
1
SCLK
LVCMOS Input
Pulldown
Serial Clock Input. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant.
2
SDI
LVCMOS Input
Pullup
Serial Data Input. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant.
3
nCS
LVCMOS Input
Pulldown
4
CE
LVCMOS Input
Pullup
5
FLSW
Analog
Fast Lock Switch. A connection should be made from the loop filter to this pin
when using the fast lock mode.
6
V_CP
Power
Charge Pump Power Supply. V_CP must have the same value as VDDA. Place
decoupling capacitors to the ground plane as close to this pin as possible.
7
CP_OUT
Analog
Charge Pump Output. When enabled, this output provides ±ICP to the
external loop filter. The output of the loop filter is connected to VTUNE to drive
the internal VCO.
8
GND_CP
Ground
Charge Pump Power Supply Ground.
9
GNDA
Ground
Analog Power Supply Ground.
10
VDDA
Power
Analog Supply. This pin ranges from 3.3V ± 5%. VDDA must have the same
value as VDDD.
©2018 Integrated Device Technology, Inc.
Description
Load Enable. High-Impedance CMOS input. 1.8V logic. 3.3V tolerant. Active
Low.
Chip Enable. On logic Low, powers down the device and puts the charge
pump into High-Impedance mode. Powers up the device on logic High.
5
September 22, 2018
8V97053 Datasheet
Table 1. Pin Description[a] (Cont.)
Pin
Name
Type
Description
11
GNDA_VCO
Ground
VCO Analog Power Supply Ground.
12
RF_OUTA
Output
Clock Output pair A. The output level is programmable.
13
nRF_OUTA
Output
Clock Output pair A. The output level is programmable.
14
RF_OUTB
Output
Clock Output pair B. The output level is programmable.
15
nRF_OUTB
Output
Clock Output pair B. The output level is programmable.
16
VVCO
Power
VCO Supply. This pin ranges from 3.3V ± 5%. VVCO must have the same
value as VDDA.
17
VVCO
Power
VCO Supply. This pin ranges from 3.3V ± 5%. VVCO must have the same
value as VDDA.
18
GNDA_VCO
Ground
VCO Analog Power Supply Ground.
19
VBIAS
Analog
Place decoupling capacitors ( 0.1µF) to ground, as close to this pin as
possible.
20
VTUNE
21
GNDA_VCO
Ground
VCO Analog Power Supply Ground.
22
RCP
Analog
Sets the charge pump current. Requires external resistor.
23
VCOM
Analog
Place decoupling capacitors (0.1µF) to ground, as close to this pin as
possible.
24
VREF
Analog
Place decoupling capacitors (0.1µF) to ground, as close to this pin as
possible.
25
LD
LVCMOS Output
26
MUTE
LVCMOS Input
27
GNDD
Ground
Digital Power Supply Ground.
28
VDDD
Power
Digital Supply. VDDD must have the same value as VDDA.
29
REF_IN
LVCMOS Input
30
MUX_OUT
LVCMOS Output
31
GND_SD
Ground
Digital Sigma Delta Modulator Power Supply Ground.
32
VDD_SD
Power
Digital Sigma Delta Modulator Supply. VDD_SD must have the same value as
VDDA.
EP
Exposed
Pad
Ground
Control Input to tune the VCO.
Lock Detect. Logic High indicates PLL lock. Logic Low indicates loss of PLL
lock.
Pullup
Analog
RF_OUTA and RF_OUTB Power-Down. A logic low on this pin mutes the
RF_OUT outputs and puts them in High-Impedance.
Reference Input. This CMOS input has a nominal threshold of V DDA/2 and a
DC equivalent input resistance of 100k. This input can be driven from a TTL
or CMOS crystal oscillator, or it can be AC-coupled.
Multiplexed Output and Serial Data Out. Refer to Table 13.
Must be connected to GND.
[a] Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Cin
Input Capacitance
ROUT
LVCMOS Output Impedance
RPULLUP
RPULLDOWN
Minimum
Typical
Maximum
Units
4
pF
38
Ω
Input Pullup Resistor
51
kΩ
Input Pulldown Resistor
51
kΩ
MUX_OUT and LD
Table 3. Supply Pins and Associated Current Return Paths
Power Supply Pin Number
Power Supply Pin Name
Associated Ground Pin Number
Associated Ground Pin Name
10
VDDA
9
GNDA
28
VDDD
27
GNDD
32
VDD_SD
31
GND_SD
16, 17
VVCO
11, 18, 21
GNDA_VCO
6
V_CP
8
GND_CP
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 8V97053 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 4. Absolute Maximum Ratings
Item
Supply Voltage, VDDX
Rating
[a]
3.63V
Analog Supply Voltage, VDDA
3.63V
Input, VI
REF_IN
Other Inputs (MUTE, SDI, FLSW, VTUNE)
-0.5 to VDDA + 0.5V
Outputs, VO
RF_OUTA-B, nRF_OUTA-B
-0.5 to VDDA + 0.5V
Outputs, VO (SCLK, LD, nCS, MUX_OUT)
-0.5 to VDDA + 0.5V
Outputs, IO
Continuous Current
Surge Current
40mA
65mA
Outputs, IO (SCLK, LD, nCS, MUX_OUT)
Continuous Current
Surge Current
8mA
13mA
Junction Temperature, TJ
125°C
Storage Temperature, TSTG
-65°C to 150°C
[a] VDDX denotes VDDD, V_CP, VDD_SD, VVCO.
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DC Electrical Characteristics
Table 5. Power Supply DC Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to +85°C[a]
Symbol
Parameter
Test Conditions
[b] [c]
Minimum
Typical
Maximum
Units
VDDX
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
IDDX[d]
Power Supply Current
130
145
mA
RF_OUTA / nRF_OUTA - Active
RF_OUTB / nRF_OUTB - Muted
60
77
mA
RF_OUTA / nRF_OUTA - Active
RF_OUTB / nRF_OUTB - Active
85
105
mA
RF_OUTA / nRF_OUTA - Muted
RF_OUTB / nRF_OUTB - Muted
40
50
mA
IDDA[e]
IVCO
Analog Supply Current
VCO Supply Current
85
Power Down Mode
10
mA
15
mA
[a] VDDX denotes VDDD, V_CP, VDD_SD, VVCO.
[b] RF Outputs Terminated 50to VDDA.
[c] Output Power set to +2dBm.
[d] IDDX denotes IDDD + I_CP + IDD_SD + IVCO.
[e] IDDA is dependent on the value of the M0 output divider. The numbers indicated for IDDA show the current consumption when using the output
divider M0 = 64, for which IDDA is higher than when using any other M0 divider value.
Table 6. Output Divider Incremental Current[a]
Parameter
Output Divider Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
Divide by 2
8.0
mA
Divide by 4
7.0
mA
Divide by 8
1.5
mA
Divide by 16
1.5
mA
Divide by 32
1.5
mA
Divide by 64
1.5
mA
[a] RF Output divider (÷MO) has an incremental increase in current as the divider value increases. This specification is the incremental current
change per output divider step. For example, current of divide-by-2 is 8mA more than divide-by-1, current of divide-by-4 is 7mA more than
divide-by-2, and so on. The total increase from ÷1 to ÷64 is 8mA + 7mA + 1.5mA + 1.5mA + 1.5mA + 1.5mA = 21mA.
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Table 7. Typical Current by Power Domain[a]
Pin Name
Pin Number
Typical Current
Units
V_CP
6
24
mA
VVCO
16, 17
22
mA
VDDD
28
0.8
mA
VDD_SD
32
9
mA
VDDA
10
63
mA
[a] Operating conditions are: REF_IN = 25MHz, INT = 100 (integer mode), RF Divider = ÷1,
RF_OUTA = RF_OUTB = 2.5GHz, RFPOWER = -1dBm, Charge Pump = 0.31mA
Table 8. LVCMOS DC Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to 85°C[a]
Symbol
VIH
VIL
Parameter
Input High Voltage
Test Conditions
Minimum
Typical
Maximum
Units
MUTE, CE
1.8
VDDx
V
SDI, SCLK,
nCS
1.5
VDDx
V
-0.3
0.6
V
Input Low Voltage
SDI, MUTE, CE
VDDx = 3.465V, VIN = 1.8V
5
µA
SCLK, nCS
VDDx = 3.465V, VIN = 1.8V
150
µA
SDI, MUTE, CE
VDDx = 3.465V, VIN = 0V
-150
µA
SCLK, nCS
VDDx = 3.465V, VIN = 0V
-5
µA
Output High Voltage
MUX_OUT, LD
VDDx = 3.465V; IOH = -500µA
VDDX - 0.4
V
Output Low Voltage
MUX_OUT, LD
VDDx = 3.465V; IOL = 500µA
IIH
Input High Current
IIL
Input Low Current
VOH
VOL
0.4
V
[a] VDDX denotes VDDD, V_CP, VDD_SD, VVCO.
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AC Electrical Characteristics
Table 9. AC Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to 85°C[a]
Symbol
Parameter
REF_IN
Input Reference Frequency[b]
VPP
Input Sensitivity
REF_IN
Test Conditions
Minimum
Ref Doubler Disabled
Typical
Maximum
Units
5
310
MHz
Ref Doubler Enabled
5
100
MHz
Biased at VDDA/2[c]
0.7
VDDA
V
fVCO
VCO Frequency
Fundamental VCO Mode
2200
4400
MHz
fRF_OUT
Output Frequency
Divider Values: 1, 2, 4, 8, 16, 32, 64
34.375
4400
MHz
fPFD
PFD Frequency
Fractional Mode
125
MHz
Integer Mode
310
MHz
KVCO
VCO Sensitivity
tLOCK
PLL Lock Time
-
Output Power Variation
-
RF Output Power
-
Min/Max VCO Tuning Voltage
Time from Low to High nCS until
at Normal Mode, Low to High LD
Muted, (M0 1)
60
MHz/V
250
µs
±1
dB
< -80
dBm
0.5 / 2.5
V
[a] VDDX denotes VDDD, V_CP, VDD_SD, VVCO.
[b] For REF_IN < 10MHz, the slew rate must be > 21V/µs.
[c] AC-coupling: the device provides an internal VDDA/2 bias.
Table 10. RF_OUT[A:B] Phase Noise and Jitter Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to
85°C[a] [b]
Symbol
Parameter
N(100k)
Test Conditions
Minimum
Typical
Maximum
Units
100kHz Offset from Carrier
-124.75
dBc/Hz
800kHz Offset from Carrier
-147.14
dBc/Hz
1MHz Offset from Carrier
-148.72
dBc/Hz
5MHz Offset from Carrier
-154.56
dBc/Hz
N(10M)
10MHz Offset from Carrier
-155.59
dBc/Hz
N()
Noise Floor (30MHz from Carrier)
-156
dBc/Hz
N(100k)
100kHz Offset from Carrier
-115.11
dBc/Hz
N(800k)
800kHz Offset from Carrier
-137.79
dBc/Hz
1MHz Offset from Carrier
-139.94
dBc/Hz
5MHz Offset from Carrier
-152.11
dBc/Hz
N(10M)
10MHz Offset from Carrier
-154.5
dBc/Hz
N()
Noise Floor ( 30MHz from Carrier)
-156
dBc/Hz
N(800k)
N(1M)
N(5M)
N(1M)
N(5M)
RF Output
Phase Noise Performance
at 730MHz (Open Loop)
RF Output
Phase Noise Performance
at 1.1GHz (Open Loop)
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Table 10. RF_OUT[A:B] Phase Noise and Jitter Characteristics, VDDX = VDDA = 3.3V ± 5%, TA = -40°C to
85°C[a] [b] (Cont.)
Symbol
Parameter
N(100k)
Test Conditions
Minimum
Typical
Maximum
Units
100kHz Offset from Carrier
-115.57
dBc/Hz
800kHz Offset from Carrier
-139,83
dBc/Hz
1MHz Offset from Carrier
-142.08
dBc/Hz
5MHz Offset from Carrier
-152.36
dBc/Hz
N(10M)
10MHz Offset from Carrier
-153.62
dBc/Hz
N()
Noise Floor ( 30MHz from Carrier)
-153.81
dBc/Hz
N(100k)
100kHz Offset from Carrier
-109
dBc/Hz
N(800k)
800kHz Offset from Carrier
-132.18
dBc/Hz
1MHz Offset from Carrier
-134.37
dBc/Hz
5MHz Offset from Carrier
-148.66
dBc/Hz
N(10M)
10MHz Offset from Carrier
-152.86
dBc/Hz
N()
Noise Floor ( 30MHz from Carrier)
-154.85
dBc/Hz
N(100k)
100kHz Offset from Carrier
-104.7
dBc/Hz
800kHz Offset from Carrier
-128.95
dBc/Hz
1MHz Offset from Carrier
-131.27
dBc/Hz
5MHz Offset from Carrier
-146.09
dBc/Hz
N(10M)
10MHz Offset from Carrier
-150.17
dBc/Hz
N()
Noise Floor ( 30MHz from Carrier)
-154
dBc/Hz
N(100k)
100kHz Offset from Carrier
-101.72
dBc/Hz
N(800k)
800kHz Offset from Carrier
-126.78
dBc/Hz
1MHz Offset from Carrier
-129.23
dBc/Hz
5MHz Offset from Carrier
-145.21
dBc/Hz
N(10M)
10MHz Offset from Carrier
-149.97
dBc/Hz
N()
Noise Floor ( 30MHz from Carrier)
-152.1
dBc/Hz
fPFD = 50MHz;
RF_OUTA = 2.2GHz
-74
dBc
N(800k)
N(1M)
N(5M)
N(1M)
N(5M)
N(800k)
N(1M)
N(5M)
N(1M)
N(5M)
-
RF Output
Phase Noise Performance
at 1.65GHz (Open Loop)
RF Output
Phase Noise Performance
at 2.3GHz (Open Loop)
RF Output
Phase Noise Performance
at 3.8GHz (Open Loop)
RF Output
Phase Noise Performance
at 4.4GHz (Open Loop)
Spurious Signals
Due to PFD Frequency
[a] VDDX denotes VDDD, V_CP, VDD_SD, VVCO.
[b] RF_OUT[A:B] output power setting = +2dBm.
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Phase Noise (Open-Loop) at 730MHz (3.3V)
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Phase Noise Performance (Open-Loop) at 1.1GHz (3.3V)
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Phase Noise Performance (Open-Loop) at 1.65GHz (3.3V)
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Phase Noise Performance (Open-Loop) at 2.3GHz (3.3V)
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Phase Noise Performance (Open-Loop) at 3.8GHz (3.3V)
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Phase Noise Performance (Open-Loop) at 4.4GHz (3.3V)
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Principles of Operation
Synthesizer Programming
The Fractional-N architecture is implemented via a cascaded programmable dual modulus prescaler. The N divider offers a division ratio
in the feedback path of the PLL, and is given by programming the value of INT, FRAC and MOD in the following equation:
N = INT + FRAC/MOD(1)
INT is the divide ratio of the binary 16-bits counter (see Table 18).
FRAC is the numerator value of the fractional divide ratio. It is programmable from 0 to (MOD – 1). Refer to Table 19 when in 12-bit mode,
or Table 83 when in 16-bit mode.
MOD is the 12-bit or 16-bit modulus. It is programmable from 2 to 4095 in 12-bit mode, and 2 to 65535 in 16-bit mode. Refer to Table 24
when in 12-bit mode, or Table 82 when in 16-bit mode.
The VCO frequency (fVCO) at RF_OUTA or RF_OUTB is given by the following equation:
fVCO = fPFD (INT + FRAC/MOD)(2)
fPFD is the frequency at the input of the Phase and Frequency Detector (PFD).
The 8V97053 offers an Integer mode. To enable that mode, the user has to program the FRAC value to 0.
The device’s VCO features three VCO band-splits to cover the entire range with sufficient margin for process, voltage, and temperature
variations. These are automatically selected by invoking the Autocal feature. The charge pump current is also programmable via the ICP
SETTING register for maximum flexibility.
Via Register 4, one can enable RF_OUTA or both outputs. Similarly, one can disable RF_OUTB or both outputs.
Reference Input Stage
The 8V97053 features one single-ended reference clock input (REF_IN). This single-ended input can be driven by an ac-coupled sine
wave or square wave.
In Power Down mode this input is set to High-Impedance to prevent loading of the reference source. The reference input signal path also
includes an optional doubler.
Reference Doubler
To improve the phase noise performance of the device, the reference doubler can be used. By using the doubler, the PFD frequency is
also doubled and the phase noise performance typically improves by 3dB. When operating the device in Fractional mode, the speed of
the Sigma Delta modulator of the N counter is limited to 125MHz, which is also the maximum PFD frequency that can be used in the
fractional mode. When the part operates in Integer-N mode, the PFD frequency is limited to 310MHz.
1. The user has the possibility to select a higher PFD frequency (up to 310MHz in Integer mode) by doing the following steps using
registers 6 and 7.
2. The user needs to increase the size of the Band Select Clock Divider (normally 8-bits) by setting the bit [D6:D3] in the Register 6 to
divide down to a frequency lower than 500kHz and higher than 125kHz.
Use the Bit[D27:D26] to increase the lock detect precision for the faster PFD frequency.
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The Lock Detect window should be set as large as possible but less than a period of the phase detector. The phase detector frequency
should be greater than 500kHz.
Table 11. Lock Detect Precision (LDP)
LDP_Ext2
(D27 of Register 6)
LDP_Ext1
(D26 of Register 6)
LDP
(D7 of Register 2)
LDP value (ns)
0
0
0
10
0
0
1
6
Use of Register 6
0
1
0
3
0
1
1
3
1
0
0
4
1
0
1
4.5
1
1
0
1.5
1
1
1
1.5
Feedback Divider
The feedback divider N supports fractional division capability in the PLL feedback path. It consists in an integer N divider of 16 bits, and a
Fractional divider of 12 bits (FRAC) over 12-bits (MOD). FRAC and MOD can be extended to 16 bits when using register 7.
To select an integer mode only, the user sets FRAC to 0.
Figure 2. RF Feedback N Divider
FROM VCO OUTPOUT
or FROM M0 OUTPUT
TO PFD
N counter
rd
3 Order
ΣΔ Modulator
12 Bit FRAC
16 Bit INT
+
12 Bit MOD
The 16 INT bits (Bit[D30:D15] in Register 0) set the integer part of the feedback division ratio.
The 12 FRAC bits (Bit[D14:D3] in Register 1) set the numerator of the fraction that goes into the Sigma Delta modulator. FRAC can be
extended to 16 bits using the EXT_FRAC bits in Register 7.
The 12 MOD bits (Bit[D14:D3] in Register 1) set the denominator of the fraction that goes into the Sigma Delta modulator. MOD can be
extended to 16 bits using the EXT_MOD bits in Register 7.
From the relation (2), the VCO minimum step frequency is determined by (1/MOD) * fPFD.
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FRAC values from 0 to (MOD – 1) cover channels over a frequency range equal to the PFD reference frequency.
The PFD frequency is calculated as follows:
(3)
Use 2R instead of R if the Reference Divide by 2 is used.
REFCLK = the input reference frequency (REF_IN)
D = the input reference doubler (0 if not active or 1 if active)
R = the 10-Bits programmable input reference pre-divider
The programmable modulus (MOD) is determined based on the input reference frequency (REF_IN) and the desired channelization (or
output frequency resolution). The high resolution provided on the R counter and the Modulus allows the user to choose from several
configuration (by using the doubler or not) of the PLL to achieve the same channelization. Using the doubler may offer better phase noise
performance. The high resolution Modulus also allows to use the same input reference frequency to achieve different channelization
requirements. Using a unique PFD frequency for several needed channelization requirements allows the user to design a loop filter for
the different needed setups and ensure the stability of the loop.
The channelization is given by
(4)
In low noise mode (dither disabled), the Sigma Delta modulator can generate some fractional spurs that are due to the quantization
noise.
The spurs are located at regular intervals equal to fPFD/L where L is the repeat length of the code sequence in the Sigma Delta modulator.
That repeat length depends on the MOD value, as described in Table 12.
Table 12. Fractional Spurs Due to the Quantization Noise
Condition (Dither Disabled)
L
Spur Intervals
MOD can be divided by 2, but not by 3
2 MOD
fPFD/(2*MOD)
MOD can be divided by 3, but not by 2
3 MOD
fPFD/(3*MOD)
MOD can be divided by 6
6 MOD
fPFD/(6*MOD)
MOD
fPFD/MOD
(channel step)
Other conditions
In order to reduce the spurs, the user can enable the dither function to increase the repeat length of the code sequence in the Sigma
Delta modulator. The increased repeat length is 221 cycles so that the resulting quantization error is spread to appear like broadband
noise. As a result, the in-band phase noise may be degraded when using the dither function.
When the application requires the lowest possible phase noise and when the loop bandwidth is low enough to filter most of the
undesirable spurs, or if the spurs won’t affect the system performance, it is recommended to use the low noise mode with dither disabled.
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Phase and Frequency Detector (PFD) and Charge Pump
The phase detector compares the outputs from the R counter and from the N counter and generates an output corresponding to the
phase and frequency difference between the two inputs the PFD. The charge pump current is programmable through the serial port (SPI)
to several different levels.
The PFD offers an anti-backlash function that helps to avoid any dead zone in the PFD transfer function.
Figure 3. Simplified PFD Circuit using D-type Flip-flop
ICP
VDD
D1
Q1
REF_IN x (1+D)/R
CP_OUT
DELAY
VDD
D1
Q1
FB
ICP
The Band Select logic operates between 125kHz and 500kHz. The Band Select clock divider needs to be set to divide down the PFD
frequency to between 125kHz to 500kHz (logic maximum frequency).
PFD Frequency
The VCO Band Selection can be used while operating at PFD frequencies up to 310MHz.
If the application requires the PFD frequency to be higher than 125MHz, the user can use one of the following two techniques
(Technique A is the recommended procedure):
▪ Technique A – The user can use the ExtBndSelDiv[4:1] bits (Bits[D6:D3]) in Register 6. These additional band select divider bits
extend the band select divider from 8-bits (available in Register 4) to 12-bits. The four additional band select divider bits in Register 4
are the most significant bits of the divide value. For proper VCO band selection, the PFD frequency divided by the band select divide
value must be 500kHz and 125kHz.
▪ Technique B – If choosing this second technique, the user must follow the three following steps:
Disable the Phase Adjust function by setting the bit D28 In Register 1 to 0, keep the PFD frequency lower than 125MHz, and program the
desired VCO frequency.
Enable the phase adjust function by setting BAND_SEL_DISABLE (Bit D28 in Register 1) to 1.
Set the desired PFD frequency and program the relevant
R divider and N counter values.
In either technique, the Lock Detect Precision should be programmed to be lower than the PFD period using the bit [D7] in Register 2 and
the bits [D27:D26] in Register 6 (see Table 11).
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External Loop Filter
The 8V97053 requires an external loop filter. The design of that filter is application specific. For additional information, refer to the
Applications Information.
Phase Detector Polarity
The phase detector polarity is set by bit D6 in Register 2. This bit should be set to 1 when using a passive loop filter or a non-inverting
active loop filter. If an inverting active filter is used, this bit should be set to 0.
Charge Pump High-Impedance
In order to put the charge pump into three-state mode, the user must set the bit D4 [CP HIGHZ] in Register 2 to Register 1. This bit
should be set to 0 for normal operation.
Integrated Low Noise VCO
The VCO function of the 8V97053 consists in three separate VCOs. This allows keeping narrow tuning ranges for the VCOs while offering
a large frequency tuning range for VCO core. Keeping narrow VCO tuning ranges allows for lower VCO sensitivity (KVCO), which results
in the best possible VCO phase noise and spurious performance.
The user does not have to select the different VCO bands. The VCO band select logic of the 8V97053 will automatically select the most
suitable band of operation at power up or when Register 0 is written.
Output Clock Distribution
The 8V97053 device provides two outputs. These two outputs can generate the same frequency (fVCO / M0) or two integer related
different frequencies (in this case, RF_OUTB would generate a frequency equal to the VCO frequency and RF_OUTA would generate
fVCO / M0).
Figure 4. Output Clock Distribution
RF_OUT and nRF_OUT are derived from the drain of an NMOS differential pair driven by the VCO output (or by the M0 Divider), as
shown in Figure 5.
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Figure 5. Output Stage
RF_OUT
nRF_OUT
÷ M0
Eight programmable output power levels can be programmed from -4dBm to +7dBm (see RF Output Power).
The 8V97053 offers an auxiliary output (RF_OUTB). If the auxiliary output stage is not used, it can be powered down by using the
RF_OutB_En bit in Register 4.
The supply current to the output stage can be shut down until the part achieves lock. To enable this mode, the user will set the MTLD bit
in Register 4. The MUTE pin can be used to mute all outputs and be used as a similar function.
Output Matching
The outputs of the 8V97053 are Open Drain Output and can be matched in different ways.
A simple broadband matching is to terminate the open drain RF_OUT output with, for example, a 50 to VDDA, and with an AC coupling
capacitor in series. An example of this termination scheme is shown on Figure 6.
Figure 6. Broadband Matching Termination
This termination scheme allows to provide one of the selected output power on the differential pair when connected to a 50 load. (See
the RF Output Power for more information about the output power selection).
The 50 resistor connected to VDDA can also be replaced by a choke, for better performance and optimal power transmission.
Figure 7. Optimal Matching Termination
The pull up inductor value is frequency dependent. For impedance
of 50 pull-up, the inductance value can be calculated as
L = 50/(2*3.14*F), where F is operating frequency. In this example,
L = 3.9nH is for an operating frequency of approximately 2GHz.
©2018 Integrated Device Technology, Inc.
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September 22, 2018
8V97053 Datasheet
For more recommendations on the termination scheme, see Applications Information.
Band Selection Disable
For a given frequency, the output phase can be adjusted when using the Band_Sel_Disable bit (Bit D28 in Register 1). When this bit is
enabled (Bit D28 set to 1), the part does not do a VCO band selection or phase resync after an update to Register 0.
When the Band_Sel_Disable bit is set to 0, and when Register 0 is updated, the part proceeds to a VCO band selection, and to a phase
resync if phase_resync is also enabled in Register 3 (Bits[D16:D15] set to D16 = 1 and D15 = 0).
The “Band_Sel_Disable” bit is useful when the user wants to make small changes in the output frequency ( 4 is recommended.
fp is frequency at pole.
5. Verify Phase Margin (PM)
Where,
b 1
Cz
Cp
The phase margin (PM) should be greater than 50°.
©2018 Integrated Device Technology, Inc.
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8V97053 Datasheet
A spreadsheet for calculating the loop filter component values is available at www.IDT.com. To use the spreadsheet, the user simply
enters the following parameters:
fc, F_ref, PV, Icp, FVCO, and .
The spreadsheet will provide the component values, Rz, Cz and Cp as the result. The spreadsheet also calculates the maximum phase
margin for verification.
3rd Order Loop Filter
This section helps design a 3rd order loop filter for the 8V97053. A general 3rd order loop filter is shown in Figure 13.
Figure 13. Typical 3rd Order Loop Filter
RP2
RZ
Cp
Cp2
CZ
The Rz, Cz and Cp can be calculated as 2nd order loop filter.
The following equation help determine the 3rd order loop filter Rp2 and Cp2.
Pick an Rp2 value. Rp2 ~ 1.5xRz is suggested.
Where,
is ratio between the 1st pole frequency and the 2nd pole frequency. > 4 is recommended.
Recommendations for Unused Input and Output Pins
Inputs
LVCMOS Control Pins
All control pins have internal pullup and pulldown resistors; additional resistance is not required but can be added for additional
protection. A 1k resistor can be used.
Outputs
Output Pins
For any unused output, it can be left floating and disabled.
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8V97053 Datasheet
Schematic Example
Figure 14 and Figure 15 show general application schematic examples for the 8V97053.
For power rails, bypass capacitors must be provided to all power supply pins. Suggest at least one bypass capacitor per power pin. Value
can be ranged from 0.01uF or 0.1uF. Mix values of bypass capacitor can help filtering wider range of power supply noise.
The 8V97053 input is high impedance. The input termination depends on the driver type termination requirements. In these examples, the
8V97053 REF_IN input is terminated with a matched load termination. For transmission line with characteristic impedance Zo = 50, the
termination resistor R8 is 50. The input is self-biased to proper DC offset after the AC coupling.
VTUNE
Figure 14. An 8V97053 General Application Schematic Example
C3
C6
0.1u
1u
C1
C2
10u
0.1u
VDD
C4
C5
0.1u
10u
V_vco
R9
24
23
22
21
20
19
18
17
R1
4.7k
R8
50
LD
MUTE
GNDD
VDDD
REF_IN
MUX_OUT
GND_SD
VDD_SD
16
15
14
13
12
11
10
9
L1
3.9n
nREF_OUTA
VDD
REF_OUTA
47u
VVCO
nRF_OUTB
RF_OUTB
nRF_OUTA
RF_OUTA
GNDA_VCO
VDDA
GNDA
33 E_PAD
R2
50
VDD
R1
50
nREF_OUTA
REF_OUTA
C9
9/ ::; !!
1n
' ) *
Zo = 50
C10
1n
Zo = 50
1
2
3
4
5
6
7
8
U1
L2
3.9n
SCLK
SDI
nCS
CE
FLSW
V_CP
CP_OUT
GND_CP
' @
25
26
27
28
29
30
31
32
C8
1n
'
/ 4
2
C21
VREF
VCOM
RCP
GNDA_VCO
VTUNE
VBIAS
GNDA_VCO
VVCO
VDD
C7
1n
/
/ 4
VDD
CP_OUT
FLSW
VTUNE
C11
R3
C12
=
?
C13
R5
? "
?
R3
CP_OUT
R3
CP_OUT
VTUNE
C11
VTUNE
C11
R6
R4
FLSW
FLSW
C12
C13
R5
C12
C13
R7
©2018 Integrated Device Technology, Inc.
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September 22, 2018
8V97053 Datasheet
The loop filter values can be calculated to meet the loop bandwidth requirement. Please refer to the Loop Filter Calculations for detailed
calculations. For fast lock mode, the loop filter can be configured as Fast Lock Loop Filter Option 1 or Fast Lock Loop Filter Option 2
shown in Figure 14.
Fast Lock Loop Filter Option 1 is Parallel Resistor Configuration. For normal operating mode, only R5 is active and R5 = Rs, where Rs is
the resistor value for normal operating mode loop bandwidth. In fast lock mode, the combination of R4 in parallel with R5 is active. For
example, in normal operation mode, if the charge pump current is set at 0000 (ICP = 310uA), then, in fast lock mode, the loop bandwidth
is set larger by increasing the charge pump current to ICP~5mA (ICP setting = 1111 or 16 times the normal charge pump current). The
combination of the R4 and R5 in parallel is 1/4 * Rs.
Fast Lock Loop Filter Option 2 is Series Resistor Configuration. For normal operating mode, both R6 and R7 are active and
R6 + R7 = Rs. For fast lock mode, only R6 is active. For example, in normal operation mode, if the charge pump current is set at 0000
(ICP = 310uA), then, in fast lock mode, the loop bandwidth is set larger by increasing the charge pump current to ICP~5mA (ICP setting
= 1111 or 16 times the normal charge pump current). The sum of R6 and R7 equals to Rs, i.e. R6 + R7 = Rs.
R6 = 1/4 * Rs and R7 = 3/4 * Rs.
The 8V97053 output pull-up loading can be resistors or inductors. The pull up resistor value is typically 50. Resistor pull up loading
covers wide range of output frequencies. For inductor pull up loading, the inductor value is frequency dependent. One inductor value
cannot cover all the output frequency range. This example shows the L = 3.9nH that is suitable for approximately 2GHz operating
frequency. The output can also drive single ended LO input. Figure 15 shows an example of the 8V97053 output driving single ended LO
input of the mixer through an LC balun. The LC balun component values are frequency dependent. These values can be adjusted to
optimize the performance. Single ended LO receiver input also can tap to one side of the differential driver using resistor loading or
inductor loading. For single ended LO input, both sides of the differential driver still need to be loaded with pull up. The output power level
can also be adjusted further through programming.
Figure 15. Schematic Example for Driving Single Ended Mixer
/
/ 4
VDD
VDD
VTUNE
'
/ 4
C3
C6
0.1u
1u
C4
C5
0.1u
10u
R2
50
C1
C2
10u
0.1u
24
23
22
21
20
19
18
17
R8
50
VDD
'
( ) *
47u
L2
VVCO
nRF_OUTB
RF_OUTB
nRF_OUTA
RF_OUTA
GNDA_VCO
VDDA
GNDA
16
15
14
13
12
11
10
9
' +
L1
+
VDD
C9
Zo = 50
!!
!"
#!
C14
#"
L3
$!
%&
C15
1
2
3
4
5
6
7
8
33 E_PAD
U1
2
C22
VREF
VCOM
RCP
GNDA_VCO
VTUNE
VBIAS
GNDA_VCO
VVCO
LD
MUTE
GNDD
VDDD
REF_IN
MUX_OUT
GND_SD
VDD_SD
C9
REF_OUTA
SCLK
SDI
nCS
CE
FLSW
V_CP
CP_OUT
GND_CP
' @
25
26
27
28
29
30
31
32
L1
3.9n
nREF_OUTA
C9
REF_OUTA
R10
VDD
C8
1n
L2
3.9n
V_vco
R1
4.7k
C7
1n
R1
50
nREF_OUTA
' +
+
VDD
R3
VTUNE
C11
R4
Optional
©2018 Integrated Device Technology, Inc.
C12
C13
R5
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8V97053 Datasheet
Power Considerations
The 8V97053 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme
cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe
and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature. The power calculation
example below was generated using a typical configuration. For many applications, the power consumption can vary depending on
configuration. Please contact IDT technical support for any concerns on calculating the power dissipation for your own specific
configuration.
Example 1: VCO Frequency Range = 1991MHz to 2846MHz
1. Power Dissipation.
The total power dissipation for the 8V97053 is the sum of the core power plus the power dissipation in the output driver.
The following is the power dissipation for VDD = 3.465V, which gives worse case results.
Power (core)MAX = VDD_MAX * (IDDA + IVCO + ICP + IDD_SD + IDDD)MAX = VDD_MAX * (IDDA + IDDX)MAX =
3.465V * (105mA + 145mA) = 866.25mW
Total Power (with two outputs active at 2dBm output power level) = 866.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures
that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 34.34°C/W per Table 88.
Therefore, Tj for an ambient temperature of 85°C with all outputs active is:
85°C + 0.866W * 34.34°C/W = 114.74°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the
type of board (multi-layer).
Table 88. Thermal Resistance JA for 32 Lead VFQFPN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2018 Integrated Device Technology, Inc.
0
1
2
34.34°C/W
30.7°C/W
29.12°C/W
52
September 22, 2018
8V97053 Datasheet
Example 2: VCO Frequency Range = 2590MHz to 3624MHz
1. Power Dissipation.
The total power dissipation for the 8V97053 is the sum of the core power plus the power dissipation in the output driver.
The following is the power dissipation for VDD = 3.465V, which gives worse case results.
Power (core)MAX = VDD_MAX * (IDDA + IVCO + ICP + IDD_SD + IDDD)MAX = VDD_MAX * (IDDA + IDDX)MAX =
3.465V * (85mA + 146.4mA) = 802mW
Total Power (with two outputs active at 2dBm output power level) = 802mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures
that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 34.34°C/W per Table 88.
Therefore, Tj for an ambient temperature of 85°C with all outputs active is:
85°C + 0.802W * 34.34°C/W = 113°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the
type of board (multi-layer).
Reliability Information
Table 89. JA vs. Air Flow for a 32-VFQFPN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
34.34°C/W
30.7°C/W
29.12°C/W
Table 90. JB vs. Air Flow for a 32-VFQFPN
JB vs. Air Flow[a]
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
0.472°C/W
[a] Note: JB is independent of airflow.
Transistor Count
The 8V97053 transistor count is: 338,270
©2018 Integrated Device Technology, Inc.
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September 22, 2018
8V97053 Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1
Marking Diagram
1. Lines 1 and 2 indicate the part number.
2. Line 3:
▪ “#” denotes stepping.
▪ “YY” is the last two digits of the year; “WW” is the work week number that the part
was assembled.
▪ “$” denotes the mark code.
Ordering Information
Part/Order Number
Marking
8V97053NLGI
IDT8V97053NLGI
8V97053NLGI8
IDT8V97053NLGI
8V97053NLGI/W
IDT8V97053NLGI
Package
Lead-free (RoHS 6),
32-VFQFPN, 5 5 mm
Shipping Packaging
Temperature
Tray
-40°C to +85°C
Tape and Reel
-40°C to +85°C
Tape and Reel
-40°C to +85°C
Table 91. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
Correct Pin 1 ORIENTATION
NLGI8
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
Correct Pin 1 ORIENTATION
NLGI/W
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Quadrant 2 (EIA-481-D)
USER DIRECTION OF FEED
©2018 Integrated Device Technology, Inc.
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8V97053 Datasheet
Revision History
Revision Date
September 22, 2018
Description of Change
Changed the functional value of REV_ID in Table 78
August 7, 2018
Changed incorrect measurement unit nF to nH in Output Matching and Schematic Example
April 23, 2018
Initial release.
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Tech Support
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Fax: 408-284-2775
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www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2018 Integrated Device Technology, Inc.
55
September 22, 2018
32-VFQFPN, Package Outline Drawing
5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.
NLG32P1, PSC-4171-01, Rev 02, Page 1
32-VFQFPN, Package Outline Drawing
5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.
NLG32P1, PSC-4171-01, Rev 02, Page 2
Package Revision History
Description
Date Created
Rev No.
April 12, 2018
Rev 02
New Format
Feb 8, 2016
Rev 01
Added "k: Value
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