ICS9161A
Dual Programmable Graphics Frequency Generator
General Description
Features
The ICS9161A is a fully programmable graphics clock
generator. It can generate user-specified clock
frequencies using an externally generated input
reference or a single crystal. The output frequency is
programmed by entering a 24-bit digital word through
the serial port. Two fully user-programmable phaselocked loops are offered in a single package. One PLL
is designed to drive the memory clock, while the
second drives the video clock. The outputs may be
changed on-the-fly to any desired frequency between
390 kHz and 120 MHz. The ICS9161A is ideally suited
for any design where multiple or varying frequencies
are required.
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This part is ideal for graphics applications. It generates
low jitter, high speed pixel clocks. It can be used to replace
multiple, expensive high speed crystal oscillators. The
flexibility of the device allows it to generate non-standard
graphics clocks.
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Pin-for-pin and function compatible with ICD2061A
Dual programmable graphics clock generator
Memory and video clocks are individually
programmable on-the-fly
Ideal for designs where multiple or varying
frequencies are required
Increased frequency resolution from optional predivide by 2 on the M counter
Output enable feature available for tristating outputs
Independent clock outputs range from 390 kHz to
120 MHz for VDD >4.75V
Power-down capabilities
Low power, high speed 0.8µ CMOS technology
Glitch-free transitions
Available in 16-pin, 300-mil SOIC or PDIP package
The ICS9161A is also ideal in disk drives. It can generate
zone clocks for constant density recording schemes. The low
profile, 16-pin SOIC or PDIP package and low jitter outputs
are especially attractive in board space critical disk drives.
The leader in the area of multiple output clocks on a single
chip, ICS has been shipping graphics frequency generators
since October, 1990, and is constantly improving the
phase-locked loop. The ICS9161A incorporates a patented
fourth generation PLL that offers the best jitter performance
available.
Block Diagram
EXTCLK
D14-D20
7
X1
X2
REF
fREF DIVIDE
(M÷)
XTAL
OSC
D11-D13
3
D0-D3
4
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
VCO
D4-D10
7
SEL0-CLK
SEL1-DATA
ADDRESS
24
24
DECODE
LOGIC
3
DATA
21
CONTROL REG
REGISTERS
21
21
21
3-TO-1
MUX
VCLK
(D0-D20)
21
MCLK
(D0-D20)
INIT1
INIT2
21
INIT
ROM
VCO
DIVIDE
(N÷)
PD
0210I—03/21/05
9161
MUX
CMOS
OUTPUT
DRIVER
Pscale
P= 2 or 4
D14-D20
7
D0-D3
4
D11-D13
3
REF
DIVIDE
(M÷)
VCO
VCO OUTPUT
DIVIDER
R=1,2,4,8,16
32,64,128
VCO
DIVIDE
(N÷)
VCLK
OE
D4-D10
7
POR
EXTSEL
Pscale
P= 2
CMOS
OUTPUT
DRIVER
MCLK
ICS9161A
Pin Configuration
16-Pin 300- mil SOIC or PDIP
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
SEL0-CLK
IN
Clock input in serial programming mode. Clock select pin in operating
mode. Has internal pull-down to GND.
2
SEL1-DATA
IN
Data input in serial programming mode. Clock select pin in operating
mode. Has internal pull-down to GND.
3
AVDD
4
OE
5
GND
6
X1
IN
7
X2
OUT
Cr ystal output which includes internal XTAL load capacitance.
8
MCLK
OUT
Memor y clock output.
9
VCLK
OUT
Video clock output.
10
ERROUT#
OUT
Output low signals an error in the serially programmed word.
11
EXTCLK
IN
External clock input. Has internal pull-up to VDD.
12
INIT0
IN
Selects initial power-up conditions, LSB. Has internal pull-down to GND.
13
VDD
PWR
14
INIT1
IN
Selects initial power-up conditions, MSB. Has internal pull-down to GND.
15
EXTSEL
IN
Selects external clock input (EXTCLK) as VCLK output. Has internal pullup to VDD.
16
PD#
IN
Power-down pin, active low. Has internal pull-up to VDD.
PWR
IN
PW R
Power.
Tristates outputs when low. Has internal pull-up to VDD.
Ground.
Cr ystal input. This input includes XTAL load capacitance and feedback
bias for the cr ystal.
Power.
0210I—03/21/05
2
ICS9161A
Register Definitions
As seen in the VCLK Selection table, OE acts to tristate
the output. The PD# pin forces the VCLK signal high while
powering down the part. The EXTCLK pin will only be
multiplexed in when EXTSEL and SEL0 are logic 0 and
SEL1 is a logic 1.
The register file consists of the following six registers:
Register Addressing
Address
(A2 - A0)
Register
000
001
010
011
100
110
REG0
REG1
REG2
MREG
PWRDWN
CNTL REG
The memory clock outputs are controlled by PD# and
OE as follows:
Definition
Video Clock Register 1
Video Clock Register 2
Video Clock Register 3
Memor y Register
Divisor for Power-down mode
Control Register
MCLK Selection
The ICS9161A places the three video clock registers and
the memory clock register in a known state upon powerup. The registers are initialized based on the state of the
INIT1 and INIT0 pins at application of power to the device.
The INIT pins must ramp up with VDD if a logical 1 on either
pin is required. These input pins are internally pulled down
and will default to a logical 0 if left unconnected.
Register Initialization
INIT0
MREG
REG0
REG1
REG2
0
0
1
1
0
1
0
1
32.500
40.000
50.350
56.644
25.175
25.175
40.000
40.000
28.322
28.322
28.322
50.350
28.322
28.322
28.322
50.350
When the ICS9161A is operating, the video clock output
is controlled with a combination of the SEL0, SEL1, PD#
and OE pins. The video clock is also multiplexed to an
external clock (EXTCLK) which can be selected with the
EXTSEL pin. The VCLK Selection Table shows how VCLK
is selected.
VCLK Selection
PD#
EXTSEL
SEL1
SEL0
VCLK
0
1
1
1
1
1
1
x
0
1
1
1
1
1
x
x
x
x
0
1
x
x
x
0
0
1
1
1
x
x
0
1
0
x
1
Tristate
Forced High
REG0
REG1
EXTCLK
REG2
REG2
MCLK
0
1
1
x
1
0
Tristate
MREG
PWRDWN
When MCLK or the active VCLK register is being reprogrammed, then the reference signal is multiplexed
glitch-free to the output during the first time-out interval. A
second time-Register out interval is also required to allow
the VCO to settle. During this period, the reference signal
is multiplexed to the appropriate output signal.
Register Selection
OE
PD#
The Clock Select pins SEL0 and SEL1 have two purposes.
In serial programming mode, these pins act as the clock
and data pins. New data bits come in on SEL1 and these
bits are clocked in by a signal on SEL0. While these pins
are acquiring new information, the VCLK signal remains
unchanged. When SEL0 and SEL1 are acting as register
selects, a time-out interval is required to determine whether
the user is selecting a new register or wants to program the
part. During this initial time-out, the VCLK signal remains
at its previous frequency. At the end of this time-out
interval, a new register is selected. A second time-out
interval is required to allow the VCO to settle to its new
value. During this period of time, typically 5ms, the input
reference signal is multiplexed to the VCLK signal.
The registers are initialized as follows:
INIT1
OE
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ICS9161A
Control Register Definitions
The control register allows the user to adjust various internal options. The register is defined as follows:
Bit
21
20
Bit Name
C5
C4
Default Value
Description
0
This bit determines which power-down mode the PD# pin will implement.
Power-down mode 1, C5=0, forces the MCLK signals to be a function of
the power-down register. Power-down mode 2, C5=1, turns off the cr ystal
and disables all outputs.
0
This bit determines which clock is multiplexed to VCLK during frequency
changes. C4=0 multiplexes the reference frequency to the VCLK output.
C4=1 multiplexes MCLK to the VCLK output for applications where the
graphics controller cannot run as slow as fREF.
19
C3
0
This bit determines the length of the time-out inter val. The time-out inter val
is derived from the MCLK VCO. If this VCO is programmed to cer tain
extremes, the time-out inter val may be too shor t. C3=0, normal time-out.
C3=1, doubled time-out inter val.
18
C2
0
Reser ved, must be set to 0.
17
C1
1
This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in output high
time. C1=1 causes no adjustment. If the load capacitance is high, the
adjustment can bring the duty cycle closer to 50%.
16
C0
0
Reser ved, must be set to 0.
15
NS2
0
Acts on register 2. NS2=0 prescales the N counter by 2. NS2=1 prescales
the P counter value to 4.
14
NS1
0
Acts on register 1. NS1=0 prescales the N counter by 2. NS1=1 prescales
the P counter value to 4.
13
NS0
0
Acts on register 0. NS1=0 prescales the N counter by 2. NS0=1 prescales
the P counter value to 4.
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ICS9161A
Serial Programming Architecture
Since the VCLK registers are selected by the SEL0 and
SEL1 pins, and since any change in their state may affect
the output frequency, new data input on the selection bits
is only permitted to pass through the decode logic after the
watchdog timer has timed out. This delay of SEL0 or SEL1
data permits a serial program cycle to occur without
affecting the current register selection.
The pins SEL0 and SEL1 perform the dual functions of
select-ing registers and serial programming. In serial
programming mode, SEL0 acts as a clock pin while SEL1
acts as the data pin. The ICS9161A-01 may not be serially
programmed when in power-down mode.
In order to program a particular register, an unlocking
sequence must occur. The unlocking sequence is detailed
in the following timing diagram:
Serial Data Register
The serial data is clocked into the serial data register in the
order described in Figure 1 below (Serial Data Timing).
The serial data is sent as follows: An individual data bit is
sampled on the rising edge of CLK.The complement of the
data bit must be sampled on the previous falling edge of
CLK. The setup and hold time requirements must be met
on both CLK edges. For specifics on timing, see the timing
diagrams on pages 10, 11 and 12.
The bits are shifted in this order: a start bit, 21 data bits,
3 address bits (which designate the desired register), and
a stop bit. A total of 24 bits must always be loaded into the
serial data register or an error is issued. Following the entry
of the last data bit, a stop bit or load command is issued
by bringing DATA high and toggling CLK high-to-low and
low-to-high. The unlocking mechanism then resets itself
following the load. Only after a time-out period are the
SEL0 and SEL1 pins allowed to return to a register
selection function.
The unlock sequence consists of at least five low-to-high
transitions of CLK while data is high, followed immediately
by a single low-to-high transition while data is low. Following
this unlock sequence, data can be loaded into the serial
data register. This programming must include the start bit,
shown in Figure 1.
Following any transition of CLK or DATA, the watchdog
timer is reset and begins counting. The watchdog timer
ensures that successive rising edges of CLK and DATA do
not violate the time-out specification of 2ms. If a time-out
occurs, the lock mechanism is reset and the data in the
serial data register is ignored.
Figure 1: Serial Data Timing
0210I—03/21/05
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ICS9161A
The serial data register is exactly 24 bits long, enough to
accept the data being sent. The stop bit acts as a load
command that passes the contents of the Serial Data
Register into the register indicated by the three address
bits. If a stop bit is not received after the serial register is
full, and more data is sent, all data in the register is ignored
and an error issued. If correct data is received, then the
unlocking mechanism re-arms, all data in the serial data
register is ignored, and an error is issued.
The equations used to determine the oscillator frequency
a
r
e
:
ERROUT# Operation
The value of FVCO must remain between 50 MHz and 120
MHz. As a result, for output frequencies below 50 MHz,
FVCO must be brought into range. To achieve this, an
output divisor is selected by setting the values of the Mux
Field (R) as follows:
Output Divisor
N=N’ + 3 M=M’ + 2
FVCO=Prescale • N/M • FREF
where 3 ≤ M ≤ 129 and 4 ≤ N ≤ 130
and prescale=2 or 4, as set in the control register
(Where N is the VCO divider & M is the reference
divider)
Any error in programming the ICS9161A is signaled by
ERROUT#. When the pin goes low, an error has been
detected. It stays low until the next unlock sequence. The
signal is invoked for any of the following errors: incorrect
start bit, incorrect data encoding, incorrect length of data
word, and incorrect stop bit.
Programming the ICS9161A
The ICS9161A has a wide operating range, but it is
recommended that it is operated within the following limits:
4.75V< VDD