DATASHEET
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Pin Configuration:
Serverworks HT2100-based systems using AMD K8
processors
X1
X2
VDDREF
FS0/REF0
FS1/REF1
FS2/REF2
GNDREF
VDD48
48MHz_0
48MHz_1
48MHz_2
GND48
SCLK
SDATA
VDDPCI
**FS3/PCICLK0
PCICLK1
GNDPCI
PD#
GND
VDDA
GNDA
IREF
VDDA
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT2
SRCCLKC2
VDDSRC
GNDSRC
Output Features:
•
•
•
•
•
•
7 - Pairs of AMD K8 clocks
6 - Pair of SRC/PCI Express* clock
3 - 14.318 MHz REF clocks
3 - 48MHz clocks
2 - PCI 33 MHz clocks
2 - 25MHz clocks
Features:
•
•
•
Spread Spectrum for EMI reduction
Outputs may be disabled via SMBus
M/N programming via SMBus
Functionality
Bit2 Bit1
FS2 FS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Bit0
FS0
CPU
(MHz)
0
1
0
1
0
1
0
1
Hi-Z
X/4
180.00
220.00
100.00
133.33
166.67
200.00
VDD
8
64
15
21,24
31, 39
55, 49, 41
3
GND
12
61
18
22
32
54, 48, 40
7
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD25MHz
25MHz_0
25MHz_1
GND25MHz
SPREAD_EN
CPUCLK8T6
CPUCLK8C6
CPUCLK8T5
CPUCLK8C5
VDDCPU
GND
CPUCLK8T4
CPUCLK8C4
CPUCLK8T3
CPUCLK8C3
VDDCPU
GND
CPUCLK8T2
CPUCLK8C2
CPUCLK8T1
CPUCLK8C1
CPUCLK8T0
CPUCLK8C0
VDDCPU
GND
VDDSRC
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
64-TSSOP
Power Groups
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
932S805
Recommended Application:
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Description
48MHz Clocks
25MHz Clocks
33 MHz PCI Clocks
IREF, Analog Core
SRC clocks
K8 CPU Clocks
REF Clocks, Xtal Osc.
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
1
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Pin Description
PIN #
PIN NAME
TYPE
IN
OUT
PWR
I/O
I/O
I/O
PWR
PWR
OUT
OUT
OUT
PWR
IN
I/O
PWR
I/O
OUT
PWR
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
X1
X2
VDDREF
FS0/REF0
FS1/REF1
FS2/REF2
GNDREF
VDD48
48MHz_0
48MHz_1
48MHz_2
GND48
SCLK
SDATA
VDDPCI
**FS3/PCICLK0
PCICLK1
GNDPCI
19
PD#
20
21
22
GND
VDDA
GNDA
PWR
PWR
PWR
23
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
24
25
26
27
28
29
30
31
32
VDDA
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT2
SRCCLKC2
VDDSRC
GNDSRC
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
3.3V power for the PLL core.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential push-pull SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin for the SRC outputs
IN
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Power pin for the 48MHz output.3.3V
48MHz clock output.
48MHz clock output.
48MHz clock output.
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
Ground pin.
3.3V power for the PLL core.
Ground pin for the PLL core.
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
2
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Pin Description (continued)
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN NAME
SRCCLKC3
SRCCLKT3
SRCCLKC4
SRCCLKT4
SRCCLKC5
SRCCLKT5
VDDSRC
GND
VDDCPU
CPUCLK8C0
CPUCLK8T0
CPUCLK8C1
CPUCLK8T1
CPUCLK8C2
CPUCLK8T2
GND
VDDCPU
CPUCLK8C3
CPUCLK8T3
CPUCLK8C4
CPUCLK8T4
GND
VDDCPU
CPUCLK8C5
CPUCLK8T5
CPUCLK8C6
CPUCLK8T6
SPREAD_EN
GND25MHz
25MHz_1
25MHz_0
VDD25MHz
TYPE
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
PWR
OUT
OUT
PWR
DESCRIPTION
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
Ground pin.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential 0.8V push-pull K8 pair.
True clock of differential 0.8V push-pull K8 pair.
Complementary clock of differential 0.8V push-pull K8 pair.
True clock of differential 0.8V push-pull K8 pair.
Complementary clock of differential 0.8V push-pull K8 pair.
True clock of differential 0.8V push-pull K8 pair.
Ground pin.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential 0.8V push-pull K8 pair.
True clock of differential 0.8V push-pull K8 pair.
Complementary clock of differential 0.8V push-pull K8 pair.
True clock of differential 0.8V push-pull K8 pair.
Ground pin.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential 0.8V push-pull K8 pair.
True clock of differential 0.8V push-pull K8 pair.
Complementary clock of differential 0.8V push-pull K8 pair.
True clock of differential 0.8V push-pull K8 pair.
Asynchronous, active high input to enable spread spectrum functionality.
Ground pin for the 25Mhz outputs
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Power supply for 25MHz clocks, 3.3V nominal.
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
3
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
General Description
The ICS932S805 is a main clock synthesizer chip that, when paired with ICS9DB108, provides all clocks required by
Serverworks HT2100-based servers.
An SMBus interface allows full control of the device.
Block Diagram
REF (2:0)
X1
X2
FS(3:0)
PD#
SPREAD_EN
XTAL
OSC.
48MHz(2:0)
FIXED PLL
25MHz PLL
25M
DIV
CPU/SRC/
PCI PLL
CPU
DIV
25MHz(1:0)
CPUCLK8(6:0)
CONTROL
LOGIC
PCI33
DIV
SDATA
SCLK
PCICLK(1:0)
SRC
DIV1
SRCCLK(5:0)
IREF
Single-ended Terminations
Number of
Series Resistor for Proper Termination
Single-ended
Output Strength Loads on Board Zo = 50 ohms Zo = 55 ohms Zo = 60 ohms
48MHz 1 Load
1
15
24
30
48MHz 2 Load
2
4.7
15
20
25MHz 1 Load
1
15
24
30
25MHz 2 Load
2
4.7
15
20
PCI 1 Load
1
15
24
30
PCI 2 Load
2
4.7
15
20
REF 1 Load
1
15
24
30
REF 2 Load
2
4.7
15
20
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
4
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
CPU Divider Ratios
Divider (1:0)
Divider (3:2)
Bit
00
01
10
11
LSB
00
0000
0001
0010
0011
Address
4
3
5
15
Div
01
0100
0101
0110
0111
Address
4
3
5
15
Div
01
0100
0101
0110
0111
Address
2
3
5
7
Div
01
0100
0101
0110
0111
Address
8
6
10
30
Div
10
1000
1001
1010
1011
Address
16
12
20
60
Div
11
1100
1101
1110
1111
Address
MSB
32
24
40
120
Div
10
1000
1001
1010
1011
Address
16
12
20
60
Div
11
1100
1101
1110
1111
Address
MSB
32
24
40
120
Div
10
1000
1001
1010
1011
Address
8
12
20
28
Div
11
1100
1101
1110
1111
Address
MSB
16
24
40
56
Div
PCI Divider Ratios
Divider (1:0)
Divider (3:2)
Bit
00
01
10
11
LSB
00
0000
0001
0010
0011
Address
8
6
10
30
Div
SRC Divider Ratios
Divider (1:0)
Divider (3:2)
Bit
00
01
10
11
LSB
00
0000
0001
0010
0011
Address
4
6
10
14
Div
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
5
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
General SMBus serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(h)
WR
WRite
Controller (host) will send start bit.
Controller (host) sends the write address D2 (h)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (h)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address D2(h)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(h)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDT® K8 Clock Chip for Serverworks HT2100 Servers
Not acknowledge
stoP bit
1131D – 05/04/10
6
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
SMBus Table: Frequency Select and Spread Control Register
Name
Control Function
Pin #
Byte 0
Latched Input or SMBus Frequency
FS Source
Bit 7
Select
Spread Enable for CPU, SRC and PCI Outputs.
Spread
Setting SPREAD_EN pin to '1', forces
Spectrum
Bit 6
Spread ON and overides this bit.
Enable
Reserved
Reserved
Bit 5
Reserved
Reserved
Bit 4
FS3
Freq
Select Bit 3
Bit 3
FS2
Freq Select Bit 2
Bit 2
FS1
Freq Select Bit 1
Bit 1
FS0
Freq Select Bit 0
Bit 0
SMBus Table: Output Control Register
Pin #
Byte 1
Name
6
REF2
Bit 7
5
REF1
Bit 6
4
REF0
Bit 5
17
PCICLK1
Bit 4
16
PCICLK0
Bit 3
11
48MHz_2
Bit 2
10
48MHz_1
Bit 1
9
48MHz_0
Bit 0
SMBus Table: Output Control Register
Byte 2
Pin #
Name
Reserved
Bit 7
59/58
CPUCLK8(6)
Bit 6
57/56
CPUCLK8(5)
Bit 5
53/52
CPUCLK8(4)
Bit 4
51/50
CPUCLK8(3)
Bit 3
47/46
CPUCLK8(2)
Bit 2
45/44
CPUCLK8(1)
Bit 1
43/42
CPUCLK8(0)
Bit 0
Type
0
RW Latched Inputs
1
PWD
SMBus
0
0
RW
OFF
ON
RW
RW
RW
RW
RW
RW
Reserved
Reserved
Reserved
Reserved
0
0
Latched
See CPU Frequency Select Latched
Table
Latched
Latched
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable (Low)
Disable (Low)
Disable (Low)
Disable (Low)
Disable (Low)
Disable (Low)
Disable (Low)
Disable (Low)
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
Control Function
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
Output Enable
When Disabled
CPUCLKT = 0
CPUCLKC = 1
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
7
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
SMBus Table: Output Control Register
Byte 3
Name
Control Function
Pin #
SRCCLK PD
SRCCLK Power Down Drive Mode
Bit 7 SRC CLKs
Reserved
Reserved
Bit 6
38/37
SRCCLK5
Output Enable
Bit 5
36/35
SRCCLK4
Output Enable
Bit 4
SRCCLK3
Output Enable
34/33
Bit 3
SRCCLK2
Output Enable
29/30
Bit 2
SRCCLK1
Output Enable
27/28
Bit 1
SRCCLK0
Output Enable
25/26
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Driven
Reserved
Disable (Hi-Z)
Disable (Hi-Z)
Disable (Hi-Z)
Disable (Hi-Z)
Disable (Hi-Z)
Disable (Hi-Z)
1
Hi-Z
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
0
1
1
1
1
1
1
SMBus Table: Drive Strength Control Register
Byte 4
Pin #
Name
Control Function
REF2
Drive Strength Select
6
Bit 7
5
REF1
Drive Strength Select
Bit 6
4
REF0
Drive Strength Select
Bit 5
17
PCICLK1
Drive Strength Select
Bit 4
16
PCICLK0
Drive Strength Select
Bit 3
11
48MHz_2
Drive Strength Select
Bit 2
10
48MHz_1
Drive Strength Select
Bit 1
9
48MHz_0
Drive Strength Select
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1 Load
1
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
2 Loads
PWD
1
1
1
1
1
1
1
1
SMBus Table: SRC Frequency Select Register
Byte 5
Name
Control Function
Pin #
25MHz_1
Output Enable
62
Bit 7
25MHz_0
Output Enable
63
Bit 6
25MHz_1
Drive Strength Select
62
Bit 5
25MHz_0
Drive Strength Select
63
Bit 4
Reserved
Reserved
Bit 3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
Reserved
Reserved
Bit 0
Type
0
RW Disable (Low)
RW Disable (Low)
RW
1 Load
RW
1 Load
RW
Reserved
RW
Reserved
RW
Reserved
RW
Reserved
1
Enable
Enable
2 Loads
2 Loads
Reserved
Reserved
Reserved
Reserved
PWD
1
1
1
1
0
0
0
0
SMBus Table: Device ID Register
Byte 6
Pin #
Name
DevID 7
Bit 7
DevID 6
Bit 6
DevID 5
Bit 5
DevID 4
Bit 4
DevID 3
Bit 3
DevID 2
Bit 2
DevID 1
Bit 1
DevID 0
Bit 0
Type
R
R
R
R
R
R
R
R
1
-
PWD
1
0
0
0
0
1
0
1
Control Function
Device ID MSB
Device ID 6
Device ID 5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID LSB
IDT® K8 Clock Chip for Serverworks HT2100 Servers
0
-
1131D – 05/04/10
8
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
SMBus Table: Vendor ID Register
Byte 7
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: Byte Count Register
Pin #
Byte 8
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Revision ID
VENDOR ID
(0001 = ICS)
Control Function
Byte Count Programming b(7:0)
SMBus Table: Reserved Register
Pin #
Name
Byte 9
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: M/N Programming Enable
Pin #
Byte 10
Name
Control Function
M/N_EN
CPU PLL M/N Programming Enable
Bit 7
Reserved
Reserved
Bit 6
Reserved
Reserved
Bit 5
Reserved
Reserved
Bit 4
Reserved
Reserved
Bit 3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
Reserved
Reserved
Bit 0
IDT® K8 Clock Chip for Serverworks HT2100 Servers
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
X
X
X
X
0
0
0
1
Type
0
1
RW
RW
Writing to this register will
RW
RW configure how many bytes
RW will be read back, default is
9 bytes.
RW
RW
RW
PWD
0
0
0
0
1
0
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
-
1
Enable
-
PWD
0
0
0
0
0
0
0
0
1131D – 05/04/10
9
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Bytes 11:14 Are Reserved
SMBus Table: CPU/SRC Frequency Control Register
Byte 15
Pin #
Name
Control Function
N Div8
N Divider Prog bit 8
Bit 7
Type
RW
Bit 6
-
N Div9
Bit 5
-
M Div5
RW
Bit 4
-
M Div4
RW
Bit 3
-
M Div3
Bit 2
-
M Div2
Bit 1
-
M Div1
RW
M Div0
RW
Bit 0
N Divider Prog bit 9
M Divider Programming
bit (5:0)
SMBus Table: CPU/SRC Frequency Control Register
Pin #
Byte 16
Name
Control Function
N Div7
Bit 7
RW
RW
RW
Type
RW
Bit 6
-
N Div6
RW
Bit 5
-
N Div5
RW
Bit 4
-
N Div4
Bit 3
-
N Div3
N Divider Programming Byte12 bit(7:0) RW
and Byte11 bit(7:6)
RW
Bit 2
-
N Div2
RW
Bit 1
-
N Div1
RW
N Div0
RW
Bit 0
SMBus Table: CPU/SRC Spread Spectrum Control Register
Byte 17
Pin #
Name
Control Function
SSP7
Bit 7
SSP6
Bit 6
SSP5
Bit 5
SSP4
Bit 4
Spread Spectrum Programming bit(7:0)
SSP3
Bit 3
SSP2
Bit 2
SSP1
Bit 1
SSP0
Bit 0
IDT® K8 Clock Chip for Serverworks HT2100 Servers
0
1
The decimal representation
of M and N Divier in Byte 15
and 16 will configure the
CPU VCO frequency.
Default at power up = latchin or Byte 0 Rom table. VCO
Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
0
1
The decimal representation
of M and N Divier in Byte 15
and 16 will configure the
CPU VCO frequency.
Default at power up = latchin or Byte 0 Rom table. VCO
Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
Type
0
1
RW
RW
These Spread Spectrum bits
RW
in Byte 17 and 18 will
RW
program the spread
RW
pecentage of CPU and SRC
RW
outputs.
RW
RW
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
1131D – 05/04/10
10
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
SMBus Table: CPU/SRC Spread Spectrum Control Register
Byte 18
Pin #
Name
Control Function
Reserved
Reserved
Bit 7
SSP14
Bit 6
SSP13
Bit 5
SSP12
Bit 4
Spread Spectrum Programming
SSP11
Bit 3
bit(14:8)
SSP10
Bit 2
SSP9
Bit 1
SSP8
Bit 0
Type
0
1
R
RW
RW These Spread Spectrum bits
in Byte 17 and 18 will
RW
program the spread
RW
RW pecentage of CPU and SRC
outputs.
RW
RW
PWD
0
X
X
X
X
X
X
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 18
Pin #
Name
Control Function
Reserved
Reserved
Bit 7
Reserved
Reserved
Bit 6
Reserved
Reserved
Bit 5
Reserved
Reserved
Bit 4
Reserved
Reserved
Bit 3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
Reserved
Reserved
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
0
0
0
0
0
SMBus Table: Programmable Output Divider Register
Pin #
Name
Control Function
Byte 19
CPUDiv3
Bit 7
CPUDiv2
Bit 6
CPU Divider Ratio Programming Bits
CPUDiv1
Bit 5
CPUDiv0
Bit 4
Reserved
Reserved
Bit 3
Reserved
Reserved
Bit 2
Reserved
Reserved
Bit 1
Reserved
Reserved
Bit 0
Type
RW
RW
RW
RW
R
R
R
R
0
1
PWD
X
X
X
X
0
0
0
0
See CPU Divider Ratios
Table
-
-
SMBus Table: Programmable Output Divider Register
Pin #
Name
Control Function
Type
0
1
Byte 20
33MHzDiv3
RW
Bit 7
33MHz Divider Ratio Programming
33MHzDiv2
RW
Bit 6
33MHz Divider Ratio Table
Bits
33MHzDiv1
RW
Bit 5
33MHzDiv0
RW
Bit 4
SRC_Div3
RW
Bit 3
SRC_Div2
RW
Bit 2
SRC_ Divider Ratio Programming Bits
SRC Divider Ratio Table
SRC_Div1
RW
Bit 1
SRC_Div0
RW
Bit 0
PWD
X
X
X
X
X
X
X
X
SMBusTable: Reserved Regsiter
Byte 21 is reserved do not write this register!
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
11
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V V
VDD_In
GND - 0.5 VDD + 0.5V V
3.3V Logic Input Supply Voltage
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tc
Case Temperature
115
°C
ESD prot Input ESD protection human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Conditions
MIN
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
Input High Current
VIL
IIH
3.3 V +/-5%
VIN = VDD
VSS - 0.3
-5
0.8
5
V
uA
1
1
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Operating Supply Current
I DD3.3OP
Full Active, CL = Full load;
Operating Current
I DD3.3OP
Powerdown Current
I DD3.3PD
Input Frequency 3
Pin Inductance1
Fi
Lpin
CIN
COUT
CINX
all outputs driven
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
Input Low Current
Input Capacitance1
Clk Stabilization1,2
Modulation Frequency
SMBus Voltage
Low-level Output Voltage
urrent sinking at VOL = 0.4
SCLK/SDATA
Clock/Data Rise Time3
SCLK/SDATA
Clock/Data Fall Time3
TSTAB
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion
of PD# to 1st clock
Triangular Modulation
VDD
VOL
TFI2C
MAX
258
30
2.7
mA
tbd
tbd
tbd
7
5
6
5
mA
mA
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
3
ms
1,2
33
5.5
0.4
kHz
V
V
mA
1
1
1
1
1000
ns
1
300
ns
1
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
UNITS NOTES
350
14.318
@ IPULLUP
IPULLUP
TRI2C
TYP
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
2
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
12
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Electrical Characteristics - K8 Push Pull Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load
PARAMETER
SYMBOL
CONDITIONS
MIN
Rising Edge Rate
δV/δt
2
10
V/ns
1
Falling Edge Rate
δV/δt
Measured at the AMD64 processor's
test load. 0 V +/- 400 mV (differential
measurement)
2
10
V/ns
1
Differential Voltage
Change in VDIFF_DC
Magnitude
Common Mode Voltage
Change in Common Mode
Voltage
VDIFF
2.3
V
1
150
mV
1
1.45
V
1
200
mV
1
200
ps
1
Jitter, Cycle to cycle
ΔVDIFF
VCM
0.4
Measured at the AMD64 processor's
test load. (single-ended
measurement)
ΔVCM
tjcyc-cyc
TYP
1.25
-150
1.05
1.25
-200
Measurement from differential
wavefrom. Maximum difference of
cycle time between 2 adjacent cycles.
0
Measured using the JIT2 software
package with a Tek 7404 scope.
TIE (Time Interval Error)
tja
Jitter, Accumulated
-1000
measurement technique:
Sample resolution = 50 ps,
Sample Duration = 10 µs
Measurement from differential
dt3
45
Duty Cycle
wavefrom
Average value during switching
RON
Output Impedance
15
transition. Used for determining
series termination value.
Measurement from differential
tsrc-skew
Group Skew
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz
3
Spread Spectrum is off
IDT® K8 Clock Chip for Serverworks HT2100 Servers
100
MAX
UNITS NOTES
1000
35
1,2,3
53
%
1
55
Ω
1
250
ps
1
1131D – 05/04/10
13
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
Voltage High
SYMBOL
CONDITIONS
MIN
Zo
VO = Vx
3000
VHigh
Statistical measurement on single
ended signal using oscilloscope math
function.
Measurement on single ended signal
using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Vovs
Vuds
Vcross(abs)
d-Vcross
ppm
Average period
Tperiod
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Tabsmin
tr
tf
d-tr
d-tf
Variation of crossing over all edges
see Tperiod min-max values
75.00 MHz nominal
75.00 MHz spread
100.00 MHz nominal
100.00 MHz spread
116.67 MHz nominal
116.67 MHz spread
133.33 MHz nominal
133.33 MHz spread
@100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
MAX
Ω
850
-150
150
1150
-300
250
350
12
550
140
-300
300
8.5684
8.5714
8.5744
8.5684
8.6244
9.9970 10.0000 10.0030
9.9970
10.0530
13.3303 13.3333 13.3363
13.3303
13.3863
7.4972
7.5002
7.5032
7.4972
7.5532
9.8720
175
700
175
700
30
125
30
125
Measurement from differential
45
55
wavefrom
Measurement from differential
tsrc-skew
Group Skew
250
wavefrom
Measurement from differential
tjcyc-cyc
125
Jitter, Cycle to cycle
wavefrom
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Duty Cycle
dt3
IDT® K8 Clock Chip for Serverworks HT2100 Servers
UNITS NOTES
1
1,3
mV
1,3
mV
mV
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1
1
1
1
1,2
2
2
2
2
2
2
2
2
1,2
1
1
1
1
%
1
mV
ps
ps
1
1131D – 05/04/10
14
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Electrical Characteristics - 33 MHz PCICLK, 25MHz Outputs
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
PCI Long Accuracy
ppm
PCI Clock period
Tperiod
25MHz Long Accuracy
25MHz Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
see Tperiod min-max values
25MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
-300
29.9910
29.9910
-100
0.0000
2.4
Output High Current
Output Low Current
IOH
IOL
TYP
MAX
300
30.0090
30.1598
100
0.0000
0.55
-33
-33
30
38
Edge Rate
1
4
δV/δt
1
4
Edge Rate
δV/δt
dt1
Duty Cycle
45
55
tsk1
250
PCI Skew
tsk1
25MHz Skew
250
tjcyc-cyc
250
Jitter, Cycle to cycle
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
UNITS Notes
ppm
ns
ns
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
%
ps
ps
ps
1,2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
Electrical Characteristics - 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
see Tperiod min-max values
48.00MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @ MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
-100
20.8257
2.4
Output High Current
IOH
Output Low Current
IOL
TYP
MAX
100
20.8340
0.55
-33
-33
30
38
1
2
Edge Rate
δV/δt
Edge Rate
1
2
δV/δt
dt1
Duty Cycle
45
55
tsk1
Group Skew
250
tjcyc-cyc
Jitter, Cycle to cycle
150
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
IDT® K8 Clock Chip for Serverworks HT2100 Servers
UNITS Notes
ppm
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
%
ps
ps
1,2
2
1
1
1
1
1
1
1
1
1
1
1
1131D – 05/04/10
15
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
-300
69.8270
2.4
Output High Current
IOH
Output Low Current
IOL
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V,
V
OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL
@MAX = 0.4 V
Rising edge rate
Falling edge rate
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
TYP
MAX
0.4
ppm
ns
V
V
1
2
1
1
-29
-23
mA
1
29
27
mA
1
1
2
V/ns
Edge Rate
δV/δt
1
2
V/ns
Edge Rate
δV/δt
tsk1
500
ps
Skew
dt1
Duty Cycle
45
55
%
t
1000
ps
Jitter, Cycle to cycle
jcyc-cyc
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
1
1
1
1
1
IDT® K8 Clock Chip for Serverworks HT2100 Servers
300
69.8550
UNITS Notes
1131D – 05/04/10
16
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin will
be pulled low. If programmability is not necessary, than only
a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS932S805
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a
5-bit internal data latch. At the end of Power-On reset, (see
AC characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
17
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
c
N
SYMBOL
L
E1
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
E
INDEX
AREA
1 2
D
VARIATIONS
A
A2
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
-1.20
-.047
0.05
0.15
.002
.006
0.80
1.05
.032
.041
0.17
0.27
.007
.011
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
-0.10
-.004
N
A1
64
-C-
D mm.
MIN
16.90
D (inch)
MAX
17.10
MIN
.665
MAX
.673
Reference Doc.: JEDEC Publication 95, MO-153
e
SEATING
PLANE
b
10-0039
aaa C
Ordering Information
Part/Order Number
932S805CGLF
932S805CGLFT
Shipping Packaging
Tubes
Tape and Reel
Package
64-pin TSSOP
64-pin TSSOP
Temperature
0 to 70° C
0 to 70° C
“LF” suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant.
“C” is the device revision designator (w ill not correlate w ith the datasheet revision)
IDT® K8 Clock Chip for Serverworks HT2100 Servers
1131D – 05/04/10
18
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Revision History
Rev.
A
B
C
D
Issue Date Description
1. Corrected Byte0 bits 7:6. They are no longer reserved.
2. Corrected SMBUS CPU PLL programming registers
2/21/2008 (Moved from Bytes 11:14 to Bytes 15:18)
2/21/2008 Updated maximum value for 48MHz Jitter, cycle to cycle
2/23/2009 Updated Functionality table.
5/4/2010 Added Tcase spec.
Page #
8, 11,12
15
1
12
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Fax: 44-1372-378851
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19
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