93732AFLF

ICS93732 Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • CYCLE - CYCLE jitter (66MHz): 100MHz): 200MHz):