950211BFLFT

ICS950211 Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ Pin Configuration VDDREF X1 X2 GND 1 PCICLK_F0 1 PCICLK_F1 PCICLK_F2 VDDPCI GND 1 *WDEN/PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 *PD# VDDA GND *Vtt_PWRGD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS950211 Recommended Application: Brookdale and Brookdale -G chipset with P4 processor. Output Features: • 3 - Pairs of differential CPU clocks (differential current mode) • 5 - 3V66 @ 3.3V • 10 - PCI @ 3.3V • 2 - 48MHz @ 3.3V fixed • 1 - REF @ 3.3V, 14.318MHz • 1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz Features/Benefits: • Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watch dog safe frequency. • Support I2C Index read/write and block read/write operations. • Uses external 14.318MHz crystal. 1. These outputs have 2X drive strength. * Internal Pull-up resistor of 120K to VDD ** these inputs have 120K internal pull-down to GND Frequency Table Block Diagram FS4 FS3 FS2 FS1 FS0 PLL2 48MHz_USB 48MHz_DOT XTAL OSC 3V66_1/VCH_CLK REF PLL1 Spread Spectrum WDEN PD# CPU_STOP# PCI_STOP# MULTSEL0 FS (4:0) SDATA SCLK Vtt_PWRGD# CPU DIVDER Reg. 3 Stop 7 3 Control Config. Stop 3 PCI DIVDER Logic 1 REF FS1 FS0 CPU_STOP#* CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTSEL0* I REF GND FS2 48MHz_USB/FS3** 48MHz_DOT AVDD48 GND 3V66_1/VCH_CLK/FS4** PCI_STOP#* 3V66_0 VDD GND SCLK SDATA 56-Pin 300-mil SSOP & 240-mil TSSOP Key Specifications: • CPU Output Jitter