951462AGLFT

ICS951462 Integrated Circuit Systems, Inc. Programmable System Clock Chip for ATI RS/RD690 - K8TM based Systems Output Features: • 2 - pairs of CPU pairs • 8 - pairs of SRC pairs • 4 - pairs of ATIG pairs • 1 - HyperTransport 66MHz clock seed • 2 - 48MHz USB clock • 3 - 14.318MHz Reference clock Key Specifications: • CPU outputs cycle-to-cycle jitter < 85ps • SRC outputs cycle-to-cycle jitter < 125ps • ATIG outputs cycle-to-cycle jitter < 125ps • +/- 300ppm frequency accuracy on CPU, SRC & ATIG clocks Features/Benefits: • 3 - Programmable Clock Request pins for SRC and ATIG clocks • ATIGCLKs are programmable for frequency • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy Functionality 0 CPU MHz Hi-Z HTT MHz Hi-Z SRC MHz 100.00 ATIG MHz 100.00 USB MHz 48.00 1 X/2 X/3 100.00 100.00 48.00 1 0 230.00 76.67 100.00 100.00 48.00 0 1 1 240.00 80.00 100.00 100.00 48.00 1 0 0 100.00 66.66 100.00 100.00 48.00 1 0 1 133.33 66.66 100.00 100.00 48.00 1 1 0 166.67 66.66 100.00 100.00 48.00 1 1 1 200.00 66.66 100.00 100.00 48.00 FS2 FS1 FS0 0 0 0 0 0 Pin Configuration GNDREF VDDREF X1 X2 VDD48 48MHz_0 48MHz_1 GND48 SMBCLK SMBDAT RESET_IN# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 SRCCLKT4 SRCCLKC4 GNDSRC VDDSRC SRCCLKT3 SRCCLKC3 SRCCLKT2 SRCCLKC2 VDDSRC GNDSRC ATIGCLKT3 ATIGCLKC3 *CLKREQB# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ICS 951462 Recommended Application: ATI RS/RD690 systems using AMD K8 processors & SB600 Southbridge 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FS0/REF0 FS1/REF1 FS2/REF2 PD** VDDHTT HTTCLK0 GNDHTT *CLKREQA# CPUCLK8T0 CPUCLK8C0 VDDCPU GNDCPU CPUCLK8T1 CPUCLK8C1 VDDA GNDA IREF SRCCLKT0 SRCCLKC0 GNDSRC VDDSRC SRCCLKT1 SRCCLKC1 ATIGCLKT0 ATIGCLKC0 VDDATIG GNDATIG ATIGCLKT1 ATIGCLKC1 ATIGCLKT2 ATIGCLKC2 *CLKREQC# 64-TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Power Groups Pin Number VDD 5 GND 8 14,23,28,44 15,22,29,45 Description USB_48 outputs SRCCLK outputs 39 38 50 49 Analog, PLL 54 53 CPUCLK8 differential outputs 60 58 HTTCLK output 2 1 REF outputs 1094J—03/16/09 ATIGCLK differential outputs *Other names and brands may be claimed as the property of others. ICS951462 Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME TYPE 1 2 3 4 5 6 7 8 9 10 GNDREF VDDREF X1 X2 VDD48 48MHz_0 48MHz_1 GND48 SMBCLK SMBDAT PWR PWR IN OUT PWR OUT OUT PWR IN I/O 11 RESET_IN# IN 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 SRCCLKT4 SRCCLKC4 GNDSRC VDDSRC SRCCLKT3 SRCCLKC3 SRCCLKT2 SRCCLKC2 VDDSRC GNDSRC ATIGCLKT3 ATIGCLKC3 OUT OUT PWR PWR OUT OUT OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT 32 *CLKREQB# IN DESCRIPTION Ground pin for the REF outputs. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48MHz clock output. 48MHz clock output. Ground pin for the 48MHz outputs Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant Real time active low input. When active, SMBus is reset to power up default. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs True clock of differential ATIGCLK clock pair. Complementary clock of differential ATIGCLK clock pair. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated 1094J—03/16/09 2 ICS951462 Integrated Circuit Systems, Inc. Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Complementary clock of differential ATIGCLK clock pair. True clock of differential ATIGCLK clock pair. Complementary clock of differential ATIGCLK clock pair. True clock of differential ATIGCLK clock pair. Ground for ATIG clocks Power supply ATIG clocks, nominal 3.3V Complementary clock of differential ATIGCLK clock pair. True clock of differential ATIGCLK clock pair. Complement clock of differential push-pull SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. 33 *CLKREQC# IN 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ATIGCLKC2 ATIGCLKT2 ATIGCLKC1 ATIGCLKT1 GNDATIG VDDATIG ATIGCLKC0 ATIGCLKT0 SRCCLKC1 SRCCLKT1 VDDSRC GNDSRC SRCCLKC0 SRCCLKT0 OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT 48 IREF OUT 49 50 51 52 53 54 55 56 GNDA VDDA CPUCLK8C1 CPUCLK8T1 GNDCPU VDDCPU CPUCLK8C0 CPUCLK8T0 PWR PWR OUT OUT PWR PWR OUT OUT 57 *CLKREQA# IN 58 59 60 GNDHTT HTTCLK0 VDDHTT 61 PD** IN Asynchronous active high input pin used to power down the device. The internal clocks are disabled and the VCO is stopped. 62 63 64 FS2/REF2 FS1/REF1 FS0/REF0 I/O I/O I/O Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. PWR OUT PWR This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Ground pin for the HTT outputs 3.3V Hyper Transport output Supply for HTT clocks, nominal 3.3V. 1094J—03/16/09 3 ICS951462 Integrated Circuit Systems, Inc. General Description The ICS951462 is a main clock synthesizer chip that provides all clocks required for ATI RS/RD690-based systems. An SMBus interface allows full control of the device. Block Diagram REF(2:0) X1 X2 Xtal Osc. 48MHz(1:0) Fixed PLL HTTCLK0 SRCCLK(7:0) FS(2:0) CLKREQA# CLKREQB# CLKREQC# RESET_IN# SMBDAT SMBCLK Control Logic Programmable Spread PLLs Programmable Dividers CPUCLK8(1:0) ATIGCLK(3:0) IREF 1094J—03/16/09 4 ICS951462 Integrated Circuit Systems, Inc. Table1: CPU and HTT Frequency Selection Table Byte 0 Bit4 Bit3 Bit2 Bit1 Bit0 CPUCLK HTT Spread Overclock (2:0) (MHz) % % CPU CPU CPU CPU CPU (MHz) SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hi-Z X/2 230.00 240.00 100.00 133.33 166.67 200.00 250.00 260.00 270.00 280.00 102.00 136.00 170.00 204.00 210.00 220.00 230.00 240.00 100.00 133.33 166.67 200.00 250.00 260.00 270.00 280.00 102.00 136.00 170.00 204.00 None None None None None None None None None None None None None None None None -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% Hi-Z X/3 76.67 80.00 66.67 66.67 66.67 66.67 83.33 86.67 90.00 93.33 68.00 68.00 68.00 68.00 70.00 73.33 76.67 80.00 66.67 66.67 66.67 66.67 83.33 86.67 90.00 93.33 68.00 68.00 68.00 68.00 1094J—03/16/09 5 15% 20% 0% 25% 30% 35% 40% 2% 5% 10% 15% 20% 0% 25% 30% 35% 40% 2% ICS951462 Integrated Circuit Systems, Inc. Table2: SRC Frequency Selection Table Byte 0 Byte 5 Bit 5 Bit3 Bit2 Bit1 Bit0 SRC(7:0) SRC SRC SRC SRC SRC (MHz) SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 100.00 0 0 0 0 1 101.00 0 0 0 1 0 102.00 0 0 0 1 1 103.00 0 0 1 0 0 104.00 0 0 1 0 1 105.00 0 0 1 1 0 106.00 0 0 1 1 1 107.00 0 1 0 0 0 100.00 0 1 0 0 1 101.00 0 1 0 1 0 102.00 0 1 0 1 1 103.00 0 1 1 0 0 104.00 0 1 1 0 1 105.00 0 1 1 1 0 106.00 0 1 1 1 1 107.00 1 0 0 0 0 100.00 1 0 0 0 1 101.00 1 0 0 1 0 102.00 1 0 0 1 1 103.00 1 0 1 0 0 104.00 1 0 1 0 1 105.00 1 0 1 1 0 106.00 1 0 1 1 1 107.00 1 1 0 0 0 100.00 1 1 0 0 1 101.00 1 1 0 1 0 102.00 1 1 0 1 1 103.00 1 1 1 0 0 104.00 1 1 1 0 1 105.00 1 1 1 1 0 106.00 1 1 1 1 1 107.00 SRC Spread OverClock % % 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% 1094J—03/16/09 6 ICS951462 Integrated Circuit Systems, Inc. Table3: ATIG Frequency Selection Table Byte 9 Byte 0 ATIG Bit 6 Bit3 Bit2 Bit1 Bit0 ATIG(2:0) Spread OverClock % ATIG ATIG ATIG ATIG ATIG (MHz) % SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% 1094J—03/16/09 7 ICS951462 Integrated Circuit Systems, Inc. Divider (1:0) Table 4: CPU Divider Ratios B19b(7:4) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (1:0) Table 5: HTT Divider Ratios B20b(3:0) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (1:0) Table 6: ATIG Divider Ratios B19b(3:0) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (3:2) 2 3 5 15 Div 01 0100 0101 0110 0111 Address 8 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 120 Div 4 3 5 15 Div Divider (3:2) 01 10 0100 8 1000 0101 6 1001 0110 10 1010 0111 30 1011 Address Address 16 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 32 24 40 120 Div 2 3 5 7 Div Divider (3:2) 01 10 0100 4 1000 0101 6 1001 0110 10 1010 0111 14 1011 Address Address 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 56 Div 1094J—03/16/09 8 4 6 10 30 10 1000 1001 1010 1011 Address ICS951462 Integrated Circuit Systems, Inc. General SMBus serial interface information for the ICS951462 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 1094J—03/16/09 9 Not acknowledge stoP bit ICS951462 Integrated Circuit Systems, Inc. SMBus Table: Spread Spectrum Enable and CPU Frequency Select Register Byte 0 Pin # Name Control Function Type Latched Input or SMBus RW FS Source Bit 7 Frequency Select ATIG SS_EN ATIG Spread Spectrum Enable RW Bit 6 SRC SS_EN SRC Spread Spectrum Enable RW Bit 5 CPU SS_EN CPU Spread Spectrum Enable RW Bit 4 CPU FS3 CPU Freq Select Bit 3 RW Bit 3 CPU FS2 CPU Freq Select Bit 2 RW Bit 2 CPU FS1 CPU Freq Select Bit 1 RW Bit 1 CPU FS0 CPU Freq Select Bit 0 RW Bit 0 Note: Each Spread Spectrum Enable bit is independent from the other. Bit(6:4) must all set to "1" in order to enable spread for CPU, SRC and ATIG clocks. SMBus Table: Output Control Register Pin # Name Byte 1 7 48MHz_1 Bit 7 6 48MHz_0 Bit 6 62 REF2 Bit 5 63 REF1 Bit 4 64 REF0 Bit 3 59 HTTCLK0 Bit 2 52,51 CPUCLK1 Bit 1 56,55 CPUCLK0 Bit 0 0 Latched Inputs Disable Disable Disable 1 PWD SMBus 0 Enable Enable Enable 0 0 0 0 Latch Latch Latch See Table 1: CPU Frequency Selection Table Control Function 48MHz_1 Output Enable 48MHz_0 Output Enable REF2 Output Enable REF1 Output Enable REF0 Output Enable HTTCLK0 Output Enable CPUCLK1 Output Enable CPUCLK0 Output Enable Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 SMBus Table: ATIGCLK and CLKREQB# Output Control Register Byte 2 Pin # Name Control Function 30,31 ATIGCLK3 ATIGCLK3 Output Enable Bit 7 35,34 ATIGCLK2 ATIGCLK2 Output Enable Bit 6 37,36 ATIGCLK1 ATIGCLK1 Output Enable Bit 5 41,40 ATIGCLK0 ATIGCLK0 Output Enable Bit 4 Type RW RW RW RW 0 Disable Disable Disable Disable Does not control Does not control Does not control Does not control 1 Enable Enable Enable Enable PWD 1 1 1 1 Controls 0 Controls 0 Controls 0 Controls 0 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Bit 3 20,21 REQBSRC4 CLKREQB# Controls SRC4 RW Bit 2 24,25 REQBSRC3 CLKREQB# Controls SRC3 RW Bit 1 26,27 REQBSRC2 CLKREQB# Controls SRC2 RW Bit 0 30,31 REQBATIG3 CLKREQB# Controls ATIG3 RW SMBus Table: SRCCLK Output Control Register Byte 3 Pin # Name Control Function 12,13 SRCCLK7 Bit 7 16,17 SRCCLK6 Bit 6 18,19 SRCCLK5 Bit 5 Master Output control. Enables 20,21 SRCCLK4 Bit 4 or disables output, regardless of 24,25 SRCCLK3 Bit 3 CLKREQ# inputs. 26,27 SRCCLK2 Bit 2 43,42 SRCCLK1 Bit 1 47,46 SRCCLK0 Bit 0 1094J—03/16/09 10 Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable ICS951462 Integrated Circuit Systems, Inc. SMBus Table: CLKREQA# and CLKREQC# Output Control Register Byte 4 Pin # Name Control Function Type Bit 7 12,13 REQASRC7 CLKREQA# Controls SRC7 RW Bit 6 16,17 REQASRC6 CLKREQA# Controls SRC6 RW Bit 5 18,19 REQASRC5 CLKREQA# Controls SRC5 RW Bit 4 43,42 REQCSRC1 CLKREQC# Controls SRC1 RW Bit 3 35,34 REQCATIG2 CLKREQC# Controls ATIG2 RW Bit 2 37,36 REQCATIG1 CLKREQC# Controls ATIG1 RW Bit 1 41,40 REQCATIG0 CLKREQC# Controls ATIG0 RW Bit 0 47,46 REQCSRC0 CLKREQC# Controls SRC0 RW SMBus Table: CPU Stop Control and SRC Frequency Select Register Byte 5 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 SRC, Differential Output Disable Hi-Z or Driven when disable Bit 4 ATIG Mode SRC FS3 SRC Freq Select Bit 3 Bit 3 Bit 2 Bit 1 Bit 0 - SRC FS2 SRC FS1 SRC FS0 SMBus Table: Device ID Register Byte 6 Pin # Name Device ID7 (MSB) Bit 7 Device ID6 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 (LSB) Bit 0 SMBus Table: Revision and Vendor ID Register Byte 7 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 0 Does not control Does not control Does not control Does not control Does not control Does not control Does not control Does not control 1 PWD Controls 0 Controls 0 Controls 0 Controls 0 Controls 0 Controls 0 Controls 0 Controls 0 Type 0 1 PWD 0 0 0 RW Driven Hi-Z 0 RW See Table 2: SRC Frequency Selection Table 0 SRC Freq Select Bit 2 SRC Freq Select Bit 1 SRC Freq Select Bit 0 RW RW RW Control Function Type R R R R R R R R 0 - 1 - PWD 0 1 1 0 0 0 1 0 Type R R R R R R R R 0 - 1 - PWD 0 0 0 1 0 0 0 1 DEVICE ID Control Function REVISION ID VENDOR ID 1094J—03/16/09 11 0 0 0 ICS951462 Integrated Circuit Systems, Inc. SMBus Table: Byte Count Register Byte 8 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Byte Count Programming b(7:0) Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 Writing to this register will 0 congiure how many bytes will be read back, default is 9 1 bytes. 0 0 1 SMBus Table: REF2, 48MHz Output Strength Control and ATIG Frequency Select Register Byte 9 Pin # Name Control Function Type 0 1 62 REF2Str REF2 Strength Control RW 1X 2X Bit 7 7 48MHz_1Str 48MHz_1 Strength Control RW 1X 2X Bit 6 6 48MHz_0Str 48MHz_0 Strength Control RW 1X 2X Bit 5 Reserved Bit 4 ATIG FS3 ATIG Freq Select Bit 3 RW Bit 3 ATIG FS2 ATIG Freq Select Bit 2 RW See Table 3: ATIG Bit 2 Frequency Selection Table ATIG FS1 ATIG Freq Select Bit 1 RW Bit 1 ATIG FS0 ATIG Freq Select Bit 0 RW Bit 0 PWD 1 1 1 0 0 0 0 0 SMBus Table: PLLs M/N Programming Enable and REF1, REF0 Output Strength Control Register Byte 10 Pin # Name Control Function Type 0 M/N_EN PLLs M/N Programming Enable RW Disable Bit 7 63 REF1Str REF1 Strength Control RW 1X Bit 6 64 REF0Str REF0 Strength Control RW 1X Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 PWD 0 1 1 0 0 0 0 0 1 Enable 2X 2X SMBus Table: CPU PLL VCO Frequency Control Register Byte 11 Pin # Name Control Function N Div8 N Divider Prog bit 8 Bit 7 N Div 9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 Type RW RW RW RW RW RW RW RW PWD X The decimal representation of X M and N Divier in Byte 11 and X 12 will configure the VCO X frequency. Default at power up = latch-in or Byte 0 Rom X table. VCO Frequency = X 14.318 x [NDiv(9:0)+8] / X [MDiv(5:0)+2] X SMBus Table: CPU PLL VCO Frequency Control Register Byte 12 Pin # Name Control Function N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 1094J—03/16/09 12 0 1 0 1 PWD X X X X X X X X ICS951462 Integrated Circuit Systems, Inc. SMBus Table: CPU PLL Spread Spectrum Control Register Byte 13 Pin # Name Control Function SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 Spread Spectrum Programming SSP4 Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 SMBus Table: CPU PLL Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 Type RW RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW SMBus Table: ATIG PLL VCO Frequency Control Register Byte 15 Pin # Name Control Function N Div8 N Divider Prog bit 8 Bit 7 N Div9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 Type RW RW RW RW RW RW RW RW SMBus Table: ATIG PLL VCO Frequency Control Register Byte 16 Pin # Name Control Function N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 Type RW RW RW RW RW RW RW RW SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 17 Pin # Name Control Function SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 SSP4 Spread Spectrum Programming Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 Type RW RW RW RW RW RW RW RW 1094J—03/16/09 13 0 1 PWD X X These Spread Spectrum bits in Byte 13 and 14 will program X X the spread pecentage. It is recommended to use ICS X Spread % table for spread X programming. X X 0 1 0 1 0 1 0 1 PWD 0 X These Spread Spectrum bits X in Byte 13 and 14 will program X the spread pecentage. It is X recommended to use ICS X Spread % table for spread X programming. X PWD X The decimal representation of X M and N Divier in Byte 17 and X 18 will configure the VCO X frequency. Default at power X up = Byte 0 Rom table. VCO X Frequency = 14.318 x X [NDiv(9:0)+8] / [MDiv(5:0)+2] X PWD X The decimal representation of X M and N Divier in Byte 17 and X 18 will configure the VCO X frequency. Default at power X up = Byte 0 Rom table. VCO X Frequency = 14.318 x X [NDiv(9:0)+8] / [MDiv(5:0)+2] X PWD X X These Spread Spectrum bits in Byte 19 and 20 will program X X the spread pecentage. It is recommended to use ICS X Spread % table for spread X programming. X X ICS951462 Integrated Circuit Systems, Inc. SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 18 Pin # Name Control Function Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 SMBus Table: CPU and ATIG Divider Ratio Programming Bits Select Register Byte 19 Pin # Name Control Function CPU_Div3 Bit 7 CPU_Div2 CPU_Divider Ratio Bit 6 Programming Bits CPU_Div1 Bit 5 CPU_Div0 Bit 4 ATIG_Div3 Bit 3 ATIG_Div2 ATIG_Divider Ratio Bit 2 Programming Bits ATIG_Div1 Bit 1 ATIG_Div0 Bit 0 SMBus Table: HTT Divider Ratio Programming Bits Select Register Byte 20 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 HTT_Div3 Bit 3 HTT_Div2 HTT_Divider Ratio Bit 2 Programming Bits HTT_Div1 Bit 1 HTT_Div0 Bit 0 1094J—03/16/09 14 Type RW RW RW RW RW RW RW Type RW RW RW RW RW RW RW RW Type RW RW RW RW 0 1 PWD 0 X These Spread Spectrum bits X in Byte 19 and 20 will program X the spread pecentage. It is X recommended to use ICS X Spread % table for spread X programming. X 0 1 See Table 4: CPU Divider Ratios See Table 5: ATIG Divider Ratios 0 1 See Table 6: HTT Divider Ratios PWD X X X X X X X X PWD 0 0 0 0 X X X X ICS951462 Integrated Circuit Systems, Inc. Absolute Maximum Rating (Above which useful life may be impaired) 1 PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage VDD_A - 3.3V Logic Input Supply Voltage VDD_In - MIN TYP GND 0.5 MAX UNITS Notes VDD + 0.5V V 1 V 1 VDD + 0.5V ° Storage Temperature Ts - -65 150 C 1 Ambient Operating Temp Tambient - 0 70 °C 1 Max Junction Temp TJ VDD MAX, 70°C 130 °C 1 Case Temperature Tcase - 115 °C 1 Input ESD protection HBM ESD prot - V 1 2000 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* Input High Voltage VIH 3.3 V +/-5% Input Low Voltage VIL 3.3 V +/-5% Input High Current IIH VIN = VDD -5 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current MIN VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors TYP MAX UNITS Notes 2 VDD + 0.3 V 1 VSS - 0.3 0.8 V 1 5 uA 1 -5 uA 1 -200 uA 1 VIH_FS 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VIL_FS 3.3 V +/-5% VSS - 0.3 0.35 V 1 IDD3.3OP Powerdown Current IDD3.3PD Input Frequency Fi Pin Inductance Lpin all outputs driven 400 mA 1 all diff pairs driven 70 mA 1 all differential pairs tri-stated 12 mA 1 MHz 2 VDD = 3.3 V 14.31818 7 nH 1 5 pF 1 CIN Logic Inputs COUT Output pin capacitance 6 pF 1 CINX 5 pF 1 1.8 ms 1 33 kHz 1 300 us 1 Tfall_PD X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of Trise_PD PD rise time of Input Capacitance Clk Stabilization T STAB Modulation Frequency Tdrive_PD SMBus Voltage 30 2.7 VDD Low-level Output Voltage VOL @ IPULLUP Current sinking at IPULLUP VOL = 0.4 V SMBCLK/SMBDAT (Max VIL - 0.15) to T RI2C Clock/Data Rise Time (Min VIH + 0.15) (Min VIH + 0.15) to SMBCLK/SMBDAT TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 5 ns 1 5 ns 1 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 4 1Guaranteed by design and characterization, not 100% tested in production. frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2 Input 1094J—03/16/09 15 ICS951462 Integrated Circuit Systems, Inc. Electrical Characteristics - K8 Push Pull Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load PARAMETER SYMBOL CONDITIONS MIN Rising Edge Rate δV/δt 2 Falling Edge Rate δV/δt Measured at the AMD64 processor's test load. 0 V +/- 400 mV (differential measurement) Differential Voltage Change in VDIFF_DC Magnitude VDIFF Common Mode Voltage Change in Common Mode Voltage ∆VDIFF VCM ∆VCM Jitter, Cycle to cycle tjcyc-cyc Jitter, Accumulated tja Duty Cycle dt3 Output Impedance RON Group Skew tsrc-skew 2 0.4 Measured at the AMD64 processor's test load. (singleended measurement) TYP 1.25 -150 1.05 1.25 -200 Measurement from differential wavefrom. Maximum difference of cycle time between 2 adjacent cycles. Measured using the JIT2 software package with a Tek 7404 scope. TIE (Time Interval Error) measurement technique: Sample resolution = 50 ps, Sample Duration = 10 µs Measurement from differential wavefrom Average value during switching transition. Used for determining series termination value. Measurement from differential wavefrom 0 10 V/ns 1 10 V/ns 1 2.3 V 1 150 mV 1 1.45 V 1 200 mV 1 85 ps 1 1000 45 53 % 1 55 Ω 1 50 ps 1 15 Guaranteed by design and characterization, not 100% tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz 3 Spread Spectrum is off 16 UNITS NOTES -1000 1 1094J—03/16/09 50 MAX 35 1,2,3 ICS951462 Integrated Circuit Systems, Inc. Electrical Characteristics - HTTCLK Clock PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread PCI33 Clock period Tperiod MAX UNITS Notes -300 300 ppm 1,2 29.9910 30.0090 ns 2 29.9910 30.1598 ns 2 66.67MHz output nominal 14.9955 15.0045 ns 2 14.9955 15.0799 ns 2 HTT66 Clock period Tperiod Output High Voltage VOH 66.67MHz output spread IOH = -1 mA Output Low Voltage VOL IOL = 1 mA Output High Current IOH V OH @MIN MIN TYP 2.4 0.55 = 1.0 V -33 VOH@ MAX = 3.135 V -33 VOL @ MIN = 1.95 V 30 V 1 V 1 mA 1 mA 1 mA 1 38 mA 1 1 Output Low Current IOL Edge Rate δV/δt Rising edge rate 1 4 V/ns Edge Rate δV/δt tr1 Falling edge rate VOL = 0.4 V, VOH = 2.4 V 1 4 V/ns 1 0.5 2 ns 1 1 Rise Time VOL @ MAX = 0.4 V Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 180 ps 1 *TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz Electrical Characteristics - SRC/ATIG 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High SYMBOL CONDITIONS* MIN Zo VO = Vx 3000 VHigh 660 Voltage Low VLow Statistical measurement on single ended signal Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm Measurement on single ended signal using absolute value. TYP -150 MAX UNITS Notes Ω 1 mV 1,3 150 mV 1,3 1150 mV 1 mV 1 550 mV 1 140 mV 1 850 -300 250 Variation of crossing over all edges see Tperiod min-max values -300 300 ppm 1,2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 ns 1,2 1 Average period Tperiod Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-tf 125 ps 1 Duty Cycle dt3 55 % 1 Skew tsk3 100 ps 1 Jitter, Cycle to cycle tjcyc-cyc VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom VT = 50% Measurement from differential wavefrom 125 ps 1 45 *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS =33.2Ω, RP=49.9Ω, IREF = 475Ω 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 1094J—03/16/09 17 ICS951462 Integrated Circuit Systems, Inc. Electrical Characteristics - USB - 48MHz PARAMETER SYMBOL CONDITIONS* MIN Long Accuracy ppm see Tperiod min-max values -100 TYP MAX 100 UNITS NOTES ppm 1,2 Clock period T period 48.00MHz output nominal 20.8229 20.8344 ns 2 2 Clock Low Time T low Measure from < 0.6V 9.3750 11.4580 ns Clock High Time T high Measure from > 2.0V 9.3750 11.4580 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL Output High Current Output Low Current IOH IOL IOL = 1 mA 0.55 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 30 VOL @ MAX = 0.4 V V 1 mA 1 mA 1 mA 1 38 mA 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 0.5 1.5 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 0.5 1.5 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 100 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 130 ps 1,2 MAX UNITS Notes 300 ppm 1,2 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN Long Accuracy ppm see Tperiod min-max values -300 TYP Clock period T period 14.318MHz output nominal 69.8270 69.8550 ns 2 Clock Low Time T low Measure from < 0.6V 30.9290 37.9130 ns 2 37.9130 ns 2 V 1 0.4 V 1 -29 -23 mA 1 29 27 mA 1 1.5 ns 1 1 Clock High Time T high Measure from > 2.0V 30.9290 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1.5 ns Skew tsk1 VT = 1.5 V 100 ps 1 Duty Cycle dt1 VT = 1.5 V 53 56 % 1 Jitter tjcyc-cyc VT = 1.5 V 200 300 ps 1 VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 44 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 1094J—03/16/09 18 ICS951462 Integrated Circuit Systems, Inc. RESET_IN# - Assertion (transition from '1' to '0') Asserting RESET_IN pin stops all the outputs including CPU, SRC, ATIG, PCI and USB with the REF[2:0] running. The pin is a Schmitt trigger input with debouncing. After it is triggered, REF clocks will wait for two clock cycle to ensure the RESET_IN is asserted. Then, it will take 3uS for the clocks to stop without glitches. The clock chip will be power down and re-power up, and SMBus will be reloaded. It will take no more than 2.5mS for the clocks to come out with correct frequencies and no glitches. ** Deassertion of RESET_IN# (transition from '0' to '1') has NO effect on the clocks. 2 clock cycles 2.5mS max 3 uS max RESET_IN# REF [2:0] *CLKS 1094J—03/16/09 19 ICS951462 Integrated Circuit Systems, Inc. SRC Routing Information SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 2, 3 2, 3 2, 3 2, 3 2, 3 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max Unit inch 2 1.8 min to 14.4 max inch 2 Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max Unit inch 3 0.225 min to 12.6 max inch 3 L1 Figure L2 L4 Rs L1’ L4’ L2’ Rs Fig.1 Figure Rt HSCL Output Buffer Rt L3’ L1 PCI Ex REF_CLK Test Load L3 L2 L4 Rs L1’ Fig.2 L4’ L2’ Rs Rt HSCL Output Buffer L3’ L1 Rt PCI Ex Board Down Device REF_CLK Input L3 L2 L4 Rs L4’ L1’ L2’ Rs Fig.3 Rt HSCL Output Buffer L3’ 1094J—03/16/09 20 Rt L3 PCI Ex Add In Board REF_CLK Input ICS951462 Integrated Circuit Systems, Inc. Shared Pin Operation Input/Output Pins The I/O pins designated by (input/output) on the ICS951462 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 1094J—03/16/09 21 ICS951462 Integrated Circuit Systems, Inc. c N L E1 INDEX AREA SYMBOL A A1 A2 b c D E E1 e L N α aaa E 1 2 a D A A2 VARIATIONS A1 N -Ce b 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° -0.10 -.004 SEATING PLANE aaa C 64 D mm. MIN 16.90 D (inch) MAX 17.10 MIN .665 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information 951462yGLFT Example: XXXX y G LF T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) 1094J—03/16/09 22 MAX .673 ICS951462 Integrated Circuit Systems, Inc. Revision History Rev. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Issue Date Description 4/7/2005 Initial Release 4/15/2005 Added Timing Diagram Page # 19 1. SMBus Byte 5 bits[6:5] are changed from CPU_STOP Enable to RESERVED. 2. Updated LF Ordering Information from "Annealed Lead Free" to "RoHS Compliant". Updated Timing Diagram. 1. Updated all description: Changed RS680 to RS580. 2. Updated Pin Description: Pin 11 and 57. 3. Updated Block Diagram: Took out CPU_STOP#. 4. Updated Electrical Characteristics: i. Input/Supply/Common Output Parameters: Took out Operating Supply Current. ii. USB: Updated Rise and Fall Time. iii. REF: Updated Rise and Fall Time. 9/9/2005 5. Updated LF Ordering Information. 9/22/2005 1. Updated Output Features. 2/8/2006 Updated pin description pin 30/31 and 42/43 6/6/2005 6/8/2005 A B C D 3/22/2006 5/26/2006 7/25/2006 9/15/2006 E F G H I J 12/5/2006 12/12/2006 1/30/2007 3/5/2007 5/23/2007 3/16/2009 11, 22 19 1, 2,3, 4, 15,18, 22 1 2-3 1. Updated REF and USB cycle to cycle jitter specs to tentative SB600 requirements. 2. Updated CPU skew and jitter numbers 3. Updated SRC and ATIG skew and jitter numbers 4. Move Data sheet to Preliminary 17, 18 1. Updated REF and USB rise/fall time specs to tentative SB600 requirements. 18 Updated Reference to CLKREQB# on Byte 4 to CLKREQA#. 11 Updated Recommended Application. 1, 4 1. Updated Table 3 description. 7, 2. Updated SMBus Pin# association. 10-11 1. Updated REF duty cycle to 56/44%. 18 1. Updated REF Rise/Fall time spec 18 1. Updated pinout and pin description for pin #61 1, 3 Added Max Junction Temperature. 15 Changed Cycle-to-cycle Jitter spec from 85 to 125ps. 17 1094J—03/16/09 23 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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