952906AGLF

ICS952906A Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for Next Gen P4™ processor Recommended Application: VIA VN800/CN700/P4M800 style chipset for P4 processor Output Features: • 3 - 0.7V current-mode differential CPU pairs • 10 - PCI, 3 free running, 33MHz • 2 - REF, 14.318MHz • 3 - 3V66, 66.66MHz • 1 - 48MHz • 1 - 24/48MHz • 2 - 25MHz @ 2.5V Features/Benefits: • Programmable output frequency. • Programmable asynchronous 3V66&PCI frequency. • Programmable output divider ratios. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watch dog safe frequency. • Support I2C Index read/write and block read/write operations. • Uses external 14.318MHz reference input. Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 125ps • 3V66 outputs cycle-cycle jitter < 250ps • PCI outputs cycle-cycle jitter < 250ps • CPU - AGP skew < +/- 350ps • AGP-PCI skew between 1~3.5ns Bit4 Bit3 Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 MHz 100.00 0 0 0 0 0 200.00 0 0 0 0 1 133.33 0 0 0 1 0 166.67 0 0 0 1 1 0 0 1 0 0 200.00 0 0 1 0 1 400.00 0 0 1 1 0 266.67 0 0 1 1 1 333.33 100.99 0 1 0 0 0 201.98 0 1 0 0 1 134.65 0 1 0 1 0 168.31 0 1 0 1 1 1 115.00 0 1 0 0 230.00 0 1 1 0 1 153.33 0 1 1 1 0 191.67 0 1 1 1 1 1 100.00 0 0 0 0 200.00 1 0 0 0 1 133.33 1 0 0 1 0 166.67 1 0 0 1 1 0 1 0 0 200.00 1 400.00 1 0 1 0 1 266.67 1 0 1 1 0 333.33 1 0 1 1 1 105.00 1 1 0 0 0 210.00 1 1 0 0 1 140.00 1 1 0 1 0 175.00 1 1 0 1 1 1 110.00 1 1 0 0 220.00 1 1 1 0 1 146.66 1 1 1 1 0 1 1 1 1 1 183.34 1236A—08/06/07 Pin Configuration AGP MHz 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 67.33 67.33 67.33 67.32 76.67 76.67 76.66 76.67 66.66 66.66 66.66 71.43 66.66 66.66 66.66 66.66 69.99 69.99 69.99 69.99 73.33 73.33 73.33 73.33 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.66 33.66 33.66 33.66 38.33 38.33 38.33 38.33 33.33 33.33 33.33 35.71 33.33 33.33 33.33 33.33 35.00 35.00 35.00 35.00 36.66 36.66 36.66 36.66 *FS1/REF0 **FS0/REF1 VDDREF X1 X2 GND **FS2/PCICLK_F0 **FS4/PCICLK_F1 PCICLK_F2 VDDPCI GND **MODE/PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI GND PCICLK5 PCICLK6 **FS3/48MHz **Sel24_48#/24_48MHz GND VDD48 * This 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS952906 Functionality 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GND IREF CPUCLKT_ITP/(PCI_STOP#) CPUCLKC_ITP/(CPU_STOP#) GND CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GND 25Mhz_0 25Mhz_1 VDD2.5 VttPWR_GD/PD# SDATA SCLK Reset# 3V66_0 GND VDD3V66 3V66_1 3V66_2 pin have 120K pull-up to VDD ** This pin have 120K pull-down to GND 48-pin SSOP & TSSOP Integrated Circuit Systems, Inc. ICS952906A Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 PIN NAME *FS1/REF0 **FS0/REF1 VDDREF X1 X2 GND **FS2/PCICLK_F0 **FS4/PCICLK_F1 PCICLK_F2 VDDPCI GND PIN TYPE DESCRIPTION I/O Frequency select latch input pin / 14.318 MHz reference clock. I/O Frequency select latch input pin / 14.318 MHz reference clock. PWR Ref, XTAL power supply, nominal 3.3V IN Crystal input, Nominally 14.318MHz. OUT Crystal output, Nominally 14.318MHz PWR Ground pin. I/O Frequency select latch input pin / 3.3V PCI free running clock output. I/O Frequency select latch input pin / 3.3V PCI free running clock output. OUT Free running PCI clock not affected by PCI_STOP# . PWR Power supply for PCI clocks, nominal 3.3V PWR Ground pin. Function select latch input pin, 0=Desktop Mode (pin 44/45 are outputs), 1=Mobile Mode (pin44/45 are STOP I/O inputs) / PCI clock output. OUT PCI clock output. OUT PCI clock output. OUT PCI clock output. OUT PCI clock output. PWR Power supply for PCI clocks, nominal 3.3V PWR Ground pin. OUT PCI clock output. OUT PCI clock output. I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V 12 **MODE/PCICLK0 13 14 15 16 17 18 19 20 21 PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI GND PCICLK5 PCICLK6 **FS3/48MHz 22 **Sel24_48#/24_48MHz I/O Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz. 23 24 25 26 27 28 29 GND VDD48 3V66_2 3V66_1 VDD3V66 GND 3V66_0 PWR PWR OUT OUT PWR PWR OUT 30 Reset# OUT 31 32 SCLK SDATA IN I/O 33 VttPWR_GD/PD# IN 34 35 36 37 VDD2.5 25Mhz_1 25Mhz_0 GND PWR OUT OUT PWR 38 CPUCLKC0 OUT 39 CPUCLKT0 OUT 40 VDDCPU PWR 41 CPUCLKC1 OUT 42 CPUCLKT1 OUT 43 GND PWR 44 CPUCLKC_ITP/(CPU_STOP#) I/O Ground pin. Power pin for the 48MHz output.3.3V 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Power pin for the 3.3V 66MHz clocks. Ground pin. 3.3V 66.66MHz clock output Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the device into a low power state. Power supply, nominal 2.5V 25MHz clock output, 2.5V 25MHz clock output, 2.5V Ground pin. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. / Stops all CPUCLK besides the free running clocks 45 CPUCLKT_ITP/(PCI_STOP#) I/O 46 IREF OUT 47 48 GND VDDA PWR PWR True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. / Stops all PCICLK besides the free running clocks This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. 3.3V power for the PLL core. 1236A—08/06/07 2 Integrated Circuit Systems, Inc. ICS952906A General Description ICS952906A is a 48 pin clock chip for VIA VN800/CN700/P4M800 style chipsets. When used with a fanout DDR buffer, such as the 93788, it provides all the necessary clock signals for such a system. The ICS952906A is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. Block Diagram Frequency Dividers PLL2 48MHz 24_48MHz X1 X2 XTAL REF (1:0) CPUCLKT (1:0)/ITP CPU_STOP# CPUCLKC (1:0)/ITP PCI_STOP# FS (4:0) SCLK Sel24_48# Control Logic Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic 25MHz (1:0) 3V66 (2:0) PCICLK (6:0) SDATA PCICLK_F (2:0) MODE RESET# VTTPWRGD#/PD# I REF Power Groups Pin Number VDD GND 3 6 10, 17 11, 18 24 23 27 28 34 37 40 43 48 47 Description REF, Xtal PCICLK outputs 48MHz Fix, Fix Digital, Fix analog 3V66 outputs 2.5V for 25MHz outputs CPU outputs CPU Analog, CPU digital 1236A—08/06/07 3 Integrated Circuit Systems, Inc. ICS952906A General I2C serial interface information for the ICS952906A How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 1236A—08/06/07 4 Not acknowledge stoP bit Integrated Circuit Systems, Inc. ICS952906A Table1: QuadRom Frequency Selection Table Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CPU AGP PCI FS4 FS3 FS2 FS1 FS0 MHz MHz MHz Spread % 0 0 0 0 0 0 0 100.00 66.67 33.33 0 to -0.5% Down 0 0 0 0 0 0 1 200.00 66.67 33.33 0 to -0.5% Down 0 0 0 0 0 1 0 133.33 66.67 33.33 0 to -0.5% Down 0 0 0 0 0 1 1 166.67 66.67 33.33 0 to -0.5% Down 0 0 0 0 1 0 0 200.00 66.67 33.33 0 to -0.5% Down 0 0 0 0 1 0 1 400.00 66.67 33.33 0 to -0.5% Down 0 0 0 0 0 0 0 0 1 1 1 1 0 1 266.67 66.67 33.33 0 to -0.5% Down 333.33 66.67 33.33 0 to -0.5% Down 0 0 0 1 0 0 0 100.99 67.33 33.66 0.25% Center 0 0 0 1 0 0 1 201.98 67.33 33.66 0.25% Center 0 0 0 0 0 0 1 1 0 0 1 1 0 1 134.65 67.33 33.66 0.25% Center 168.31 67.32 33.66 0.25% Center 0 0 0 1 1 0 0 115.00 76.67 38.33 No Spread 0 0 0 1 1 0 1 230.00 76.67 38.33 No Spread 0 0 0 0 0 0 1 1 1 1 1 1 0 1 153.33 76.66 38.33 No Spread 191.67 76.67 38.33 No Spread 0 0 1 0 0 0 0 100.00 66.66 33.33 0.25% Center 0 0 1 0 0 0 1 200.00 66.66 33.33 0.25% Center 0 0 1 0 0 1 0 133.33 66.66 33.33 0.25% Center 0 0 1 0 0 1 1 166.67 71.43 35.71 0.25% Center 0 0 1 0 1 0 0 200.00 66.66 33.33 0.25% Center 0 0 1 0 1 0 1 400.00 66.66 33.33 0.25% Center 0 0 0 0 1 1 0 0 1 1 1 1 0 1 266.67 66.66 33.33 0.25% Center 333.33 66.66 33.33 0.25% Center 0 0 1 1 0 0 0 105.00 69.99 35.00 No Spread 0 0 1 1 0 0 1 210.00 69.99 35.00 No Spread 0 0 0 0 1 1 1 1 0 0 1 1 0 1 140.00 69.99 35.00 No Spread 175.00 69.99 35.00 No Spread 0 0 1 1 1 0 0 110.00 73.33 36.66 No Spread 0 0 1 1 1 0 1 220.00 73.33 36.66 No Spread 0 0 0 0 1 1 1 1 1 1 1 1 0 1 146.66 73.33 36.66 No Spread 183.34 73.33 36.66 No Spread 1236A—08/06/07 5 Integrated Circuit Systems, Inc. ICS952906A Table1: QuadRom Frequency Selection Table (Continued) Bit6 Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 Bit3 Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 MHz 0 0 0 0 0 103.00 0 0 0 0 1 206.00 0 0 0 1 0 137.33 0 0 0 1 1 171.67 0 0 1 0 0 228.89 0 0 1 0 1 412.00 0 0 1 1 0 274.67 0 0 1 1 1 343.33 0 1 0 0 0 105.00 0 1 0 0 1 210.00 0 1 0 1 0 140.00 0 1 0 1 1 175.00 0 1 1 0 0 233.33 0 1 1 0 1 420.00 0 1 1 1 0 280.00 0 1 1 1 1 350.00 1 0 0 0 0 107.00 1 0 0 0 1 214.00 1 0 0 1 0 142.66 1 0 0 1 1 178.34 1 0 1 0 0 237.78 1 0 1 0 1 428.00 1 0 1 1 0 285.34 1 0 1 1 1 356.66 1 1 0 0 0 110.00 1 1 0 0 1 220.00 1 1 0 1 0 146.66 1 1 0 1 1 183.34 1 1 1 0 0 244.44 1 1 1 0 1 440.00 1 1 1 1 0 293.34 1 1 1 1 1 366.66 AGP PCI Spread MHz 68.66 68.66 68.66 68.66 68.66 68.66 68.66 68.66 69.99 69.99 69.99 69.99 69.99 69.99 69.99 69.99 71.33 71.33 71.33 71.33 71.33 71.33 71.33 71.33 73.33 73.33 73.33 73.33 73.33 73.33 73.33 73.33 MHz 34.33 34.33 34.33 34.33 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 35.00 35.00 35.00 35.00 35.66 35.66 35.66 35.66 35.66 35.66 35.66 35.66 36.66 36.66 36.66 36.66 36.66 36.66 36.66 36.66 % No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread 1236A—08/06/07 6 Integrated Circuit Systems, Inc. ICS952906A Table1: QuadRom Frequency Selection Table (Continued) Bit6 Bit5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit4 Bit3 Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 MHz 0 0 0 0 0 95.00 0 0 0 0 1 190.00 0 0 0 1 0 126.66 0 0 0 1 1 158.34 0 0 1 0 0 211.11 0 0 1 0 1 380.00 0 0 1 1 0 253.34 0 0 1 1 1 316.66 0 1 0 0 0 90.00 0 1 0 0 1 180.00 0 1 0 1 0 120.00 0 1 0 1 1 150.00 0 1 1 0 0 200.00 0 1 1 0 1 360.00 0 1 1 1 0 240.00 0 1 1 1 1 300.00 1 0 0 0 0 85.00 1 0 0 0 1 170.00 1 0 0 1 0 113.33 1 0 0 1 1 141.67 1 0 1 0 0 188.89 1 0 1 0 1 340.00 1 0 1 1 0 226.67 1 0 1 1 1 283.33 1 1 0 0 0 80.00 1 1 0 0 1 160.00 1 1 0 1 0 106.66 1 1 0 1 1 133.34 1 1 1 0 0 177.78 1 1 1 0 1 320.00 1 1 1 1 0 213.34 1 1 1 1 1 266.66 AGP PCI Spread MHz 63.33 63.33 63.33 63.33 63.33 63.33 63.33 63.33 59.99 59.99 59.99 59.99 59.99 59.99 59.99 59.99 56.66 56.66 56.66 56.66 56.66 56.66 56.66 56.66 53.33 53.33 53.33 53.33 53.33 53.33 53.33 53.33 MHz 31.66 31.66 31.66 31.66 31.66 31.66 31.66 31.66 30.00 30.00 30.00 30.00 30.00 30.00 30.00 30.00 28.33 28.33 28.33 28.33 28.33 28.33 28.33 28.33 26.66 26.66 26.66 26.66 26.66 26.66 26.66 26.66 % No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread 1236A—08/06/07 7 Integrated Circuit Systems, Inc. ICS952906A Table1: QuadRom Frequency Selection Table (Continued) Bit6 Bit5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 Bit3 Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 MHz 0 0 0 0 0 115.00 0 0 0 0 1 230.00 0 0 0 1 0 153.33 0 0 0 1 1 191.67 0 0 1 0 0 255.55 0 0 1 0 1 460.00 0 0 1 1 0 306.67 0 0 1 1 1 383.33 0 1 0 0 0 115.00 0 1 0 0 1 230.00 0 1 0 1 0 153.33 0 1 0 1 1 191.67 0 1 1 0 0 255.55 0 1 1 0 1 460.00 0 1 1 1 0 306.67 0 1 1 1 1 383.33 1 0 0 0 0 78.00 1 0 0 0 1 156.00 1 0 0 1 0 104.00 1 0 0 1 1 130.00 1 0 1 0 0 173.33 1 0 1 0 1 312.00 1 0 1 1 0 208.00 1 0 1 1 1 260.00 1 1 0 0 0 75.00 1 1 0 0 1 150.00 1 1 0 1 0 100.00 1 1 0 1 1 125.00 1 1 1 0 0 166.67 1 1 1 0 1 300.00 1 1 1 1 0 200.00 1 1 1 1 1 250.00 AGP PCI Spread MHz 76.66 76.66 76.66 76.66 76.66 76.66 76.66 76.66 79.99 79.99 79.99 79.99 79.99 79.99 79.99 79.99 51.99 51.99 51.99 51.99 51.99 51.99 51.99 51.99 50.00 50.00 50.00 50.00 50.00 50.00 50.00 50.00 MHz 38.33 38.33 38.33 38.33 38.33 38.33 38.33 38.33 40.00 40.00 40.00 40.00 40.00 40.00 40.00 40.00 26.00 26.00 26.00 26.00 26.00 26.00 26.00 26.00 25.00 25.00 25.00 25.00 25.00 25.00 25.00 25.00 % No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread No Spread 1236A—08/06/07 8 Integrated Circuit Systems, Inc. ICS952906A 2 I C Table: Frequency Select Register Byte 0 Pin # Name Bit 7 - FS Source Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - FS6 FS5 FS4 FS3 FS2 FS1 FS0 Control Function Frequency H/W IIC Select Freq Select Bit 6 Freq Select Bit 5 Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Type 0 1 PWD RW Latch Inputs IIC 0 RW RW RW RW RW RW RW See Table 1: QuadRom Frequency Selection Table 0 0 0 0 0 0 0 2 I C Table: Spreading and Device Behavior Control Register Byte 1 Pin # Name Control Function Spread Select 1** Spread Select 0** Spread Enable Control WD Soft Reset Enable Reserved Type 0 1 SS1 RW 00 = 0.20% 10 = 0.35% SS0 RW 01 = 0.25% Reserved SS_EN RW ON OFF WDS_EN RW ON OFF Reserved RW CPUCLKT/C_ITP, 45, 44 Disable Enable Output Control RW Bit 2 CPU1T/C, CPU0T/C CPUCLKT/C_1 Output Control RW 42,41 Disable Enable Bit 1 39, 38 Disable Enable CPUCLKT/C_0 Output Control RW Bit 0 ** Spread program m ing only applies for ROM table entries 0001000 to 0001011 and 0010000 to 0010111 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 - PWD 0 1 1 0 1 1 1 1 2 I C Table: Output Control Register Byte 2 Pin # Name Control Function Output Control Output Control Type 0 1 PWD RW RW Disable Disable Enable Enable 1 1 Bit 7 Bit 6 36 35 25MHz_0 25MHz_1 Bit 5 - CPUT Stop Mode 0: CPUT Driven during PD#; 1: Tri-stated RW Driven Hi-Z 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 26 42,41 39, 38 Reserved 3V66_1 Reserved CPUCLKT/C_1 CPUCLKT/C_0 Reserved Output Control Reserved Output Stop Control Output Stop Control RW RW RW RW RW Disable Free Run Free Run Enable Stoppable Stoppable 1 1 1 1 1 Type 0 1 PWD 2 I C Table: Output Control Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 20 19 16 15 14 13 12 Name ASEL1 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function 3V66/PCI Freq Select Output Control Output Control Output Control Output Control Output Control Output Control Output Control 1236A—08/06/07 9 RW RW RW RW RW RW RW RW See Table 5: Async AGP/PCI Freq Table Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable 0 1 1 1 1 1 1 1 Integrated Circuit Systems, Inc. ICS952906A Table 5: Asynchronous 3V66/PCI Frequency Table Byte6 Bit7 Byte3 Bit7 3V66/PCI Frequency 0 0 66.66/33.33 0 1 80.00/40.00 1 0 72.73/36.36 2 I C Table: Output Control Register Byte 4 Pin # Name Control Function Type 0 1 PWD 0=2x drive RW 2x drive normal 1 RW AGP/2 PLL3 Freq/24 0 RW RW RW RW RW RW Disable Disable Disable Disable Enable Enable Enable Enable 1 1 1 1 1 1 Type 0 1 PWD RW RW RW RW RW RW RW RW - - 0 0 0 1 X X X X Bit 7 - 48MHz_0 2x output drive Bit 6 - PCI ADIV 29 9 8 7 Reserved 3V66_0 Reserved PCICLK_F2 PCICLK_F1 PCICLK_F0 Bit Bit Bit Bit Bit Bit 5 4 3 2 1 0 PCI Async Divider Cntr Reserved Output Control Reserved Output Control Output Control Output Control 2 I C Table: Reserved Register Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit Pin # 25 - 7 6 5 4 3 2 1 0 Name Reserved Mode Sel1 Mode Sel0 3V66_2 M PLL2 Div3 M PLL2 Div2 M PLL2 Div1 M PLL2 Div0 Control Function Reserved PLL Mode Selection Bits Output Control M Divider Programming bits for Async mode 2&3 See Table 4: Mode Selection Table Disable Enable The decimal representation of M PLL2 Div (3:0) + 2 is equal to REF divider value for PLL2 Table 4: Mode Selection Table Mode IIC Control Standard Overclock Mode(I) Byte 5 bit(6:5) = 00 CPU Overclock Mode(II) Byte 5 bit(6:5) = 01 Graphic Overclock Mode(III) Byte 5 bit(6:5) = 10 25MHz From? PLL3 PLL3 PLL1 3V66/PCI From? Spreading PLL1 (Needed to be align w/ CPU) PLL3 PLL3 CPU/3V66/PCI have spread Only CPU clocks have spread. Only CPU clocks have spread. 2 I C Table: Vendor & Revision ID Register Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name ASEL0 N PLL2 Div6 N PLL2 Div5 N PLL2 Div4 N PLL2 Div3 N PLL2 Div2 N PLL2 Div1 N PLL2 Div0 Control Function 3V66/PCI Freq Select N Divider Programming bits for Async mode 2&3 1236A—08/06/07 10 Type RW RW RW RW RW RW RW RW 0 1 See Table 5: Async AGP/PCI Freq Table The decimal representation of N PLL2 Div (6:0) + 8 is equal to VCO divider value for PLL2. PWD 0 X X X X X X X Integrated Circuit Systems, Inc. ICS952906A 2 I C Table: Vendor & Revision ID Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit Pin # Name - 7 6 5 4 3 2 1 0 RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function Type 0 1 PWD R R R R R R R R - - X X X X 0 0 0 1 Control Function Type 0 1 PWD Byte Count Programming b(7:0) RW RW RW RW RW RW RW RW REVISION ID VENDOR ID 2 I C Table: Byte Count Register Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. 0 0 0 0 1 1 1 1 2 I C Table: Watchdog Timer Register Byte 9 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Control Function WD Timer Bit 7 WD Timer Bit 6 WD Timer Bit 5 WD Timer Bit 4 WD Timer Bit 3 WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 Type RW RW RW RW RW RW RW RW 0 1 These bits represent X*290ms the watchdog timer waits before it goes to alarm mode. Default is 11 x 293ms = 3.2s. PWD 0 0 0 0 1 0 1 1 2 I C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Bit 7 - M/NEN Bit 6 - WDEN Bit 5 - WDFSEN Bit Bit Bit Bit Bit - WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 4 3 2 1 0 Control Function M/N Programming Enable Watchdog Enable WD Safe Frequency Mode Watch Dog Safe Freq Programming bits 1236A—08/06/07 11 Type 0 1 PWD RW Disable Enable 0 0 R Disable Enable RW Latched FS/Byte0 WD B10 b(4:0) RW RW RW RW RW Writing to these bit will configure the safe frequency as Byte0 bit (4:0). 0 0 0 0 0 0 Integrated Circuit Systems, Inc. ICS952906A 2 I C Table: VCO Frequency Control Register Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Prog bit 8 M Divider Programming bits Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2] PWD X X X X X X X X 2 I C Table: VCO Frequency Control Register Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Control Function Type N Divider Programming b(8:0) RW RW RW RW RW RW RW RW Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2] PWD X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Control Function Type Spread Spectrum Programming b(7:0) RW RW RW RW RW RW RW RW Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 0 1 These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. PWD X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 14 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Reserved Reserved SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Reserved Reserved Spread Spectrum Programming b(13:8) 1236A—08/06/07 12 Type 0 1 PWD R R RW RW RW RW RW RW - - 0 0 X X X X X X These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. Integrated Circuit Systems, Inc. ICS952906A 2 I C Table: Output Divider Control Register Byte 15 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name 25MHz Div3 25Mhz Div2 25MHz Div1 25MHz Div0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function 25MHz Divider Ratio Programming Bits CPUDivider Ratio Programming Bits 0 Type RW RW RW RW RW RW RW RW 0000:/2 0001:/3 0010:/5 0011:/7 0000:/2 0001:/3 0010:/5 0011:/7 1 0100:/4 0101:/6 0110:/10 0111:/14 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1000:/8 1001:/12 1010:/20 1011:/28 PWD 1100:/16 1101:/24 1110:/40 1111:/56 1100:/16 1101:/24 1110:/40 1111:/56 X X X X X X X X 2 I C Table: Output Divider Control Register Byte 16 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Reserved Reserved Reserved Reserved 3V66Div3 3V66Div2 3V66Div1 3V66Div0 Control Function Reserved 3V66/PCI Divider Ratio Programming Bits for Mode 1 Type 0 1 PWD RW RW RW RW RW RW RW RW - - X X X X X X X X 0000:/2 0001:/3 0010:/5 0011:/7 0100:/4 1000:/8 1100:/16 0101:/6 1001:/12 1101:/24 0110:/10 1010:/20 1110:/40 0111:/14 1011:/28 1111:/56 2 I C Table: Output Divider Control Register Byte 17 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Reserved Reserved Reserved CPUINV Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved CPU Phase Invert Reserved Reserved Reserved Reserved Type 0 1 PWD RW RW RW RW RW RW RW RW Default - Inverse - X X X 1 1 1 1 1 Type 0 1 PWD RW RW RW RW RW RW RW RW - - 0 0 0 0 0 0 0 0 2 I C Table: Group Skew Control Register Byte 18 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1236A—08/06/07 13 Integrated Circuit Systems, Inc. ICS952906A 2 I C Table: Group Skew Control Register Pin # Byte 19 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 - Name 3V66Skw3 3V66Skw2 3V66Skw1 3V66Skw0 PCISkw3 PCISkw2 PCISkw1 PCISkw0 Control Function CPU-3V66 7 Step Skew Control (ps) CPU-PCI 7 Step Skew Control (ps) Type RW RW RW RW RW RW RW RW 0 0000:0 0001:N/A 0010:N/A 0011:N/A 0000:0 0001:N/A 0010:N/A 0011:N/A 1 0100:150 0101:N/A 0110:N/A 0111:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A PWD 1100:450 1101:600 1110:750 1111:900 1100:450 1101:600 1110:750 1111:900 0 0 0 0 1 1 0 0 2 I C Table: Group Skew Control Register Byte 20 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 Reserved Reserved Reserved Reserved Control Function CPU-PCI F(2:0) 7 Step Skew Control (ps) Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 0000:0 0001:N/A 0010:N/A 0011:N/A 1 0100:150 0101:N/A 0110:N/A 0111:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A PWD 1100:450 1101:600 1110:750 1111:900 - - 1 1 0 0 0 0 0 0 0 1 PWD RW RW RW RW 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 00 = 0.70X 01 = 0.80X 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 10 = 0.90X 11 = 1.00X 1 1 1 1 1 1 1 1 2 I C Table: Slew Rate Control Register Byte 21 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name PCIFStr1 PCIFStr0 PCIFStr1 PCIFStr0 Reserved Reserved AGPStr1 AGPStr0 Control Function PCICLKF (2:0) Strength Control PCICLK (6) Strength Control Reserved Reserved AGPCLK Strength Control Type RW RW 2 I C Table: Slew Rate Control Register Byte 22 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD REF_Slw REF Slew Rate Control RW RW PCIFStr1 PCIFStr0 PCIFStr1 PCIFStr0 PCIFStr1 PCIFStr0 PCICLK (5) Strength Control PCICLK (4:2) Strength Control RW PCICLK (1:0) Strength Control RW 00 = Medium 01 = Weak 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 00 = 0.63X 01 = 0.75X 10 = Strong 11 = N/A 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 10 = 0.88X 11 = 1.00X 1 0 1 1 1 1 1 1 1236A—08/06/07 14 RW Integrated Circuit Systems, Inc. ICS952906A 2 I C Table: Output Control Register Byte 23 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name 48MHz_0 24_48MHz REF1 REF0 REF2 48MHz_1 Reserved Reserved Control Function Output Control Output Control Output Control Output Control Output Control Output Control Reserved Reserved Type 0 1 PWD RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable - Enable Enable Enable Enable Enable Enable - 1 1 1 1 1 1 0 0 Type 0 1 PWD R - - X R - - X R R R R R R - - 0 X X X X X 2 I C Table: Read Back Register Pin # Byte 24 Name Bit 7 - WDHRB Bit 6 - WDSRB Bit Bit Bit Bit Bit Bit - Reserved FS4RB FS3RB FS2RB FS1RB FS0RB 5 4 3 2 1 0 Control Function WD Hard Alarm Status Read back WD Soft Alarm Status Read back Reserved FS4 Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back 1236A—08/06/07 15 Integrated Circuit Systems, Inc. ICS952906A Absolute Maximum Ratings Core Operating Voltage . . . . . . . . . . . . . . . . . . . I/O Operating Voltage . . . . . . . . . . . . . . . . . . . . . Lo gic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND –0.5 V to VDD + 0.5 V 0°C to +70°C –65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage Input MID Voltage Input Low Voltage Input High Current VIH VMID VIL I IH IIL1 Input Low Current CONDITIONS MIN TYP 3.3V +/-5% 2 3.3V +/-5% 1 3.3V +/-5% V SS -0.3 VIN = VDD -5 VIN = 0 V; Inputs with no pull-5 up resistors MAX V DD + 0.3 1.8 0.8 5 UNITS NOTES V V V uA uA IIL2 VIN = 0 V; Inputs with pull-up resistors Operating Supply Current IDD3.3OP Full Active, CL = Full load; 350 mA Powerdown Current I DD3.3PD 35 12 Input Frequency 3 Pin Inductance1 Fi Lpin CIN COUT CINX all diff pairs driven all differential pairs tri-stated V DD = 3.3 V 7 5 6 5 mA mA MHz nH pF pF pF 3 1 1 1 1 1.8 ms 1,2 33 kHz 1 1 Input Capacitance Clk Stabilization1,2 Modulation Frequency TSTAB Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock. Triangular Modulation 1 -200 uA 14.31818 30 Guaranteed by design, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2 1236A—08/06/07 16 Integrated Circuit Systems, Inc. ICS952906A Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3V +/-5%; CL =2pF PARAMETER SYMBOL Current Source Output Impedance Zo Voltage High VHigh 1 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy Rise Time Fall Time Rise Time Variation Fall Time Variation ppm tr tf d-tr d-tf CONDITIONS MIN VO = Vx 3000 Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 Variation of crossing over all edges see Tperiod min-max values VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V TYP MAX UNITS NOTES Ω 1 850 1 mV -150 150 1150 -300 250 -300 175 175 1 550 mV 1 1 1 140 mV 1 300 700 700 125 125 ppm ps ps ps ps 1,2 1 1 1 1 mV Measurement from differential 45 55 % wavefrom tsk3 VT = 50% Skew 100 ps Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 125 ps wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Duty Cycle dt3 1236A—08/06/07 17 1 1 1 Integrated Circuit Systems, Inc. ICS952906A Electrical Characteristics - 3V66 TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values Output High Voltage VOH IOH = -1 mA IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V Output High Current I OH VOH@MAX = 3.135 V VOL @MIN = 1.95 V Output Low Current I OL V OL@MAX = 0.4 V Edge Rate Rising edge rate Edge Rate Falling edge rate Rise Time t r1 VOL = 0.4 V, VOH = 2.4 V Fall Time t f1 VOH = 2.4 V, V OL = 0.4 V MIN -300 2.4 TYP MAX 300 1 1 0.5 0.5 38 4 4 2 2 UNITS ppm V V mA mA mA mA V/ns V/ns ns ns 45 55 % 1 0.55 -33 -33 30 Notes 1,2 1 1 1 1 Duty Cycle dt1 VT = 1.5 V Skew t sk1 VT = 1.5 V 250 ps 1 Jitter t jcyc-cyc VT = 1.5 V 3V66 250 ps 1 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Output High Voltage Output Low Voltage ppm VOH VOL -300 2.4 Output High Current I OH see Tperiod min-max values I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V VOH@MAX = 3.135 V VOL@MIN = 1.95 V VOL@MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66 1 1 0.5 0.5 45 Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter I OL t r1 t f1 dt1 t sk1 tjcyc-cyc 1 TYP MAX UNITS Notes 300 1,2 38 ppm V V mA mA mA mA 4 4 2 2 55 500 250 V/ns V/ns ns ns % ps ps 1 1 1 1 1 1 1 0.55 -33 -33 30 Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 2 1236A—08/06/07 18 Integrated Circuit Systems, Inc. ICS952906A Electrical Characteristics - 48MHz, 24MHz TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Output High Voltage Output Low Voltage ppm VOH VOL see Tperiod min-max values I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V VOH@MAX = 3.135 V VOL @MIN = 1.95 V VOL@MAX = 0.4 V Rising edge rate Falling edge rate -200 2.4 1 1 Output High Current Output Low Current I OH I OL Edge Rate Edge Rate TYP MAX 200 UNITS Notes 1,2 38 2 2 ppm V V mA mA mA mA V/ns V/ns 0.55 -33 -33 30 1 1 Rise Time t r1 VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time Duty Cycle t f1 dt1 VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V 125us period jitter (8kHz frequency modulation amplitude) 1 45 2 55 ns % 1 1 6 ns 1 Long Term Jitter 1 Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 2 Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN Long Accuracy Output High Voltage ppm V OH1 see Tperiod min-max values IOH = -1 mA -300 2.4 Output Low Voltage V OL1 IOL = 1 mA Output High Current IOH1 Output Low Current IOL1 Rise Time t r11 Fall Time t f11 tsk11 dt11 Skew Duty Cycle Jitter 1 t jcyc-cyc V = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, VOL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V OH@MIN V OH = 2.4 V, VOL = 0.4 V MAX UNITS Notes 300 ppm V 1 0.4 V -29 -23 mA 29 27 mA 1 2 ns 1 1 2 ns 1 500 ps 1 55 % 1 1000 ps 1 V T = 1.5 V V T = 1.5 V 1 V T = 1.5 V Guaranteed by design, not 100% tested in production. 1236A—08/06/07 19 45 TYP Integrated Circuit Systems, Inc. ICS952906A Shared Pin Operation Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K W Via to Gnd Device Pad 8.2K W Clock trace to load Series Term. Res. Fig. 1 1236A—08/06/07 20 Integrated Circuit Systems, Inc. ICS952906A c N SYMBOL L E1 A A1 b c D E E1 e h L N α E INDEX AREA 1 2 α h x 45° D A A1 -Ce In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS N SEATING PLANE b In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° 48 .10 (.004) C D mm. MIN 15.75 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS952906AFLFT Example: ICS XXXX A F LF- T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator Device Type Prefix ICS = Standard Device 1236A—08/06/07 21 D (inch) MAX 16.00 MIN .620 MAX .630 Integrated Circuit Systems, Inc. ICS952906A 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N α 0° 8° 0° 8° aaa -0.10 -.004 c N L E1 E INDEX AREA 1 2 α D A A2 VARIATIONS A1 -Ce N SEATING PLANE b 48 D mm. MIN MAX 12.40 12.60 Ref erence Doc.: JEDEC Publicat ion 95, M O-153 aaa C 10-0039 Ordering Information ICS952906AGLFT Example: ICS XXXX A G LF- T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator Device Type Prefix ICS = Standard Device 1236A—08/06/07 22 D (inch) MIN .488 MAX .496 Integrated Circuit Systems, Inc. ICS952906A Revision History Rev. N/A 0.1 A Issue Date Description 06/15/06 Initial Release 08/29/06 Updated I2C 1. Updated 48/24MHz Electrical Characteristics 08/06/07 2. Final release 1236A—08/06/07 23 Page # 13 19 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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