954119DFLF

ICS954119 Advance Information Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for Next Gen P4™ processor Recommended Application: CK410 compliant clock Output Features: • 2 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential SRC pair • 6 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - 24/48 MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 2 - REF, 14.318MHz • 5 - PCI-Express 0.7V current differential pairs Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 85ps • PCI outputs cycle-cycle jitter < 250ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Bit2 Bit1 Bit0 CPU PCIEX SRC Bit4 Bit3 FSLC FSLB FSLA MHz MHz MHz 266.66 100.00 100.00 0 0 0 0 0 133.33 100.00 100.00 0 0 0 0 1 0 0 0 1 0 200.00 100.00 100.00 166.66 100.00 100.00 0 0 0 1 1 0 0 1 0 0 333.33 100.00 100.00 100.00 100.00 100.00 0 0 1 0 1 0 0 1 1 0 400.00 100.00 100.00 200.00 100.00 100.00 0 0 1 1 1 266.66 133.33 133.33 0 1 0 0 0 133.33 133.33 133.33 0 1 0 0 1 200.00 133.33 133.33 0 1 0 1 0 166.66 125.00 125.00 0 1 0 1 1 333.33 125.00 125.00 0 1 1 0 0 100.00 133.33 133.33 0 1 1 0 1 400.00 133.33 133.33 0 1 1 1 0 200.00 133.33 133.33 0 1 1 1 1 1 0 0 0 0 269.33 101.00 101.00 1 0 0 0 1 134.66 101.00 101.00 1 0 0 1 0 202.00 101.00 101.00 1 0 0 1 1 168.33 101.00 101.00 1 0 1 0 0 274.66 103.00 103.00 1 0 1 0 1 137.33 103.00 103.00 1 0 1 1 0 206.00 103.00 103.00 1 0 1 1 1 171.66 103.00 103.00 1 1 0 0 0 279.99 105.00 105.00 1 1 0 0 1 140.00 105.00 105.00 1 1 0 1 0 210.00 105.00 105.00 1 1 0 1 1 174.99 105.00 105.00 1 1 1 0 0 287.99 108.00 108.00 1 1 1 0 1 144.00 108.00 108.00 1 1 1 1 0 216.00 108.00 108.00 1 1 1 1 1 179.99 108.00 108.00 * Entries 00111 & 01111 are 250MHz on the B & C revision. 0875—05/24/04 • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. Pin Configuration PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.67 33.67 33.67 33.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 36.00 36.00 36.00 36.00 GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PCICLK_F0 FSLA/PCICLK_F1 FSLB/PCICLK_F2 VDD48 **SEL24_48#/24_48MHz USB_48MHz GND DOTT_ 96MHz DOTC_96MHz Vtt_PwrGd#/PD PCIEXT0 PCIEXC0 VDDPCIEX GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 GND SRCCLKT SRCCLKC VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS954119 Functionality Features/Benefits: • Programmable output frequencies • Programmable output skew. • Programmable spread percentage for EMI control. • Programmable watch dog safe frequency. • Supports tight ppm accuracy clocks for Serial-ATA • Supports spread spectrum modulation, 0 to -0.5% down spread, ±0.25% center spread, and ±0.3% center spread 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDPCI PCICLK2 PCICLK1 PCICLK0 Reset# REF0/FSLC REF1 GND X1 X2 VDDREF SCLK SDATA CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND IREF GNDA VDDA VDDPCIEX PCIEXT4 PCIEXC4 PCIEXT3 PCIEXC3 GND 56-Pin SSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICS954119 Advance Information Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME PIN TYPE PWR OUT OUT OUT PWR PWR OUT 1 2 3 4 5 6 7 GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PCICLK_F0 8 FSLA/PCICLK_F1 I/O 9 FSLB/PCICLK_F2 I/O 10 VDD48 11 **SEL24_48#/24_48MHz 12 13 14 15 USB_48MHz GND DOTT_ 96MHz DOTC_96MHz OUT PWR OUT OUT 16 Vtt_PwrGd#/PD IN 17 18 19 20 21 22 23 24 25 PCIEXT0 PCIEXC0 VDDPCIEX GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 GND OUT OUT PWR PWR OUT OUT OUT OUT PWR 26 SRCCLKT OUT 27 SRCCLKC OUT 28 VDDSRC PWR PWR I/O DESCRIPTION Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# . 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock output. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock output. Power pin for the 48MHz output.3.3V Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz. 48.00MHz USB clock Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply for PCI Express clocks, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Ground pin. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Supply for SRC clocks, 3.3V nominal 0875—05/24/04 2 ICS954119 Advance Information Integrated Circuit Systems, Inc. Pin Description PIN # PIN NAME TYPE DESCRIPTION 29 30 31 32 33 34 GND PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 VDDPCIEX PWR OUT OUT OUT OUT PWR Ground pin. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Power supply for PCI Express clocks, nominal 3.3V 35 VDDA PWR 3.3V power for the PLL core. 36 GNDA PWR Ground pin for the PLL core. 37 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 38 GND PWR 39 CPUCLKC1 OUT 40 CPUCLKT1 OUT 41 VDDCPU PWR 42 CPUCLKC0 OUT 43 CPUCLKT0 OUT 44 45 46 47 48 49 50 SDATA SCLK VDDREF X2 X1 GND REF1 I/O IN PWR OUT IN PWR OUT 51 REF0/FSLC 52 Reset# OUT 53 54 55 56 PCICLK0 PCICLK1 PCICLK2 VDDPCI OUT OUT OUT PWR I/O Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. 14.318 MHz reference clock. 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V 0875—05/24/04 3 ICS954119 Advance Information Integrated Circuit Systems, Inc. General Description ICS954119 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS954119 is driven with a 14.318MHz crystal. Block Diagram 24/48MHz 48MHz, USB Frequency Dividers PLL2 DOTT_96MHz DOTC_96MHz X1 X2 XTAL REF (1:0) CPUCLKT (1:0) CPUCLKC (1:0) Programmable Spread PLL1 SCLK SDATA Vtt_PWRGD#/PD FSLA FSLB FSLC Sel24/48 Programmable Frequency Dividers Control Logic STOP Logic SRCCLKT SRCCLKC PCICLK (5:0) PCICLKF (2:0) PCI-Express (4:0) Reset# I REF Power Busing VDD GND Description 6,56 1,5 PCI pads and Prepad 10 13 USB _48M Hz, DOT_96M Hz, Fix P LL 19,34 20,29 Differnetial PCIEX pair 28 25 Differnetial SRC pair 35 36 Analog Core, CPU PLL 41 38 Differnetial CPU pair 46 49 Xtal, Ref, CPU PLL Digital 0875—05/24/04 4 ICS954119 Advance Information Integrated Circuit Systems, Inc. General I2C serial interface information for the ICS954119 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0875—05/24/04 5 Not acknowledge stoP bit ICS954119 Advance Information Integrated Circuit Systems, Inc. Table1: Frequency Selection Table Bit4 Bit2 Bit1 Bit0 Bit3 FSLC FSLB FSLA CPU PCIEX SRC PCI Spread MHz MHz MHz MHz % 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center 0 0 0 0 0 266.66 100.00 100.00 33.33 0 0 0 0 1 133.33 100.00 100.00 33.33 0 0 0 1 0 200.00 100.00 100.00 33.33 0 0 0 1 1 166.66 100.00 100.00 33.33 0 0 1 0 0 333.33 100.00 100.00 33.33 0 0 1 0 1 100.00 100.00 100.00 33.33 0 0 1 1 0 400.00 100.00 100.00 33.33 0 0 1 1 1 200.00 100.00 100.00 33.33 0 1 0 0 0 266.66 133.33 133.33 33.33 0 1 0 0 1 133.33 133.33 133.33 33.33 0 1 0 1 0 200.00 133.33 133.33 33.33 0 1 0 1 1 166.66 125.00 125.00 33.33 0 1 1 0 0 333.33 125.00 125.00 33.33 0 1 1 0 1 100.00 133.33 133.33 33.33 0 1 1 1 0 400.00 133.33 133.33 33.33 0 1 1 1 1 200.00 133.33 133.33 33.33 1 0 0 0 0 269.33 101.00 101.00 33.67 1 0 0 0 1 134.66 101.00 101.00 33.67 1 0 0 1 0 202.00 101.00 101.00 33.67 1 0 0 1 1 168.33 101.00 101.00 33.67 1 0 1 0 0 274.66 103.00 103.00 34.33 1 0 1 0 1 137.33 103.00 103.00 34.33 1 0 1 1 0 206.00 103.00 103.00 34.33 1 0 1 1 1 171.66 103.00 103.00 34.33 1 1 0 0 0 279.99 105.00 105.00 35.00 1 1 0 0 1 140.00 105.00 105.00 35.00 1 1 0 1 0 210.00 105.00 105.00 35.00 1 1 0 1 1 174.99 105.00 105.00 35.00 1 1 1 0 0 287.99 108.00 108.00 36.00 1 1 1 0 1 144.00 108.00 108.00 36.00 1 1 1 1 1 1 1 1 0 1 216.00 108.00 108.00 36.00 179.99 108.00 108.00 36.00 0875—05/24/04 6 ICS954119 Advance Information Integrated Circuit Systems, Inc. I2C Table: Frequency Select Register Byte 0 Pin # Name Bit 7 - FS Source Bit 6 - SS_EN1 Bit 5 - Reserved Bit 4 - Bit4 Control Function Type 0 1 RW Latch Inputs IIC 0 RW OFF ON 1 Reserved RW - - Freq Select Bit 4 RW Frequency H/W IIC Select PLL1 Spread Enable PWD 1 0 Bit 3 - Bit3 Freq Select Bit 3 RW Bit 2 - FSLC Freq Select Bit 2 RW 0 Bit 1 - FSLB Freq Select Bit 1 RW Latch Bit 0 - FSLA Freq Select Bit 0 RW Latch Name Control Function Type 0 1 See Table 1: PLL 1 Frequency Selection Table Latch I2C Table: Output Control Register Byte 1 Pin # PWD Bit 7 7 PCICLK_F0 Output Control RW Disable Enable 1 Bit 6 14,15 DOTT/C_96MHz Output Control RW Disable Enable 1 Bit 5 12 USB_48MHz Output Control RW Disable Enable 1 Bit 4 51 REF0 Output Control RW Disable Enable 1 Bit 3 50 REF1 Output Control RW Disable Enable 1 Bit 2 40,39 CPUCLKT/C1 Output Control RW Disable Enable 1 Bit 1 43,42 CPUCLKT/C0 Disable Enable 1 - CPUCLK's Output Control PD Mode Output State Control RW Bit 0 RW Driven Hi-Z 0 I2C Table: Output Control Register Byte 2 Pin # Name Control Function Type 0 1 PWD Output Control Output Control Output Control Output Control RW RW RW RW Disable Disable Disable Enable Enable Enable 1 1 1 1 Bit 4 55 PCICLK5 PCICLK4 PCICLK3 PCICLK2 Disable Enable Bit 3 54 PCICLK1 Output Control RW Disable Enable 1 Bit 2 53 PCICLK0 Output Control RW Disable Enable 1 Bit 7 Bit 6 Bit 5 4 3 2 Bit 1 9 PCICLK_F2 Output Control RW Disable Enable 1 Bit 0 8 PCICLK_F1 Output Control RW Disable Enable 1 I2C Table: Output Control Register Byte 3 Pin # Name Control Function Type 0 1 PWD RW Driven Hi-Z 0 RW - - 1 1 Bit 7 - PCIEXCLK's Bit 6 - Reserved PD Mode Output State Control Reserved Bit 5 33,32 PCIEXCLKT/C4 Output Control RW Disable Enable Bit 4 31,30 PCIEXCLKT/C3 Output Control RW Disable Enable 1 Bit 3 27,26 SRCCLKT/C Output Control RW Disable Enable 1 Bit 2 24,23 PCIEXCLKT/C2 Output Control RW Disable Enable 1 Bit 1 22,21 PCIEXCLKT/C1 Output Control RW Disable Enable 1 Bit 0 18,17 PCIEXCLKT/C0 Output Control RW Disable Enable 1 Control Function Type 0 1 PWD Stop all PCI / PCIEX / SRC clocks Stop Control Enable Disable 1 RW Free Running Stoppable 0 I2C Table: Output Control Register Pin # Byte 4 Name Bit 7 - PCI/SRC Stop EN Bit 6 - PCICLK_F2 Bit 5 - PCICLK_F1 Stop Control RW Free Running Stoppable 0 Bit 4 - PCICLK_F0 Stop Control RW Free Running Stoppable 0 Bit 3 - PCIEXCLKT/C (5:3) Stop Control RW Free Running Stoppable 1 Bit 2 - SRCCLKT/C Stop Control RW Free Running Stoppable 1 Bit 1 - PCIEXCLKT/C (2:0) Stop Control RW Free Running Stoppable 1 Bit 0 - Reserved Reserved RW - - 1 0875—05/24/04 7 ICS954119 Advance Information Integrated Circuit Systems, Inc. I2C Table: Programmable Skew Control Register Byte 5 Pin # Name Control Function Bit 7 - PCISkw3 Bit 6 - PCISkw2 Bit 5 - PCISkw1 Bit 4 - PCISkw0 Bit 3 - ASYNC1 Bit 2 - ASYNC0 Bit 1 - REF0 REF0 select Bit 0 - Reserved Reserved Name Control Function CPU-PCI 7 Steps Skew Control (ps) PCI Async Freq Type 0 1 PWD RW 0000:0 0100:150 1000:300 1100:450 0 RW 0001:N/A 0101:N/A 1001:N/A 1101:600 0 RW 0010:N/A 0110:N/A 1010:N/A 1110:750 0 RW 0011:N/A 0111:N/A 1011:N/A 1111:900 RW 00 = PLL1 RW RW 0 10 = 37.7 0 01 = 33.0 11 = 44.0 0 XTAL Fixed PLL 0 RW - - 0 Type 0 1 PWD RW - - 1 RW - - 1 RW - - 1 RW - - 1 RW - - 0 RW - - 1 RW - - 0 RW - - 1 I2C Table: Output Drive Control Register Byte 6 Pin # Bit 7 - Reserved Bit 6 - Reserved Bit 5 - Reserved Bit 4 - Reserved Bit 3 - Reserved Bit 2 - Reserved Bit 1 - Reserved Bit 0 - Reserved Reserved Reserved Reserved Reserved I2C Table: Vendor ID Register Name Control Function Type 0 1 PWD Bit 7 Byte 7 - Pin # Reserved Reserved RW - - 0 Bit 6 - Reserved Reserved RW - - 0 Bit 5 - Reserved Reserved RW - - 0 Bit 4 - Reserved Reserved RW - - 0 Bit 3 - VID3 R - - 0 Bit 2 - VID2 R - - 0 Bit 1 - VID1 R 001 = ICS - 0 Bit 0 - VID0 R - - 1 Type 0 1 PWD VENDOR ID I2C Table: Byte Count Register Byte 8 Pin # Name Control Function Bit 7 - BC7 RW 0 Bit 6 - BC6 RW 0 Bit 5 - BC5 RW Bit 4 - BC4 Bit 3 - BC3 Bit 2 - BC2 RW 1 Bit 1 - BC1 RW 1 Bit 0 - BC0 RW 1 Byte Count Programming b(7:0) RW RW 0 Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. 0 1 I2C Table: WD Time Control Register Byte 9 Pin # Name Bit 7 - Bit 6 - WD_SEL Bit 5 - WD Hard Status Bit 4 - WD Soft Status Bit 3 - WDTCtrl Bit 2 - Bit 1 - Bit 0 - WD_EN Control Function Watchdog Alarm Enable Watchdog Hard/Soft Alarm Select WD Hard Alarm Status Type 0 1 PWD RW Disable Enable 0 RW Hard only Hard and Soft 0 R Normal Alarm X R Normal Alarm X RW 290ms Base 1160ms Base 0 WD2 WD Soft Alarm Status Watch Dog Time base Control WD Timer Bit 2 WD1 WD Timer Bit 1 RW WD0 WD Timer Bit 0 RW 0875—05/24/04 8 RW These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. 1 1 1 ICS954119 Advance Information Integrated Circuit Systems, Inc. I2C Table: M/N Programming & WD Safe Frequency Control Register Byte 10 Pin # Name Control Function Type 0 1 PWD RW Disable Enable 0 RW - - 0 RW B10b(4:0) Latch Inputs 0 Reserved PLL1 M/N Programming Enable Reserved - WD Safe Freq Source WD Safe Freq Source Bit 4 - WD SF4 RW Bit 3 - WD SF3 RW Bit 2 - WD SF2 Bit 1 - WD SF1 Bit 0 - WD SF0 Bit 7 - M/N_EN Bit 6 - Bit 5 Watch Dog Safe Freq Programming bits RW RW 0 Writing to these bit will configure the safe frequency as Byte0 bit (4:0). RW 0 0 0 0 I2C Table: PLL1 Frequency Control Register Name Control Function Type Bit 7 Byte 11 - Pin # N Div8 N Divider Prog bit 8 RW Bit 6 - N Div9 N Divider Prog bit 9 RW Bit 5 - M Div5 RW Bit 4 - M Div4 RW Bit 3 - M Div3 Bit 2 - M Div2 Bit 1 - M Div1 RW X Bit 0 - M Div0 RW X M Divider Programming bit (5:0) RW RW 0 1 PWD X X The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] X X X X I2C Table: PLL1 Frequency Control Register Byte 12 Pin # Name Control Function Type 0 1 PWD Bit 7 - N Div7 RW Bit 6 - N Div6 RW Bit 5 - N Div5 Bit 4 - N Div4 Bit 3 - N Div3 Bit 2 - N Div2 RW Bit 1 - N Div1 RW X Bit 0 - N Div0 RW X RW N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) RW RW X X The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] X X X X I2C Table: PLL1 Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 0 1 PWD Bit 7 - SSP7 RW X Bit 6 - SSP6 RW X Bit 5 - SSP5 RW Bit 4 - SSP4 Bit 3 - SSP3 Bit 2 - SSP2 RW X Bit 1 - SSP1 RW X Bit 0 - SSP0 RW X Spread Spectrum Programming bit(7:0) RW RW X These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 X X I2C Table: PLL1 Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Type 0 1 PWD R - - 0 Bit 7 - Reserved Bit 6 - SSP14 RW X Bit 5 - SSP13 RW X Bit 4 - SSP12 RW Bit 3 - SSP11 Bit 2 - SSP10 Bit 1 - SSP9 RW X Bit 0 - SSP8 RW X Spread Spectrum Programming bit(14:8) 0875—05/24/04 9 RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 X X X ICS954119 Advance Information Integrated Circuit Systems, Inc. I2C Table: Reserved Register Byte 15 Pin # 1 0 PWD Name Control Function Type Bit 7 - Reserved Reserved RW X Bit 6 - Reserved Reserved RW X Bit 5 - Reserved Reserved RW X Bit 4 - Reserved Reserved RW Bit 3 - Reserved Reserved RW Bit 2 - Reserved Reserved RW X Bit 1 - Reserved Reserved RW X Bit 0 - Reserved Reserved RW X Name Control Function Type X Reserved X I2C Table: Reserved Register Byte 16 Pin # 1 0 PWD Bit 7 - Reserved RW X Bit 6 - Reserved RW X Bit 5 - Reserved RW Bit 4 - Reserved Bit 3 - Reserved Bit 2 - Reserved RW X Bit 1 - Reserved RW X Bit 0 - Reserved RW X X RW Reserved X Reserved RW X I2C Table: Reserved Register Byte 17 Pin # Name Control Function Type 1 0 PWD Bit 7 - Reserved RW X Bit 6 - Reserved RW X Bit 5 - Reserved RW Bit 4 - Reserved Bit 3 - Reserved Bit 2 - Reserved RW X Bit 1 - Reserved RW X Bit 0 - Reserved RW X X RW Reserved X Reserved RW X I2C Table: Reserved Register Byte 18 Pin # Name Control Function Type 0 1 PWD Bit 7 - Reserved RW 0 Bit 6 - Reserved RW X Bit 5 - Reserved RW X Bit 4 - Reserved RW Bit 3 - Reserved Bit 2 - Reserved RW X Bit 1 - Reserved RW X Bit 0 - Reserved RW X Reserved X Reserved RW X I2C Table: Programmable Output Divider Register Byte 19 Pin # Name Bit 7 - CPUDiv3 Bit 6 - CPUDiv2 Bit 5 - CPUDiv1 Bit 4 - CPUDiv0 Bit 3 - PCIEXDiv3 Bit 2 - PCIEXDiv2 Bit 1 - PCIEXDiv1 Bit 0 - PCIEXDiv0 Control Function CPU Divider Ratio Programming Bits PCIEX Divider Ratio Programming Bits 0875—05/24/04 10 Type 0 1 PWD RW 0000:/2 0100:/4 1000:/8 1100:/16 X RW 0001:/3 0101:/6 1001:/12 1101:/24 X RW 0010:/5 0110:/10 1110:/40 X RW 0011:/7 0111:/14 1010:/20 1011:/28 1111:/56 X RW 0000:/2 0100:/4 1000:/8 1100:/16 X RW 0001:/3 0101:/6 1001:/12 1101:/24 X RW 0010:/5 0110:/10 X 0011:/7 0111:/14 1010:/20 1011:/28 1110:/40 RW 1111:/56 X ICS954119 Advance Information Integrated Circuit Systems, Inc. I2C Table: Programmable Output Divider Register Byte 20 Pin # Name Bit 7 - PCIDiv3 Bit 6 - PCIDiv2 Bit 5 - PCIDiv1 Bit 4 - PCIDiv0 Bit 3 - Reserved Bit 2 - Reserved Bit 1 - Reserved Bit 0 - Reserved Control Function PCI Divider Ratio Programming Bits Reserved 0875—05/24/04 11 Type 0 1 PWD RW 0000:/2 0100:/4 1000:/8 1100:/16 X RW 0001:/3 0101:/6 1001:/12 1101:/24 X RW 0010:/5 0110:/10 1010:/20 1110:/40 X RW 0011:/15 0111:/30 1011:/60 1111:/120 X RW - - X RW - - X RW - - X RW - - X ICS954119 Advance Information Integrated Circuit Systems, Inc. Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes VDD + 0.5V V 1 V 1 ° 1 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature VDD_A - VDD_In - Ts - -65 150 Ambient Operating Temp Tambient - 0 70 °C 1 Case Temperature Tcase - 115 °C 1 Input ESD protection HBM ESD prot - V 1 MAX UNITS Notes VDD + 0.5V GND - 0.5 2000 C 1 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 -5 uA 1 -200 uA 1 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current Operating Current IDD3.3OP Powerdown Current 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VIL_FSL 3.3 V +/-5% VSS - 0.3 0.35 V 1 IDD3.3OP Full Active, CL = Full load; 350 mA 1 IDD3.3PD Fi Pin Inductance Lpin all outputs driven 400 mA 1 all diff pairs driven 70 mA 1 all differential pairs tri-stated 12 mA 1 VDD = 3.3 V 14.31818 2 nH 1 5 pF 1 Logic Inputs COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins 5 pF 1 1.8 ms 1 33 kHz 1 300 us 1 5 ns 1 5 ns 1 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 Tfall_Pd# Trise_Pd# PD# rise time of TSTAB Modulation Frequency Tdrive_PD# SMBus Voltage MHz 7 CIN From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of Clk Stabilization TYP VIH_FSL Input Frequency Input Capacitance VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors MIN 30 2.7 VDD Low-level Output Voltage VOL @ IPULLUP Current sinking at IPULLUP VOL = 0.4 V SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 4 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 0875—05/24/04 12 ICS954119 Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High SYMBOL CONDITIONS* MIN Zo VO = Vx 3000 VHigh 850 mV 1,3 VLow Statistical measurement on single ended signal 660 Voltage Low -150 150 mV 1,3 Measurement on single ended signal using absolute value. 1150 mV 1 -300 mV 1 550 mV 1 140 mV 1 1,2 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm Average period Absolute min period Tperiod Tabsmin TYP 250 MAX NOTES Ω 1 Variation of crossing over all edges see Tperiod min-max values -300 300 ppm 400MHz nominal 2.4993 2.5008 ns 2 400MHz spread 2.4993 2.5133 ns 2 333.33MHz nominal 2.9991 3.0009 ns 2 333.33MHz spread 2.9991 3.016 ns 2 266.66MHz nominal 3.7489 3.7511 ns 2 266.66MHz spread 3.7489 3.77 ns 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 166.66MHz nominal 5.9982 6.0018 ns 2 2 166.66MHz spread 5.9982 6.0320 ns 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 7.5400 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 400MHz nominal/spread 2.4143 ns 1,2 333.33MHz nominal/spread 2.9141 ns 1,2 266.66MHz nominal/spread 3.6639 ns 1,2 200MHz nominal/spread 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 125 ps 1 55 % 1 100 ps 1 150 ps 1 125 ps 1 85 ps 1 VOH = 0.525V VOL = 0.175V Measurement from differential Duty Cycle dt3 wavefrom CPU(1:0), VT = 50% Skew tsk3 CPU(1:0) to CPU2_ITP, Skew tsk4 VT = 50% Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom (CPU2_ITP) Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom, (CPU(1:0)) *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω Fall Time Variation d-tf 45 1 Guaranteed by design and characterization, not 100% tested in production. 2 UNITS All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 3 0875—05/24/04 13 ICS954119 Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High SYMBOL CONDITIONS* MIN Zo VO = Vx 3000 VHigh VLow Statistical measurement on single ended signal 660 Voltage Low -150 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm Measurement on single ended signal using absolute value. TYP MAX UNITS Notes Ω 1 850 mV 1,3 150 mV 1,3 1150 mV 1 -300 250 mV 1 550 mV 1 140 mV 1 Variation of crossing over all edges see Tperiod min-max values -300 300 ppm 1,2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 ns 1,2 Average period Tperiod Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-tf 125 ps 1 55 % 1 250 ps 1 125 ps 1 MAX UNITS NOTES 55 Ω 1 V 1 0.55 V 1 mA 1 -33 mA 1 mA 1 1 VOH = 0.525V VOL = 0.175V Measurement from differential Duty Cycle dt3 wavefrom Skew tsk3 VT = 50% Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω 45 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 3 Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS* MIN Output Impedance RDSP VO = VDD*(0.5) 12 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL 38 mA Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 V OH @MIN = 1.0 V TYP -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V 30 VOL @ MAX = 0.4 V Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 500 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 250 ps 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (unless otherwise specified) 1 Guaranteed by design and characterization, not 100% tested in production. 0875—05/24/04 14 ICS954119 Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - 48MHz/USB48MHz/24_48MHz PARAMETER Long Accuracy SYMBOL ppm CONDITIONS* see Tperiod min-max values MIN -100 Clock period Tperiod 48.00MHz output nominal TYP NOTES MAX 100 UNITS ppm 20.8313 20.8354 ns 55 Ω 1 V 1 0.55 V 1 mA 1 -33 mA 1 mA 1 1 Output Impedance RDSP VO = VDD*(0.5) 12 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL 38 mA 1 Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Edge Rate tslewr/f_USB USB48 Rising/Falling edge rate 1 2 V/ns 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 UNITS Notes Ω 1 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V 30 VOL @ MAX = 0.4 V *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - DOT_96MHz 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High SYMBOL CONDITIONS* MIN Zo VO = Vx 3000 VHigh 850 mV 1,3 VLow Statistical measurement on single ended signal 660 Voltage Low -150 150 mV 1,3 Max Voltage Vovs 1150 mV 1 mV 1 550 mV 1 140 mV 1 1,2 Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vcross Measurement on single ended signal using absolute value. TYP MAX -300 250 Long Accuracy ppm Variation of crossing over all edges see Tperiod min-max values -100 100 ppm Average period Tperiod 96.00MHz nominal 10.4135 10.4198 ns 2 Absolute min period Tabsmin 96.00MHz nominal 10.1635 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 125 ps 1 55 % 1 250 ps 1 VOH = 0.525V VOL = 0.175V Measurement from differential Duty Cycle dt3 wavefrom Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, Ι REF = 475Ω Fall Time Variation d-tf 45 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 3 0875—05/24/04 15 ICS954119 Advance Information Integrated Circuit Systems, Inc. Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 69.8550 ns 2 V 1 0.4 V 1 -29 -23 mA 1 29 27 mA 1 Clock period T period 14.318MHz output nominal 69.8270 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA VOH @MIN = 1.0 V, TYP Output High Current IOH Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter tjcyc-cyc VT = 1.5 V 1000 ps 1 VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 0875—05/24/04 16 ICS954119 Advance Information Integrated Circuit Systems, Inc. 56-Lead, 300 mil Body, 25 mil, SSOP c N SYMBOL L E1 INDEX AREA A A1 b c D E E1 e h L N a E 1 2 α h x 45° D A In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS A1 -Ce In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° N SEATING PLANE b .10 (.004) C 56 D mm. MIN 18.31 D (inch) MAX 18.55 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS954119yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0875—05/24/04 17 MIN .720 MAX .730