954141CFLF

954141 Datasheet Programmable Timing Control Hub™ for Next Gen P4™ processor Recommended Application: CK410 compliant clock Output Features: • 2 - 0.7V current-mode differential CPU pairs • 6 - 0.7V current-mode differential SRC pair • 1 - 0.7V current-mode differential CPU_ITP/SRC selectable pair • 6 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 1 - REF, 14.318MHz Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 85ps • PCI outputs cycle-cycle jitter < 250ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit2 Bit1 Bit0 CPU Bit3 FSLC FSLB FSLA MHz 266.66 0 0 0 0 133.33 0 0 0 1 0 0 1 0 200.00 166.66 0 0 1 1 0 1 0 0 333.33 100.00 0 1 0 1 0 1 1 0 400.00 200.00 0 1 1 1 266.66 1 0 0 0 133.33 1 0 0 1 200.00 1 0 1 0 166.66 1 0 1 1 333.33 1 1 0 0 100.00 1 1 0 1 400.00 1 1 1 0 200.00 1 1 1 1 0 0 0 0 269.33 0 0 0 1 134.66 0 0 1 0 202.00 0 0 1 1 168.33 0 1 0 0 274.66 0 1 0 1 137.33 0 1 1 0 206.00 0 1 1 1 171.66 1 0 0 0 279.99 1 0 0 1 140.00 1 0 1 0 210.00 1 0 1 1 174.99 1 1 0 0 287.99 1 1 0 1 144.00 1 1 1 0 216.00 1 1 1 1 179.99 0934A—03/30/09 • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. Pin Configuration SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 125.00 125.00 133.33 133.33 133.33 101.00 101.00 101.00 101.00 103.00 103.00 103.00 103.00 105.00 105.00 105.00 105.00 108.00 108.00 108.00 108.00 SATA MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 125.00 125.00 133.33 133.33 133.33 101.00 101.00 101.00 101.00 103.00 103.00 103.00 103.00 105.00 105.00 105.00 105.00 108.00 108.00 108.00 108.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.67 33.67 33.67 33.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 36.00 36.00 36.00 36.00 VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 PCICLK_F1 PCICLK_F2 VDD48 USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB Vtt_PwrGd#/PD FSLA SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS954141 Functionality Features/Benefits: • Programmable output frequencies • Programmable output skew. • Programmable spread percentage for EMI control. • Programmable watch dog safe frequency. • Supports tight ppm accuracy clocks for Serial-ATA • Supports spread spectrum modulation, 0 to -0.5% down spread, ±0.25% center spread, and ±0.3% center spread 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCICLK2 PCICLK1 PCICLK0 FSLC REFOUT GND X1 X2 VDDREF SDATA SCLK GND CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 IREF GNDA VDDA CPUCLKT2_ITP/SRCCLKT_7 CPUCLKC2_ITP/SRCCLKC_7 VDDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GND 56-Pin SSOP and TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 954141 Datasheet Pin Description PIN # PIN NAME TYPE DESCRIPTION 1 2 3 VDDPCI GND PCICLK3 PWR PWR OUT Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. 4 PCICLK4 OUT PCI clock output. 5 PCICLK5 OUT PCI clock output. 6 7 GND VDDPCI PWR PWR 8 ITP_EN/PCICLK_F0 Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair 0 = SRC pair I/O 9 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# . 10 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# . 11 VDD48 PWR Power pin for the 48MHz output.3.3V 12 13 14 15 USB_48MHz GND DOTT_96MHz DOTC_96MHz OUT PWR OUT OUT 48.00MHz USB clock Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. 16 FSLB IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. 17 Vtt_PwrGd#/PD IN Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 18 FSLA IN 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 20 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 21 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 22 SRCCLKT2 OUT True clock of differential SRC clock pair. 23 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 24 25 26 27 28 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC OUT OUT OUT OUT PWR True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC/SATA pair. Complement clock of differential SRC/SATA pair. Supply for SRC clocks, 3.3V nominal 0934A—03/30/09 2 954141 Datasheet Pin Description PIN # PIN NAME TYPE 29 30 31 32 33 34 GND SRCCLKC5 SRCCLKT5 SRCCLKC6 SRCCLKT6 VDDSRC PWR OUT OUT OUT OUT PWR 35 CPUCLKC2_ITP/SRCCLKC_7 OUT 36 CPUCLKT2_ITP/SRCCLKT_7 OUT 37 38 VDDA GNDA PWR PWR 39 IREF OUT 40 CPUCLKC1 OUT 41 CPUCLKT1 OUT 42 VDDCPU PWR 43 CPUCLKC0 OUT 44 CPUCLKT0 OUT 45 46 47 48 49 GND SCLK SDATA VDDREF X2 PWR IN I/O PWR OUT 50 51 52 X1 GND REFOUT IN PWR OUT 53 FSLC 54 55 56 PCICLK0 PCICLK1 PCICLK2 IN OUT OUT OUT DESCRIPTION Ground pin. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. Reference Clock output 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. PCI clock output. PCI clock output. PCI clock output. 0934A—03/30/09 3 954141 Datasheet General Description ICS954141A follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS954141A is driven with a 14.318MHz crystal. Block Diagram 48MHz, USB Frequency Dividers PLL2 DOTT_96MHz DOTC_96MHz X1 X2 XTAL REFOUT CPUCLKT (1:0) CPUCLKC (1:0) SRCCLKT (6:1) SCLK SDATA Vtt_PWRGD#/PD FSLA FSLB FSLC ITP_EN Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic SRCCLKC (6:1) PCICLK (5:0) Control Logic PCICLKF (2:0) CPU_ITP/SRC7T CPU_ITP/SRC7C I REF 0934A—03/30/09 4 954141 Datasheet General I2C serial interface information for the ICS954141A How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0934A—03/30/09 5 Not acknowledge stoP bit 954141 Datasheet Table1: Frequency Selection Table Bit4 Bit2 Bit1 Bit0 Bit3 FSLC FSLB FSLA CPU SRC SATA PCI Spread MHz MHz MHz MHz % 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center 0 0 0 0 0 266.66 100.00 100.00 33.33 0 0 0 0 1 133.33 100.00 100.00 33.33 0 0 0 1 0 200.00 100.00 100.00 33.33 0 0 0 1 1 166.66 100.00 100.00 33.33 0 0 1 0 0 333.33 100.00 100.00 33.33 0 0 1 0 1 100.00 100.00 100.00 33.33 0 0 1 1 0 400.00 100.00 100.00 33.33 0 0 1 1 1 200.00 100.00 100.00 33.33 0 1 0 0 0 266.66 133.33 133.33 33.33 0 1 0 0 1 133.33 133.33 133.33 33.33 0 1 0 1 0 200.00 133.33 133.33 33.33 0 1 0 1 1 166.66 125.00 125.00 33.33 0 1 1 0 0 333.33 125.00 125.00 33.33 0 1 1 0 1 100.00 133.33 133.33 33.33 0 1 1 1 0 400.00 133.33 133.33 33.33 0 1 1 1 1 200.00 133.33 133.33 33.33 1 0 0 0 0 269.33 101.00 101.00 33.67 1 0 0 0 1 134.66 101.00 101.00 33.67 1 0 0 1 0 202.00 101.00 101.00 33.67 1 0 0 1 1 168.33 101.00 101.00 33.67 1 0 1 0 0 274.66 103.00 103.00 34.33 1 0 1 0 1 137.33 103.00 103.00 34.33 1 0 1 1 0 206.00 103.00 103.00 34.33 1 0 1 1 1 171.66 103.00 103.00 34.33 1 1 0 0 0 279.99 105.00 105.00 35.00 1 1 0 0 1 140.00 105.00 105.00 35.00 1 1 0 1 0 210.00 105.00 105.00 35.00 1 1 0 1 1 174.99 105.00 105.00 35.00 1 1 1 0 0 287.99 108.00 108.00 36.00 1 1 1 0 1 144.00 108.00 108.00 36.00 1 1 1 1 1 1 1 1 0 1 216.00 108.00 108.00 36.00 179.99 108.00 108.00 36.00 0934A—03/30/09 6 954141 Datasheet I2C Table: Frequency Select Register Name Control Function Type 0 1 PWD - FS Source Frequency H/W IIC Select RW Latch Inputs IIC 0 Bit 6 - SS_EN1 PLL1 Spread Enable RW OFF ON 1 Bit 5 - SS_EN2 PLL2 Spread Enable RW OFF ON Bit 4 - Bit4 Freq Select Bit 4 RW Bit 3 - Bit3 Freq Select Bit 3 RW Bit 2 - FSLC Freq Select Bit 2 RW Bit 1 - FSLB Freq Select Bit 1 RW Latch Bit 0 - FSLA Freq Select Bit 0 RW Latch Name Control Function Type Byte 0 Bit 7 Pin # 1 0 0 See Table 1: PLL 1 Frequency Selection Table Latch I2C Table: Output Control Register Byte 1 Pin # 0 1 PWD Bit 7 - PCICLK_F0 Output Control RW Disable Enable 1 Bit 6 - DOTT/C_96MHz Output Control RW Disable Enable 1 Bit 5 - USB_48MHz Output Control RW Disable Enable 1 Bit 4 - REFOUT Output Control RW Disable Enable 1 Bit 3 - Reserved Reserved RW - - 1 Bit 2 - CPUCLKT/C1 Output Control RW Disable Enable 1 Bit 1 - CPUCLKT/C0 Output Control RW Disable Enable 1 CPUCLK's PD Mode Output State Control RW Driven Hi-Z 0 Name Control Function Type 0 1 PWD Bit 0 - I2C Table: Output Control Register Byte 2 Pin # Bit 7 - PCICLK5 Output Control RW Disable Enable 1 Bit 6 - PCICLK4 Output Control RW Disable Enable 1 Bit 5 - PCICLK3 Output Control RW Disable Enable 1 Bit 4 - PCICLK2 Output Control RW Disable Enable 1 Bit 3 - PCICLK1 Output Control RW Disable Enable 1 Bit 2 - PCICLK0 Output Control RW Disable Enable 1 Bit 1 - PCICLK_F2 Output Control RW Disable Enable 1 Bit 0 - PCICLK_F1 Output Control RW Disable Enable 1 Name Control Function Type 0 1 PWD I2C Table: Output Control Register Byte 3 Pin # Bit 7 - SRCCLK's PD Mode Output State Control RW Driven Hi-Z 0 Bit 6 - CPUCLKT/C2 / SRCCLK7 Output Control RW Disable Enable 1 Bit 5 - SRCCLKT/C6 Output Control RW Disable Enable 1 Bit 4 - SRCCLKT/C5 Output Control RW Disable Enable 1 Bit 3 - SRCCLKT/C_SATA4 Output Control RW Disable Enable 1 Bit 2 - SRCCLKT/C3 Output Control RW Disable Enable 1 Bit 1 - SRCCLKT/C2 Output Control RW Disable Enable 1 Bit 0 - SRCCLKT/C1 Output Control RW Disable Enable 1 0934A—03/30/09 7 954141 Datasheet I2C Table: Output Control Register Byte 4 Pin # Name Control Function Type 0 1 PWD RW Enable Disable 1 Free Running Stoppable 0 Stoppable 0 0 Bit 7 - PCI/SRC Stop EN Stop all PCI / SRC clocks Bit 6 - PCICLK_F2 Stop Control Bit 5 - PCICLK_F1 Stop Control RW Free Running Bit 4 - PCICLK_F0 Stop Control RW Free Running Stoppable Bit 3 - SRCCLKT/C (7:5) Stop Control RW Free Running Stoppable 1 Bit 2 - SRCCLKT/C 4 Stop Control RW Free Running Stoppable 1 Bit 1 - SRCCLKT/C (3:1) Stop Control RW Free Running Stoppable 1 Bit 0 - Reserved RW - - 1 Control Function Type 0 1 PWD Reserved I2C Table: Programmable Skew Control Register Byte 5 Pin # Name Bit 7 - Bit 6 - PCISkw2 Bit 5 - PCISkw1 Bit 4 - PCISkw0 Bit 3 - ASYNC1 Bit 2 - Bit 1 - Bit 0 - PCISkw3 CPU-PCI 7 Steps Skew Control (ps) (Also see Table 3) RW 0000:0 0100:150 1000:300 1100:450 0 RW 0001:N/A 0101:N/A 1001:N/A 1101:600 0 RW 0010:N/A 0110:N/A 1010:N/A 1110:750 0 RW 0011:N/A 0111:N/A 1011:N/A 1111:900 0 RW 00 = PLL1/ PLL2 10 = 37.7 0 ASYNC0 PCI Async Freq (see Table 6) RW 01 = 33.0 11 = 44.0 0 Reserved Reserved RW - - 0 Reserved Reserved RW - - 0 Control Function Type 0 1 PWD I2C Table: Output Drive Control Register Byte 6 Pin # Name Bit 7 - Reserved RW - - 1 Bit 6 - Reserved RW - - 1 Bit 5 - Reserved RW - - 1 Bit 4 - Reserved RW - - 1 Bit 3 - Reserved RW - - 1 Bit 2 - Reserved RW - - 1 Bit 1 - Reserved RW - - 1 Bit 0 - Reserved RW - - 1 PWD Reserved Reserved Reserved Reserved I2C Table: Vendor ID Register Byte 7 Pin # Name Control Function Type 0 1 Bit 7 - SRC _SOURCE SRC comes from RW PLL1 PLL2 0 Bit 6 - PCI_SOURCE PCI comes from RW PLL1 PLL2 0 Bit 5 - SRC_SATA_Source SATA comes from RW PLL1 PLL2 0 PLL2 Sync PLL2 (SATA, SRC,PCI ) Synchronization RW Async Sync 0 - 0 Bit 4 - Bit 3 - VID3 R - Bit 2 - VID2 R - - 0 Bit 1 - VID1 R 001 = ICS - 0 Bit 0 - VID0 R - - 1 VENDOR ID 0934A—03/30/09 8 954141 Datasheet I2C Table: Byte Count Register Byte 8 Pin # Name Control Function Type 0 1 PWD Bit 7 - BC7 RW 0 Bit 6 - BC6 RW 0 Bit 5 - BC5 RW Bit 4 - BC4 Bit 3 - BC3 Bit 2 - BC2 RW 1 Bit 1 - BC1 RW 1 Bit 0 - BC0 RW 1 Byte Count Programming b(7:0) RW RW 0 Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. 0 1 I2C Table: WD Time Control Register Byte 9 Pin # Name Control Function Type 0 1 PWD Bit 7 - WDH_EN Watchdog Hard Alarm Enable RW Disable Enable 0 Bit 6 - WDS_EN Watchdog Soft Alarm Enable RW Disable Enable 0 Bit 5 - WD Hard Status WD Hard Alarm Status R Normal Alarm X Bit 4 - WD Soft Status WD Soft Alarm Status R Normal Alarm X Bit 3 - WDTCtrl Watch Dog Time base Control RW 290ms Base 1160ms Base 0 Bit 2 - WD2 WD Timer Bit 2 RW Bit 1 - WD1 WD Timer Bit 1 RW Bit 0 - WD0 WD Timer Bit 0 RW These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. 1 1 1 I2C Table: M/N Programming & WD Safe Frequency Control Register Byte 10 Pin # Name Control Function Type 0 1 PWD RW Disable Enable 0 Bit 7 - M/N_EN PLL1 M/N Programming Enable Bit 6 - RW - - 0 - WD Safe Freq Source RW B10b(4:0) Latch Inputs/B0(4:0) 0 Bit 4 - Reserved WD Safe Freq Source WD SF4 Reserved Bit 5 Bit 3 - WD SF3 Bit 2 - WD SF2 Bit 1 - WD SF1 RW 0 Bit 0 - WD SF0 RW 0 RW 0 RW Watch Dog Safe Freq Programming bits RW 0 Writing to these bit will configure the safe frequency as Byte0 bit (4:0). 0 I2C Table: PLL1 Frequency Control Register Byte 11 Pin # Name Control Function Type 0 1 PWD Bit 7 - N Div8 N Divider Prog bit 8 RW Bit 6 - N Div9 N Divider Prog bit 9 RW Bit 5 - M Div5 RW Bit 4 - M Div4 RW Bit 3 - M Div3 RW Bit 2 - M Div2 Bit 1 - M Div1 RW X Bit 0 - M Div0 RW X M Divider Programming bit (5:0) RW 0934A—03/30/09 9 X X The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] X X X X 954141 Datasheet I2C Table: PLL1 Frequency Control Register Byte 12 Pin # Name Control Function Type 0 1 PWD Bit 7 - N Div7 RW Bit 6 - N Div6 RW Bit 5 - N Div5 RW Bit 4 - N Div4 Bit 3 - N Div3 Bit 2 - N Div2 RW Bit 1 - N Div1 RW X Bit 0 - N Div0 RW X N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) RW RW X X The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] X X X X I2C Table: PLL1 Spread Spectrum Control Register Byte 13 Pin # Name Control Function Type 0 1 PWD Bit 7 - SSP7 RW X Bit 6 - SSP6 RW X Bit 5 - SSP5 RW X Bit 4 - SSP4 RW Bit 3 - SSP3 Bit 2 - SSP2 RW X Bit 1 - SSP1 RW X Bit 0 - SSP0 RW X Spread Spectrum Programming bit(7:0) RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 X X I2C Table: PLL1 Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Type 0 1 R - - PWD Bit 7 - Reserved Bit 6 - SSP14 RW X Bit 5 - SSP13 RW X Bit 4 - SSP12 RW Bit 3 - SSP11 Bit 2 - SSP10 RW X Bit 1 - SSP9 RW X Bit 0 - SSP8 RW X Spread Spectrum Programming bit(14:8) RW 0 X These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 X I2C Table: PLL2 Frequency Control Register Byte 15 Pin # Name Control Function Type 0 1 PWD Bit 7 - N Div8 N Divider Prog bit 8 RW Bit 6 - N Div9 N Divider Prog bit 9 RW Bit 5 - M Div5 Bit 4 - M Div4 Bit 3 - M Div3 Bit 2 - M Div2 Bit 1 - M Div1 RW X Bit 0 - M Div0 RW X RW RW RW M Divider Programming bits RW 0934A—03/30/09 10 X X The decimal representation of M and N Divier in Byte 15 and 16 will configure the PLL2 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] X X X X 954141 Datasheet I2C Table: PLL2 Frequency Control Register Byte 16 Pin # Name Control Function Type 0 1 PWD Bit 7 - N Div7 RW Bit 6 - N Div6 RW Bit 5 - N Div5 RW Bit 4 - N Div4 Bit 3 - N Div3 Bit 2 - N Div2 RW Bit 1 - N Div1 RW X Bit 0 - N Div0 RW X N Divider Programming b(7:0) RW RW X X The decimal representation of M and N Divier in Byte 15 and 16 will configure the PLL2 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] X X X X I2C Table: PLL2 Spread Spectrum Control Register Byte 17 Pin # Name Control Function Type 0 1 PWD Bit 7 - SSP7 RW X Bit 6 - SSP6 RW X Bit 5 - SSP5 RW Bit 4 - SSP4 Bit 3 - SSP3 Bit 2 - SSP2 RW X Bit 1 - SSP1 RW X Bit 0 - SSP0 RW X Spread Spectrum Programming b(7:0) RW RW X These Spread Spectrum bits in Byte 17 and 18 will program the spread pecentage of PLL2 X X I2C Table: PLL2 Spread Spectrum Control Register Byte 18 Pin # Name Control Function Reserved Type 0 1 PWD R - - 0 Bit 7 - Reserved Bit 6 - SSP14 RW X Bit 5 - SSP13 RW X Bit 4 - SSP12 RW Bit 3 - SSP11 Bit 2 - SSP10 RW X Bit 1 - SSP9 RW X Bit 0 - SSP8 RW X Spread Spectrum Programming b(14:8) RW X These Spread Spectrum bits in Byte 17 and 18 will program the spread pecentage of PLL2 X I2C Table: Programmable Output Divider Register Byte 19 Pin # Name Bit 7 - CPUDiv3 Bit 6 - CPUDiv2 Bit 5 - CPUDiv1 Bit 4 - CPUDiv0 Bit 3 - SRCDiv3 Bit 2 - SRCDiv2 Bit 1 - SRCDiv1 Bit 0 - SRCDiv0 Control Function CPU Divider Ratio Programming Bits for PLL1 SRC Divider Ratio Programming Bits for PLL1 Type 0 1 PWD RW 0000:/2 0100:/4 1000:/8 1100:/16 X RW 0001:/3 0101:/6 1001:/12 1101:/24 X RW 0010:/5 0110:/10 1010:/20 1110:/40 X RW 0011:/7 0111:/14 1011:/28 1111:/56 X RW 0000:/2 0100:/4 1000:/8 1100:/16 X RW 0001:/3 0101:/6 1001:/12 1101:/24 X RW 0010:/5 0110:/10 1010:/20 1110:/40 X RW 0011:/7 0111:/14 1011:/28 1111:/56 X 0934A—03/30/09 11 954141 Datasheet Absolute Maximum Rating 1 PARAMETER SYMBOL CONDITIONS MIN TYP 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature VDD_A - VDD_In - Ts - -65 150 Ambient Operating Temp Tambient - 0 70 Case Temperature Tcase - 115 °C 1 Input ESD protection HBM ESD prot - V 1 GND - 0.5 MAX UNITS Notes VDD + 0.5V V 1 V 1 ° C 1 °C 1 VDD + 0.5V 2000 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS Notes Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 -5 uA 1 -200 uA 1 IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors TYP VIH_FSL 3.3 V +/-5% 0.7 VDD + 0.3 V 1 VIL_FSL 3.3 V +/-5% VSS - 0.3 0.35 V 1 Operating Supply Current IDD3.3OP Full Active, CL = Full load; 350 mA 1 Operating Current IDD3.3OP all outputs driven 400 mA 1 all diff pairs driven 70 mA 1 all differential pairs tri-stated 12 mA 1 MHz 2 Powerdown Current IDD3.3PD Input Frequency Fi Pin Inductance Lpin Input Capacitance VDD = 3.3 V 14.31818 nH 1 5 pF 1 CIN Logic Inputs COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins 5 pF 1 1.8 ms 1 33 kHz 1 300 us 1 5 ns 1 5 ns 1 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 Tfall_Pd# From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of Trise_Pd# PD# rise time of Clk Stabilization 7 T STAB Modulation Frequency Tdrive_PD# SMBus Voltage VDD Low-level Output Voltage Current sinking at VOL = 0.4 V VOL 30 2.7 @ IPULLUP 4 IPULLUP SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) SCLK/SDATA (Min VIH + 0.15) to TFI2C Clock/Data Fall Time (Max VIL - 0.15) *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 0934A—03/30/09 12 954141 Datasheet Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh Voltage Low VLow Statistical measurement on single ended signal 660 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm Average period Absolute min period Tperiod Tabsmin Measurement on single ended signal using absolute value. -150 MAX UNITS  1 850 mV 1,3 150 mV 1,3 1150 mV 1 mV 1 550 mV 1 140 mV 1 -300 250 NOTES Variation of crossing over all edges see Tperiod min-max values -300 300 ppm 1,2 400MHz nominal 2.4993 2.5008 ns 2 400MHz spread 2.4993 2.5133 ns 2 333.33MHz nominal 2.9991 3.0009 ns 2 2 333.33MHz spread 2.9991 3.016 ns 266.66MHz nominal 3.7489 3.7511 ns 2 266.66MHz spread 3.7489 3.77 ns 2 200MHz nominal 4.9985 5.0015 ns 2 200MHz spread 4.9985 5.0266 ns 2 166.66MHz nominal 5.9982 6.0018 ns 2 166.66MHz spread 5.9982 6.0320 ns 2 133.33MHz nominal 7.4978 7.5023 ns 2 133.33MHz spread 7.4978 7.5400 ns 2 100.00MHz nominal 9.9970 10.0030 ns 2 10.0533 100.00MHz spread 9.9970 ns 2 400MHz nominal/spread 2.4143 ns 1,2 333.33MHz nominal/spread 2.9141 ns 1,2 266.66MHz nominal/spread 3.6639 ns 1,2 200MHz nominal/spread 4.8735 ns 1,2 166.66MHz nominal/spread 5.8732 ns 1,2 133.33MHz nominal/spread 7.3728 ns 1,2 100.00MHz nominal/spread 9.8720 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V 125 ps 1 Fall Time Variation d-tf 125 ps 1 Duty Cycle dt3 55 % 1 Skew tsk3 VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom CPU(1:0), VT = 50% 100 ps 1 150 ps 1 125 ps 1 85 ps 1 45 CPU(1:0) to CPU2_ITP, tsk4 Skew VT = 50% Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom (CPU2_ITP) Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom, (CPU(1:0)) *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF 1 TYP Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 0934A—03/30/09 13 954141 Datasheet Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh Voltage Low VLow Statistical measurement on single ended signal 660 Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vx(abs) Crossing Voltage (var) d-Vx Long Accuracy ppm Measurement on single ended signal using absolute value. -150 MAX UNITS  1 850 mV 1,3 150 mV 1,3 1150 mV 1 mV 1 550 mV 1 140 mV 1 -300 250 Notes Variation of crossing over all edges see Tperiod min-max values -300 300 ppm 1,2 100.00MHz nominal 9.9970 10.0030 ns 2 100.00MHz spread 9.9970 10.0533 ns 2 9.8720 ns 1,2 Average period Tperiod Absolute min period Tabsmin 100.00MHz nominal/spread Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential dt3 Duty Cycle wavefrom VT = 50% tsk3 Skew Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF Fall Time Variation 1 TYP d-tf 45 125 ps 1 125 ps 1 55 % 1 250 ps 1 125 ps 1 MAX UNITS NOTES 55  1 V 1 0.55 V 1 mA 1 mA 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. Electrical Characteristics - PCICLK/PCICLK_F SYMBOL RDSP CONDITIONS* VO = VDD*(0.5) MIN Output Impedance PARAMETER Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH V OH @MIN = 1.0 V TYP 12 -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 30 1 38 mA 1 Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Group Skew tskew VT = 1.5 V 500 ps 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 250 ps 1 VOL @ MAX = 0.4 V *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 4 pF with Rs = 33 (unless otherwise specified) 1 mA Guaranteed by design and characterization, not 100% tested in production. 0934A—03/30/09 14 954141 Datasheet Electrical Characteristics - 48MHz/USB48MHz/24_48MHz PARAMETER SYMBOL CONDITIONS* MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1 Clock period Tperiod 48.00MHz output nominal 20.8313 20.8354 ns 55  1 V 1 Output Impedance RDSP VO = VDD*(0.5) 12 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH TYP 0.55 V OH @MIN = 1.0 V -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -33 30 V 1 mA 1 mA 1 mA 1 38 mA 1 Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Edge Rate tslewr/f_USB USB48 Rising/Falling edge rate 1 2 V/ns 1 Rise Time tr VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns 1 Fall Time tf VOH = 2.4 V, VOL = 0.4 V 0.5 2 ns 1 Rise Time tr_USB VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf_USB VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 500 ps 1 UNITS Notes  1 VOL @ MAX = 0.4 V *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 4 pF with Rs = 33 (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - DOT_96MHz 0.7V Current Mode Differential Pair PARAMETER SYMBOL CONDITIONS* MIN Current Source Output Impedance Zo VO = Vx 3000 Voltage High VHigh 850 mV 1,3 VLow Statistical measurement on single ended signal 660 Voltage Low -150 150 mV 1,3 Max Voltage Vovs 1150 mV 1 Min Voltage Vuds mV 1 Crossing Voltage (abs) Vx(abs) 550 mV 1 140 mV 1 1,2 Measurement on single ended signal using absolute value. MAX -300 250 Long Accuracy ppm Variation of crossing over all edges see Tperiod min-max values -100 100 ppm Average period Tperiod 96.00MHz nominal 10.4135 10.4198 ns 2 Absolute min period Tabsmin 96.00MHz nominal 10.1635 ns 1,2 Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps 1 Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps 1 Rise Time Variation d-tr VOL = 0.175V, VOH = 0.525V Crossing Voltage (var) d-Vcross VOH = 0.525V VOL = 0.175V Measurement from differential dt3 Duty Cycle wavefrom Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9REF Fall Time Variation 1 TYP d-tf 45 125 ps 1 125 ps 1 55 % 1 250 ps 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. 0934A—03/30/09 15 954141 Datasheet Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 TYP 300 ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8270 69.8550 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL 0.4 V 1 -29 -23 mA 1 29 27 mA 1 IOL = 1 mA VOH @MIN = 1.0 V, Output High Current IOH Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate 1 4 V/ns 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 2 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 1 2 ns 1 Duty Cycle dt1 VT = 1.5 V 45 55 % 1 Jitter tjcyc-cyc VT = 1.5 V 1000 ps 1 VOH@MAX = 3.135 V VOL @MIN = 1.95 V, @MAX = 0.4 V VOL *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 4 pF with Rs = 39 (Rs is used in USB48MHz test only) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 0934A—03/30/09 16 954141 Datasheet 56-Lead, 300 mil Body, 25 mil, SSOP c N SYMBOL L E1 INDEX AREA E 1 2 α h x 45° D A In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS A1 -Ce A A1 b c D E E1 e h L N a In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° SEATING PLANE b .10 (.004) C N 56 D mm. MIN 18.31 D (inch) MAX 18.55 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information 954141AFLF-T Example: XXXX A F LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type 0934A—03/30/09 17 MIN .720 MAX .730 954141 Datasheet c N L E1 INDEX AREA E 1 2 α h x 45° D A A1 -Ce SEATING PLANE b .10 (.004) C 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS N 56 D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 Ref erence Doc.: JEDEC Publicat ion 95, M O-153 10-0039 Ordering Information 954141AGLF-T Example: XXXX A G LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type 0934A—03/30/09 18 MAX .555 954141 Datasheet Revision History Rev. N/A A Issue Date Description 10/13/2004 Added TSSOP ordering information 1. Corrected single-ended clock loading. 2. Updated part ordering information. 3/30/2009 3. Removed water marks. 4. Moved to final. 0934A—03/30/09 19 Page # 18 Various IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. 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