95V857AG

57 95V857 Absolute Maximum Ratings Supply Voltage (VDD & AVDD).......... . -0.5V to 4.6V Logic Inputs ......................... GND -0.5 V to Voo + 0.5 V Ambient Operating Temperature .......... 0° c to+85° C Storage Temperature ... ................ - 6 5° C to+1 50 ° C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.T hese ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied.Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85° C; Supply Voltage Avoo, Voo = 2.5V ± 0.2V SYMBOL PARAMETER CONDITIONS V1 = Voo or GND Input High Current l 1H V1 = Voo or GND Input Low Current l 1L Operating Supply I002.s CL = 0pf @ 200MHz Current looPD CL = 0pf Voo = 2.3V, Vwr = 1V Output High Current loH Voo = 2.3V, Vwr = 1.2V Output Low Current loL High Impedance Cutout Current Input Clamp Voltage 1oz MIN T YP MAX UNITS 148 5 1 70 100 µA mA 5 -32 mA 26 35 mA Vooa = 2.3V lin = -18mA Voo = min to max, Vooo- 0.1 loH = -1 mA High-level output VoH voltage Vooa = 2.3V, 1.7 loH = -1 2 mA Voo = min to max loL= 1 mA Low-level output voltage VoL Vooa = 2.3V loH= 1 2 mA 1 V1 = GND or Voo C1N lnout Caoacitance 1 Cour Vour = GND or Voo Out out Caoacitance 1Guaranteed by design at 2 20MHz, not 100% tested in production. V1K 4 µA -18 V 00= 2.7V, Vout = V 00 or GND 06745- 3/3/2015 µA ±10 mA -1.2 V V V 3 3 0.1 V 0.6 V pF pF 95V857 Timing Requirements TA= O - 85 ° C; Supply Voltage Avoo, V00 = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS MIN SYMBOL PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freq0p freqApp ° 2.5V±0.2V@ 25 C 2.5V±0.2V@ 25 °C dtin MAX 233 UNITS MHz 95 220 MHz 40 60 % 15 µs 45 TsTAB Switching Characteristics (see note 3) SYMBOL PARAMETER Low-to high level tPLH 1 propaqation delay time High-to low level propagation tPLL 1 delav time Output enable time tEN Output disable time tdis Period jitter T;;1 loerl tOit hper) Half-period jitter Input clock slew rate tsllil Output clock slew rate tsllol Tcvc-Tcvc Cvcle to Cvcle Jitter1 Static Phase Offset trstatic nhase ottsetl 4 Output to Output Skew Tskew CONDITION MIN TYP MAX UNITS CLK_IN to any output 3.5 ns CLK_IN to any output 3.5 ns 3 3 ns ns ps PD# to any output PD# to any output 100MHz to 200MHz 100MHz to 200MHz 100MHz to 200MHz -30 -75 1 1 -50 -50 Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twHltc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. 06745- 3/3/2015 6 0 30 75 4 2 50 50 40 PS V/ns V/ns ps ps ps 95V857 95 95V857 Parameter Measurement Information IN C C LK _INT r'.___________ C LK I I FB_IN C ·X�------)1( 1 .....___ ----Ii\- I I X.._____ ! FB_INT ------..., 1 _.J X..___ _ ----:--! I I+- t(0) n t(