ICS98ULPA877A
1.8V Low-Power Wide-Range Frequency Clock Driver
Pin Configuration
1
E
F
G
H
J
K
52-Ball BGA
Top View
CLKT6
VDDQ
31
CLKT5
34
CLKC6
CLKC5
35
32
VDDQ
36
33
CLKT0
CLKC0
5
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
VDDQ
1
30
CLKC7
CLKT2
CLKC2
2
29
CLKT7
CLKT2
3
28
VDDQ
21
OS
FBIN_INC
CLKC7
20
10
CLKT7
VDDQ
OE
GND
CLKC6
19
22
CLKT8
9
18
VDDQ
VDDQ
CLKT6
CLKC8
23
17
8
CLKC5
CLKC9
FBOUTT
AVDD
CLK_INC
15
24
16
7
VDDQ
FBOUTC
AGND
CLKT9
25
14
6
CLKT4
VDDQ
13
FB_INC
CLKC4
CLKC4
FB_INT
26
12
27
5
11
4
CLK_INC
CLKT3
CLK_INT
CLKT4
CLKT5
CLKT8
CLKC8
CLKT9
CLKC9
NOTE:
1. The Logic Detect (LD) powers down the device
when a logic LOW is applied to both CLK_INT and
CLK_INC.
1177F—12/10/09
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
CLKC1
CLK_INT
FBIN_INT
4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
37
CLKT1
CLKC3
PLL
3
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
CLKC0
CLKT3
- 100K
CLKT1
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
CLKC1
1
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
39
A
B
C
D
E
F
G
H
J
K
CLKT0
CLKC2
10K
6
D
CLKC3
OS
AVDD
LD or OE
POWER
DOWN
AND
LD, OS, or OE
TEST
MODE
PLL BYPASS
LOGIC
LD
5
C
(1)
OE
4
B
40
Block Diagram
3
A
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800)
• OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• CYCLE - CYCLE jitter 40ps
2
38
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR2 DIMM logic solution
FBOUTT
FBOUTC
40-Pin MLF
ICS98ULPA877A
Pin Descriptions
Te r m i n a l
Name
Electrical
Characteristics
Description
AGND
Analog Ground
Ground
AVDD
A n a l o g p ow e r
1.8 V nominal
CLK_INT
C l o ck i n p u t w i t h a ( 1 0 K - 1 0 0 K O h m ) p u l l d o w n r e s i s t o r
Differential input
CLK_INC
Complentar y clock input with a (10K-100K Ohm) pulldown resistor
Differential input
FB_INT
Feedback clock input
Differential input
FB_INC
Complementary feedback clock input
Differential input
FB_OUTT
Feedback clock output
Differential output
FB_OUTC
Complementary feedback clock output
Differential output
OE
Output Enable (Asynchronous)
LVCMOS input
OS
Output Select (tied to GND or VDDQ)
LVCMOS input
GND
Ground
Ground
VDDQ
Logic and output power
1.8V nominal
CLKT[0:9]
Clock outputs
Differential outputs
CLKC[0:9]
Complementary clock outputs
Differential outputs
NB
No ball
The PLL clock buffer, ICS98ULPA877A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and
output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS98ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When
OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time tSTAB.
The PLL in ICS98ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).
ICS98ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
1177F—12/10/09
2
ICS98ULPA877A
ICS98ULPA877A is available in Commercial Temperature Range (0°C to 70°C) and Industrial Temperature Range (-40°C
to +85°C). See Ordering Information for details
Function Table
Inputs
Outputs
PLL
AVDD
OE
OS
CLK_INT
CLK_INC
CLKT
CLKC
FB_OUTT
FB_OUTC
GND
H
X
L
H
L
H
L
H
Bypassed/Off
GND
H
X
H
L
H
L
H
L
Bypassed/Off
GND
L
H
L
H
*L(Z)
*L(Z)
L
H
Bypassed/Off
GND
L
L
H
L
*L(Z),
CLKT7
active
*L(Z),
CLKC7
active
H
L
Bypassed/Off
1.8V(nom)
L
H
L
H
*L(Z)
*L(Z)
L
H
On
1.8V(nom)
L
L
H
L
*L(Z),
CLKT7
active
*L(Z),
CLKC7
active
H
L
On
1.8V(nom)
H
X
L
H
L
H
L
H
On
1.8V(nom)
H
X
H
L
H
L
H
L
On
1.8V(nom)
X
X
L
L
*L(Z)
*L(Z)
*L(Z)
*L(Z)
Off
1.8V(nom)
X
X
H
H
Reser ved
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
1177F—12/10/09
3
ICS98ULPA877A
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
-0.5V to 2.5V
GND - 0.5V to VDDQ + 0.5V
-40°C to +85°C
-65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
SYMBOL
MIN
PARAMETER
CONDITIONS
Input High Current
IIH
VI = VDDQ or GND
(CLK_INT, CLK_INC)
Input Low Current (OE,
IIL
VI = VDDQ or GND
OS, FB_INT, FB_INC)
Output Disabled Low
IODL
OE = L, VODL = 100mV
100
Current
CL = 0pf @ 410MHz
IDD1.8
Operating Supply
Current
CL = 0pf
IDDLD
VIK
VDDQ = 1.7V Iin = -18mA
Input Clamp Voltage
VDDQ - 0.2
IOH = -100 µA
VOH
High-level output voltage
IOH = -9 mA
1.1
IOL=100 µA
VOL
Low-level output voltage
IOL=9 mA
1
VI = GND or VDDQ
CIN
2
Input Capacitance
COUT
2
VOUT = GND or VDDQ
Output Capacitance1
1
Guaranteed by design, not 100% tested in production.
1177F—12/10/09
4
TYP
MAX
UNITS
±250
µA
±10
µA
µA
300
500
-1.2
1.45
0.25
0.10
0.6
3
3
mA
µA
V
V
V
V
V
pF
pF
ICS98ULPA877A
Recommended Operating Condition (see note1)
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
1.8
1.9
V
Supply Voltage
VDDQ, AVDD
CLK_INT, CLK_INC, FB_INC,
V
0.35 x VDDQ
Low level input voltage
VIL
FB_INT
V
OE, OS
0.35 x VDDQ
CLK_INT, CLK_INC, FB_INC,
V
0.65 x V DDQ
High level input voltage
VIH
FB_INT
OE, OS
0.65 x V DDQ
V
DC input signal voltage
VIN
-0.3
VDDQ + 0.3
V
(note 2)
DC - CLK_INT, CLK_INC,
V
0.3
VDDQ + 0.4
Differential input signal
FB_INC, FB_INT
VID
voltage (note 3)
AC - CLK_INT, CLK_INC,
V
0.6
VDDQ + 0.4
FB_INC, FB_INT
Output differential crossVOX
VDDQ/2 - 0.10
VDDQ/2 + 0.10
V
voltage (note 4)
Input differential crossVIX
VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15
V
voltage (note 4)
High level output current
IOH
-9
mA
Low level output current
IOL
9
mA
Operating free-air
TA
-40
85
°C
temperature
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDDQ and is the
voltage at which the differential signal must be crossing.
1177F—12/10/09
5
ICS98ULPA877A
Timing Requirements
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
Max clock frequency
freqop
1.8V+0.1V @ 25°C
95
410
MHz
Application Frequency
Range
freqApp
1.8V+0.1V @ 25°C
160
410
MHz
Input clock duty cycle
dtin
40
60
%
15
µs
CLK stabilization
TSTAB
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t∅), after power-up. During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK# may be left floating after they have been driven low for one
complete clock cycle.
1177F—12/10/09
6
ICS98ULPA877A
1
Switching Characteristics
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
CONDITION
SYMBOL
ten
Output enable time
OE to any output
tdis
OE to any output
Output disable time
Period jitter
tjit (per)
Half-period jitter
tjit(hper)
Input slew rate
SLr1(i)
Output clock slew rate
SLr1(o)
Cycle-to-cycle period jitter
tjit(cc+)
tjit(cc-)
Dynamic Phase Offset
t(Ø)dyn
Static Phase Offset
t jit (per) + t (Ø)dyn + t skew(o)
t(Ø)dyn + tskew(o)
tSPO2
∑(su)
∑t (h)
Output to Output Skew
(MHz)
MIN
30.00
3
40
-40
50
20
50
80
60
40
30
33
UNITS
ns
ns
ps
ps
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
kHz
0.00
-0.50
%
160 to 410
160 to 270
271 to 410
160 to 270
271 to 410
Input Clock
Output Enable (OE), (OS)
160 to 410
160 to 270
271 to 410
271 to 410
-40
-30
-60
-50
1
0.5
1.5
0
0
-50
-20
-50
160 to 270
271 to 410
tskew
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
1177F—12/10/09
7
TYP
4.73
5.82
2.5
2.5
0
MAX
8
8
40
30
60
50
4
MHz
ICS98ULPA877A
Parameter Measurement Information
VDD
ICS98ULPA877A
V(CLK)
V (CLK)
GND
Figure 1: IBIS Model Output Load
VDD/2
GND
C = 10pF
ICS98ULPA877A
R = 10
Z = 60
SCOPE
Z = 50
L = 2.97"
R = 1M
C = 1pF
Z = 120
R = 10
Z = 60
Z = 50
VTT
C = 10pF
L = 2.97"
R = 1M
C = 1pF
VTT
GND
Note: VTT = GND
VDD/2
Figure 2: Output Load Test Circuit
Yx, FB_OUTC
Yx, FB_OUTT
tC(N + 1)
tC(N)
tJIT(CC) = tC(N) + tC(N + 1)
Figure 3: Cycle-to-Cycle Jitter
1177F—12/10/09
8
ICS98ULPA877A
Parameter Measurement Information
CLK_INC
CLK_INT
CLK_INC
CLK_INT
t( )n+1
t( )n
n =N
t( ) =
t( )n
1
N
Figure 4: Static Phase Offset
Yx#
Yx
Yx, FB_OUTC
Yx, FB_OUTT
tSKEW
Figure 5: Output Skew
Yx, FB_OUTC
Yx, FB_OUTT
tC(n)
Yx, FB_OUTC
Yx, FB_OUTT
1
fo
t(JIT_PER) = tC(n) -
1
fo
Figure 6: Period Jitter
1177F—12/10/09
9
ICS98ULPA877A
Parameter Measurement Information
Yx, FB_OUTC
Yx, FB_OUTT
tJIT(HPER_n+1)
tJIT(HPER_n)
1
fo
tJIT(HPER) = tJIT(HPER_n) -
1
2xfo
Figure 7: Half-Period Jitter
80%
80%
VID V OD
20%
20%
Clock Inputs
and outputs
tSLR
tSLF
Figure 8: Input and Output Slew Rates
1177F—12/10/09
10
ICS98ULPA877A
CLK#
CLK
FBIN#
FBIN
t( )
t( )
SSC OFF
SSC OFF
SSC ON
SSC ON
t( )dyn
t( )dyn
t( )dyn
t( )dyn
Figure 9: Dynamic Phase Offset
50% VDDQ
OE
Y#
tEN
50% VDDQ
Y. Y#
Y
OE
50% VDDQ
tDIS
Y
50% VDDQ
Y#
Figure 10: Time Delay Between OE and Clock Output (Y, Y#)
1177F—12/10/09
11
ICS98ULPA877A
VIA
CARD
1
BEAD
0603
AVDD
VDDQ
4.7uF
1206
0.1uF
0603
2200pF
0603
PLL
GND
AGND
VIA
CARD
Figure 11. AVDD Filtering
*Place the 2200pF capacitors close to the PLL.
*Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect
trace to one GND via (farthest from PLL).
*Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8 DC max., 600 at 100MHz).
1177F—12/10/09
12
ICS98ULPA877A
C
SEATING
PLANE
Numeric Designations
for Horizontal Grid
A1
b REF
T
4
3
2
1
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q, and
S not used)
D
d TYP
D1
-e- TYP
TOP VIEW
E
c REF
-e- TYP
h TYP
0.12 C
E1
ALL DIMENSIONS IN MILLIMETERS
D
E
7.00 Bsc
4.50 Bsc
T
Min/Max
0.86/1.00
e
0.65 Bsc
----- BALL GRID ----HORIZ
VERT
6
10
Max.
TOTAL
60
d
Min/Max
0.25/0.45
h
Min/Max
0.15/0.31
D1
E1
5.85 Bsc
3.25 Bsc
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
* Source Ref.: JEDEC Publication 95,
MO-205*, MO-225**
10-0055
Ordering Information
98ULPA877AHLFT
Example:
XXXX y H z LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Temperature Grade
Blank = 0°C to +70°C (Commercial)
I = -40°C to +85°C (Industrial)
Package Type
H = BGA
Revision Designator (will not correlate with datasheet revision)
Device Type
1177F—12/10/09
13
REF. DIMENSIONS
b
c
0.575
0.625
**
ICS98ULPA877A
Seating Plane
A1
Index Area
L
A3
N
(Ref.)
ND & NE
Even
(ND - 1) x e
(Ref.)
(Typ.)
If ND & NE
are Even
e/2
1
1
Anvil
Singulation
2
2
or
E
(NE - 1) x e
(Ref.)
E2
Sawn
Singulation
E2/2
Top View
b
(Ref.)
ND & NE
Odd
A
D
e
C
0.08
D2/2
D2
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
ALL DIMENSION S IN MILLIMETERS
N
ND
NE
D x E BASIC
D2 MIN. / MAX.
E2 MIN. / MAX.
L MIN. / MAX.
40
10
10
6.00 x 6.00
2.75 / 3.05
2.75 / 3.05
0.30 / 0.50
SYMBOL
A
A1
A3
b
e
MIN.
MAX.
0.80
1.00
0
0.05
0.25 Reference
0.18
0.30
0.50 BASIC
Source Reference: MLF2™ S
10-0053
Ordering Information
98ULPA877AKLFT
Example:
XXXX y K z LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Temperature Grade
Blank = 0°C to +70°C (Commercial)
I = -40°C to +85°C (Industrial)
Package Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
Device Type
1177F—12/10/09
14
Thermal
Base
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