9DB102BGLFT

DATASHEET ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Description Features/Benefits The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. • • • • • • Output Features • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Industrial temperature range available Key Specifications 2 - 0.7V current mode differential output pairs (HCSL) • • Cycle-to-cycle jitter < 35ps Output-to-output skew < 25ps Functional Block Diagram CLKREQ0# CLKREQ1# PCIEX0 CLK_INT C LK_IN C SPREAD COMPATIBLE PLL PCIEX1 PLL_BW SMBDAT CONTROL LOGIC SMBCLK IREF IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 1 REV Q 08/27/13 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 PLL_BW CLK_INT CLK_INC vCLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 Power Groups ICS9DB102 Pin Configuration 20 19 18 17 16 15 14 13 12 11 Pin Number VDD GND 5,9,12,16 6,15 9 6 20 19 20 19 VDDA GNDA IREF vCLKREQ1# VDD GND PCIEXT1 PCIEXC1 VDD SMBCLK Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors 20-pin SSOP & TSSOP Pin Description PIN # PIN NAME PIN TYPE 1 PLL_BW IN 2 3 CLK_INT CLK_INC IN IN 4 vCLKREQ0# IN 5 6 7 8 9 10 11 12 13 14 15 16 VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT SMBCLK VDD PCIEXC1 PCIEXT1 GND VDD PWR PWR OUT OUT PWR I/O IN PWR OUT OUT PWR PWR 17 vCLKREQ1# IN 18 IREF OUT 19 20 GNDA VDDA PWR PWR DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high True Input for differential reference clock. Complementary Input for differential reference clock. Output enable for PCI Expres s output pair 0. 0 = enabled, 1 =disabled Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complementary clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complementary clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Output enable for PCI Expres s output pair 1. 0 = enabled, 1 =disabled This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. Ground pin for the PLL c ore. 3.3V power for the PLL core. Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 2 REV Q 08/27/13 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Absolute Max Symbol VDDA VDD Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Ts Tcase Storage Temperature Case Temperature Input ESD protection human body model ESD prot Min GND - 0.5 Max VDD + 0.5V VDD + 0.5V -65 Units V V ° C °C 150 115 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters TA = Tambient; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage Tambcom Tambind VIH Commercial range Industrial range 3.3 V +/-5% 0 -40 2 70 85 VDD + 0.3 °C °C V 1 1 1 Input Low Voltage Input High Current VIL IIH 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated VDD = 3.3 V VSS - 0.3 -5 0.8 5 V uA 1 1 -5 uA 1 -200 uA 1 100 50 101 7 5 4.5 mA mA MHz nH pF pF 1 1 1 1 1 1 1.8 ms 1 Tambient IIL1 Input Low Current IIL2 Operating Supply Current IDD3.3OP Input Frequency 3 Pin Inductance1 Fi Lpin CIN COUT Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Spread Spectrum Modulation Frequency TSTAB tLATOE# PLL Bandwidth BW SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time UNITS NOTES 30 33 kHz 1 Lexmark Modulation 25 45 KHz 1 1 3 cycles 1,2 DIF start after OE# assertion DIF stop after OE# deassertion PLL Bandwidth when PLL_BW=0 PLL Bandwidth when PLL_BW=1 VDD VOLSMBUS IPULLUP 75 27 100 MAX Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock Triangular Modulation fMOD OE# Latency 99 TYP 400 500 1000 KHz 1 2 2.5 3 MHz 1 5.5 0.4 V V mA 1 1 1 2.7 @ IPULLUP SMBus SDATA pin 4 TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Time from deassertion until outputs are >200mV IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 3 REV Q 08/27/13 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair TA = Tambient; VDD = 3.3 V +/-5%; CL PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage Low VLow Max Voltage Vovs Min Voltage Vuds =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω CONDITIONS MIN TYP VO = Vx 3000 Statistical measurement on single ended signal using Measurement on single ended signal using absolute value. 660 -150 Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Tabsmin tr tf d-tr d-tf tpd tpdbyp Input to Output Delay Duty Cycle dt3 Output-to-Output Skew tsk3 Jitter, Cycle to cycle tjcyc-cyc tjcyc-cycbyp 850 150 1150 VT = 50% PLL mode. Measurement from differential wavefrom Additve Jitter in Bypass Mode mV mV 1 1,3 1,3 1,3 1,3 350 550 mV 1,3 12 140 mV 1,3 0 10.0030 10.0533 0 3.7 700 700 125 125 150 4.2 ppm ns ns ns ps ps ps ps ps ns 1,2 2 2 1,2 1 1 1 1 1 1 45 55 % 1 25 ps 1 35 ps 1 30 ps 1 9.9970 9.9970 9.8720 175 175 30 30 PLL Mode. Bypass mode Measurement from differential wavefrom UNITS NOTES Ω -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MAX . Guaranteed by design, not 100% tested in production. 2 The 9DB102 does not add a ppm error to the input clock 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and VOH = 0.7V @ ZO=50Ω. 1 IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 4 REV Q 08/27/13 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PLL Parameters TA = Tambient; Supply Voltage VDD = 3.3 V +/-5% Group Parameter Description Min Typ Max Units Notes PLL Jitter Peaking jpeak-hibw (PLL_BW = 1) 0 1 2.5 dB 1,4 PLL Jitter Peaking jpeak-lobw (PLL_BW = 0) 0 1 2 dB 1,4 PLL Bandwidth PLL Bandwidth pllHIBW pllLOBW (PLL_BW = 1) (PLL_BW = 0) PCIe Gen 1 phase jitter (1.5 - 22 MHz) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band