9DB306BLLF

9DB306 PCI Express Jitter Attenuator Data Sheet GENERAL DESCRIPTION FEATURES The 9DB306 is a high performance 1-to-6 Differential-toLVPECL Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 9DB306 has 2 PLL bandwidth modes. In low bandwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum profile. There is also a high bandwidth mode which sets the PLL bandwidth at 1MHz which will pass more spread spectrum modulation. • Six differential LVPECL output pairs • One differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 140MHz • Input frequency range: 90MHz - 140MHz • VCO range: 450MHz - 700MHz • Output skew: 135ps (maximum) • Cycle-to-Cycle jitter: 30ps (maximum) • RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical) For serdes which have x30 reference multipliers instead of x25 multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1). Output PCIEX0 will always run at the reference clock frequency (usually 100MHz) in desktop PC PCI Express Applications. • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT 1 Disabled 0 Enabled nOE0 ÷5 0 PCIEXT0 nPCIEXC0 1 Buffer CLK nCLK Phase Detector Loop Filter VCO 0 ÷4 1 ÷5 PCIEXT1 nPCIEXC1 0 PCIEXT2 nPCIEXC2 1 FS0 VEE PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VCC nOE0 nOE1 VCC PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PCIEXC0 PCIEXT0 FS0 nCLK CLK PLL_BW VCCA VEE BYPASS FS1 PCIEXT5 PCIEXC5 VCC ÷5 9DB306 Internal Feedback 0 ÷5 1 ÷4 PCIEXT3 nPCIEXC3 0 PCIEXT4 nPCIEXC4 PCIEXT5 nPCIEXC5 1 FS1 BYPASS nOE1 28-Lead TSSOP, 173-MIL 4.4mm x 9.7mm x 0.925mm body package L Package Top View 9DB306 28-Lead, 209-MIL SSOP 5.3mm x 10.2mm x 1.75mm body package F Package Top View 1 Disabled 0 Enabled ©2016 Integrated Device Technology, Inc 1 Revision C February 18, 2016 9DB306 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name 1, 14, 20 Type VEE PCIEXT1, PCIEXC1 PCIEXT2, PCIEXC2 2, 3 4, 5 Power Negative supply pins. Output Differential output pairs. LVPECL interface levels. Output Differential output pairs. LVPECL interface levels. Core supply pins. 6, 9, 15, 28 VCC Power 7, 8 nOE0, nOE1 Input 10, 11 12, 13 16, 17 PCIEXC3, PCIEXT3 PCIEXC4, PCIEXT4 PCIEXC5, PCIEXT5 Description Output enable. When HIGH, forces true outputs (PCIEXTx) to go LOW Pulldown and the inverted outputs (PCIEXCx) to go HIGH. When LOW, outputs are enabled. LVCMOS/LVTTL interface levels. Output Differential output pairs. LVPECL interface levels. Output Differential output pairs. LVPECL interface levels. Output Differential output pairs. LVPECL interface levels. 18 FS1 Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 19 BYPASS Input 21 VCCA Power 22 PLL_BW Input 23 CLK Input Pulldown Non-inverting differential clock input. 24 nCLK Input Pullup/ Inverting differential clock input. V /2 default when left floating. Pulldown 25 FS0 Input Pulldown Bypass select pin. When HIGH, the PLL is in bypass mode, and the device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels. Analog supply pin. Requires 24Ω series resistor. Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. CC Pullup Frequency select pin. LVCMOS/LVTTL interface levels. PCIEXT0, Output Differential output pairs. LVPECL interface levels. PCIEXC0 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 26, 27 TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. RATIO OF OUTPUT FREQUENCY TO INPUT FREQUENCY FUNCTION TABLE, FS0 Inputs Typical Maximum Units TABLE 3B. RATIO OF OUTPUT FREQUENCY TO INPUT FREQUENCY FUNCTION TABLE, FS1 Outputs Inputs Outputs FS0 PCIEX0 PCIEX1 PCIEX2 FS1 PCIEX3 PCIEX4 PCIEX5 0 1 5/4 5/4 0 1 1 1 1 1 1 1 1 5/4 5/4 5/4 TABLE 3C. OUTPUT ENABLE FUNCTION TABLE, nOE0 TABLE 3E. PLL BANDWIDTH FUNCTION TABLE TABLE 3D. OUTPUT ENABLE FUNCTION TABLE, nOE1 TABLE 3F. PLL MODE FUNCTION TABLE Inputs Outputs Inputs Outputs Inputs nOE0 PCIEX0:2 nOE1 PCIEX3:5 PLL_BW 0 Enabled 0 Enabled 0 500kHz 1 Disabled 1 Disabled 1 Disabled 1 1MHz 0 Enabled ©2016 Integrated Device Technology, Inc 2 Bandwidth Inputs BYPASS PLL Mode Revision C February 18, 2016 9DB306 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 49.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±10%, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.97 3.3 3.63 V VCC – 0.60 3.3 VCCA Analog Supply Voltage VCC V ICC Power Supply Current 135 mA ICCA Analog Supply Current 25 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±10%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions nOE0, nOE1, FS1, BYPASS Minimum Maximum Units 2 Typical VCC + 0.3 mV -0.3 0.8 mV 150 µA 5 µA VCC = VIN = 3.63V FS0, PLL_BW IIL Input Low Current nOE0, nOE1, FS1, BYPASS VCC = 3.63V, VIN = 0V FS0, PLL_BW -5 µA -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±10%, TA = 0°C TO 70°C Symbol Parameter Maximum Units IIH Input High Current CLK, nCLK Test Conditions VCC = VIN = 3.63V Minimum Typical 150 µA IIL Input Low Current CLK, nCLK VCC = 3.63V, VIN = 0V 150 µA VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V VEE + 0.5 VCC - 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. ©2016 Integrated Device Technology, Inc 3 Revision C February 18, 2016 9DB306 Data Sheet TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±10%, TA = 0°C TO 70°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 0.6 1.0 V Maximum Units 140 MHz 135 ps 25 ps NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tsk(o) Output Skew; NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter, NOTE 2 tjit(Ø) RMS Phase Jitter (Random); NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 55 Integration Range: 1.5MHz - 22MHz 20% to 80% 3 ps 200 700 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot following this section. TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V±10%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tsk(o) Output Skew; NOTE 1, 2 tjit(cc) Cycle-to-Cycle Jitter, NOTE 2 tjit(Ø) RMS Phase Jitter (Random); NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 25 Integration Range: 1.5MHz - 22MHz 20% to 80% Maximum Units 140 MHz 100 ps 30 ps 3 ps 200 700 ps 47 53 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot following this section. ©2016 Integrated Device Technology, Inc 4 Revision C February 18, 2016 9DB306 Data Sheet TYPICAL PHASE NOISE AT 100MHZ ➤ 0 -10 -20 PCI Express™ Filter -30 -40 100MHz -50 RMS Phase Jitter (Random) 1.5MHz to 22MHz = 3ps (typical) -70 -80 -90 -100 Raw Phase Noise Data -110 -120 ➤ NOISE POWER dBc Hz -60 -130 -140 ➤ -150 -160 Phase Noise Result by adding PCI Express™ Filter to raw data -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the PLL, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance. The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under test. Due ©2016 Integrated Device Technology, Inc 5 Revision C February 18, 2016 9DB306 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2016 Integrated Device Technology, Inc 6 Revision C February 18, 2016 9DB306 Data Sheet APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 9DB306 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 24Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 24Ω .01µF 10µF VCCA FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT ©2016 Integrated Device Technology, Inc 7 Revision C February 18, 2016 9DB306 Data Sheet DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN IDT LVHSTL DRIVER FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE ©2016 Integrated Device Technology, Inc 8 Revision C February 18, 2016 9DB306 Data Sheet TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used FIGURE 4A. LVPECL OUTPUT TERMINATION FIGURE 4B. LVPECL OUTPUT TERMINATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ©2016 Integrated Device Technology, Inc LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 9 Revision C February 18, 2016 9DB306 Data Sheet SCHEMATIC EXAMPLE F i g u r e 5 s h ow s a n ex a m p l e o f 9 D B 3 0 6 a p p l i c a t i o n schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a HCSL driver. For LVPECL output drivers, one of terminations approaches is shown in this schematic. For additional termination approaches, please refer to the LVPECL Termination Application Note. Zo = 50 VCC + R11 1K VCC R7 Zo = 50 - 24 VCCA LVPECL U1 ICS9DB306 VCC C16 10uF 33 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Zo = 50 Zo = 50 HCSL R13 33 R1 50 R4 50 C11 0.1uF VCC R12 VCC R2 50 VCC PCIEXC5 PCIEXT5 FS1 BY PASS VEE VCCA PLL_BW CLK nCLK FS0 PCIEXT0 PCIEXC0 VCC VEE PCIEXT4 PCIEXC4 PCIEXT3 PCIEXC3 VCC nOE1 nOE0 VCC PCIEXC2 PCIEXT2 PCIEXC1 PCIEXT1 VEE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R5 50 R6 50 R8 1K R10 1K R9 1K Zo = 50 + Zo = 50 (U1-15) VCC (U1-28) (U1-6) LVPECL (U1-9) R14 50 VCC=3.3V C1 0.1uF C2 0.1uF C3 0.1uF R15 50 C3 0.1uF R16 50 FIGURE 5. EXAMPLE OF 9DB306 SCHEMATIC ©2016 Integrated Device Technology, Inc 10 Revision C February 18, 2016 9DB306 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 9DB306. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 9DB306 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 135mA = 490.1mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW Total Power_MAX (3.63V, with all outputs switching) = 490.1mW + 180mW = 670.1mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.670W * 43.9°C/W = 99.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 28-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 82.9°C/W 49.8°C/W 200 68.7°C/W 43.9°C/W 500 60.5°C/W 41.2°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ©2016 Integrated Device Technology, Inc 11 Revision C February 18, 2016 9DB306 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC- 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc 12 Revision C February 18, 2016 9DB306 Data Sheet RELIABILITY INFORMATION TABLE 7A. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP PACKAGE θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 82.9°C/W 49.8°C/W 200 500 68.7°C/W 43.9°C/W 60.5°C/W 41.2°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7B. θJAVS. AIR FLOW TABLE FOR 28 LEAD SSOP PACKAGE θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 49°C/W 36°C/W 30°C/W TRANSISTOR COUNT The transistor count for 9DB306 is: 2190 ©2016 Integrated Device Technology, Inc 13 Revision C February 18, 2016 9DB306 Data Sheet PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP PACKAGE OUTLINE - F SUFFIX FOR 28 LEAD SSOP TABLE 8A. PACKAGE DIMENSIONS TABLE 8B. PACKAGE DIMENSIONS SYMBOL Millimeters Millimeters Minimum N Maximum Minimum 28 N A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 9.60 9.80 E E1 SYMBOL 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 α aaa Maximum 28 A -- 2.0 A1 0.05 -- A2 1.65 1.85 b 0.22 0.38 c 0.09 0.25 D 9.90 10.50 E 7.40 8.20 E1 5.0 5.60 0.75 e 0° 8° L 0.55 0.95 -- 0.10 α 0° 8° Reference Document: JEDEC Publication 95, MO-153 ©2016 Integrated Device Technology, Inc 0.65 BASIC Reference Document: JEDEC Publication 95, MO-150 14 Revision C February 18, 2016 9DB306 Data Sheet TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 9DB306BLLF ICS9DB306BLLF 28 Lead “Lead-Free” TSSOP Tube 0°C to 70°C 9DB306BLLFT ICS9DB306BLLF 28 Lead “Lead-Free” TSSOP tape & reel 0°C to 70°C 9DB306BFLF ICS9DB306BFLF 28 Lead “Lead-Free” SSOP Tube 0°C to 70°C 9DB306BFLFT ICS9DB306BFLF 28 Lead “Lead-Free” SSOP tape & reel 0°C to 70°C ©2016 Integrated Device Technology, Inc 15 Revision C February 18, 2016 9DB306 Data Sheet REVISION HISTORY SHEET Rev A Table Page T3F 2 Added PLL Mode Function Table. 4/7/05 3 Power Supply Table - minimum VCCA changed from 3.135V to VCC - 0.60V, and maximum set to VCC. Corrected 3.3V Output Load AC Test Circuit diagram to correspond with Power Supply table. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free SSOP part number. 6/16/06 Features Section - added Input Frequency Range and VCO Range bullets. 7/14/06 Changed power supply from 3.3V±5% to 3.3V±10% throughout the datasheet. AC Characteristics Table - changed Output Skew from 55ps typ./135ps max. to 25ps typ./100ps max. Changed Cycle-toCycle Jitter from 25ps max. to 30ps max. Changed Output Duty Cycle from 48% min./52% max. to 47% min./53% max. Power Considerations - correct Power Dissipation to coincide with the power supply change. 9/22/06 6 T9 B 8 15 1 T5 4 C 11 T4C T5A - T5B C T9 3 4 7 8 9 15 14 C C Date T4A B C Description of Change T9 15 T9 15 Differential DC Characteristics Table - updated notes. AC Characteristics Tables - added thermal note. Power Supply Filtering Techniques - deleted last line “ The 10ohm resistor can also be replaced by a ferrite bead.” Updated Differential Clock Input Interface section. Updated Figures 4A and 4B. Ordering Information Table - deleted ICS prefix in Part/Order Number column. Added 28 Lead SSOP Lead-free marking. Package Information - Table 8A and 8B corrected D and N dimensions. Ordering Information - removed leaded devices. Updated data sheet format. Ordering Information - removed quantities in tape and reel. Deleted LF note below table. Updated header and footer. ©2016 Integrated Device Technology, Inc 16 8/13/09 3/14/12 7/24/15 2/18/16 Revision C February 18, 2016 Part Number Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. 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