9DB633AGLF

DATASHEET Six Output Differential Buffer for PCIe Gen3 9DB633 Features/Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low EMI • SMBus Interface/unused outputs can be disabled Recommended Application: 6 output PCIe Gen3 zero-delay/fanout buffer General Description: The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications. Output Features: • 6 - 0.7V current mode differential HCSL output pairs Key Specifications: • Cycle-to-cycle jitter < 50 ps • Output-to-output skew < 50 ps • PCIe Gen3 phase jitter < 1.0ps RMS Block Diagram OE1# OE4# DIF1 SRC_IN SRC_IN# SPREAD COMPATIBLE PLL DIF4 PLL_BW SMBDAT SMBCLK DIF(0,2,3,5) CONTROL LOGIC IREF IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 1 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet PLL_BW SRC_IN SRC_IN# vOE1# DIF_0 DIF_0# VDD GND DIF_1 DIF_1# DIF_2 DIF_2# VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 9DB633 Pin Configuration 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VD DA GNDA IREF vOE4# DIF_5 DIF_5# VD D GND DIF_4 DIF_4# DIF_3 DIF_3# VD D SMBCLK Note:Pins preceeded by ' v ' have internal 120K ohm pull down resistors Power Distribution Table Pin Number VDD GND 7, 13, 16, 22 8,21 13 8 N/A 27 28 27 Description Differential Outputs SMBus IREF Analog VDD & GND for PLL core IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 2 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Pin Description PIN # PIN NAME PIN TYPE 1 PLL_BW IN 2 3 SRC_IN SRC_IN# IN IN 4 vOE1# IN 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DIF_0 DIF_0# VDD GND DIF_1 DIF_1# DIF_2 DIF_2# VDD SMBDAT SMBCLK VDD DIF_3# DIF_3 DIF_4# DIF_4 GND VDD DIF_5# DIF_5 25 vOE4# OUT OUT PWR IN OUT OUT OUT OUT PWR I/O IN PWR OUT OUT OUT OUT PWR PWR OUT OUT IN 26 IREF OUT 27 28 GNDA VDDA PWR PWR DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power suppl y, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Power suppl y, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power suppl y, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output Ground pin. Power suppl y, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Active low input for enabling DIF pair 4. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs This pi n establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. Ground pin for the PLL core. 3.3V power for the PLL core. Note: Pins preceeded by ' v ' have internal 120K ohm pull down resistors IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 3 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage VDDA VDD VIL VIH VIHSMB Storage Temperature Junction Temperature Input ESD protection Ts Tj ESD prot CONDITIONS MIN TYP UNITS NOTES MAX 4.6 4.6 V V V V V GND-0.5 Except for SMBus interface SMBus clock and data pins VDD+0.5V 5.5V -65 Human Body Model 1,2 1,2 1 1 1 1 1 1 ° 150 125 C °C V 2000 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Ambient Operating Temperature TCOM TIND Input High Voltage VIH Input Low Voltage VIL I IN Input Current Input Frequency Pin Inductance Capacitance IINP Fibyp Fipll Lpin CIN CINDIF_IN CONDITIONS MIN Commmercial range Industrial range Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, VIN = GND, VIN = VDD 0 -40 TYP MAX 70 85 UNITS NOTES °C °C 1 1 2 VDD + 0.3 V 1 GND - 0.3 0.8 V 1 -5 5 uA 1 Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 VDD = 3.3 V, Bypass mode VDD = 3.3 V, 100MHz PLL mode 10 33 Logic Inputs, except DIF_IN DIF_IN differential clock inputs 1.5 1.5 110 110 7 5 2.7 MHz MHz nH pF pF 2 2 1 1 1,4 100.00 COUT Output pin capacitance 6 pF 1 Clk Stabilization TSTAB From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 1.8 ms 1,2 Input SS Modulation Frequency f MODIN Allowable Frequency (Triangular Modulation) 30 33 kHz 1 OE# Latency t LATOE# 1 3 cycles 1,3 Tdrive_PD# t DRVPD Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of control inputs Rise time of control inputs VILSMB V IHSMB VOLSMB I PULLUP VDDSMB t RSMB t FSMB @ I PULLUP @ VOL 3V to 5V +/- 10% (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) f MAXSMB Maximum SMBus operating frequency 2.1 4 2.7 300 us 1,3 5 5 0.8 5.5 1000 300 ns ns V V V mA V ns ns 1,2 1,2 1 1 1 1 1 1 1 100 kHz 1,5 VDDSMB 0.4 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 DIF_IN input 2 5 The differential input clock must be running for the SMBus to be active IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 4 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Electrical Characteristics - DIF_IN Clock Input Parameters TAMB=TCOM or TIND unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER Input Crossover Voltage DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN SYMBOL CONDITIONS MIN TYP MAX VCROSS Cross Over Voltage 150 375 900 V SWING Differential value 300 dv/dt Measured differentially 1 UNITS NOTES mV 1 mV 1 8 V/ns 1,2 Input Leakage Current I IN V IN = VDD , V IN = GND -5 5 uA Input Duty Cycle dtin Measurement from differential wavefrom 45 55 % 1 Input Jitter - Cycle to Cycle J DIFIn Differential Measurement 0 125 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Slew rate Slew rate matching Trf Trf CONDITIONS MIN TYP MAX UNITS NOTES V/ns 1, 2, 3 % 1, 2, 4 Scope averaging on 0.6 2.5 4 9.5 20 Slew rate matching, Scope averaging on Statistical measurement on single-ended signal Voltage High VHigh 660 740 850 1 using oscilloscope math function. (Scope averaging mV Voltage Low VLow -150 8 150 1 on) Measurement on single ended signal using absolute Vmax 760 1150 1 Max Voltage mV value. (Scope averaging off) Vmin -300 -3 1 Min Voltage Vswing Vswing Scope averaging off 300 1506 mV 1, 2 Vcross_abs Scope averaging off 250 378 550 mV 1, 5 Crossing Voltage (abs) -Vcross Crossing Voltage (var) Scope averaging off 54 140 mV 1, 6 1 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100 differential impedance). 2 Measured from differential waveform Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 3 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics - Current Consumption TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Operating Supply Current Powerdown Current 1 I DD3.3OP I DD3.3PD I DD3.3PDZ CONDITIONS All outputs active @100MHz, CL = Full load; All diff pairs driven All differential pairs tri-stated MIN TYP MAX 134 150 N/A N/A UNITS NOTES mA mA mA 1 1 1 Guaranteed by design and characterization, not 100% tested in production. IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 5 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX PLL Bandwidth BW PLL Jitter Peaking Duty Cycle Duty Cycle Distortion 2 0.4 t JPEAK t DC -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain Measured differentially, PLL Mode 45 2.3 0.5 1 48 4 1 2 55 MHz MHz dB % 1 1 1 1 t DCD Measured differentially, Bypass Mode @100MHz -2 1 2 % 1,4 Jitter, Cycle to cycle t jcyc-cyc Bypass Mode, VT = 50% Hi BW PLL Mode VT = 50% VT = 50% PLL mode Additive Jitter in Bypass Mode 2500 -250 Skew, Output to Output t pdBYP t pdPLL t sk3 3660 0 15 40 10 4500 250 50 50 50 ps ps ps ps ps 1 1 1 1,3 1,3 Skew, Input to Output UNITS NOTES 1 Guaranteed by design and characterization, not 100% tested in production. I REF = V DD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and VOH = 0.7V @ ZO=50Ω. 3 Measured from differential waveform 4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 2 Electrical Characteristics - PCIe Phase Jitter Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Phase Jitter, PLL Mode SYMBOL t jphPCIeG1 t jphPCIeG2 t jphPCIeG3 t jphPCIeG1 Additive Phase Jitter, Bypass Mode t jphPCIeG2 t jphPCIeG3 CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) MIN TYP 32 MAX 86 1.1 3 2.3 3.1 0.5 1 2 5 0.2 0.3 0.8 1 0.1 0.2 UNITS Notes ps (p-p) 1,2,3 ps 1,2 (rms) ps 1,2 (rms) ps 1,2,4 (rms) ps (p-p) ps (rms) ps (rms) ps (rms) 1,2,3 1,2 1,2 1,2,4 1 Applies to all outputs. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 2 IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 6 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT® Six Output Differential Buffer for PCIe Gen3 PCI Express Add-in Board REF_CLK Input L3 1668F—10/20/16 7 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® Six Output Differential Buffer for PCIe Gen3 PCIe Device REF_CLK Input 1668F—10/20/16 8 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet General SMBus serial interface information for the 9DB633 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controlle r (Host) starT bit T Slave A ddress D4(H ) W Rite WR Controller (Host) T starT bit Slave Address D4(H) WR WRite ICS (Sla ve /Re ce ive r) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK Data By te Count = X RT Repeat starT Slave Address D5(H) RD ReaD ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDT® Six Output Differential Buffer for PCIe Gen3 Not acknowledge stoP bit 1668F—10/20/16 9 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet SMBusTable: Device Control Register, READ/WRITE ADDRESS (D5/D4) Byte 0 0 1 Default Pin # Name Control Function Type Enables SMBus PLL controlled PLL controlled 1 SW_EN Control of bits RW by SMBus Bit 7 by device pins (1:0) registers RW X RESERVED Bit 6 RW X RESERVED Bit 5 RW X RESERVED Bit 4 RW X RESERVED Bit 3 RESERVED RW X Bit 2 Selects PLL PLL BW #adjust RW Low BW High BW 1 Bit 1 Bandwidth Bypasses PLL for PLL bypassed PLL enabled PLL Enable RW 1 Bit 0 board test (fan out mode) (ZDB mode) SMBusTable: Output Enable Byte 1 Pin # Bit 7 Bit 6 24,23 Bit 5 Bit 4 18,17 Bit 3 11,12 Bit 2 Bit 1 5,6 Bit 0 Register Name Control Function Type RESERVED RW RESERVED RW PCIEX5 Output Control RW RESERVED RW PCIEX3 Output Control RW PCIEX2 Output Control RW RW RESERVED PCIEX0 Output Control RW SMBusTable: Function Select Register Byte 2 Pin # Name Control Function Type RESERVED RW Bit 7 RESERVED RW Bit 6 RESERVED RW Bit 5 RESERVED RW Bit 4 RESERVED RW Bit 3 RW RESERVED Bit 2 RW RESERVED Bit 1 RESERVED RW Bit 0 SMBusTable: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type RID3 R Bit 7 RID2 R Bit 6 REVISION ID RID1 R Bit 5 RID0 R Bit 4 VID3 R Bit 3 VID2 R Bit 2 VENDOR ID VID1 R Bit 1 VID0 R Bit 0 IDT® Six Output Differential Buffer for PCIe Gen3 0 1 - Disable Enable - Disable Disable Enable Enable - Disable Enable 0 1 Default X X X X X X X X 1 - Default 0 0 0 1 0 0 0 1 - 0 - Default X X 1 X 1 1 X 1 1668F—10/20/16 10 9DB633 Six Output Differential Buffer for PCIe Gen3 SMBusTable: DEVICE ID Pin # Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Datasheet Control Function Type R R R Device ID R = 06 Hex R R R R 0 1 Default 0 0 0 0 0 1 1 0 - SMBusTable: Byte Count Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - Name Control Function Type 0 1 Default BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 0 1 1 0 IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 11 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet 28-pin SSOP Package Drawing and Dimensions 209 mil SSOP SYMBOL A A1 A2 b c D E E1 e L N α In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° VARIATIONS N 28 D mm. MIN 9.90 D (inch) MAX 10.50 MIN .390 MAX .413 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 209 mil SSOP IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 12 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet 28-pin TSSOP Package Drawing and Dimensions 4.40 mm. Body, 0.65 mm. Pitch TSSOP c N (173 mil) SYMBOL L E1 INDEX AREA A A1 A2 b c D E E1 e L N α aaa E 1 2 a D In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS A A2 (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 N A1 28 D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 MAX .386 -CReference Doc.: JEDEC Publication 95, MO-153 e SEATING PLANE b 10-0035 aaa C Ordering Information Part / Order Number Shipping Packaging 9DB633AFLF Tubes 9DB633AFLFT Tape and Reel 9DB633AFILF Tubes 9DB633AFILFT Tape and Reel 9DB633AGLF Tubes 9DB633AGLFT Tape and Reel 9DB633AGILF Tubes 9DB633AGILFT Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C "LF" after the package code are the Pb-Free configuration and are RoHS compliant. "A" is the device revision designator (will not correlate to the datasheet revision). IDT® Six Output Differential Buffer for PCIe Gen3 1668F—10/20/16 13 9DB633 Six Output Differential Buffer for PCIe Gen3 Datasheet Revision History Rev. A B C Originator Issue Date RDW 6/30/2010 RDW 7/12/2010 RDW 4/20/2011 D E RDW RDW F RDW Description Released to final Changed "PWD" to "Default" in SMBus Register descriptions Changed pull down indicator from '**' to 'v'. Corrected typo for 28SSOP T&R orderable part number; "I" and "L" were 10/22/2013 swapped. 2/19/2014 Corrected typo for Read/Write address from D4/D5 to D5/D4 respectively Updated input clock electrical table to latest format. No change to form, fit or 10/20/2016 function of the device Page # 10,11 13 9,10 5 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 www.idt.com/go/support Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 14 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.