9DBL0252BKILF

2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Description Features The 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 buffers are low-power, high-performance members of Renesas' full featured PCIe family. The buffers support PCIe Gen1 through Gen5. ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference (IR) with and without spread spectrum (SRIS, SRNS) Typical Applications ▪ ▪ ▪ ▪ ▪ PCIe Riser Cards nVME Storage Networking Accelerators Industrial Control/Embedded 9DBLxx4x devices provide integrated 100Ω terminations 9DBLxx5x devices provide integrated 85Ω terminations See AN-891 for easy coupling to other logic families Spread-spectrum compatible Dedicated OE# pin for each output 1MHz to 200MHz operation in fan-out mode 3 selectable SMBus addresses Extensive SMBus-selectable features allow optimization to customer requirements ▪ SMBus interface not required for device operation ▪ -40°C to +85°C operating temperature range ▪ Space-saving 4 × 4 mm 24-VFQFPN to 6 × 6 mm 48-VFQFPN packages (see Ordering Information table for details) Key Specifications ▪ Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode) ▪ PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode) Block Diagram FB_DNC# FB_DNC# PLL CLK_IN# DIFn# CLK_IN DIFn vSADR_tri SCLK_3.3 SDATA_3.3 SMBus Factory Engine Configuration DIF0# ^vHIBW_BYPM-LOBW# ^CKPWRGD_PD# vOE[n:0]# 2, 4, 6, 8 Outputs n = 1, 3, 5, 7 n+1 ©2021 Renesas Electronics Corporation DIF0 Control Logic 1 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9DBL02x2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9DBL04x2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9DBL06x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9DBL08x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9DBL02x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9DBL04x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9DBL06x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9DBL08x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ©2021 Renesas Electronics Corporation 2 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Pin Assignments 9DBL02x2 Pin Assignment vOE1# NC VDDO3.3 ^CKPWRGD_PD# vSADR_tri ^vHIBW_BYPM_LOBW# Figure 1. Pin Assignment for 4 × 4 mm 24-VFQFPN Package – Top View 24 23 22 21 20 19 1 2 3 4 5 6 18 17 16 15 14 13 DIF1# DIF1 VDDA3.3 vOE0# DIF0# DIF0 NC NC 9 10 11 12 VDDO3.3 8 SCLK_3.3 7 VDDDIG3.3 9DBL0242 9DBL0252 epad is GND SDATA_3.3 FB_DNC FB_DNC# VDDR3.3 CLK_IN CLK_IN# GNDDIG 9DBL04x2 Pin Assignment vSADR_tri ^CKPWRGD_PD# NC vOE3# DIF3# DIF3 NC VDDO3.3 Figure 2. Pin Assignment for 5 × 5 mm 32-VFQFPN Package – Top View 32 31 30 29 28 27 26 25 ^vHIBW_BYPM _LOBW# 1 FB_DNC 2 FB_DNC# 3 VDDR3.3 4 CLK_IN 5 CLK_IN# 6 24 vOE2# 23 DIF2# 9DBL0442 9DBL0452 epad is GND 22 DIF2 21 VDDA3.3 20 NC 19 vOE1# 18 DIF1# 17 DIF1 NC 7 GNDDIG 8 SCLK_3.3 SDATA_3.3 VDDDIG3.3 vOE0# DIF0 DIF0# VDDO3.3 NC 9 10 11 12 13 14 15 16 ©2021 Renesas Electronics Corporation 3 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet 9DBL06x1 Pin Assignment VDD3.3 VDDIO DIF4 DIF4# vOE4# DIF5 DIF5# vOE5# VDDIO ^CKPWRGD_PD# Figure 3. Pin Assignment for 5 × 5 mm 40-VFQFPN Package – Top View 40 39 38 37 36 35 34 33 32 31 vSADR_tri 1 ^vHIBW_BYPM _LOBW# 2 30 NC 29 vOE3# FB_DNC 3 FB_DNC# 4 28 DIF3# 27 DIF3 9DBL0641 9DBL0651 epad is GND VDDR3.3 5 CLK_IN 6 CLK_IN# 7 GNDDIG 8 26 VDDIO 25 VDDA3.3 24 vOE2# 23 DIF2# SCLK_3.3 9 SDATA_3.3 10 22 DIF2 21 vOE1# NC DIF1# DIF1 VDDIO VDD3.3 DIF0# DIF0 vOE0# VDDIO VDDDIG3.3 11 12 13 14 15 16 17 18 19 20 9DBL08x1 Pin Assignment vOE5# VDD3.3 VDDIO GND DIF6 DIF6# vOE6# DIF7 DIF7# vOE7# VDDIO ^CKPWRGD_PD# Figure 4. Pin Assignment for 6 × 6 mm 48-VFQFPN Package – Top View 48 47 46 45 44 43 42 41 40 39 38 37 vSADR_tri ^vHIBW_BYPM _LOBW# FB_DNC FB_DNC# VDDR3.3 CLK_IN CLK_IN# 1 36 DIF5# 2 35 DIF5 3 34 vOE4# 4 33 DIF4# GNDR GNDDIG SCLK_3.3 SDATA_3.3 VDDDIG3.3 8 5 32 DIF4 9DBL0841 9DBL0851 epad is GND 6 7 31 VDDIO 30 VDDA3.3 29 GNDA 9 28 vOE3# 10 27 DIF3# 11 26 DIF3 12 25 vOE2# ©2021 Renesas Electronics Corporation 4 DIF2# DIF2 GND VDDIO VDD3.3 DIF1# DIF1 vOE1# DIF0# DIF0 vOE0# VDDIO 13 14 15 16 17 18 19 20 21 22 23 24 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Pin Descriptions Table 1. Pin Descriptions Pin Name [a] [b] [c] ^CKPWRGD_PD# ^vHIBW_BYPM_LOBW# Type Description 08x1 Pin No. 06x1 Pin No. 04x2 Pin No. 02x2 Pin No. Input Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal 120kΩ pull-up resistor. 48 40 31 22 Latched In Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2 (Bypass mode) with internal pull-up/pull-down resistors. 2 2 1 24 CLK_IN Input True input of differential input clock. 6 6 5 4 CLK_IN# Input Complementary input if differential input clock. 7 7 6 5 DIF0 Output Differential true clock output. 15 14 13 13 DIF0# Output Differential complementary clock output. 16 15 14 14 DIF1 Output Differential true clock output. 18 18 17 17 DIF1# Output Differential complementary clock output. 19 19 18 18 DIF2 Output Differential true clock output. 23 22 22 – DIF2# Output Differential complementary clock output. 24 23 23 – DIF3 Output Differential true clock output. 26 27 27 – DIF3# Output Differential complementary clock output. 27 28 28 – DIF4 Output Differential true clock output. 32 33 – – DIF4# Output Differential complementary clock output. 33 34 – – DIF5 Output Differential true clock output. 35 36 – – DIF5# Output Differential complementary clock output. 36 37 – – DIF6 Output Differential true clock output. 41 – – – DIF6# Output Differential complementary clock output. 42 – – – DIF7 Output Differential true clock output. 44 – – – DIF7# Output Differential complementary clock output. 45 – – – EPAD GND Connect to ground. 49 41 33 25 DNC True clock of differential feedback. The feedback output and feedback input are connected internally on this pin. Do not connect anything to this pin. 3 3 2 1 FB_DNC# DNC Complement clock of differential feedback. The feedback output and feedback input are connected internally on this pin. Do not connect anything to this pin. 4 4 3 2 GND GND Ground pin. 22, 40 – – – GND GND Ground pin. 40 – – – FB_DNC ©2021 Renesas Electronics Corporation 5 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 1. Pin Descriptions (Cont.) Pin Name [a] [b] [c] Type Description 08x1 Pin No. 06x1 Pin No. 04x2 Pin No. 02x2 Pin No. GNDA GND Ground pin for the PLL core. 29 – – – GNDDIG GND Ground pin for digital circuitry. 9 8 8 6 GNDR GND Analog ground pin for the differential input (receiver). 8 – – – No connection. - 20, 30 7, 16, 20, 26, 30 11, 12, 20 NC SCLK_3.3 SDATA_3.3 – Input Clock pin of SMBus circuitry, 3.3V tolerant. 10 9 9 9 I/O Data pin for SMBus circuitry, 3.3V tolerant. 11 10 10 7 VDD3.3 Power Power supply, nominal 3.3V. 20, 38 16, 31 – – VDDA3.3 Power 3.3V power for the PLL core. 30 25 21 16 VDDDIG3.3 Power 3.3V digital power (dirty power). 12 11 11 8 VDDIO Power Power supply for differential outputs. 13, 21, 31, 39, 47 12, 17, 26, 32, 39 – – VDDO3.3 Power Power supply for outputs. Nominally 3.3V. – – 15, 25 10, 21 VDDR3.3 Power 3.3V power for differential input clock (receiver). This VDD should be treated as an Analog power rail and filtered appropriately. 5 5 4 3 vOE0# Input Active low input for enabling output 0. This pin has an internal 120kohm pull-down. 1 =disable outputs, 0 = enable outputs 14 13 12 15 vOE1# Input Active low input for enabling output 1. This pin has an internal 120kΩ pull-down. 1 =disable outputs, 0 = enable outputs 17 21 19 19 vOE2# Input Active low input for enabling output 2. This pin has an internal 120kΩ pull-down. 1 =disable outputs, 0 = enable outputs 25 24 24 – vOE3# Input Active low input for enabling output 3. This pin has an internal 120kΩ pull-down. 1 =disable outputs, 0 = enable outputs 28 29 29 – Latched In Tri-level latch to select SMBus Address. It has an internal pull-down resistor. See the SMBus Address Selection table. 1 1 32 23 vSADR_tri [a] A ‘^’ prefix indicates internal 120kΩ pull-up resistor. [b] A ‘^v’ prefix indicates internal 120kΩ pull-up and pull-down resistor (biased to VDD/2). [c] A ‘v’ prefix indicates internal 120kΩ pull-down resistor. ©2021 Renesas Electronics Corporation 6 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Table 2. Absolute Maximum Ratings[a] Symbol Parameter VDDx Supply Voltage[b] VIN Input Voltage[c] VIHSMB Input High Voltage, SMBus Ts Storage Temperature Tj Junction Temperature ESD prot Input ESD Protection Conditions Applies to VDD, VDDA and VDDIO. Minimum Maximum Units -0.5 3.9 V -0.5 VDD + 0.5 V 3.9 V 150 °C 125 °C SMBus clock and data pins. -65 Human Body Model. 2000 Typical V [a] Guaranteed by design and characterization, not 100% tested in production. [b] Operation under these conditions is neither implied nor guaranteed. [c] Not to exceed 3.9V. ©2021 Renesas Electronics Corporation 7 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Electrical Characteristics Table 3. Additive PCIe Phase Jitter (Fan-out Buffer Mode) [a] [b] Conditions Minimum Typical Maximum Industry Limit PCIe Gen1 (2.5 GT/s) SSC < -0.5% – 2.6 5.0 86 ps (pk-pk) PCIe Gen2 Hi Band (5.0 GT/s) SSC < -0.5% – 0.357 0.428 3.1 ps (RMS) PCIe Gen2 Lo Band (5.0 GT/s) SSC < -0.5% – 0.023 0.033 3 ps (RMS) PCIe Gen3 (8.0 GT/s) SSC < -0.5% – 0.091 0.149 1 ps (RMS) tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) [c] [d] SSC < -0.5% – 0.092 0.156 0.5 ps (RMS) tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) [c] [e] SSC < -0.5% – 0.031 0.059 0.15 ps (RMS) tjphPCIeG1-SRIS PCIe Gen1 (2.5 GT/s) SSC < -0.3% – N/A N/A N/A ps (pk-pk) tjphPCIeG2-SRIS PCIe Gen2 Band (5.0 GT/s) SSC < -0.3% – 0.455 0.524 N/A ps (RMS) PCIe Gen3 (8.0 GT/s) SSC < -0.3% – 0.131 0.150 N/A ps (RMS) tjphPCIeG4-SRIS PCIe Gen4 (16.0 GT/s) [c] [d] SSC < -0.3% – 0.111 0.128 N/A ps (RMS) tjphPCIeG5-SRIS PCIe Gen5 (32.0 GT/s) [c] [e] SSC < -0.3% – 0.040 0.045 N/A ps (RMS) Symbol Parameter tjphPCIeG1-CC tjphPCIeG2-CC tjphPCIeG3-CC tjphPCIeG3-SRIS Additive PCIe Phase Jitter (Common Clocked Architecture) Additive PCIe Phase Jitter (SRIS Architecture) [f] ©2021 Renesas Electronics Corporation 8 Units April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 4. PCIe Phase Jitter (Zero-Delay Buffer Mode)[a] [b] Conditions Minimum Typical Maximum Industry Limit PCIe Gen1 (2.5 GT/s), SSC < -0.5% Any BW ZDB Mode – 23 33 86 ps (pk-pk) PCIe Gen2 Hi Band (5.0 GT/s), SSC < -0.5%, Any BW ZDB Mode – 1.4 1.9 3.1 ps (RMS) PCIe Gen2 Lo Band (5.0 GT/s), SSC < -0.5%, Any BW ZDB Mode – 0.5 0.81 3 ps (RMS) PCIe Gen3 (8.0 GT/s), SSC < -0.5%, High BW ZDB Mode – 0.28 0.53 1 ps (RMS) tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) [c] [d] SSC < -0.5%, High BW ZDB Mode – 0.26 0.48 0.5 ps (RMS) tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) [c] [e], SSC < -0.5%, High BW ZDB Mode – 0.07 0.149 0.15 ps (RMS) tjphPCIeG1-SRIS PCIe Gen1 (2.5 GT/s), SSC < -0.5% High BW ZDB Mode – N/A N/A N/A ps (pk-pk) PCIe Gen2 (5.0 GT/s), SSC < -0.5% High BW ZDB Mode – 0.99 1.23 N/A ps (RMS) PCIe Gen3 (8.0 GT/s), SSC < -0.5% High BW ZDB Mode – 0.61 0.69 N/A ps (RMS) Symbol Parameter tjphPCIeG1-CC tjphPCIeG2-CC tjphPCIeG3-CC tjphPCIeG2-SRIS PCIe Phase Jitter (Common Clocked Architecture) PCIe Phase Jitter (SRIS Architecture) [f] tjphPCIeG3-SRIS Units [a] The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The total Ref Clk jitter limits for each data rate are listed for convenience. Jitter may be subtracted from the limit using RSS subtraction to determine remaining margin. Guaranteed by design and characterization, not 100% tested in production. [b] Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results the RTO result must be used. [c] SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content. [d] Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. [e] Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. [f] While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specification limits, hence the N/A in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by 2. It is up to the user to divide the clock output budget or the clock input budget by 2 to arrive at a target limit. ©2021 Renesas Electronics Corporation 9 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 5. 12kHz to 20MHz Phase Jitter [a] [b] Symbol Parameter Conditions Minimum Typical Maximum Units tjph156M12k-20 Additive Phase Jitter, Fanout Mode 156.25MHz, 12kHz to 20MHz. – 363 – fs (rms) [a] Guaranteed by design and characterization, not 100% tested in production. [b] Additive jitter is calculated using Root-Sum-Square (RSS) subtraction. Table 6. Clock Input Parameters Symbol Parameter Conditions Minimum Typical Maximum Units VCROSS Input Crossover Voltage [a] Crossover voltage. 150 – 900 mV Differential value. 300 – Measured differentially. 0.4 – 8 V/ns VIN = VDD , VIN = GND. -5 – 5 μA 45 – 55 % 0 – 125 ps Conditions Minimum Typical Maximum Units -3dB point in High BW Mode (100MHz). 2 3.3 4 MHz -3dB point in Low BW Mode (100MHz). 1 1.5 2 MHz 0.8 2 dB VSWING dv/dt IIN dtin JDIFIn [a] Input Swing Input Slew Rate [a] [b] Input Leakage Current Input Duty Cycle [a] Input Jitter – Cycle to Cycle [a] Differential measurement. mV [a] Guaranteed by design and characterization, not 100% tested in production. [b] Slew rate measured through ±75mV window centered around differential zero. Table 7. Output Duty Cycle, Skew and PLL Characteristics Symbol BW tJPEAK tDC tDCD tpdBYP tpdPLL Parameter PLL BW [b] PLL Jitter Peaking Duty Cycle [c] Duty Cycle Distortion [c] [d] Skew, Input to Output [e] tsk3 Skew, Output to Output [e] tjcyc-cyc Jitter, Cycle to Cycle [a] Peak Pass band gain (100MHz). Measured differentially, PLL Mode. 45 50 55 % Measured differentially, Bypass Mode. -1 0.0 1 % Bypass Mode, VT = 50%. 2500 3406 4500 ps PLL Mode VT = 50%. -100 8 100 ps VT = 50%. 21 55 ps PLL Mode. 15 50 ps [a] Guaranteed by design and characterization, not 100% tested in production. [b] The Minimum/Typical/Maximum values of each BW setting track each other, i.e., maximum low BW will never occur with minimum high BW. [c] Measured from differential waveform. [d] Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. [e] All outputs at default slew rate. ©2021 Renesas Electronics Corporation 10 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 8. LP-HCSL (DIF) Output Characteristics Symbol Parameter dV/dt Slew Rate [a] [b] [c] ΔtR/tF Rise/Fall Matching [a] [d] Single-ended measurement. VHIGH Voltage High [e] VLOW Voltage Low [e] Statistical measurement on single-ended signal using oscilloscope math function (scope averaging on). Vmax Max Voltage [e] Vmin Min Voltage [e] Vcross_abs Δ-Vcross Conditions Minimum Typical Maximum Scope averaging on, fast setting. 2 2.8 4 Scope averaging on, slow setting. 1.2 1.9 3.1 7 20 660 768 850 -150 -11 150 811 1150 Measurement on single ended signal using absolute value (scope averaging off). -300 -49 Crossing Voltage (abs) [a] [f] Scope averaging off. 250 357 550 [a] [g] Scope averaging off. 14 140 Crossing Voltage (var) Units V/ns % mV [a] Guaranteed by design and characterization, not 100% tested in production. [b] Measured from differential waveform. [c] Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a ±150mV window around differential 0V. [d] Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. [e] At default SMBus settings. [f] Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). [g] The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. Table 9. Current Consumption – 9DBL02xx Symbol Parameter IDDA IDDDIG Operating Supply Current IDDO+R IDDRPD IDDDIGPD Powerdown Current IDDAOPD ©2021 Renesas Electronics Corporation [a] Conditions Minimum Typical Maximum Units VDDA, PLL Mode at 100MHz. – 7 10 mA VDDDIG, PLL Mode at 100MHz. – 3.4 5 mA VDDO+VDDR, PLL Mode, all outputs at 100MHz. – 20 25 mA VDDA, CKPWRGD_PD# = 0. – 0.6 1.0 mA VDDDIG, CKPWRGD_PD# = 0. – 3.0 4.3 mA VDDO+VDDR, CKPWRGD_PD# = 0. – 0.9 1.3 mA 11 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 10. Current Consumption – 9DBL04xx Symbol Parameter Conditions Minimum Typical Maximum Units VDDA, PLL Mode at 100MHz. – 7 10 mA VDDDIG, PLL Mode at 100MHz. – 3.4 5 mA VDDO+VDDR, PLL Mode, all outputs at 100MHz. – 30 37 mA VDDA, CKPWRGD_PD# = 0. – 0.6 1.0 mA VDDDIG, CKPWRGD_PD# = 0. – 3.1 4.3 mA VDDO+VDDR, CKPWRGD_PD# = 0. – 0.9 1.3 mA Conditions Minimum Typical Maximum Units VDDA, PLL Mode, at 100MHz. – 7 10 mA VDDx, all outputs active at 100MHz. – 17 22 mA VDDIO, all outputs active at 100MHz. – 20 25 mA VDDA, CKPWRGD_PD# = 0. – 0.6 1 mA VDDx, CKPWRGD_PD# = 0. – 3.8 6 mA VDDIO, CKPWRGD_PD# = 0. – 0.04 0.10 mA Conditions Minimum Typical Maximum Units VDDA, PLL Mode, at 100MHz. – 7 10 mA VDDx, all outputs active at 100MHz. – 22 32 mA IDDIO VDDIO, all outputs active at 100MHz. – 35 45 mA IDDAPD VDDA, CKPWRGD_PD# = 0. – 0.6 1 mA VDDx, CKPWRGD_PD# = 0. – 4.9 7 mA VDDIO, CKPWRGD_PD# = 0. – 0.04 0.10 mA IDDA IDDDIG Operating Supply Current IDDO+R IDDRPD IDDDIGPD Powerdown Current [a] IDDAOPD Table 11. Current Consumption – 9DBL06xx Symbol Parameter IDDA IDD Operating Supply Current IDDIO IDDAPD IDDPD Powerdown Current [a] IDDIOPD Table 12. Current Consumption – 9DBL08xx Symbol Parameter IDDA IDD IDDPD Operating Supply Current Powerdown Current [a] IDDIOPD [a] Input clock stopped. ©2021 Renesas Electronics Corporation 12 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 13. Input/Supply/Common Parameters – Normal Operating Conditions Symbol Parameter VDDx Supply Voltage VDDIO Output Supply Voltage [a] TAMB Ambient Operating Temperature VIH Input High Voltage VIL Input Low Voltage VIHtri Input High Voltage VIMtri Input Mid Voltage VILtri Input Low Voltage IIN Single-ended Input Current IINP FIN Input Frequency Lpin [b] Pin Inductance CIN CINDIF_IN Capacitance Conditions Minimum Typical Supply voltage for core and analog. 3.135 3.3 3.465 V Supply voltage for Low Power HCSL outputs. 0.95 1.05-3.3 3.465 V Industrial range. -40 25 85 °C 0.75 VDDx VDDx + 0.3 V -0.3 0.25 VDDx V 0.75 VDDx VDD + 0.3 V 0.6 VDDx V -0.3 0.25 VDDx V Inputs without internal pull-up/pull-down resistors VIN = GND, VIN = VDD. -5 5 μA Inputs with internal pull-up resistors, VIN = 0V. Inputs with internal pull-down resistors, VIN = VDD. -50 50 μA Bypass Mode. 1 200 MHz 100MHz PLL Mode. 60 100.00 140 MHz 50MHz PLL Mode. 30 50.00 65 MHz 125MHz PLL Mode. 75 125.00 175 MHz 7 nH Single-ended inputs, except SMBus. Single-ended tri-level inputs ('_tri' suffix). Clk Stabilization [c] 0.5 VDDx Logic Inputs, except DIF_IN. 1.5 5 pF DIF_IN differential clock inputs. 1.5 2.7 pF Output pin capacitance. 6 pF From VDD Power-Up and after input clock stabilization or deassertion of PD# to 1st clock. 1 ms [b] COUT TSTAB 0.4 VDDx Maximum Units fSSCMODIN Input SS Modulation Frequency PCIe applications. 30 33 kHz Non-PCIe applications. 0 66 kHz 1 3 clock s tLATOE# OE# Latency [b] [c] DIF start after OE# assertion DIF stop after OE# deassertion. tDRVPD Tdrive_PD# [b] [d] DIF output enable after PD# deassertion. 300 μs tF Tfall [c] Fall time of single-ended control inputs. 5 ns tR Trise [c] Rise time of single-ended control inputs. 5 ns [a] Only present on 9DBL06xx and 9DBL08xx devices. [b] Guaranteed by design and characterization, not 100% tested in production. [c] Control inputs must be monotonic from 20% to 80% of input swing. [d] Time from deassertion until outputs are > 200 mV. ©2021 Renesas Electronics Corporation 13 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 14. SMBus Parameters Symbol Parameter Conditions VILSMB SMBus Input Low Voltage VDDSMB = 3.3V. VIHSMB SMBus Input High Voltage VDDSMB = 3.3V. VOLSMB SMBus Output Low Voltage At IPULLUP. IPULLUP SMBus Sink Current At VOL. VDDSMB Nominal Bus Voltage Minimum Typical 2.1 Maximum Units 0.8 V 3.6 V 0.4 V 4 mA 2.7 3.6 V tRSMB SCLK/SDATA Rise Time [a] (Max VIL - 0.15) to (Min VIH + 0.15). 1000 ns tFSMB SCLK/SDATA Fall Time [a] (Min VIH + 0.15) to (Max VIL - 0.15). 300 ns SMBus operating frequency. 500 kHz fSMB SMBus Operating Frequency [b] [c] [a] Guaranteed by design and characterization, not 100% tested in production. [b] The device must be powered up for the SMBus to function. [c] The differential input clock must be running for the SMBus to be active. Power Management Table 15. Power Management CKPWRGD_PD# CLK_IN SMBus OEn bit OEn# Pin DIFn DIFn# PLL State (ZDB Mode) 0 X X X Low [a] Low [a] Off 1 Running 0 X Low [a] Low [a] On [b] 1 Running 1 0 Running Running On [b] 1 Running 1 1 Low [a] Low [a] On [b] [a] The output state is set by B11[1:0] (Low/Low default) [b] If Bypass mode is selected, the PLL will always be off. ©2021 Renesas Electronics Corporation 14 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Test Loads Figure 5. Test Load for AC/DC Measurements and ZDB Mode PCIe Jitter Measurements CL CK+ CKIN+ Clock Source L CK+ Zo (differential) DUT CK- CKIN- Test Points for High Impedance Probe CK- CL Table 16. Parameters for Measurements Using Test Setup in Figure 5 [a] Clock Source Device Under Test (DUT) Differential Zo (Ω) L (cm) CL (pF) SMA100B 9DBLxx5x 85 12.7 2 SMA100B 9DBLxx4x 100 12.7 2 9FGL08x1C 9DBLxx5x 85 12.7 2 9FGL08x1C 9DBLxx4x 100 12.7 2 Parameters Measured AC/DC parameters ZDB-mode PCIe Jitter [a] A DSO is used for all measurements in this table. Equipment noise is removed from all jitter measurements taken with this setup. Figure 6. Test Loads for Additive Phase Jitter Measurements PNA Coax Cables L CK+ CKIN+ Clock Source CK- CK+ Zo (differential) DUT CKIN- Balun 0.1uF CK- SMA Connectors 50 Table 17. Parameters for Measurements Using Test Setup in Figure 6 Clock Source Device Under Test (DUT) Differential Zo (Ω) L (cm) CL (pF) SMA100B 9DBLxx5x 85 12.7 2 SMA100B 9DBLxx4x 100 12.7 2 ©2021 Renesas Electronics Corporation 15 Parameters Measured Fan-out Mode Additive PCIe Jitter April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet General SMBus Serial Interface Information How to Write How to Read ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Controller (host) sends a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) sends the byte count = X Renesas clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 Renesas clock will acknowledge each byte one at a time Controller (host) sends a stop bit Index Block Write Operation Controller (Host) T Renesas (Slave/Receiver) Controller (host) will send a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Renesas clock will acknowledge Renesas clock will send the data byte count = X Renesas clock sends Byte N+X-1 Renesas clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit starT bit Slave Address WR WRite ACK Index Block Read Operation Beginning Byte = N ACK T Data Byte Count = X ACK WR Beginning Byte N Renesas ACK ACK X Byte O O O Controller (Host) starT bit Slave Address WRite Beginning Byte = N ACK O O O RT RD Byte N + X - 1 Repeat starT Slave Address ReaD ACK ACK P stoP bit Data Byte Count=X ACK Beginning Byte N O O O X Byte ACK O O O Byte N + X - 1 N P ©2021 Renesas Electronics Corporation 16 Not acknowledge stoP bit April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 18. SMBus Address Selection State of SADR_tri pin on first high assertion of CKPWRGD_PD# Address[a] 0 1101011x M 1101100x 1 1101101x [a] ‘x’ is the Read/Write bit. Table 19. Byte 0: Output Enable Control Byte 0 Device 9DBL08xx 9DBL06xx 9DBL04xx 9DBL02xx Bit 7 Function Output Enable Type RW 6 5 4 3 2 1 0 RW RW RW RW RW RW RW 0 = Output is disabled [a] 1 = OE# Pin Controls Output Definition Name DIF7oe DIF6oe DIF5oe DIF4oe DIF3oe DIF2oe DIF1oe DIF0oe Default 1 1 1 1 1 1 1 1 Name DIF5oe DIF4oe Reserved DIF3oe DIF2oe DIF1oe Reserved DIF0oe Default 1 1 – 1 1 1 – 1 Name Reserved DIF3oe Reserved DIF2oe DIF1oe Reserved DIF0oe Reserved Default – 1 - 1 1 – 1 – DIF1oe DIF0oe 1 1 Reserved Name Default – – – Reserved – – – [a] See Byte11[1:0] for disabled state. Table 20. Byte 1: PLL Operating Mode and Output Amplitude Control Byte 1 Bit Function Type Definition All Devices 7 6 PLL Mode Readback R R See PLL Operating Mode Table 5 4 Enable software PLL Mode control RW 0 = B1[7:6] sets PLL Mode 1 = B1[4:3] sets PLL Mode 3 Software PLL Mode Control [a] RW RW See PLL Operating Mode Table 2 – – Reserved 1 0 Output Amplitude RW RW 00 = 0.60V 01 = 0.68V 10 = 0.75V 11 = 0.85V Name PLLrbk1 PLLrbk0 PLLmdctrl PLLmd1 PLLmd0 – Amp1 Amp0 Default Latch Latch 0 0 0 1 1 0 [a] B1[5] must be set to a 1 for these bits to have any effect on the part. ©2021 Renesas Electronics Corporation 17 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 21. Byte 2: Slew Rate Control 0 Byte 2 Bit 7 6 5 4 Function 9DBL08xx 9DBL06xx 9DBL04xx 9DBL02xx 2 1 0 RW RW RW Slew Rate Selection Type Device 3 RW RW RW RW RW 0 = Slow Setting 1 = Fast Setting See electrical characteristics for actual slew rates. Definition Name DIF7slew DIF6slew DIF5slew DIF4slew DIF3slew DIF2slew DIF1slew DIF0slew Default 1 1 1 1 1 1 1 1 Name DIF5slew DIF4slew Reserved DIF3slew DIF2slew DIF1slew Reserved DIF0slew Default 1 1 – 1 1 1 – 1 Name Reserved DIF3slew Reserved DIF2slew DIF1slew Reserved DIF0slew Reserved Default – 1 – 1 1 – 1 – DIF1slew DIF0slew 1 1 Reserved Name Default – – – Reserved – – – Table 22. Byte 3: ZDB Mode Frequency Select and Feedback Slew Rate Control Byte 3 Bit 7 6 5 Function – – Enable software (SW) selection of ZDB frequency Type – – RW Definition All Devices Reserved 4 0 = SW frequency select disabled 1 = SW frequency select enabled 3 2 1 0 ZDB Frequency Select [a] – – Feedback Slew Rate RW – – RW RW 00 = 100M 01 = 50M 10 = 125M 11= Reserved 0 = Slow Setting 1 = Fast Setting Reserved Name – – FSelEn FSel1 Fsel0 – – FBKslew Default 1 1 0 0 0 1 1 1 [a] B3[5] must be set to a 1 for these bits to have any effect on the part. Byte 4 is Reserved. Table 23. Byte 5: Revision ID/Vendor ID Byte 5 Bit 7 6 5 Function All Devices 4 3 2 Revision ID 1 0 VENDOR ID Type R R R R R R R R Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Default ©2021 Renesas Electronics Corporation B rev = 0001 0001 = IDT 18 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 24. Byte 6: Device Type/Device ID Byte 6 Bit 7 Function All Devices 6 5 4 3 Device Type 2 1 0 Device ID Type R R R R R R R R Name DevType 1 DevType0 Dev ID5 Dev ID4 Dev ID3 Dev ID2 Dev ID1 Dev ID0 Default 9DBL08x1 = 0b001000 9DBL06x1 = 0b000110 9DBL04x2 = 0b000100 9DBL02x2 = 0b000010 01 = DBx ZDB/FOB Table 25. Byte 7: Byte Count Byte 7 Bit 7 6 5 Function – – – Type – – – 4 3 2 1 0 RW RW Byte Count Programming RW RW RW Writing to this register will configure how many bytes will be read back on a block read. Default is = 8 bytes. Reserved Device Definition All Name – – – BC4 BC3 BC2 BC1 BC0 Default 0 0 0 0 1 0 0 0 Bytes 8 and 9 are reserved. Table 26. Byte 10: Power-Down (PD) Restore Byte 10 All Devices Bit 7 6 5 4 3 2 1 0 Function – Restore Default Config in Power Down – – – – – – Type – RW – – – – – – Definition Reserved 0 = Clear Config. in Power Down 1 = Keep Config. in Power Down Name – PD_Restore – – – – – – Default 1 1 0 0 0 0 0 0 ©2021 Renesas Electronics Corporation 19 Reserved April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 27. Byte 11: Impedance Control 0 and Stop State Byte 11 Bit Function Type Device Definition Name All Default 7 6 5 4 3 2 Output Impedance -Feedback – – – – RW – – – – RW 00 = 33ohm 01 = 85ohm 10 = 100ohm 11 = Reserved FBz1 FBz0 10 = 9DBLxx4x 01 = 9DBLxx5x 1 0 DIF/DIF# Disable State RW RW 00 = Low/Low 01 = HiZ/HiZ 10 = High/Low 11 = Low/High Reserved – – – – Stop1 Stop0 0 0 0 0 0 0 Table 28. Byte 12: Impedance Control 1 Byte 12 Bit 7 6 5 4 Function Type Device 9DBL08xx 9DBL06xx RW RW 1 0 RW RW RW RW DIF0z1 DIF0z0 DIF0z1 DIF0z0 00 = 33ohm, 01 = 85ohm, 10 = 100ohm, 11 = Reserved DIF3z1 DIF3z0 DIF2z1 DIF2z0 DIF1z1 DIF1z0 9DBL084x = 0b10101010 9DBL085x = 0b01010101 DIF2z1 DIF2z0 DIF1z1 DIF1z0 Reserved 9DBL064x = 0b1010xx10 9DBL065x = 0b0101xx01 DIF1z1 DIF1z0 Reserved DIF0z1 DIF0z0 Reserved 9DBL044x = 0b10xx10xx 9DBL045x = 0b01xx01xx Default Name 9DBL02xx RW Default Name 9DBL04xx RW Default Name 2 Output Impedance Definition Name 3 DIF0z1 Reserved DIF0z0 9DBL024x = 0b10xxxxxx 9DBL025x = 0b01xxxxxx Default ©2021 Renesas Electronics Corporation 20 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 29. Byte 13: Impedance Control 2 Byte 13 Bit 7 6 5 4 Function Type Device 9DBL08xx 9DBL06xx RW RW DIF7z1 DIF7z0 RW DIF6z1 0 RW RW RW RW DIF6z0 DIF5z1 DIF4z1 DIF4z0 DIF3z1 DIF3z0 DIF2z1 DIF2z0 DIF1z1 DIF1z0 2 1 0 RW RW RW DIF5z0 9DBL084x = 0b10101010 9DBL085x = 0b01010101 DIF5z1 DIF5z0 DIF4z1 Reserved DIF4z0 9DBL064x = 0b1010xx10 9DBL065x = 0b0101xx01 Default Reserved DIF3z1 DIF3z0 Reserved 9DBL044x = 0bxx10xx10 9DBL045x = 0bxx01xx01 Default Reserved Name 9DBL02xx 1 00 = 33ohm, 01 = 85ohm, 10 = 100ohm, 11 = Reserved Name 9DBL04xx RW Default Name 2 Output Impedance Definition Name 3 9DBL024x = 0bxxxxxx10 9DBL025x = 0bxxxxxx01 Default Table 30. Byte 14: Pull-up/Pull-down Control 0 Byte 14 Bit 7 6 5 Function Type Device 9DBL08xx 9DBL06xx 9DBL04xx 9DBL02xx 4 3 Pull-up (PuP)/Pull-down (Pdwn) control RW RW Definition RW RW RW 00 = None, 01 = Pdwn, 10 = Pup, 11 = Pup+Pdwn Name OE3pu/pd1 OE3pu/pd0 OE2pu/pd1 OE2pu/pd0 OE1pu/pd1 OE1pu/pd0 OE0pu/pd1 OE0pu/pd0 Default 0 1 0 1 0 1 0 1 Name OE2pu/pd1 OE2pu/pd0 OE1pu/pd1 OE1pu/pd0 OE0pu/pd1 OE0pu/pd0 Default 0 1 0 1 0 1 Name OE1pu/pd1 OE1pu/pd0 Default 0 1 Name OE0pu/pd1 OE0pu/pd0 Default 0 1 ©2021 Renesas Electronics Corporation Reserved – – Reserved – – OE0pu/pd1 OE0pu/pd0 0 1 – – – – – Reserved Reserved – – 21 – April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 31. Byte 15 Byte 15: Pull-up/Pull-down Control 1 Bit 7 6 5 Function Type Device 9DBL08xx 9DBL06xx 9DBL04xx 9DBL02xx 4 3 2 1 0 RW RW RW Pull-up (PuP)/Pull-down (Pdwn) control RW RW RW Definition RW RW 00 = None, 01 = Pdwn, 10 = Pup, 11 = Pup+Pdwn Name OE7pu/pd1 OE7pu/pd0 OE6pu/pd1 OE6pu/pd0 OE5pu/pd1 OE5pu/pd0 OE4pu/pd1 OE4pu/pd0 Default 0 1 0 1 0 1 0 1 Name OE5pu/pd1 OE5pu/pd0 OE4pu/pd1 OE4pu/pd0 OE3pu/pd1 OE3pu/pd0 Default 0 1 0 1 0 1 OE3pu/pd1 OE3pu/pd0 OE2pu/pd1 OE2pu/pd0 0 1 0 1 OE1pu/pd1 OE1pu/pd0 0 1 Name Default Reserved – – Name Default Reserved – – Reserved – – Reserved – – – – – – Table 32. Byte 16: Pull-up_Pull-down Control 2 Byte 16 Device All Bit 7 6 5 4 3 2 1 Function – – – – – – Pull-up(PuP)/ Pull-down (Pdwn) control Type – – – – – – Definition RW 0 RW 00 = None, 01 = Pdwn, 10 = Pup, 11 = Pup+Pdwn Reserved Name – – – – – – CKPWRGD_PD_ pu/pd1 CKPWRGD_PD_ pu/pd0 Default 0 0 0 0 0 0 1 0 Byte 17 is Reserved. ©2021 Renesas Electronics Corporation 22 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Table 33. Byte 18: Polarity Control 0 Byte 18 Bit Function Type Device 9DBL08xx 9DBL06xx 9DBL04xx 9DBL02xx 7 6 RW 5 RW 4 3 OE pin polarity RW RW RW 2 1 0 RW RW RW 0 = Output enabled when OE pin is Low 1 = Output enabled when OE pin is High Definition Name OE7pol OE6pol OE5pol OE4pol OE3pol OE2pol OE1pol OE0pol Default 0 0 0 0 0 0 0 0 Name OE5pol OE4pol Reserved OE3pol OE2pol OE1pol Reserved OE0pol Default 0 0 0 0 0 0 0 0 Name Reserved OE3pol Reserved OE2pol OE1pol Reserved OE0pol Reserved Default 0 0 0 0 0 0 0 0 OE1pol OE0pol 0 0 Name Reserved Default 0 0 0 Reserved 0 0 0 Table 34. Byte 19: Polarity Control 1 Byte 19 Bit 7 6 5 4 3 2 1 0 Function – – – – – – – CKPWRGD_PD pin polarity Type – – – – – – – RW All Devices 0 = Power Down when Low 1 = Power Down when High Reserved Definition Name – – – – – – – CKPWRGD_Pdpol Default 0 0 0 0 0 0 0 0 ©2021 Renesas Electronics Corporation 23 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. 9DBL02x2: www.idt.com/us/en/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-090-mm-body050mm-pitchepad-260-x-260-mm-nlg24p3 9DBL04x2: www.idt.com/us/en/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1 9DBL06x1: www.idt.com/document/psc/ndndg40-package-outline-50-x-50-mm-bodyepad-350mm-sq-040-mm-pitch-qfn 9DBL08x1: www.idt.com/us/en/document/psc/48-vfqfpn-package-outline-drawing60-x-60-x-090-mm-body-epad-42-x-42-mm-040mm-pitchndg48p2 Thermal Characteristics Table 35. Thermal Characteristics Parameter 9DBL08xx Thermal Resistance 9DBL06xx 9DBL04xx Thermal Resistance 9DBL02xx Thermal Resistance Symbol [a] Conditions Package Typical Values Units θJC Junction to case. 33 °C/W θJb Junction to base. 2 °C/W θJA0 Junction to air, still air. 37 °C/W θJA1 Junction to air, 1 m/s air flow. 30 °C/W θJA3 Junction to air, 3 m/s air flow. 27 °C/W θJA5 Junction to air, 5 m/s air flow. 26 °C/W θJC Junction to case. 42 °C/W θJb Junction to base. 2 °C/W θJA0 Junction to air, still air. 39 °C/W θJA1 Junction to air, 1 m/s air flow. 33 °C/W θJA3 Junction to air, 3 m/s air flow. 28 °C/W θJA5 Junction to air, 5 m/s air flow. 27 °C/W θJC Junction to case. 60 °C/W θJb Junction to base. 5.4 °C/W θJA0 Junction to air, still air. 50 °C/W θJA1 Junction to air, 1 m/s air flow. 43 °C/W θJA3 Junction to air, 3 m/s air flow. 39 °C/W θJA5 Junction to air, 5 m/s air flow. 38 °C/W NDG48 NDG40 NLG32 NLG24 [a] epad soldered to ground ©2021 Renesas Electronics Corporation 24 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Marking Diagrams 9DBL02x2 ▪ Line 1: “LOT” is the lot sequence number. ▪ Line 2: truncated part number. • “I” denotes industrial temperature range device. ▪ Line 3: “YYWW” is the last two digits of the year and week that the part was assembled. 9DBL04x2 ▪ Line 2: truncated part number. • “I” denotes industrial temperature range. ▪ Line 3: “YYWW” is the last two digits of the year and week the part was assembled. ▪ Line 4: “COO” denotes country of origin. ▪ Line 5: “LOT” is the lot sequence number. 9DBL06x1 ▪ Line 2: truncated part number. • “I” denotes industrial temperature range. ▪ Line 3: “YYWW” is the last two digits of the year and week the part was assembled. ▪ Line 4: “COO” denotes country of origin. ▪ Line 5: “LOT” is the lot sequence number. 9DBL08x1 ▪ Line 2: truncated part number. • “I” denotes industrial temperature range. ▪ Line 3: “YYWW” is the last two digits of the year and week the part was assembled. ▪ Line 4: “COO” denotes country of origin. ▪ Line 5: “LOT” is the lot sequence number. ©2021 Renesas Electronics Corporation 25 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Ordering Information Table 36. Ordering Information Output Impedance (ohms) [a] [b] [c] [d] Number of Clock Outputs Package Orderable Part Number 2 24-VFQFPN - 4 × 4 × 0.9 mm, 0.50mm Pitch 4 32-VFQFPN - 5 × 5 × 0.9 mm, 0.50mm Pitch 6 40-VFQFPN - 5 × 5 × 0.9 mm, 0.40mm Pitch 8 48-VFQFPN - 6 × 6 × 0.9 mm, 0.40mm Pitch 2 24-VFQFPN - 4 × 4 × 0.9 mm, 0.50mm Pitch 4 32-VFQFPN - 5 × 5 × 0.9 mm, 0.50mm Pitch 6 40-VFQFPN - 5 × 5 × 0.9 mm, 0.40mm Pitch 8 48-VFQFPN - 6 × 6 × 0.9 mm, 0.40mm Pitch 85 100 Shipment Packing 9DBL0252BKILF Trays 9DBL0252BKILFT “T” = Tape and Reel 9DBL0452BKILF Trays 9DBL0452BKILFT “T” = Tape and Reel 9DBL0651BKILF Trays 9DBL0651BKILFT “T” = Tape and Reel 9DBL0851BKILF Trays 9DBL0851BKILFT “T” = Tape and Reel 9DBL0242BKILF Trays 9DBL0242BKILFT T” = Tape and Reel 9DBL0442BKILF Trays 9DBL0442BKILFT “T” = Tape and Reel 9DBL0641BKILF Trays 9DBL0641BKILFT “T” = Tape and Reel 9DBL0841BKILF Trays 9DBL0841BKILFT “T” = Tape and Reel [a] “B” is the device revision designator (will not correlate with the datasheet revision). [b] “LF” denotes Pb-free configuration, RoHS compliant. [c] “I” indicates that all devices are specified over the '-40°C to +85°C (industrial) temperature range. [d] “T” = Tape and Reel, Pin 1 Orientation: EIA-481C (see Table 37 for more details) Table 37. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION T CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED ©2021 Renesas Electronics Corporation 26 April 1, 2021 9DBL02x2/9DBL04x2/ 9DBL06x1/9DBL08x1 Datasheet Revision History Table 38. Revision History Revision Date April 1, 2021 August 13, 2020 July 8, 2020 Description of Change Corrected pin numbers on vSADR_tri pin for 04x2 and 02x2 in pin descriptions table. ▪ Changed the shipment packing for the 9DBL0242B and 0252B from “Cut Tape” to “Trays” in the Ordering Information table. ▪ ▪ ▪ ▪ Merged 9DBL02x2, 9DBL04x2, 9DBL06x1 and 9DBL08x1 into single document. Updated PCIe jitter tables to show PCIe Gen5. Updated Test Loads figures to indicate PCIe Jitter Test setup. Updated package outline drawings link for the 9DBL08x1 devices to NDG48P2. February 8, 2017 Last update of 9DBL0242/0252 data sheet. February 9, 2017 Last update of 9DBL0442/0452 data sheet. February 8, 2017 Last update of 9DBL0641/0651 data sheet. February 9, 2017 Last update of 9DBL0841/0851 data sheet. ©2021 Renesas Electronics Corporation 27 April 1, 2021 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.60 x 2.60 mm NLG24P3, PSC-4192-03, Rev 02, Page 1 © Integrated Device Technology, Inc. 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.60 x 2.60 mm NLG24P3, PSC-4192-03, Rev 02, Page 2 Package Revision History © Integrated Device Technology, Inc. Description Date Created Rev No. June 15, 2016 Rev 01 Oct 3, 2018 Rev 02 New Format, Recalculate Land Pattern Change QFN to VFQFPN Correct Title Block 32-VFQFPN, Package Outline Drawing 5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm. NLG32P1, PSC-4171-01, Rev 02, Page 1 32-VFQFPN, Package Outline Drawing 5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm. NLG32P1, PSC-4171-01, Rev 02, Page 2 Package Revision History Description Date Created Rev No. April 12, 2018 Rev 02 New Format Feb 8, 2016 Rev 01 Added "k: Value 48-VFQFPN Package Outline Drawing 6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch NDG48P2, PSC-4212-02, Rev 03, Page 1 © Renesas Electronics Corporation 48-VFQFPN Package Outline Drawing 6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch NDG48P2, PSC-4212-02, Rev 03, Page 2 Package Revision History © Renesas Electronics Corporation Description Date Created Rev No. July 24, 2018 Rev 02 New Format Change QFN to VFQFPN, Recalculate Land Pattern Feb 25, 2020 Rev 03 Tolerance Format Change IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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