9DBU0541AKILFT

5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms 9DBU0541 DATASHEET Description Features/Benefits The 9DBU0541 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 transmission lines. The device has 5 output enables for clock management, and 3 selectable SMBus addresses. • Integrated terminations; save 20 resistors compared to • • Recommended Application • • 1.5V PCIe Gen1-2-3 Fanout Buffer (FOB) Output Features • • 5 1–167MHz Low-Power (LP) HCSL DIF pairs with ZO=100 Key Specifications • • • • • DIF additive cycle-to-cycle jitter < 5ps DIF output-to-output skew < 60ps DIF additive phase jitter is < 300fs rms for PCIe Gen3 DIF additive phase jitter < 350fs rms for SGMII • • • standard HCSL outputs 35mW typical power consumption; eliminates thermal concerns Spread Spectrum (SS) compatible; allows SS for EMI reduction OE# pins; support DIF power management HCSL-compatible differential input; can be driven by common clock sources SMBus-selectable features; optimize signal integrity to application • slew rate for each output • differential output amplitude Device contains default configuration; SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Selectable SMBus addresses; multiple devices can easily share an SMBus segment 5 × 5 mm 32-VFQFPN; minimal board space Block Diagram vOE(4:0)# 5 CLK_IN DIF4 CLK_IN# DIF3 vSADR ^CKPWRGD_PD# SDATA_3.3 DIF2 CONTROL LOGIC DIF1 DIF0 SCLK_3.3 9DBU0541 MARCH 9, 2017 1 ©2017 Integrated Device Technology, Inc. 9DBU0541 DATASHEET VDDO1.5 GND DIF3 DIF3# vOE3# GND ^CKPWRGD_PD# ^SADR_tri Pin Configuration 32 31 30 29 28 27 26 25 vOE4# 1 24 vOE2# 23 DIF2# DIF4 2 DIF4# 3 22 DIF2 21 VDDO1.5 9DBU0541 VDDR1.5 4 CLK_IN 5 20 GND epad is GND CLK_IN# 6 GNDR 7 GNDDIG 8 19 DIF1# 18 DIF1 17 vOE1# VDDO1.5 GND DIF0# DIF0 vOE0# SDATA_3.3 SCLK_3.3 VDDDIG1.5 9 10 11 12 13 14 15 16 32-pin VFQFPN, 5x5 mm, 0.5mm pitch ^ prefix indicates internal 120KOhm pull up resistor ^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor SMBus Address Selection Table State of SADR on first application of CKPWRGD_PD# SADR 0 M 1 Address 1101011 1101100 1101101 + Read/Write bit x x x Power Management Table CKPWRGD_PD# CLK_IN 0 1 1 1 X Running Running Running SMBus OEx bit X 0 1 1 OEx# Pin X X 0 1 DIFx True O/P Comp. O/P Low Low Low Low Running Running Low Low Power Connections Pin Number VDD GND 4 7 9 8 16, 21, 25 15,20,26,30 Description Input receiver analog Digital power DIF outputs Note: EPAD on this device is not electrically connected to the die. It should be connected to ground for best thermal performance. 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 2 MARCH 9, 2017 9DBU0541 DATASHEET Pin Descriptions Pin# Pin Name Type 1 vOE4# IN 2 3 DIF4 DIF4# OUT OUT 4 VDDR1.5 PWR 5 6 7 8 9 10 11 CLK_IN CLK_IN# GNDR GNDDIG VDDDIG1.5 SCLK_3.3 SDATA_3.3 IN IN GND GND PWR IN I/O 12 vOE0# 13 14 15 16 DIF0 DIF0# GND VDDO1.5 17 vOE1# 18 19 20 21 22 23 DIF1 DIF1# GND VDDO1.5 DIF2 DIF2# 24 vOE2# 25 26 27 28 VDDO1.5 GND DIF3 DIF3# 29 vOE3# 30 GND 31 ^CKPWRGD_PD# 32 ^SADR_tri 33 EPAD MARCH 9, 2017 IN OUT OUT GND PWR IN OUT OUT GND PWR OUT OUT IN PWR GND OUT OUT IN GND IN Pin Description Active low input for enabling output 4. This pin has an internal 120kohm pull-down. 1 = disable outputs, 0 = enable outputs. Differential true clock output. Differential complementary clock output. 1.5V power for differential input clock (receiver). This VDD should be treated as an Analog power rail and filtered appropriately. True input for differential reference clock. Complementary input for differential reference clock. Analog ground pin for the differential input (receiver) Ground pin for digital circuitry. 1.5V digital power (dirty power) Clock pin of SMBus circuitry, 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Active low input for enabling output 0. This pin has an internal 120kohm pull-down. 1 = disable outputs, 0 = enable outputs. Differential true clock output. Differential complementary clock output. Ground pin. Power supply for outputs, nominally 1.5V. Active low input for enabling output 1. This pin has an internal 120kohm pull-down. 1 = disable outputs, 0 = enable outputs. Differential true clock output. Differential complementary clock output. Ground pin. Power supply for outputs, nominally 1.5V. Differential true clock output. Differential complementary clock output. Active low input for enabling output 2. This pin has an internal 120kohm pull-down. 1 = disable outputs, 0 = enable outputs. Power supply for outputs, nominally 1.5V. Ground pin. Differential true clock output. Differential complementary clock output. Active low input for enabling output 3. This pin has an internal 120kohm pull-down. 1 = disable outputs, 0 = enable outputs. Ground pin. Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal 120kohm pull-up resistor. LATCHED Tri-level latch to select SMBus Address. It has an internal 120kohm pull up resistor. IN See SMBus Address Selection Table. GND Connect EPAD to ground. 3 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 9DBU0541 DATASHEET Test Loads Low-Power HCSL Differential Output Test Load 5 inches Rs Zo=100 2pF Rs 2pF Note: The device can drive transmission line lengths greater than those allowed by the PCIe SIG Driving LVDS 3.3V Driving LVDS Cc R7a R7b R8a R8b Rs Zo Cc Rs LVDS Clock input Device Driving LVDS Inputs Value Component R7a, R7b R8a, R8b Cc Vcm Receiver has Receiver does not termination have termination 10K ohm 5.6K ohm 0.1µF 1.2 volts 140 ohm 75 ohm 0.1µF 1.2 volts 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 4 MARCH 9, 2017 9DBU0541 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBU0541. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS Supply Voltage Input Voltage Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD Protection VDDx VIN VIHSMB Ts Tj ESD prot Applies to all VDD pins MIN -0.5 -0.5 TYP SMBus clock and data pins -65 Human Body Model MAX 2 VDD+0.5 3.3 150 125 2000 UNITS NOTES V V V °C °C V 1,2 1, 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.0V. 2 Electrical Characteristics–Clock Input Parameters TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions PARAMETER Input Common Mode Voltage - DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle 1 2 SYMBOL CONDITIONS MIN VCOM Common mode input voltage VSWING dv/dt IIN dtin J DIFIn TYP MAX UNITS 200 725 mV Differential value Measured differentially VIN = VDD , VIN = GND Measurement from differential waveform 300 0.4 -5 45 1450 8 5 55 mV V/ns uA % Differential measurement 0 150 ps 50 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero. MARCH 9, 2017 5 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 9DBU0541 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX Supply Voltage Ambient Operating Temperature Input High Voltage Input Mid Voltage Input Low Voltage VDDx Supply voltage for core and analog Commercial range Industrial range Single-ended inputs, except SMBus Single-ended tri-level inputs ('_tri' suffix) Single-ended inputs, except SMBus Single-ended inputs, VIN = GND, VIN = VDD Single-ended inputs VIN = 0 V; inputs with internal pull-up resistors VIN = VDD; inputs with internal pull-down resistors 1.425 0 -40 0.75 VDD 0.4 VDD -0.3 -5 1.5 25 25 1.575 70 85 VDD + 0.3 0.6 VDD 0.25 VDD 5 V °C °C V V V µA -200 200 µA 1 167 7 5 2.7 6 MHz nH pF pF pF 2 1 1 1,5 1 1 ms 1,2 30 33 kHz 0 66 kHz 1 3 clocks 1,3 300 µs 1,3 5 5 0.6 3.3 0.4 2 2 3.3 1000 300 ns ns V V V mA V ns ns 1 1 400 kHz 6 Input Current TAMB VIH VIM VIL IIN IINP Input Frequency Pin Inductance Fin Lpin CIN Capacitance CINDIF_IN COUT Clk Stabilization TSTAB OE# Latency tLATOE# Tdrive_PD# tDRVPD Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR Logic Inputs, except DIF_IN DIF_IN differential clock inputs Output pin capacitance From VDD power-up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable frequency for PCIe applications (Triangular modulation) Allowable frequency for non-PCIe applications (Triangular modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of single-ended control inputs Rise time of single-ended control inputs VILSMB VIHSMB VOLSMB IPULLUP VDDSMB tRSMB t FSMB VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V at IPULLUP at VOL Bus voltage (Max VIL - 0.15V) to (Min VIH + 0.15V) (Min VIH + 0.15V) to (Max VIL - 0.15V) fMAXSMB Maximum SMBus operating frequency Input SS Modulation Frequency PCIe Input SS Modulation Frequency non-PCIe fMODINPCIe fMODIN 1.5 1.5 2.1 4 1.425 UNITS NOTES 1 1 4 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are > 200 mV. 4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB 2 5 DIF_IN input. 6 The differential input clock must be running for the SMBus to be active. 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 6 MARCH 9, 2017 9DBU0541 DATASHEET Electrical Characteristics–DIF Low-Power HCSL Outputs TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions PARAMETER SYMBOL CONDITIONS MIN TYP Scope averaging on, fast setting Scope averaging on, slow setting Slew rate matching, scope averaging on 1 0.7 Slew Rate Matching dV/dt dV/dt ΔdV/dt 2.4 1.7 9 Voltage High VHIGH 630 750 Slew Rate 1 2 Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs Δ-Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS NOTES V/ns 1,2,3 3.5 V/ns 1,2,3 2.5 % 20 1,2,4 850 7 mV -150 26 150 763 22 1448 390 11 1150 -300 300 250 550 140 7 7 7 1,2 1,5 1,6 mV mV mV mV Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform. 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 At default SMBus settings. Electrical Characteristics–Current Consumption TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions PARAMETER Operating Supply Current Powerdown Current 1 2 SYMBOL CONDITIONS IDDR VDDR at 100MHz IDDDIG VDDIG, all outputs at 100MHz IDDAO VDDO1.5+VDDO, all outputs at 100MHz IDDRPD VDDR, CKPWRGD_PD# = 0 VDDDIG, CKPWRGD_PD# = 0 VDDO1.5+VDDO, CKPWRGD_PD# = 0 IDDDIGPD IDDAOPD MIN TYP MAX UNITS 1.9 3 mA 0.1 0.5 mA 20 0.001 0.1 0.5 25 0.3 0.2 1 mA mA mA mA NOTES 2 2 2 Guaranteed by design and characterization, not 100% tested in production. Input clock stopped. MARCH 9, 2017 7 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 9DBU0541 DATASHEET Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle Distortion Skew, Input to Output Skew, Output to Output Jitter, Cycle to Cycle tDCD tpdBYP tsk3 Measured differentially, at 100MHz VT = 50% VT = 50% -1 2400 -0.2 2862 30 0.5 3700 50 % ps ps 1,3 1 1,4 t jcy c-cy c Additive Jitter 0.1 5 ps 1,2 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform. 3 Duty cycle distortion is the difference in duty cycle between the output and the input clock. 4 All outputs at default slew rate. 2 Electrical Characteristics–Phase Jitter Parameters TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions PARAMETER SYMBOL CONDITIONS tjphPCIeG1 PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (2-4MHz or 2-5MHz, CDR = 10MHz) 125MHz, 1.5MHz to 10MHz, -20dB/decade rollover < 1.5MHz, -40db/decade rolloff > 10MHz tjphPCIeG2 Additive Phase Jitter tjphPCIeG3 tjphSGMIIM0 tjphSGMIIM1 MIN 125MHz, 12kHz to 20MHz, -20dB/decade rollover < 1.5MHz, -40db/decade rolloff > 10MHz INDUSTRY LIMIT UNITS TYP MAX 0.1 5 N/A 0.1 0.4 N/A 0.1 0.7 N/A 0.1 0.3 N/A 200 250 N/A 313 350 N/A ps (p-p) ps (rms) ps (rms) ps (rms) fs (rms) fs (rms) Notes 1,2,3,5 1,2,3,4, 5 1,2,3,4 1,2,3,4 1,6 1,6 1 Guaranteed by design and characterization, not 100% tested in production. See http://www.pcisig.com for complete specs. 2 3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12. 4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]. 5 Driven by 9FGV0831 or equivalent. 6 Rohde & Schwarz SMA100. 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 8 MARCH 9, 2017 9DBU0541 DATASHEET Additive Phase Jitter Plot: 125M (12kHz to 20MHz) RMS additive jitter: 313fs MARCH 9, 2017 9 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 9DBU0541 DATASHEET General SMBus Serial Interface Information How to Write How to Read • • • • • • • • • • • • • • • • • • • • • Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a stop bit • • • Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T Index Block Read Operation IDT (Slave/Receiver) Controller (Host) starT bit T Slave Address WR IDT (Slave/Receiver) starT bit Slave Address WRite WR WRite ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK Data Byte Count = X RT ACK Slave Address Beginning Byte N RD ACK O O ACK O Data Byte Count=X O ACK O Beginning Byte N Byte N + X - 1 ACK ACK P ReaD stoP bit X Byte X Byte O Repeat starT O O O O O O Note: SMBus Address is Latched on SADR pin. 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS Byte N + X - 1 10 N Not acknowledge P stoP bit MARCH 9, 2017 9DBU0541 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 Reserved Bit 7 DIF OE3 Output Enable RW Low/Low Bit 6 DIF OE2 Output Enable RW Low/Low Bit 5 Reserved Bit 4 DIF OE1 Output Enable RW Low/Low Bit 3 Reserved Bit 2 DIF OE0 Output Enable RW Low/Low Bit 1 Reserved Bit 0 1. A low on these bits will override the OE# pin and force the differential output Low/Low SMBus Table: PLL Operating Mode and Output Amplitude Control Register Byte 1 Name Control Function Type 0 Reserved Bit 7 Reserved Bit 6 DIF OE4 Output Enable RW Low/Low Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 AMPLITUDE 1 RW 00 = 0.55V Bit 1 Controls Output Amplitude AMPLITUDE 0 RW 10 = 0.7V Bit 0 1. A low on the DIF OE bit will override the OE# pin and force the differential output Low/Low SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Type Reserved Bit 7 SLEWRATESEL DIF3 Slew Rate Selection RW Bit 6 SLEWRATESEL DIF2 Slew Rate Selection RW Bit 5 Reserved Bit 4 SLEWRATESEL DIF1 Slew Rate Selection RW Bit 3 Reserved Bit 2 Slow Setting Fast Setting RW Bit 1 Reserved Bit 0 Note: See "DIF 0.7V Low-Power HCSL Outputs" table for slew rates. SMBus Table: DIF Slew Rate Control Register Byte 3 Name Control Function Type Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 RW Bit 0 Note: See "DIF 0.7V Low-Power HCSL Outputs" table for slew rates. 1 Enabled Enabled Enabled Enabled 1 Enabled 01= 0.65V 11 = 0.8V 0 1 Slow Setting Slow Setting Fast Setting Fast Setting Slow Setting Fast Setting Slow Setting Fast Setting 0 1 Slow Setting Fast Setting Default 1 1 1 1 1 1 1 1 Default 0 1 1 0 1 1 1 0 Default 1 1 1 1 1 1 1 1 Default 1 1 0 0 0 1 1 1 Byte 4 is Reserved and reads back 'hFF MARCH 9, 2017 11 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 9DBU0541 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 12 Type RW RW RW RW RW 0 1 A rev = 0000 0001 = IDT/ICS 0 1 00 = FGx, 01 = DBx, 10 = DMx, 11= DBx w/oPLL 000101 binary or 05 hex 0 Default 0 0 0 0 0 0 0 1 Default 1 1 0 0 0 1 0 1 1 Default 0 0 0 0 Writing to this register will configure how 1 many bytes will be read back, default is 0 = 8 bytes. 0 0 MARCH 9, 2017 9DBU0541 DATASHEET Marking Diagrams ICS BU0541AL YYWW COO LOT ICS BU0541AIL YYWW COO LOT Notes: 1. “LOT” is the lot sequence number. 2. “COO” denotes country of origin. 3. YYWW is the last two digits of the year and week that the part was assembled. 4. Line 2: truncated part number 5. “L” denotes RoHS compliant package. 6. “I” denotes industrial temperature range device. Thermal Characteristics PARAMETER SYMBOL Thermal Resistance θJC θJb θJA0 θJA1 θJA3 θJA5 TYP VALUE Junction to Case 42 Junction to Base 2.4 Junction to Air, still air 39 NLG32 Junction to Air, 1 m/s air flow 33 Junction to Air, 3 m/s air flow 28 Junction to Air, 5 m/s air flow 27 CONDITIONS PKG UNITS NOTES °C/W °C/W °C/W °C/W °C/W °C/W 1 1 1 1 1 1 1 ePad soldered to board MARCH 9, 2017 13 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 9DBU0541 DATASHEET www.IDT.com IDT Package Outline and Dimensions (NLG32) 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 14 MARCH 9, 2017 9DBU0541 DATASHEET www.IDT.com IDT Package Outline and Dimensions (NLG32), cont. MARCH 9, 2017 15 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 9DBU0541 DATASHEET Ordering Information Part / Order Number Shipping Packaging 9DBU0541AKLF Trays 9DBU0541AKLFT Tape and Reel 9DBU0541AKILF Trays 9DBU0541AKILFT Tape and Reel Package 32-pin VFQFPN 32-pin VFQFPN 32-pin VFQFPN 32-pin VFQFPN Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). Revision History Rev. A B C D E F Initiator Issue Date Description Page # RDW 7/15/2014 Final update and release - front page and electrical tables. Various 1. Removed VDDIO reference in the Electrical Characteristics Input/Supply/Common Parameters and Absolute Maximum Ratings RDW 7/24/2014 6 tables. This power rail does not exist on this device. The pinout and the pin descriptions are correct. Updated SMBus Input High/Low parameters conditions, MAX values, RDW 9/19/2014 6 and footnotes. 1. Updated Key Specifications to be consistent across the family. 2. Updated pin out and pin descriptions to show ePad on package connected to ground. RDW 4/22/2015 1-3,5 3. Updated Clock Input Parameters table to be consistent with PCIe Vswing parameter. 4. Add note about epad to Power Connections table. 1. Updated pins 21 and 20 from VDDA1.5/GNDA to VDDO1.5/GND to 2, 3 RDW 2/16/2017 clearly indicate that this part has no PLL. 1. Removed "Bypass Mode" reference in "Output Duty Cycle..." and "Phase Jitter Parameters" tables; update note 3 under Output Duty Cycle table. 7, 8 RDW 3/9/2017 2. Corrected spelling errors/typos. 3. Change VDDA to VDDO1.5 in Current Consumption table. 4. Update Additive Phase Jitter conditions for PCIe Gen3. 5-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 16 MARCH 9, 2017 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.idt.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved. 9DBU0541 MARCH 9, 2017 17 ©2017 Integrated Device Technology, Inc. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.