9DBV0231AKILF

2-Output 1.8V PCIe Zero-Delay/Fanout Clock Buffer with Zo = 33Ohms 9DBV0231 DATASHEET Description Features/Benefits The 9DBV0231 is a member of Renesas’ 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. • LP-HCSL outputs; save 4 resistors compared to standard Recommended Application • • 1.8V PCIe Gen1–5 Zero-Delay/Fan-out Buffer (ZDB/FOB) • • Output Features • Two 1–200MHz Low-Power (LP) HCSL DIF pairs • Key Specifications • • • • DIF cycle-to-cycle jitter < 50ps DIF output-to-output skew < 50ps PCIe Gen5 CC additive phase jitter < 40fs RMS 12kHz–20MHz additive phase jitter = 156fs RMS at 156.25MHz (typical) • • • • • Block Diagram vOE(1:0)# HCSL outputs 35mW typical power consumption in PLL mode; reduced thermal concerns Spread Spectrum (SS) compatible; allows use of SS for EMI reduction OE# pins; support DIF power management HCSL compatible differential input; can be driven by common clock sources SMBus-selectable features; optimize signal integrity to application • Slew rate for each output • Differential output amplitude Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application Outputs blocked until PLL is locked; clean system start-up Device contains default configuration; SMBus interface not required for device control 3.3V tolerant SMBus interface works with legacy controllers Space saving 4 × 4mm 24-VFQFPN; minimal board space , 2 DIF1 CLK_IN CLK_IN# SSCompatible PLL DIF0 ^vHIBW_BYPM_LOBW# ^CKPWRGD_PD# SDATA_3.3 CONTROL LOGIC SCLK_3.3 9DBV0231 R31DS0074EU0700 JULY 30, 2021 1 ©2021 Renesas Electronics Corporation 9DBV0231 DATASHEET vOE1# VDDO1.8 GND ^CKPWRGD_PD# ^vHIBW_BYPM_LOBW# FB_DNC Pin Configuration 24 23 22 21 20 19 FB_DNC# 1 VDDR1.8 2 CLK_IN 3 CLK_IN# 4 9DBV0231 epad is Gnd GNDR 5 18 DIF1# 17 DIF1 16 VDDA1.8 15 GNDA 14 DIF0# GNDDIG 6 13 DIF0 vOE0# VDDO1.8 9 10 11 12 GND SCLK_3.3 8 SDATA_3.3 VDDDIG1.8 7 24-pin VFQFPN, 4x4 mm, 0.5mm pitch ^ prefix indicates internal 120KOhm pull up resistor ^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 120KOhm pull down resistor Power Management Table SMBus DIFx OEx# Pin True O/P Comp. O/P OEx bit 0 X X X Low Low 1 Running 0 X Low Low 1 Running 1 0 Running Running 1 Running 1 1 Low Low 1. If Bypass mode is selected, the PLL will be off, and outputs will be running. CKPWRGD_PD# CLK_IN SMBus Address Table Address 1101101 + Off On1 On1 On1 Frequency Select Table Read/Write bit x Power Connections Pin Number VDD 2 7 11,20 16 PLL GND 5 6 10,21 15 Description Input receiver analog Digital Power DIF outputs PLL Analog 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS FSEL Byte3 [4:3] 00 (Default) 01 10 11 CLK_IN (MHz) 100.00 50.00 125.00 Reserved DIFx (MHz) CLK_IN CLK_IN CLK_IN Reserved PLL Operating Mode HiBW_BypM_LoBW# 0 M 1 2 MODE PLL Lo BW Bypass PLL Hi BW Byte1 [7:6] Readback 00 01 11 Byte1 [4:3] Control 00 01 11 R31DS0074EU0700 JULY 30, 2021 9DBV0231 DATASHEET Pin Descriptions Pin# Pin Name Description Complement clock of differential feedback. The feedback output 1 FB_DNC# DNC and feedback input are connected internally on this pin. Do not connect anything to this pin. 1.8V power for differential input clock (receiver). This VDD should 2 VDDR1.8 PWR be treated as an Analog power rail and filtered appropriately. 3 CLK_IN IN True Input for differential reference clock. 4 CLK_IN# IN Complementary Input for differential reference clock. 5 GNDR GND Analog Ground pin for the differential input (receiver) 6 GNDDIG GND Ground pin for digital circuitry 7 VDDDIG1.8 PWR 1.8V digital power (dirty power) 8 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 9 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 10 GND GND Ground pin. 11 VDDO1.8 PWR Power supply for outputs, nominally 1.8V. Active low input for enabling DIF pair 0. This pin has an internal pull12 vOE0# IN down. 1 =disable outputs, 0 = enable outputs 13 DIF0 OUT Differential true clock output 14 DIF0# OUT Differential Complementary clock output 15 GNDA GND Ground pin for the PLL core. 16 VDDA1.8 PWR 1.8V power for the PLL core. 17 DIF1 OUT Differential true clock output 18 DIF1# OUT Differential Complementary clock output Active low input for enabling DIF pair 1. This pin has an internal pull19 vOE1# IN down. 1 =disable outputs, 0 = enable outputs 20 VDDO1.8 PWR Power supply for outputs, nominally 1.8V. 21 GND GND Ground pin. Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high 22 ^CKPWRGD_PD# IN assertions exit Power Down Mode. This pin has internal pull-up resistor. LATCHED Trilevel input to select High BW, Bypass or Low BW mode. 23 ^vHIBW_BYPM_LOBW# IN See PLL Operating Mode Table for Details. True clock of differential feedback. The feedback output and 24 FB_DNC DNC feedback input are connected internally on this pin. Do not connect anything to this pin. 25 ePad GND Connect epad to ground. NOTE: DNC indicates Do Not Connect anything to this pin. R31DS0074EU0700 JULY 30, 2021 Type 3 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 9DBV0231 DATASHEET Test Loads Low-Power HCSL Differential Output Test Load L Rs Zo=100ohm 2pF Rs 2pF Device L = 5 inches Differential Output Terminations Rs 33 27 Zo 100 85 Units Ohms Alternate Terminations The 9DBV family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with "Universal" Low-Power HCSL Outputs” for details. 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 4 R31DS0074EU0700 JULY 30, 2021 9DBV0231 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBV0231. These ratings, which are standard values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBOL CONDITIONS 1.8V Supply Voltage Input Voltage Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD protection VDDxx VIN VIHSMB Ts Tj ESD prot Applies to all VDD pins MIN -0.5 -0.5 TYP SMBus clock and data pins -65 Human Body Model MAX 2.5 VDD+0.5V 3.6V 150 125 2000 UNITS NOTES V V V °C °C V 1,2 1, 3 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. 3 Not to exceed 2.5V. Electrical Characteristics–Clock Input Parameters TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER Input Common Mode Voltage - DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES V COM Common Mode Input Voltage 150 1000 VSWING Differential value 300 1450 mV 1 dv/dt Measured differentially 0.4 8 V/ns 1,2 mV 1 Input Leakage Current IIN VIN = VDD , V IN = GND -5 5 uA Input Duty Cycle dtin Measurement from differential waveform 45 55 % 1 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 125 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero. R31DS0074EU0700 JULY 30, 2021 5 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 9DBV0231 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX Supply Voltage VDDx Supply voltage for core and analog 1.7 1.8 1.9 V Ambient Operating Temperature TAMB Commercial range 0 25 70 °C Industrial range -40 25 85 °C Input High Voltage V IH Single-ended inputs, except SMBus 0.75 VDD V DD + 0.3 V Input Mid Voltage V IM Single-ended tri-level inputs ('_tri' suffix) 0.4 V DD 0.6 V DD V Input Low Voltage V IL Single-ended inputs, except SMBus -0.3 0.25 V DD V IIN Single-ended inputs, V IN = GND, VIN = VDD -5 5 uA IINP Single-ended inputs V IN = 0 V; Inputs with internal pull-up resistors -200 200 uA Input Current UNITS NOTES V IN = VDD; Inputs with internal pull-down resistors Input Frequency Pin Inductance Capacitance Fiby p Bypass mode 1 200 MHz 2 Fipll 100MHz PLL mode 50 100.00 140 MHz 2 Fipll 125MHz PLL mode 62.5 125.00 175 MHz 2 Fipll 50MHz PLL mode 25 50.00 65 MHz 2 7 nH 1 CIN Logic Inputs, except DIF_IN 1.5 5 pF 1 CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1,5 6 pF 1 1 ms 1,2 30 33 kHz 0 66 kHz 1 3 clocks 1,3 300 us 1,3 Lpin Output pin capacitance COUT OE# Latency tLATOE# Tdrive_PD# t DRVPD Tfall tF From V DD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency for PCIe Applications (Triangular Modulation) Allowable Frequency for non-PCIe Applications (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of single-ended control inputs Trise tR Rise time of single-ended control inputs Clk Stabilization Input SS Modulation Frequency PCIe Input SS Modulation Frequency non-PCIe TSTAB fMODINPCIe fMODIN SMBus Input Low Voltage V ILSMB VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V SMBus Input High Voltage VIHSMB VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V SMBus Output Low Voltage V OLSMB At IPULLUP SMBus Sink Current IPULLUP At V OL 4 1.7 V 3.6 V 0.4 4 V mA Bus Voltage 3.6 V tRSMB (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Fall Time SMBus Operating Frequency tFSMB (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 fMAXSMB Maximum SMBus operating frequency 400 kHz 6 Control input must be monotonic from 20% to 80% of input swing. 6 0.6 V DDSMB Guaranteed by design and characterization, not 100% tested in production. 5 2 2 Nominal Bus Voltage 2 4 ns ns SCLK/SDATA Rise Time 1 3 2.1 5 5 Time from deassertion until outputs are >200 mV. For VDDSMB < 3.3V, V IHSMB >= 0.8xVDDSMB. DIF_IN input. The differential input clock must be running for the SMBus to be active. 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 6 R31DS0074EU0700 JULY 30, 2021 9DBV0231 DATASHEET Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP Scope averaging on, fast setting Scope averaging on, slow setting Slew rate matching, Scope averaging on 1.9 1.4 Slew rate matching dV/dt dV/dt  dV/dt 3.2 2.3 5 4 3.3 20 Voltage High VHIGH 660 779 850 Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) -150 21 150 835 -42 409 14 1150 -300 250 Slew rate Measurement on single ended signal using Vmax absolute value. (Scope averaging off) Vmin Vcross_abs Scope averaging off Scope averaging off Δ-Vcross 1 Guaranteed by design and characterization, not 100% tested in production. Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) 2 MAX UNITS NOTES 550 140 V/ns V/ns % 1,2,3 1,2,3 1,2,4 7 mV 7 7 7 1,5 1,6 mV mV mV Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 At default SMBus settings. Electrical Characteristics–Current Consumption TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS IDDA VDDA+VDDR, PLL Mode, @100MHz I DD VDD, All outputs active @100MHz IDDAPD IDDPD VDDA+VDDR, PLL Mode, @100MHz Operating Supply Current Powerdown Current VDD, Outputs Low/Low 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input clock stopped. R31DS0074EU0700 JULY 30, 2021 7 MIN TYP MAX UNITS NOTES 4.4 6 mA 1 14.2 18 mA 1 0.014 0.9 1 1.4 mA mA 1, 2 1, 2 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 9DBV0231 DATASHEET Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES PLL Bandwidth BW 2 1 tJPEAK t DC -3dB point in High BW Mode -3dB point in Low BW Mode Peak Pass band Gain Measured differentially, PLL Mode 45 2.7 1.4 1.05 50 4 2 2 55 MHz MHz dB % 1,5 1,5 1 1 PLL Jitter Peaking Duty Cycle Duty Cycle Distortion t DCD Measured differentially, Bypass Mode @100MHz -1 -0.1 1 % 1,3 Jitter, Cycle to cycle t jcyc-cyc Bypass Mode, VT = 50% PLL Mode VT = 50% V T = 50% PLL mode Additive Jitter in Bypass Mode 2600 0 Skew, Output to Output tpdBYP tpdPLL t sk3 3370 112 33 13 0.1 4200 200 50 50 5 ps ps ps ps ps 1 1,4 1,4 1,2 1,2 Skew, Input to Output 1 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform 3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 4 All outputs at default slew rate 5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN. Electrical Characteristics–Phase Jitter Parameters – 12kHz to 20MHz TAMB = over the specified operating range. Supply Voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Symbol Conditions Minimum Typical Maximum 12k-20M Additive Phase Jitter, Fan-out Buffer Mode, tjph12k-20MFOB 156 Fan-out Buffer Mode SSC OFF, 156.25M Hz Notes: 1. Applies to all differential outputs, guaranteed by design and characterization. See Test Loads for measurement setup details. 2. 12kHz to 20M Hz brick wall filter. 2 Specification Limit Units Notes n/a fs (rms) 1, 2, 3 2 3. For RM S values additive jitter is calculated by solving for b where [b = sqrt(c - a )], a is rms input jitter and c is rms total jitter. 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 8 R31DS0074EU0700 JULY 30, 2021 9DBV0231 DATASHEET Electrical Characteristics–Additive PCIe Phase Jitter for Fanout Buffer Mode[7] TAMB = over the specified operating range. Supply Voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Symbol Conditions Minimum Typical Maximum Limit tjphPCIeG1-CC PCIe Gen 1 (2.5 GT/s) 1.7 3.0 86 PCIe Gen 2 Hi Band (5.0 GT/s) 0.033 0.049 3 PCIe Gen 2 Lo Band (5.0 GT/s) 0.122 0.199 3.1 tjphPCIeG3-CC PCIe Gen 3 (8.0 GT/s) 0.059 0.098 1 tjphPCIeG4-CC PCIe Gen 4 (16.0 GT/s) 0.059 0.098 0.5 tjphPCIeG5-CC PCIe Gen 5 (32.0 GT/s) 0.023 0.038 0.15 tjphPCIeG1-SRIS PCIe Gen 1 (2.5 GT/s) 0.175 0.038 n/a tjphPCIeG2-SRIS PCIe Gen 2 (5.0 GT/s) 0.156 0.275 n/a tjphPCIeG3-SRIS PCIe Gen 3 (8.0 GT/s) 0.041 0.247 n/a tjphPCIeG4-SRIS PCIe Gen 4 (16.0 GT/s) 0.043 0.064 n/a tjphPCIeG5-SRIS PCIe Gen 5 (32.0 GT/s) 0.036 0.066 n/a tjphPCIeG2-CC Additive PCIe Phase Jitter, Fan-out Buffer Mode (Common Clocked Architecture) Additive PCIe Phase Jitter, Fan-out Buffer Mode (SRIS Architecture) Units ps (p-p) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) Notes 1, 2 1, 2 1, 2 1, 2 1, 2, 3, 4 1, 2, 3, 5 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 Notes: 1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The total Ref Clk jitter limits for each data rate are listed for convenience. The worst case results for each data rate are summarized in this table. If oscilloscope data is used, equipment noise is removed from all results. 2. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately Jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200 MHz (at 300 MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results the RTO result must be used. 3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 MHz taking care to minimize removal of any non-SSC content. 4. Note that 0.7 ps RMS is to be used in channel simulations to account for additional noise in a real system. 5. Note that 0.25 ps RMS is to be used in channel simulations to account for additional noise in a real system. 6. The PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, however, it does not provide specification limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by 2. And additional consideration is the value for which to divide by 2. The conservative approach is to divide the ref clock jitter limit, and the case can be made for dividing the channel simulation values by 2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A "rule-of-thumb" SRIS limit would be either 0.5ps RMS/2 = 0.35ps RMS if the clock chip is far from the clock input, or 0.7ps RM S/2 = 0.5ps RMS if the clock chip is near the clock input.. 7. Additive jitter for RMS values is calculated by solving for b where b √ 𝑐2 𝑎2 , and a is rms input jitter and c is rms output jitter. R31DS0074EU0700 JULY 30, 2021 9 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 9DBV0231 DATASHEET Additive Phase Jitter Plot: 125M (12kHz to 20MHz) RMS additve jitter: 251fs 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 10 R31DS0074EU0700 JULY 30, 2021 9DBV0231 DATASHEET General SMBus Serial Interface Information How to Write • • Controller (host) sends a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) sends the byte count = X Renesas clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 Renesas clock will acknowledge each byte one at a time Controller (host) sends a Stop bit • • • Index Block Write Operation Controller (Host) T starT bit WRite ACK Beginning Byte = N ACK ACK Data Byte Count = X ACK RT ACK RD Repeat starT Slave Address Beginning Byte N ReaD X Byte ACK O Data Byte Count=X O O ACK ACK ACK Beginning Byte N Byte N + X - 1 P Renesas starT bit Slave Address Beginning Byte = N O Controller (Host) WR ACK O Index Block Read Operation T WRite O Controller (host) will send a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Renesas clock will acknowledge Renesas clock will send the data byte count = X Renesas clock sends Byte N+X-1 Renesas clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Renesas (Slave/Receiver) Slave Address WR • • • • • • • • • • • stoP bit X Byte • • • • • • • • How to Read O O Note: SMBus Address is 1101101x, where x is the read/write bit. R31DS0074EU0700 JULY 30, 2021 11 O O O O Byte N + X - 1 N Not acknowledge P stoP bit 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 9DBV0231 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 Reserved Bit 7 Reserved Bit 6 DIF OE1 Output Enable RW Low/Low Bit 5 Reserved Bit 4 DIF OE0 Output Enable RW Low/Low Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 1. A low on these bits will override the OE# pin and force the differential output Low/Low SMBus Table: PLL Operating Mode and Output Amplitude Control Register Byte 1 Name Control Function Type PLLMODERB1 PLL Mode Readback Bit 1 Bit 7 R PLLMODERB0 PLL Mode Readback Bit 0 Bit 6 R Bit 5 PLLMODE_SWCNTRL Enable SW control of PLL Mode RW PLLMODE1 PLL Mode Control Bit 1 Bit 4 PLLMODE0 PLL Mode Control Bit 0 Bit 3 Reserved Bit 2 AMPLITUDE 1 Bit 1 Controls Output Amplitude AMPLITUDE 0 Bit 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: DIF Slew Rate Control Register Byte 2 Name Control Function Reserved Bit 7 Reserved Bit 6 SLEWRATESEL DIF1 Slew Rate Selection Bit 5 Reserved Bit 4 SLEWRATESEL DIF0 Slew Rate Selection Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 SMBus Table: Frequency Select Control Register Byte 3 Name Control Function Reserved Bit 7 Reserved Bit 6 Enable SW selection of FREQ_SEL_EN Bit 5 frequency FSEL1 Freq. Select Bit 1 Bit 4 FSEL0 Freq. Select Bit 0 Bit 3 Reserved Bit 2 Reserved Bit 1 SLEWRATESEL FB Adjust Slew Rate of FB Bit 0 1. B3[5] must be set to a 1 for these bits to have any effect on the part. 0 1 Enabled Enabled 1 See PLL Operating Mode Table Values in B1[7:6] set PLL Mode Values in B1[4:3] set PLL Mode 1 RW RW 1 See PLL Operating Mode Table RW RW 00 = 0.6V 10= 0.8V 01 = 0.7V 11 = 0.9V Type 0 1 RW Slow setting Fast setting RW Slow setting Fast setting Type 0 1 RW SW frequency change disabled SW frequency change enabled RW 1 RW 1 RW See Frequency Select Table Slow setting Fast setting Default 1 1 1 1 1 1 1 1 Default Latch Latch 0 0 0 1 1 0 Default 1 1 1 1 1 1 1 1 Default 1 1 0 0 0 1 1 1 Byte 4 is Reserved and reads back 'hFF 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 12 R31DS0074EU0700 JULY 30, 2021 9DBV0231 DATASHEET SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function RID3 Bit 7 RID2 Bit 6 Revision ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R SMBus Table: Device Type/Device ID Byte 6 Name Device Type1 Bit 7 Device Type0 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 Bit 0 Type R R R R R R R R SMBus Table: Byte Count Register Byte 7 Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 R31DS0074EU0700 JULY 30, 2021 Control Function Device Type Device ID Control Function Reserved Reserved Reserved Byte Count Programming 13 Type RW RW RW RW RW 0 1 A rev = 0000 0001 = IDT 0 1 00 = FGx, 01 = DBx, 10 = DMx, 11= Reserved 000100 binary or 02 hex 0 Default 0 0 0 0 0 0 0 1 Default 0 1 0 0 0 0 1 0 1 Default 0 0 0 0 Writing to this register will configure how 1 many bytes will be read back, default is 0 = 8 bytes. 0 0 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 9DBV0231 DATASHEET Marking Diagrams LOT 031AL YYWW LOT 031AIL YYWW Notes: 1. “LOT” is the lot sequence number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. Line 2: truncated part number 4. “L” denotes RoHS compliant package. 5. “I” denotes industrial temperature range device. Thermal Characteristics 1 PARAMETER SYMBOL CONDITIONS Thermal Resistance θJC θJb θJA0 θJA1 θJA3 θJA5 Junction to Case Junction to Base Junction to Air, still air Junction to Air, 1 m/s air flow Junction to Air, 3 m/s air flow Junction to Air, 5 m/s air flow TYP UNITS NOTES VALUE 62 °C/W 1 5.4 °C/W 1 50 °C/W 1 NLG20 NLG24 43 °C/W 1 39 °C/W 1 C/W 38 ° 1 PKG ePad soldered to board 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 14 R31DS0074EU0700 JULY 30, 2021 9DBV0231 DATASHEET Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 24-VFQFPN (NLG24P1) Ordering Information Part / Order Number Shipping Packaging 9DBV0231AKLF Tubes 9DBV0231AKLFT Tape and Reel 9DBV0231AKILF Tubes 9DBV0231AKILFT Tape and Reel Package 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN 24-pin VFQFPN Temperature 0 to +70° C 0 to +70° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). Revision History Revision Date Description 1. Updated electrical characteristics tables. August 13, 2012 2. Move to final. 1. Changed VIH min. from 0.65*VDD to 0.75*VDD 2. Changed VIL max. from 0.35*VDD to 0.25*VDD September 16, 2014 3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to 0.6*VDD. 4. Changed Shipping Packaging from "Trays" to "Tubes". 5. Reformatted to new template 1. Updated block diagram with new format showing individual outputs instead of bussed outputs. 2. Updated pin out and pin descriptions to show ePad on package connected to ground. April 3, 2015 3. Updated front page text to standard format for these devices. Added explicit bullet indicated Spread Spectrum compatibilty. Changed data sheet title, etc. 4. Added additive phase jitter plot and updated phase jitter spec table. 1. Replaced "Driving LVDS" with "Alternate Terminations", adding reference to AN-891. 2. Updated "Clock Input Parameters Table" correcting inconsistency with PCIe SIG specifications. August 10, 2015 3. Widened allowable input frequency at each PLL mode frequency. 4. Updated NLG24 package drawing with actual package info instead of generic drawing. 1. Minor typographical corrections throughout the data sheet 2. Updated test load diagram to generic diagram. Length of test load listed outside the drawing. 3. Minor updates to electrical tables for formatting. Removed Schmitt trigger info and output high/low voltage specifications for single-ended outputs, since this part does not have any. 4. "Low-Power HCSL Outputs" table: corrected inversion of slew rate setting with specifications. Changed reference November 5, 2015 from 2 V/ns and 3 V/ns to slow setting and fast setting. Also change references in SMBus Bytes[3:2] 5. "Low-Power HCSL Outputs" table: Removed Vswing parameter since this is an input parameter and is covered in "Clock Input Parameters" Table. 6. Reduced current consumption limits. 7. Minor updates to other electrical tables. April 28, 2016 July 30, 2021 1. 2. 3. 1. 2. 3. 4. 5. Updated max frequency of 100MHz PLL mode to 140MHz Updated max frequency of 125MHz PLL mode to 175MHz Updated max frequency of 50MHz PLL mode to 65MHz Updated document title. Updated Recommended Applications. Updated Key Specifications. Updated Package Outline Drawings section. Updated Phase Jitter tables. R31DS0074EU0700 JULY 30, 2021 15 2-OUTPUT 1.8V PCIE ZERO-DELAY/FANOUT CLOCK BUFFER WITH ZO = 33OHMS 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm NLG24P1, PSC-4192-01, Rev 02, Page 1 © Integrated Device Technology, Inc. 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.90 mm Body,0.50mm Pitch,Epad 2.45 x 2.45 mm NLG24P1, PSC-4192-01, Rev 02, Page 2 Package Revision History © Integrated Device Technology, Inc. Description Date Created Rev No. Sept 9, 2016 Rev 01 Sept 13, 2018 Rev 02 New Format, Recalculate Land Pattern Change QFN to VFQFPN Add Chamfer on Epad IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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