9DML0451AKILF

2:4 3.3V PCIe Gen1–5 Clock Mux 9DML0441 / 9DML0451 DATASHEET Description Features The 9DML0441 and 9DML0451 devices are 3.3V members of IDT's Full-Featured PCIe family. They support PCIe Gen1–5 Common Clocked (CC), Separate Reference no Spread (SRnS), and Separate Reference Independent Spread (SRIS) architectures. The parts provide a choice of asynchronous or glitch-free, gapped-clock switching modes, and offer a choice of integrated output terminations for direct connection to 85Ω or 100Ω transmission lines. • Direct connection to 100 (xx41) or 85 (xx51) • • • • • Typical Applications • • • • Servers ATE Storage Master/Slave applications • • Key Specifications • • • • • Output Features • • • • transmission lines saves up to 16 resistors 79mW typical power consumption Spread Spectrum Clocking (SSC) compatible OE# pins for each output HCSL-compatible differential inputs Selectable asynchronous or glitch-free, gapped-clock switching; allows the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode Space saving 4 × 4 mm 24-VFQFPN Contact factory for customized versions Four 1–200MHz Low-Power HCSL (LP-HCSL) DIF pairs 9DML0441 default ZOUT = 100 9DML0451 default ZOUT = 85 See AN-891 for easy termination to other logic levels PCIe Gen1–5 CC support PCIe Gen1–5 SRIS support Output-to-output skew < 50ps PCIe Gen5 additive jitter (CC) is < 0.06 ps rms 12kHz–20MHz additive phase jitter 285fs rms typical at156.25MHz Block Diagram VDDR3.3 x2 ^OE(3:0)# VDD3.3 4 DIF_INA# DIF_INA A DIF_INB# DIF_INB B DIF3# DIF3 DIF2# DIF2 DIF1# DIF1 DIF0# DIF0 vSW_MODE ^SEL_A_B# GNDR x2 EPAD/GND Note: Default resistors are internal on 41/51 devices. 9DML0441 / 9DML0451 MAY 22, 2019 1 GND 9DML0441 / 9DML0451 DATASHEET DIF3 ^OE2# DIF3# ^OE3# GNDR ^SEL_A_B# Pin Configuration 24 23 22 21 20 19 DIF_INA 1 DIF2# DIF2 VDD3.3 GND DIF1# DIF1 9 10 11 12 DIF0# ^OE1# 8 GNDR vSW_MODE 7 DIF0 VDDR3.3 4 DIF_INB 5 DIF_INB# 6 9DML0441 9DML0451 Connect EPAD to GND ^OE0# DIF_INA# 2 VDDR3.3 3 18 17 16 15 14 13 24-VFQFPN, 4 x 4 mm, 0.5mm pitch ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor Power Management Table OEx# Pin DIF_IN 0 1 Running Running DIFx True O/P Comp. O/P Running Running Low Low Power Connections Pin Number VDD GND 3 24 4 7 16 15 2:4 3.3V PCIE GEN1–5 CLOCK MUX Description Input A receiver analog Input B receiver analog DIF outputs 2 MAY 22, 2019 9DML0441 / 9DML0451 DATASHEET Pin Descriptions Pin# Pin Name 1 DIF_INA 2 DIF_INA# Type IN IN 3 VDDR3.3 PWR 4 VDDR3.3 PWR 5 6 7 DIF_INB DIF_INB# GNDR IN IN GND 8 vSW_M ODE IN 9 ^OE0# IN 10 11 DIF0 DIF0# OUT OUT 12 ^OE1# IN 13 14 15 16 17 18 DIF1 DIF1# GND VDD3.3 DIF2 DIF2# OUT OUT GND PWR OUT OUT 19 ^OE2# IN 20 21 DIF3 DIF3# OUT OUT 22 ^OE3# IN 23 ^SEL_A_B# IN 24 25 GNDR EPAD MAY 22, 2019 GND GND Pin Description True input of differential clock Complement input of differential clock Power supply for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. Nominally 3.3V. Power supply for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. Nominally 3.3V. True input of differential clock Complement input of differential clock Analog ground pin for the differential input (receiver). Switch M ode. This pin selects either asynchronous or glitch-free, gapped clock switching of the mux. Use asynchronous mode if 0 or 1 of the input clocks is running. Glitch-free, gapped clock mode may be used if both input clocks are running. This pin has an internal pull down resistor. 0 = asynchronous switching mode 1 = glitch-free, gapped clock switching mode Active low input for enabling output 0. This pin has an internal pull-up resistor. 1 = disable output, 0 = enable output. Differential true clock output. Differential complementary clock output. Active low input for enabling output 1. This pin has an internal pull-up resistor. 1 = disable output, 0 = enable output. Differential true clock output. Differential complementary clock output. Ground pin. Power supply, nominally 3.3V Differential true clock output. Differential complementary clock output. Active low input for enabling output 2. This pin has an internal pull-up resistor. 1 = disable output, 0 = enable output. Differential true clock output. Differential complementary clock output. Active low input for enabling output 3. This pin has an internal pull-up resistor. 1 = disable output, 0 = enable output. Input to select differential input clock A or differential input clock B. This input has an internal pull-up resistor. 0 = Input B selected, 1 = Input A selected. Analog ground pin for the differential input (receiver). Connect to Ground. 3 2:4 3.3V PCIE GEN1–5 CLOCK MUX 9DML0441 / 9DML0451 DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DML0441 / 9DML0451. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Supply Voltage Input Voltage Symbol VDDx VIN Conditions Minimum Input High Voltage, SMBus Storage Temperature Junction Temperature Input ESD protection VIHSMB Ts Tj ESD prot SMBus clock and data pins Typical -0.5 -65 Human Body Model Maximum 4.6 VDD+0.5 Units V V Notes 1,2 1,3 3.9 150 125 V °C °C V 1 1 1 1 Maximum Units Notes 2500 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these Conditions is neither implied nor guaranteed. 3 Not to exceed 4.6V. Electrical Characteristics–Clock Input Parameters T A = T AMB, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions Parameter Symbol Conditions Minimum Typical Input Common Mode Voltage DIF_IN Input Swing - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current VCOM Common Mode Input Voltage 150 900 mV 1 VSWING dv/dt IIN Differential value Measured differentially VIN = VDD , VIN = GND 300 0.4 -5 8 5 mV V/ns uA 1 1,2 Input Duty Cycle dtin Measurement from differential waveform 45 55 % 1 Input Jitter - Cycle to Cycle JDIFIn Differential Measurement 0 125 ps 1 Notes 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero. Electrical Characteristics–Current Consumption T A = T AMB, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions Parameter Operating Supply Current Powerdown Current 1 Symbol Conditions IDD IDDPD Minimum Typical Maximum Units VDD, All outputs active at 100MHz 24 31 mA VDD, all outputs disabled 2 3 mA 1 Input clock stopped. 2:4 3.3V PCIE GEN1–5 CLOCK MUX 4 MAY 22, 2019 9DML0441 / 9DML0451 DATASHEET Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions T A = T AMB, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions Parameter Symbol Supply Voltage VDDx Ambient Operating Temperature T AMB Conditions Supply voltage for core and analog Industrial range Minimum 3.135 -40 Typical 3.3 25 Maximum 3.465 85 Units V °C Notes Input High Voltage VIH Single-ended inputs, except SMBus 0.75 VDD VDD + 0.3 V Input Low Voltage VIL Single-ended inputs, except SMBus -0.3 0.25 VDD V IIN Single-ended inputs, VIN = GND, VIN = VDD Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors -5 5 uA -50 50 uA 1 200 MHz 2 7 nH 1 pF 1 Input Current IINP VIN = VDD; Inputs with internal pull-down resistors Input Frequency F ibyp Pin Inductance Lpin Capacitance CIN Logic Inputs, except DIF_IN 1.5 5 CINDIF_IN DIF_IN differential clock inputs 1.5 2.7 pF 1 COUT Output pin capacitance 6 pF 1 0.74 1 ms 1,2 31.5 33 kHz 66 kHz 3 clocks OE# Latency tLATOE# Tfall tF From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency for PCIe Applications (Triangular Modulation) Allowable Frequency for non-PCIe Applications (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion Fall time of single-ended control inputs Trise tR Rise time of single-ended control inputs Clk Stabilization T STAB Input SS Modulation Frequency fMODINPCIe PCIe Input SS Modulation Frequency fMODIN non-PCIe 1 Guaranteed by design and characterization, not 100% tested in production. 2 Control input must be monotonic from 20% to 80% of input swing. Time from deassertion until outputs are > 200 mV. 3 MAY 22, 2019 5 30 0 1 2 1,3 5 ns 2 5 ns 2 2:4 3.3V PCIE GEN1–5 CLOCK MUX 9DML0441 / 9DML0451 DATASHEET Electrical Characteristics–DIF Low-Power HCSL Outputs T A = T AMB, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions Parameter Symbol Conditions Minimum 1.5 Slew rate dV/dt Scope averaging on, default settings Slew rate matching ΔdV/dt Slew rate matching Voltage High VHIGH Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Maximum Voltage Minimum Voltage Crossing Voltage (abs) Crossing Voltage (var) VMaximum VMinimum Vcross_abs Δ-Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Typical Maximum Units Notes 2.4 4 V/ns 1, 2, 3 8.1 20 % 1, 4 660 783 850 -150 -24 150 814 -66 368 17 1150 -300 250 550 140 7 mV 7 7 7 1, 5 1, 6 mV mV mV 1 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. These are defaults for the 41/51 devices, alternate settings are available in the P1 device. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_Minimum/Maximum (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 These are defaults for the 41/51 devices. They are factory adjustable in the P1 device. Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics T A = T AMB, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions Parameter Symbol Conditions Minimum Typical Maximum Units Notes Duty Cycle Distortion tDCD Measured differentially, at 100MHz 0 0.2 0.7 % 1,3 2637 3381 4273 ps 1 23 50 ps 1 1 ps 1,2 Skew, Input to Output tpd VT = 50% Skew, Output to Output tsk3 VT = 50% Jitter, Cycle to cycle tjcyc-cyc Additive Jitter 1 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform. 3 Duty cycle distortion is the difference in duty cycle between the output and the input clock. 2:4 3.3V PCIE GEN1–5 CLOCK MUX 6 MAY 22, 2019 9DML0441 / 9DML0451 DATASHEET Electrical Characteristics–Additive PCIe Phase Jitter T AMB = over the specified operating range. Supply Voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Symbol tjphPCIeG1-CC tjphPCIeG2-CC Additive PCIe Phase Jitter (Common Clocked Architecture) tjphPCIeG3-CC tjphPCIeG4-CC tjphPCIeG5-CC tjphPCIeG1-SRIS tjphPCIeG2-SRIS Additive PCIe Phase Jitter (SRIS Architecture) tjphPCIeG3-SRIS tjphPCIeG4-SRIS tjphPCIeG5-SRIS Conditions Minimum Typical Maximum PCIe Gen 1 (2.5 GT/s) SSC < -0.5% PCIe Gen 2 Hi Band (5.0 GT/s) SSC < -0.5% PCIe Gen 2 Lo Band (5.0 GT/s) SSC < -0.5% PCIe Gen 3 (8.0 GT/s) SSC < -0.5% PCIe Gen 4 (16.0 GT/s) SSC < -0.5% PCIe Gen 5 (32.0 GT/s) SSC < -0.5% PCIe Gen 1 (2.5 GT/s) SSC < -0.3% PCIe Gen 2 Band (5.0 GT/s) SSC < -0.3% PCIe Gen 3 (8.0 GT/s) SSC < -0.3% PCIe Gen 4 (16.0 GT/s) SSC < -0.3% PCIe Gen 5 (32.0 GT/s) SSC < -0.3% Limit 0.214 2.6 5.0 86 0.322 0.357 0.428 3.1 0.008 0.023 0.033 3 0.036 0.091 0.149 1 0.036 0.092 0.156 0.5 0.010 0.031 0.059 0.15 n/a n/a n/a n/a 0.436 0.455 0.524 n/a 0.126 0.131 0.150 n/a 0.107 0.111 0.128 n/a 0.038 0.040 0.045 n/a Units ps (pk-pk) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (pk-pk) ps (RMS) ps (RMS) ps (RMS) ps (RMS) Notes 1, 2 1, 2 1, 2 1, 2 1, 2, 3, 4 1, 2, 3, 5 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 1, 2, 6 Notes: 1. The Refclk jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. T he total Ref Clk jitter limits for each data rate are listed for convenience. The addtiive jitter may be subtracted from the limit using RSS subtraction to determine remaining margin. 2. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RT O measurements. Alternately - Jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200 MHz (at 300 MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data ratem the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results the RT O result must be used. 3. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2 MHz taking care to minimize removal of any non-SSC content. 4. Note that 0.7 ps RMS is to be used in channel simulations to account for additional noise in a real system. 5. Note that 0.25 ps RMS is to be used in channel simulations to account for additional noise in a real system. 6. While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specifcation limits, hence the n/a in the Limit column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by  2. MAY 22, 2019 7 2:4 3.3V PCIE GEN1–5 CLOCK MUX 9DML0441 / 9DML0451 DATASHEET Test Loads Test Load for AC/DC Measurements CL CK+ CKIN+         CK+ L DUT Zo (differential) Clock Source CK- Clock Source SMA100B SMA100B CKIN‐ DUT 9DML0451 9DML0441 Test Points CK‐ CL L (cm) Differential Zo (ohms) 12.7 12.7 85 100 CL (pF) 2 2 Test Load for Phase Jitter Measurements PNA Coax Cables L CK+ CKIN+         CK+ CK- Clock Source SMA100B SMA100B CKIN‐ DUT 9DML0451 9DML0441 Balun Zo (differential) DUT Clock Source 0.1uF CK‐ SMA Connectors L (cm) Differential Zo (ohms) 25.4 25.4 85 100 50 Alternate HCSL Terminations Device 9DML0441 9DML0441 9DML0451 9DML0451 Differential Zo (Ω) 85 100 85 100 Rs (Ω) N/A None needed None needed 7.5 Alternate Terminations The 9DML family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's "Universal" Low-Power HCSL Outputs” for details. 2:4 3.3V PCIE GEN1–5 CLOCK MUX 8 MAY 22, 2019 9DML0441 / 9DML0451 DATASHEET Marking Diagrams LOT 451AI YYWW LOT 441AI YYWW Notes: 1. Line 1: “LOT” is the lot sequence number. 2. Line 2: truncated part number. 3. Line 3: “YYWW” is the digits of the year and work-week that the part was assembled. Thermal Characteristics 1 Parameter Symbol Thermal Resistance θJC θJb θJA0 θJA1 θJA3 θJA5 Typical VALUE Junction to Case 42 Junction to Base 2.4 Junction to Air, still air 39 NLG24 Junction to Air, 1 m/s air flow 33 Junction to Air, 3 m/s air flow 28 Junction to Air, 5 m/s air flow 27 Conditions PKG Units Notes °C/W °C/W °C/W °C/W °C/W °C/W 1 1 1 1 1 1 EPAD soldered to board. Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-090-mm-body050mm-pitchepad-245-x-245-mm-nlg24p1 Ordering Information Part / Order Number 9DML0441AKILF 9DML0441AKILFT 9DML0451AKILF 9DML0451AKILFT Notes 100Ω 85Ω ShippingPackaging Trays Tape and Reel Trays Tape and Reel Package 24-VFQFPN 24-VFQFPN 24-VFQFPN 24-VFQFPN Temperature -40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). MAY 22, 2019 9 2:4 3.3V PCIE GEN1–5 CLOCK MUX Revision History Issue Date 5/22/2019 8/27/2018 6/6/2016 Description 1. Added PCIe Gen5 parameters to electrical tables 2. Removed 'P' devices from data sheet. 1. Minor updates to electrical tables. 2. Updated front page text. 3. Updated block diagram. 1. 2. 3. 4. 5. Updated leakage current spec for inputs with pull/up/down to +/-50µA. Updated electrical tables with characterization data. Update Front page text. Updated ordering information. Move to Final. Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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