9DMU0141AKILF

2:1 1.5V PCIe Gen1-2-3 Clock Mux w/Zo=100ohms 9DMU0141 DATASHEET General Description Features/Benefits The 9DMU0141 is a member of IDT's SOC-Friendly 1.5V Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has integrated output terminations providing Zo=100ohms for direct connection to 100ohm transmission lines. The output has an OE# pin for optimal system control and power management. The part provides asynchronous or glitch-free switching modes. • LP-HCSL output w/integrated terminations; saves 4 • • • • • Recommended Application 2:1 1.5V PCIe Gen1-2-3 Clock Mux • • Output Features • 1 – Low-Power (LP) HCSL DIF pair w/Zo=100 resistors compared to standard HCSL output 1.5V operation; 11mW typical power consumption Selectable asynchronous or glitch-free switching; allows the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode Spread Spectrum Compatible; supports EMI reduction OE# pins; support DIF power management HCSL differential inputs; can be driven by common clock sources 1MHz to 167MHz operating frequency Space saving 16-pin 3x3mm VFQFPN; minimal board space Key Specifications • DIF additive cycle-to-cycle jitter 200 mV 2 4 DIF_IN input 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS 4 REVISION A 09/30/14 9DMU0141 DATASHEET Electrical Characteristics–Clock Input Parameters TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL Input High Voltage - DIF_IN VIHDIF Input Low Voltage - DIF_IN VILDIF Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle 1 CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) MIN TYP MAX UNITS NOTES 300 750 1150 mV 1 VSS - 300 0 300 mV 1 VCOM Common Mode Input Voltage 200 725 mV 1 VSWING dv/dt IIN dtin J DIFIn Peak to Peak value (VIHDIF - VILDIF) Measured differentially VIN = VDD , VIN = GND Measurement from differential wavefrom Differential Measurement 300 0.35 -5 45 0 1450 8 5 55 150 mV V/ns uA % ps 1 1,2 50 1 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero 2 Electrical Characteristics–DIF Low-Power HCSL Outputs TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Slew rate Slew rate matching dV/dt ΔdV/dt Scope averaging on, fast setting Slew rate matching, Scope averaging on 1.2 2.4 13 3.6 20 Voltage High VHIGH 550 755 850 Voltage Low VLOW Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) -150 21 150 Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs Δ-Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off 766 -25 1469 367 12 1150 -300 300 250 V/ns % 1,2,3 1,2,4 mV 550 140 mV mV mV mV 1,2 1,5 1,6 1 Guaranteed by design and characterization, not 100% tested in production. Measured from differential waveform 2 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. Electrical Characteristics–Current Consumption TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER Operating Supply Current Powerdown Current SYMBOL IDD CONDITIONS VDD, All outputs active @100MHz IDDPD VDD, all outputs disabled MIN TYP MAX 7 1.4 11 2.5 UNITS mA mA NOTES 1 1, 2 1 Guaranteed by design and characterization, not 100% tested in production. 2 Input clock stopped. REVISION A 09/30/14 5 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS 9DMU0141 DATASHEET Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Duty Cycle Distortion Skew, Input to Output Skew, Output to Output Jitter, Cycle to cycle tDCD Measured differentially @100MHz Bypass Mode, VT = 50% VT = 50% Additive Jitter -1 2196 -0.2 2923 N/A 0.1 1 3978 N/A 8 % ps ps ps 1,3 1 1 1,2 tpdBYP tsk3 tjcyc-cyc 1 Guaranteed by design and characterization, not 100% tested in production. 2 Measured from differential waveform 3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. Electrical Characteristics–Phase Jitter Parameters TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS tjphPCIeG1 PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4 or 2-5MHz, CDR = 10MHz) tjphPCIeG2 Additive Phase Jitter, Bypass Mode tjphPCIeG3 MIN INDUSTRY LIMIT UNITS TYP MAX 0.4 5 N/A 0.4 0.6 N/A 0.1 0.2 N/A 0.050 0.1 N/A ps (p-p) ps (rms) ps (rms) ps (rms) Notes 1,2,3,5 1,2,3,4, 5 1,2,3,4 1,2,3,4 tjph125M0 125MHz, 1.5MHz to 10MHz, -20dB/decade rollover < 1.5MHz, -40db/decade rolloff > 10MHz 365 380 N/A fs (rms) 1,6 tjph125M1 125MHz, 12KHz to 20MHz, -20dB/decade rollover < 1.5MHz, -40db/decade rolloff > 10MHz 535 550 N/A fs (rms) 1,6 1 Guaranteed by design and characterization, not 100% tested in production. 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2] 5 Driven by 9FGU0831 or equivalent 6 Rohde&Schartz SMA100 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS 6 REVISION A 09/30/14 9DMU0141 DATASHEET Marking Diagrams XXX YYWW U41AI Notes: 1. “XXX” is the last 3 characters of the lot number. 2. “YYWW” is the last two digits of the year and week that the part was assembled. 3. Line 3: truncated part number 4. “I” denotes industrial temperature grade. Thermal Characteristics PARAMETER SYMBOL Thermal Resistance θJC θJb θJA0 θJA1 θJA3 θJA5 TYP VALUE Junction to Case 66 Junction to Base 5 Junction to Air, still air 63 NLG16 Junction to Air, 1 m/s air flow 56 Junction to Air, 3 m/s air flow 51 Junction to Air, 5 m/s air flow 49 CONDITIONS PKG UNITS NOTES °C/W °C/W °C/W °C/W °C/W °C/W 1 1 1 1 1 1 1 ePad soldered to board REVISION A 09/30/14 7 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS 9DMU0141 DATASHEET Package Outline and Package Dimensions (NLG16) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane A1 Index Area N 1 2 (Ref) ND & NE Even (ND-1)x e (Ref) L A3 e N 1 (Typ) If ND & NE 2 are Even 2 Sawn Singulation E E2 E2 Top View (NE-1)x e (Ref) 2 b A (Ref) ND & NE Odd D C 0.08 C Symbol Millimeters Min Max A A1 A3 b e N ND NE D x E BASIC D2 E2 L 0.80 1.00 0 0.05 0.20 Reference 0.18 0.30 0.50 BASIC 16 4 4 3.00 x 3.00 1.55 1.80 1.55 1.80 0.30 0.50 e Thermal Base D2 2 D2 Ordering Information Part / Order Number Shipping Packaging 9DMU0141AKILF Trays 9DMU0141AKILFT Tape and Reel Package 16-pin VFQFPN 16-pin VFQFPN Temperature -40 to +85° C -40 to +85° C “LF” to the suffix denotes Pb-Free configuration, RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS 8 REVISION A 09/30/14 9DMU0141 DATASHEET Revision History Rev. A Initiator Issue Date Description 1. Update front page text and electrical tables with char data. RDW 9/29/2014 2. Update pinout diagram with note about package paddle. 3. Move to final. REVISION A 09/30/14 9 Page # Various 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.