Advance Information
ICS9DS400
Four Output Differential Buffer for PCIe Gen 2 with Spread
General Description
Features/Benefits
The 9DS400 is pin compatible to the 9DB403, but adds the
ability to inject spread spectrum onto the incoming differential
clock, while maintaining good phase noise.
•
Bypass mode
•
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Recommended Application
Output Features
DB400 where spread spectrum needs to be added to the
incoming clock.
•
•
•
Key Specifications
•
•
•
•
Output cycle-cycle jitter < 50ps
Output to Output skew 200 mV
4
SRC_IN input
5
The differential input clock must be running for the SMBus to be active
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
TYP
MAX
V
V
uA
1
1
1
-5
uA
1
-200
uA
1
125
mA
1
30
6
110
400
7
5
2.7
6
mA
mA
MHz
MHz
nH
pF
pF
pF
1
1
1
1
1
1
1,4
1
1
ms
1,2
33
kHz
1
3
cycles
1,3
300
us
1,3
5
5
5.5
0.4
ns
ns
V
V
mA
1
2
1
1
1
1000
ns
1
300
ns
1
100
kHz
1,5
90
33
VDD + 0.3
0.8
5
UNITS NOTES
100.00
1.5
1.5
30
1
32.000
4
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
Electrical Characteristics - Differential Clock Input Parameters
TA =Over the Specified Operating Range; VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage DIF_IN
Input Low Voltage DIF_IN
Input Common Mode
Voltage - DIF_IN
VIHDIF
VILDIF
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
MIN
TYP
MAX
UNITS NOTES
600
800
1150
mV
1
VSS - 300
0
300
mV
1
VCOM
Common Mode Input Voltage
300
1000
mV
1
Input Amplitude - DIF_IN
VSWING
Peak to Peak value
300
1450
mV
1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to
Cycle
I IN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
-5
45
5
55
uA
%
1
1
J DIFIn
Differential Measurement
0
125
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through Vswing min centered around differential zero
2
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA =Over the Specified Operating Range; VDD = 3.3 V +/-5%; CL =2pF, RS=33Ω, RP=49.9Ω, RREF=475Ω
PARAMETER
SYMBOL
Current Source Output
Impedance
Zo1
Voltage High
VHigh
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Skew, Input to Output
Skew, Output to Output
Jitter, Cycle to cycle
Jitter, Phase
VLow
CONDITIONS
TYP
MAX
Statistical measurement on single ended
signal using oscilloscope math function.
660
UNITS NOTES
Ω
3000
Measurement on single ended signal
Vovs
using absolute value.
Vuds
Vcross(ab
s)
d-Vcross
Variation of crossing over all edges
VOL = 0.175V, VOH = 0.525V
tr
tf
VOH = 0.525V VOL = 0.175V
d-tr
d-tf
dt3
Measurement from differential wavefrom
t pdBYP
Bypass Mode, VT = 50%
PLL Mode VT = 50%, Spread Off
t pdPLL
t sk3
VT = 50%
PLL mode
tjcyc-cyc
Additive Jitter in Bypass Mode
PCIe Gen1 phase jitter
(Additive in Bypass Mode)
PCIe Gen 2 Low Band phase jitter
t jphaseBYP
(Additive in Bypass Mode)
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
t jphasePLL
MIN
850
1
1,2
mV
-150
150
1150
mV
1
1
550
mV
1
140
700
700
125
125
55
4500
250
50
50
50
mV
ps
ps
ps
ps
%
ps
ps
ps
ps
ps
ps
(pk2pk)
ps
(rms)
ps
(rms)
ps
(pk2pk)
ps
(rms)
ps
(rms)
1
1
1
1
1
1
1
1
1
1,3
1,3
-300
250
175
175
45
2500
-250
1,2
10
0.1
0.5
PCIe Gen 1 phase jitter
86
PCIe Gen 2 Low Band phase jitter
3
PCIe Gen 2 High Band phase jitter
3.1
1,4,5
1,4,5
1,4,5
1,4,5
1,4,5
1,4,5
1
Guaranteed by design and characterization, not 100% tested in production.
IREF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and VOH = 0.7V @ ZO=50Ω.
3 Measured from differential waveform
4
See http://www.pcisig.com for complete specs
5
Device driven by 932S421C or equivalent.
2
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
Clock Periods Differential Outputs with Spread Spectrum Enabled
Measurement
Window
Symbol
Signal Name
Definition
DIF 100
DIF 133
DIF 166
DIF 200
DIF 266
DIF 333
DIF 400
1 Clock
LgAbsolute
Period
Minimum
Absolute
Period
9.87400
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
1us
-SSC
Short-term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
-ppm error
Long-Term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
0ppm
Period
0.1s
1us
+ ppm error
+SSC
Long-Term Short-term
Average
Average
1 Clock
Lg+
Period
Nominal
Maximum
Maximum
Maximum
10.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
10.05130
7.53845
6.03076
5.02563
3.76922
3.01538
2.51282
10.17630
7.62345
6.11576
5.11063
3.85422
3.10038
2.59782
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
1,2,4
Clock Periods Differential Outputs with Spread Spectrum Disabled
Measurement
Window
Symbol
Signal Name
Definition
DIF 100
DIF 133
DIF 166
DIF 200
DIF 266
DIF 333
DIF 400
1 Clock
LgAbsolute
Period
Minimum
Absolute
Period
9.87400
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
1us
-SSC
Short-term
Average
Minimum
Absolute
Period
0.1s
-ppm error
Long-Term
Average
Minimum
Absolute
Period
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
0.1s
0ppm
Period
0.1s
1us
+ ppm error
+SSC
Long-Term Short-term
Average
Average
Nominal
Maximum
10.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
Maximum
1 Clock
Lg+
Period
Maximum
10.17630
7.62345
6.11576
5.11063
3.85422
3.10038
2.59782
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK409/CK410B/CK505 accuracy requirements. The 9DS400/800 itself does not contribute to ppm error.
3
4
Driven by SRC output of main clock, PLL or Bypass mode
Driven by CPU output of CK410B/CK505 main clock, Bypass mode only
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs
33
Rt
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
HCSL Output Buffer
Rt
L3'
PCI Express
Down Device
REF_CLK Input
L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
HCSL Output Buffer
Rt
L3'
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
PCI Express
Add-in Board
REF_CLK Input
L3
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v
0.22v
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.80
0.40
0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
R2a
HCSL Output Buffer
R2b
L3'
Down Device
REF_CLK Input
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6a
R6b
Cc
L4
L4'
Cc
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
PCIe Device
REF_CLK Input
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
General SMBus serial interface information for the ICS9DS400
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D8 (h)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D8(h)
WRite
WR
Controller (host) will send start bit.
Controller (host) sends the write address D8 (h)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D9 (h)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address D8(h)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D9(h)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
Not acknowledge
stoP bit
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (D8/D9)
Byte 0
Pin #
Name
Control Function
PD_Mode
PD# drive mode
Bit 7
STOP_Mode
SRC_Stop# drive mode
Bit 6
Reserved
Bit 5
Advance Information
Type
RW
RW
Bit 4
1
SPREAD_AMT(1)
Spread % MSB
RW
Bit 3
-
SPREAD_AMT(0)
Spread % LSB
RW
0
driven
driven
1
Hi-Z
Hi-Z
00 = -0.125%
01 = -0.25%
10 = -0.375%
11 = -0.50%
Default
0
0
0
Latch
1
28
SPREAD_EN
Turns on spread
RW
SS Off
SS On
Latch
Bit 2
22
BYPASS#
BYPASS#_SSCG
RW
fan-out
SSCG
Latch
Bit 1
Byte0 CONTROL
Selects control source of Byte 0
RW
Smbus Input Pins
1
Bit 0
Notes: Pins 1, 22 and 28 are latched into Byte 0 on the first power up of the device. Bits [4:1] will NOT reflect
changes in these pin states after power up, even though the pins are controlling the function of the part. Setting
Byte 0 bit 0 to 0 allows the SMBus to write Bits [4:1] and transfers control of the functions from the pins to SMBus.
Once Byte 0 bit 0 is set to 0, the pins no longer impact Byte 0, bits [4:1] or the device function.
SMBus Table: Output Control Register
Byte 1
Pin #
Name
Control Function
Type
0
1
Reserved
Reserved
RW
Reserved
Bit 7
22,23
DIF_6
Output Enable
RW
Disable
Enable
Bit 6
19,20
DIF_5
Output Enable
RW
Disable
Enable
Bit 5
Reserved
Reserved
RW
Reserved
Bit 4
Reserved
Reserved
RW
Reserved
Bit 3
9,10
DIF_2
Output Enable
RW
Disable
Enable
Bit 2
6,7
DIF_1
Output Enable
RW
Disable
Enable
Bit 1
Reserved
Reserved
RW
Reserved
Bit 0
NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Byte 2
Pin #
Name
Reserved
Bit 7
22,23
DIF_6
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
6,7
DIF_1
Bit 1
Reserved
Bit 0
SMBus Table: Reserved Register
Byte 3
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
DIF_6 Stoppable with OE6
Reserved
Reserved
Reserved
Reserved
DIF_1 Stoppable with OE1
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
0
1
0
1
Default
Reserved
0
Free-run Stoppable
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Free-run Stoppable
0
Reserved
0
Default
X
X
X
X
X
X
X
X
1626
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Default
1
1
1
1
1
1
1
1
09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
SMBus Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: DEVICE ID
Byte 5
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
REVISION ID
VENDOR ID
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Advance Information
Type
R
R
R
R
R
R
R
R
0
-
1
-
Default
0
0
0
0
0
0
0
1
Type
R
R
R
R
R
R
R
R
0
1
Default
X
X
0
0
0
0
0
0
Device ID is 80 Hex
for 9DS800 and 40
Hex for 9DS400
SMBus Table: Byte Count Register
Pin #
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Control
Function
Type
0
1
Default
Writing to this register configures how
many bytes will be read back.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
1
1
1
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting
off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the
device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#
drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
Tstable
200 mV) within 10 ns of de-assertion.
DIF_STOP_1 (DIF_Stop = Driven, PD = Driven)
1mS
SRC_Stop#
DIF
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
DIF_STOP_2 (DIF_Stop =Tristate, PD = Driven)
1mS
SRC_Stop#
DIF
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
DIF_STOP_3 (DIF_Stop = Driven, PD = Tristate)
1mS
DIF
SRC_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
DIF_STOP_4 (DIF_Stop = Tristate, PD = Tristate)
1mS
SRC_Stop#
DIF
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
28-pin SSOP Package Dimensions
209 mil SSOP
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-2.00
0.05
-1.65
1.85
0.22
0.38
0.09
0.25
SEE VARIATIONS
7.40
8.20
5.00
5.60
0.65 BASIC
0.55
0.95
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
-.079
.002
-.065
.073
.009
.015
.0035
.010
SEE VARIATIONS
.291
.323
.197
.220
0.0256 BASIC
.022
.037
SEE VARIATIONS
0°
8°
VARIATIONS
N
28
D mm.
MIN
9.90
D (inch)
MAX
10.50
MIN
.390
MAX
.413
Reference Doc.: JEDEC Publication 95, MO-150
209 mil SSOP
10-0033
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
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09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe for Gen 2 with Spread
Advance Information
28-pin TSSOP Package Dimensions
4.40 mm. Body, 0.65 mm. Pitch TSSOP
c
N
(173 mil)
L
E1
SYMBOL
E
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
INDEX
AREA
1 2
a
D
A
A2
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
A1
VARIATIONS
-Ce
N
SEATING
PLANE
b
28
D mm.
MIN
9.60
D (inch)
MAX
9.80
MIN
.378
MAX
.386
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
9DS400 Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Ambient
Operating
Temperature
9DS400AGLF
9DS400AGLF
Tubes
28-pin TSSOP
0 to +70° C
9DS400AGLFT
9DS400AGLF
Tape and Reel
28-pin TSSOP
0 to +70° C
9DS400AGILF
9DS400AGILF
Tubes
28-pin TSSOP
-40 to +85° C
9DS400AGILFT
9DS400AGILF
Tape and Reel
28-pin TSSOP
-40 to +85° C
9DS400AFLF
9DS400AFLFT
9DS400AFILF
9DS400AFILFT
9DS400AFLF
9DS400AFLF
9DS400AFILF
9DS400AFILF
Tubes
Tape and Reel
Tubes
Tape and Reel
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
18
09/17/09
ICS9DS400
Four Output Differential Buffer for PCIe Gen 2 with Spread
Advance Information
Revision History
Rev.
0.1
0.2
Issue Date Description
9/16/2009 Initial release.
9/17/2009 Updated IDD specs in Input/Supply/Common Output Parameters table
Page #
5
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