DATASHEET
Embedded 64-Pin Industrial Temperature
Range CK505 Compatible Clock
Recommended Application:
Industrial temperature CK505 compatible clock for embedded
systems
Output Features:
•
2 - CPU differential low power push-pull pairs
•
9 - SRC differential low power push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull
pair
•
1 - SRC/DOT selectable differential low power push-pull
pair
•
5 - PCI, 33MHz
•
1 - PCI_F, 33MHz free running
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
•
Does not require external pass transistor for voltage
regulator
•
Integrated 33ohm series resistors on differential outputs,
Zo=50Ω
• Supports spread spectrum modulation, default is 0.5%
down spread
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Selectable between one SRC differential push-pull pair
and two single-ended outputs
•
Meets PCIEX Gen2 specification on dedicated SRC
outputs. Muxed SRC outputs meet PCIEX Gen1
specification, except SRC1.
•
Meets PCIEX SRC0
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
1
Enable CR#_A
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
Default
0
0
0
0
0
0
0
0
Byte 3 SRC Output Enable Register
Bit
7
6
5
4
3
2
1
0
Name
SRC11_OE
SRC10_OE
SRC9_OE
SRC8/ITP_OE
SRC7_OE
SRC6_OE
Reserved
SRC4_OE
Byte 4 SRC/CPU/DOT Output Enable & Spread Spectrum Disable Register
Bit
7
6
5
4
3
2
1
0
Name
SRC3_OE
SATA/SRC2_OE
SRC1_OE
SRC0/DOT96_OE
CPU1_OE
CPU0_OE
PLL5_SSC_ON
PLL2_SSC_ON
Description
Output enable for SRC3
Output enable for SATA/SRC2
Output enable for SRC1
Output enable for SRC0/DOT96
Output enable for CPU1
Output enable for CPU0
Enable PLL5's spread modulation
Enable PLL2's spread modulation
Byte 5 Clock Request Enable/Configuration Register
Bit
7
6
5
4
3
2
1
0
Name
CR#_A_EN
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
CR#_D_EN
CR#_D_SEL
Description
Enable CR#_A (clk req) for SRC0 or SRC2
Sets CR#_A to control either SRC0 or SRC2
Enable CR#_B (clk req) for SRC1 or SRC4
Sets CR#_B to control either SRC1 or SRC4
Enable CR#_C (clk req) for SRC0 or SRC2
Sets CR#_C to control either SRC0 or SRC2
Enable CR#_D (clk req) for SRC1 or SRC4
Sets CR#_D to control either SRC1 or SRC4
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
19
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 6 Clock Request Enable/Configuration Register
Bit
7
6
5
4
3
2
Name
CR#_E_EN
CR#_F_EN
CR#_G_EN
CR#_H_EN
Description
Enable CR#_E (clk req) for SRC6
Enable CR#_F (clk req) for SRC8
Enable CR#_G (clk req) for SRC9
Enable CR#_H (clk req) for SRC10
Type
RW
RW
RW
RW
0
Disable CR#_E
Disable CR#_F
Disable CR#_G
Disable CR#_H
Reserved
Reserved
Reserved
Reserved
RW
RW
-
1
Enable CR#_E
Enable CR#_F
Enable CR#_G
Enable CR#_H
-
1
LCD/SRC1_STP_CRTL•
If set, LCD_SS/SRC1 stops with PCI_STOP#
RW
Free Running
0
SRC0_STP_CRTL
If set, SRC0 stop with PCI_STOP#
RW
Free Running
Description
Type
R
R
R
R
R
R
R
R
0
0
Reserved
Reserved
Output enable for SE1
Output enable for SE2
Type
R
R
R
R
RW
RW
RW
RW
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Default
0
0
0
0
0
0
0
0
Byte 7 Vendor ID/ Revision ID Register
Bit
7
6
5
4
3
2
1
0
Name
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Revision ID
Vendor ID
ICS is 0001, binary
1
Default
0
0
0
1
0
0
0
1
1
Default (TSSOP)
0
0
0
1
0
0
1
1
Vendor specific
Byte 8 Device ID & Output Enable Register
Bit
7
6
5
4
3
2
1
0
Name
Device_ID3
Device_ID2
Device_ID1
Device_ID0
Reserved
Reserved
27MHz_nonSS/SE1_OE
27MHz_SS/SE2_OE
Description
Table of Device identifier codes, used for differentiating between
CK505 package options, etc.
See Device ID Table 4
Disabled
Disabled
Enabled
Enabled
1
Stops with PCI_STOP#
assertion
no overclocking
Outputs = REF/N
Test mode
Default (MLF)
0
0
0
0
0
0
1
1
Byte 9 Test and Output Control Register
Bit
Name
Description
Type
0
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of PCI_STOP#
RW
Free running
6
5
4
3
2
1
0
TME_Readback
Reserved
Test Mode Select
Test Mode Entry
CPU IO_VOUT2
CPU IO_VOUT1
CPU IO_VOUT0
Truested Mode Enable (TME) strap status
Reserved
Allows test select, ignores REF/FSC/TestSel
Allows entry into test mode, ignores FSB/TestMode
CPU IO Output Voltage Select (Most Significant Bit)
CPU IO Output Voltage Select
CPU IO Output Voltage Select (Least Significant Bit)
R
RW
RW
RW
RW
RW
RW
normal operation
Outputs HI-Z
Normal operation
Description
Readback of 27_Select latch
Type
R
0
Dot96/ LCD_SS /SE
See Table 3: V_IO Selection
(Default is 0.8V)
Default
0
TME latch
1
0
0
1
0
1
Byte 10 Output Control Register
Bit
7
Name
27_SEL Latch Readback
6
PCI4 STOP EN
Allows control of PCI4 with assertion of PCI_STOP#
RW
Free running
5
PCI3 STOP EN
Allows control of PCI3 with assertion of PCI_STOP#
RW
Free running
4
PCI2 STOP EN
Allows control of PCI2 with assertion of PCI_STOP#
RW
Free running
3
PCI1 STOP EN
Allows control of PCI1 with assertion of PCI_STOP#
RW
Free running
2
PCI0 STOP EN
Allows control of PCI0 with assertion of PCI_STOP#
RW
Free running
1
0
CPU1 Stop Enable
CPU0 Stop Enable
Enables control of CPU1 with CPU_STOP#
Enables control of CPU0 with CPU_STOP#
RW
RW
Free Running
Free Running
1
SRC0/ 27MHz
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stoppable
Stoppable
Description
Reserved
Reserved
Reserved
Reserved
M1 mode clk enable, only if ITP_EN=1
M1 mode clk enable
Reserved
Enables control of CPU2 with CPU_STOP#
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Free Running
1
Enable
Enable
Stoppable
Default
27_SEL latch
Default
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
Byte 11 iAMT/CPU2 Control Register
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
CPU2_AMT_EN
CPU1_AMT_EN
Reserved
CPU2 Stop Enable
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
20
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 12 Byte Count Register
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
BC5
BC4
BC3
BC2
BC1
BC0
Description
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Read Back byte count register,
max bytes = 32
0
-
1
-
Default
0
0
0
0
1
1
0
1
Byte 13 Single Ended Output Slew Rate Control Register
Bit
7
6
5
4
3
2
1
0
Name
REF
REF
27M_FIX
27M_FIX
27M_SS
27M_SS
Reserved
Reserved
Description
RW
0
1
Default
RW
RW
RW
RW
RW
RW
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
0
1
0
1
0
1
Reserved
Reserved
RW
RW
-
-
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
1
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Default
Slew Rate Control
Slew Rate Control
Slew Rate Control
Byte 14 Reserved
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 15 Reserved
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 16 Reserved
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 17 SRC Output Control Register
Bit
7
6
5
4
3
2
1
0
Name
Description
RW
0
SATA/SRC2_STP_CRTL
If set, SATA/SRC2 stops with PCI_STOP#
RW
Free Running
SRC3_STP_CRTL
If set, SRC3 stops with PCI_STOP#
RW
Free Running
SRC4_STP_CRTL
If set, SRC4 stops with PCI_STOP#
RW
Free Running
SRC6_STP_CRTL
If set, SRC6 stops with PCI_STOP#
RW
Free Running
SRC7_STP_CRTL
If set, SRC7 stops with PCI_STOP#
RW
Free Running
Reserved
Reserved
RW
-
SRC8_STP_CRTL
If set, SRC8 stops with PCI_STOP#
RW
Free Running
SRC9_STP_CRTL
If set, SRC9 stops with PCI_STOP#
RW
Free Running
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
21
0
0
0
0
0
0
0
0
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 18 Differential Output Control Register
Bit
7
6
5
4
3
2
1
0
Name
Description
RW
0
SRC10_STP_CRTL
If set, SRC10 stops with PCI_STOP#
RW
Free Running
RW
Free Running
SRC11_STP_CRTL
SRC/CPUITP_SRC8 IO_VOUT2
SRC/CPUITP_SRC8 IO_VOUT1
SRC/CPUITP_SRC8 IO_VOUT0
SATA/SRC2 IO_VOUT2
SATA/SRC2 IO_VOUT1
SATA/SRC2 IO_VOUT0
If set, SRC11 stops with PCI_STOP#
SRC & CPUITP_SRC8 IO Output Voltage Select (Most Significant
Bit)
SRC IO & CPUITP_SRC8 Output Voltage Select
SRC & CPUITP_SRC8 IO Output Voltage Select (Least
Significant Bit)
SATA_SRC2 IO Output Voltage Select (Most Significant Bit)
SATA_SRC2 IO Output Voltage Select
SATA_SRC2 IO Output Voltage Select (Least Significant Bit)
1
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
RW
RW
0
0
1
See Table 3: V_IO Selection
(Default is 0.8V)
RW
RW
RW
RW
Default
0
1
See Table 3: V_IO Selection
(Default is 0.8V)
1
0
1
Byte 19 Differential Output Control Register
Bit
7
6
5
4
3
2
1
0
Name
LCD_SS (SRC1) IO_VOUT2
LCD_SS (SRC1) IO_VOUT1
LCD_SS (SRC1) IO_VOUT0
Description
LCD_SS IO Output Voltage Select (Most Significant Bit)
LCD_SS IO Output Voltage Select
LCD_SS IO Output Voltage Select (Least Significant Bit)
RW
RW
RW
RW
SRC0/DOT96 IO_VOUT2
SRC0_DOT96 IO Output Voltage Select (Most Significant Bit)
RW
SRC0/DOT96 IO_VOUT1
SRC0_DOT96 IO Output Voltage Select
RW
SRC0/DOT96 IO_VOUT0
SRC0_DOT96 IO Output Voltage Select (Least Significant Bit)
RW
Reserved
Reserved
Reserved
Reserved
RW
RW
Description
Type
RW
RW
RW
RW
0
1
See Table 3: V_IO Selection
(Default is 0.8V)
Default
1
0
1
1
See Table 3: V_IO Selection
(Default is 0.8V)
0
1
-
-
0
0
0
1
Default
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
0
1
0
1
0
Byte 20 Single Ended Slew Rate Control Register
Bit
7
6
5
4
3
2
1
0
Name
48MHz
48MHz
PCIF5
PCIF5
PCI4
PCI4
PCI3
PCI3
Slew Rate Control
Slew Rate Control
Slew Rate Control
RW
RW
Slew Rate Control
RW
RW
1
0
1
Byte 21 Single Ended Slew Rate & M/N Enable Control Register
Bit
7
6
5
4
3
2
1
0
Name
PCI2
PCI2
PCI1
PCI1
PCI0
PCI0
Reserved
Reserved
Description
Slew Rate Control
Slew Rate Control
Slew Rate Control
Reserved
Reserved
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
22
Type
0
1
Default
RW
RW
RW
RW
RW
RW
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
0
1
0
1
0
1
RW
RW
-
-
0
0
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Test Clarification Table
Comments
CK_PWRG=1 w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If CK_PWRG=1 w/ V>2.0V then use TEST_SEL
If CK_PWRG=1 w/ Vlow Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 after CK_PWRG=1,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
HW
SW
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MODE
HW PIN
TEST ENTRY
BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
2.0V
>2.0V
>2.0V
X
0
0
1
0
X
X
X
0
0
1
0
NORMAL
HI-Z
REF/N
REF/N
>2.0V
1
X
1
REF/N
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