DATASHEET
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2
& FBD
Description
Features/Benefits
ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the
. The
can provide outputs up to 400MHz.
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Key Specifications
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DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 100ps across all outputs in 1:1
mode
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56-pin SSOP/TSSOP package
RoHS compliant packaging
Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU
Host Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Functional Block Diagram
OE#
SPREAD
COMPATIBLE
1:1 PLL
STOP
LOGIC
2
SPREAD
COMPATIBLE
GEARING PLL
STOP
LOGIC
10
DIF(11:10)
10
OE(9:0)#
CLK_IN
CLK_IN#
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
DIF(9:0)
CONTROL
LOGIC
IREF
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
1
02/08/10
ICS9FG1200D-1
HIGH_BW#
CLK_IN
CLK_IN#
SMB_A0
OE0#
DIF_0
DIF_0#
OE1#
DIF_1
DIF_1#
VDD
GND
DIF_2
DIF_2#
OE2#
DIF_3
DIF_3#
OE3#
DIF_4
DIF_4#
OE4#
VDD
GND
DIF_5
DIF_5#
OE5#
SMB_A1
SMBDAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
9FG1200-1
Pin Configuration
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDA
GNDA
IREF
OE10_11#
DIF_11
DIF_11#
VDD
GND
DIF_10
DIF_10#
FS_A_410
VTT_PWRGD#/PD
OE9#
DIF_9
DIF_9#
OE8#
DIF_8
DIF_8#
VDD
GND
DIF_7
DIF_7#
OE7#
DIF_6
DIF_6#
OE6#
SMB_A2_PLLBYP#
SMBCLK
56-pin SSOP & TSSOP
Power Groups
VDD
56
11,22,38,50
Pin Number
GND
55
12,23,37,49
Description
Main PLL, Analog
DIF clocks
Functionality at Power Up (PLL Mode)
CLK_IN (CPU FSB)
DIF_(11:0)
MHz
MHz
1
100
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