9FG430AGILF

DATASHEET Four Output Differential Frequency Generator for PCIe Gen3 and QPI 9FG430 General Description: Features/Benefits: The 9FG430 is a Frequency Timing Generator that provides 4 HCSL differential output pairs. These outputs support PCI-Express Gen3, and QPI applications. The part supports Spread Spectrum and synthesizes several additional output frequencies from either a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock. The 9FG430 also outputs a copy of the reference clock. Complete control of the device is available via strapping pins or via the SMBus inteface. • • • • • Recommended Application: 4 Output Differential Frequency Generator for PCIe Gen3 and QPI • • Key Specifications: • • • • • Output Features: 4 - 0.7V current mode differential HCSL output pairs 1 - 3.3V LVTTL REF output Pin-to-Pin with 9FG104D/Easy upgrade to PCIe Gen3 Generates common frequencies from 14.318 MHz or 25 MHz; single part supports mulitple applications Provides copy of reference output; eleminates need for additional crystal or oscillator Unused outputs may be disabled in Hi-Z; save system power Device may be configured by SMBus and/or strap pins; can be used in systems without SMBus Cycle-to-cycle jitter: < 50ps with 25MHz input Output-to-output skew: 200 mV 4 DIF_IN input 2 5 The differential input clock must be running for the SMBus to be active IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17 4 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads s for loading conditions. PARAMETER SYMBOL CONDITIONS MIN Slew rate Slew rate matching Trf ∆Trf Scope averaging on Slew rate matching, Scope averaging on 1 Voltage High VHigh 660 Voltage Low VLow Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs ∆-Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off TYP MAX UNITS NOTES V/ns 1, 2, 3 4 % 20 1, 2, 4 850 1 mV -150 150 1150 -300 300 250 550 140 1 mV mV mV mV 1 1 1, 2 1, 5 1, 6 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance). 1 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics - Current Consumption TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading PARAMETER Operating Supply Current Powerdown Current SYMBOL CONDITIONS I DD3.3 VDD, All outputs active @100MHz VDDA, All outputs active @100MHz VDD, All outputs active @400MHz VDDA, All outputs active @400MHz VDD, All differential pairs driven VDDA, All differential pairs driven VDD, All differential pairs tri-stated VDDA, All differential pairs tri-stated I DDA3.3OP I DD3.3 I DDA3.3OP I DD3.3PD I DDA3.3PD IDD3.3PDZ I DDA3.3PDZ MIN TYP MAX 80 25 100 25 75 25 25 25 95 30 120 30 90 30 30 30 TYP MAX UNITS NOTES mA mA mA mA mA mA mA mA 1 1 1 1 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. I REF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 2 Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading PARAMETER SYMBOL CONDITIONS MIN Duty Cycle Skew, Output to Output Jitter, Cycle to cycle Jitter, Cycle to cycle tDC t sk3 Measured differentially, PLL Mode VT = 50% 25M input 14.318M input 45 t jcyc-cyc t jcyc-cyc 55 50 50 60 UNITS NOTES % ps ps ps 1 1 1,3 1,3 1 Guaranteed by design and characterization, not 100% tested in production. I REF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 3 Measured from differential waveform 4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 2 IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17 5 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Electrical Characteristics - Phase Jitter Parameters TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions PARAMETER Phase Jitter, PCI Express SYMBOL t jphPCIeG1 t jphPCIeG2 t jphPCIeG3 Phase Jitter, QPI/SMI tjphQPI_SMI CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) MIN TYP MAX 86 3 3.1 1 0.5 0.3 0.2 UNITS Notes ps (p-p) 1,2,3,6 ps 1,2,6 (rms) ps 1,2,6 (rms) ps 1,2,4,5, (rms) 6 ps 1,5,6 (rms) ps 1,5,6 (rms) ps 1,5,6 (rms) 1 Guaranteed by design and characterization, not 100% tested in production. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3 6 Applies to all differential outputs 2 Electrical Characteristics - REF-14.318/25 MHz TA = TCOM or TIND; Supply Voltage VDD = 3.3 V PARAMETER SYMBOL Long Accuracy ppm Clock period Tperiod Clock period Tperiod +/-5%, See Test Loads for loading CONDITIONS see Tperiod min-max values 14.318MHz output nominal 25.000MHz output nominal MIN Output High Voltage VOH I OH = -1 mA Output Low Voltage Output High Current Output Low Current Rise/Fall Time VOL I OH I OL t rf1 I OL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V -29 29 0.5 Duty Cycle dt1 VT = 1.5 V 45 Jitter t jcyc-cyc VT = 1.5 V TYP 0 69.8413 40 MAX 2.4 0.8 250 UNITS ppm ns ns Notes 1 1,2 1,2 V 1 0.4 -23 27 2 V mA mA ns 1 1 1 1 55 % 1 400 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818 or 25.00 MHz IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17 6 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Output Termination and Layout Information Common Recommendations for Differential Routing Dimension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing (Test Load) L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI PCI Express Add-in Board REF_CLK Input L3 1681D—04/04/17 7 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Termination for Cable AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc PCIe Device REF_CLK Input Figure 5. REF Output Test Load Zo = 50 ohms 33 5pF 9FGxxx REF Output IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17 8 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Differential Clock Tolerances x1 = 25MHz Clock Periods - Differential Outputs with Spread Spectrum Disabled SSC OFF or SSC +/- Synthesis 0.25% Error Center (ppm) Spread DIF 0 0 0 10 0 6 10 0 1 Clock Center Freq. MHz 100.00 125.00 133.33 166.67 200.00 266.67 333.33 400.00 1us Measurement Window 0.1s 0.1s 0.1s 1us 1 Clock +SSC -SSC - ppm + ppm +c2c Units -c2c jitter 0 ppm ShortShort-Term Long-Term Long-Term jitter AbsPer Period Term Average Average Average AbsPer Min Nominal Average Min Min Max Max Max 9.95000 10.00000 10.00000 10.00000 10.05000 ns 7.95000 8.00000 8.00000 8.00000 8.05000 ns 7.45000 7.50000 7.50000 7.50000 7.55000 ns 5.94994 5.99994 6.00000 6.00006 6.05006 ns 4.95000 5.00000 5.00000 5.00000 5.05000 ns 3.69998 3.74998 3.75000 3.75002 3.80002 ns 2.94997 2.99997 3.00000 3.00003 3.05003 ns 2.45000 2.50000 2.50000 2.50000 2.55000 ns Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Clock Periods - Differential Outputs with Spread Spectrum Enabled 1 2 1 Clock SSC ON -0.5% Down Spread Synthesis Error (ppm) Center Freq. MHz DIF 96 19 96 10 96 -98 10 96 99.75 124.69 133.00 166.25 199.50 266.00 332.50 399.00 1us Measurement Window 0.1s 0.1s 0.1s 1us +SSC -SSC - ppm + ppm -c2c jitter 0 ppm ShortShort-Term Long-Term Long-Term AbsPer Period Term Average Average Average Min Nominal Average Min Min Max Max 9.94906 9.99906 10.02406 10.02506 10.02603 10.05103 7.94925 7.99925 8.01925 8.02005 8.02020 8.04020 7.44930 7.49930 7.51805 7.51880 7.51952 7.53827 5.94943 5.99943 6.01443 6.01504 6.01510 6.03010 4.94953 4.99953 5.01203 5.01253 5.01301 5.02551 3.69965 3.74965 3.75902 3.75940 3.75903 3.76841 2.94972 2.99972 3.00722 3.00752 3.00755 3.01505 2.44977 2.49977 2.50602 2.50627 2.50651 2.51276 1 Clock +c2c Units jitter AbsPer Max 10.10103 8.09020 7.58827 6.08010 5.07551 3.81841 3.06505 2.56276 ns ns ns ns ns ns ns ns Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Guaranteed by design and characterization, not 100% tested in production. All ppm specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL frequency. IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 1681D—04/04/17 9 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Differential Clock Tolerances, x1 = 14.31818MHz Clock Periods - Differential Outputs with Spread Spectrum Disabled SSC OFF or SSC +/- Synthesis 0.25% Error Center (ppm) Spread DIF 35 -114 35 -104 35 42 -104 35 1 Clock Center Freq. MHz 100.00 125.00 133.33 166.67 200.00 266.67 333.33 400.00 1us Measurement Window 0.1s 0.1s 0.1s 1us 1 Clock +SSC -SSC - ppm + ppm +c2c Units -c2c jitter 0 ppm ShortShort-Term Long-Term Long-Term jitter AbsPer Period Term Average Average Average AbsPer Min Nominal Average Min Min Max Max Max 9.94965 9.99965 10.00000 10.00035 10.05035 ns 7.95091 8.00091 8.00000 7.99909 8.04909 ns 7.44974 7.49974 7.50000 7.50026 7.55026 ns 5.95062 6.00062 6.00000 5.99937 6.04937 ns 4.94983 4.99983 5.00000 5.00018 5.05018 ns 3.69984 3.74984 3.75000 3.75016 3.80016 ns 2.95031 3.00031 3.00000 2.99969 3.04969 ns 2.44991 2.49991 2.50000 2.50009 2.55009 ns Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Clock Periods - Differential Outputs with Spread Spectrum Enabled 1 2 1 Clock SSC ON -0.5% Down Spread Synthesis Error (ppm) Center Freq. MHz DIF 199 -100 199 10 199 -140 10 199 99.75 124.69 133.00 166.25 199.50 266.00 332.50 399.00 1us Measurement Window 0.1s 0.1s 0.1s 1us +SSC -SSC - ppm + ppm -c2c jitter 0 ppm ShortShort-Term Long-Term Long-Term AbsPer Period Term Average Average Average Nominal Average Min Min Min Max Max 9.94906 9.99906 10.02406 10.02506 10.02706 10.05206 7.94925 7.99925 8.01925 8.02005 8.01925 8.03925 7.44930 7.49930 7.51805 7.51880 7.52029 7.53904 5.94943 5.99943 6.01443 6.01504 6.01510 6.03010 4.94953 4.99953 5.01203 5.01253 5.01353 5.02603 3.69965 3.74965 3.75902 3.75940 3.75887 3.76825 2.94972 2.99972 3.00722 3.00752 3.00755 3.01505 2.44977 2.49977 2.50602 2.50627 2.50676 2.51301 1 Clock +c2c jitter AbsPer Max 10.10206 8.08925 7.58904 6.08010 5.07603 3.81825 3.06505 2.56301 Units Notes ns ns ns ns ns ns ns ns 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Guaranteed by design and characterization, not 100% tested in production. All ppm specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL frequency. IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 10 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI General SMBus serial interface information for the 9FG430 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address DC (H) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • IDT clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controlle r (Host) starT bit T Slave Address DC(H ) W Rite WR Controller (host) will send start bit. Controller (host) sends the write address DC (H) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N + X -1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controlle r (Host) T starT bit Slave Address DC(H ) WR W Rite IDT (Sla ve /Re ce ive r) IDT (Sla ve /Re ce ive r) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address DD(H ) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 11 Not acknowledge stoP bit 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Bit 7 Pin # 17 Name FS31 Control Function Type RW 0 1 Default Pin 17 Bit 6 6 FS21 RW Bit 5 Bit 4 24 25 FS11 FS01 RW RW Bit 3 16 Spread Enable1 RW Bit 2 - Enable Software Control of Frequency, Spread Enable (Spread Type always Software Control) RW Bit 1 DIF_STOP# drive mode RW Driven Hi-Z 0 Bit 0 SPREAD TYPE RW Down Center 0 0 1 Default See Frequency Selection Table, Page 1 Off On Pin 6 Pin 24 Pin 25 Pin 16 Hardware Select Software Select 0 Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. SMBus Table: Output Enable Register Byte 1 Pin # Bit 7 - Bit 6 - DIF_3 EN Output Enable RW Disable Enable 1 Bit 5 - DIF_2 EN Output Enable RW Disable Enable 1 Bit 4 - Bit 3 - Bit 2 - DIF_1 EN Output Enable RW Disable Enable 1 Bit 1 - DIF_0 EN Output Enable RW Disable Enable 1 Bit 0 - Name Control Function Type Reserved 1 1 Reserved 1 Reserved Reserved 1 SMBus Table: Output Stop Control Register Byte 2 Pin # Bit 7 - Bit 6 Name Control Function Type 0 1 Default - DIF_3 STOP EN Free Run/ Stop Enable RW Free-run Stop-able Bit 5 - DIF_2 STOP EN Bit 4 - Free Run/ Stop Enable RW Free-run Stop-able Bit 3 - Bit 2 - DIF_1 STOP EN Free Run/ Stop Enable RW Free-run Stop-able Bit 1 - DIF_0 STOP EN Free Run/ Stop Enable RW Free-run Stop-able Bit 0 - 0 Reserved 0 Reserved IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 12 0 0 Reserved Reserved 0 0 0 0 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: Frequency Select Readback Register Byte 3 Pin # Name Control Function Type Bit 7 27 SEL14M_25M#1 (FS3) State of pin 17 R Bit 6 6 FS21 State of pin 6 R Bit 5 44 FS11 State of pin 24 R Bit 4 45 FS01 State of pin 25 R Bit 3 16 SPREAD1 State of pin 26 R 0 1 Default Pin 17 See Frequency Selection Table, Page 1 Pin 6 Pin 24 Pin 25 Off On Pin 16 Bit 2 Reserved 0 Bit 1 Reserved 0 Bit 0 Reserved 0 Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. SMBus Table: Vendor & Revision ID Register Byte 4 Pin # Name Bit 7 - Bit 6 - Bit 5 - RID1 Bit 4 - RID0 R - - 0 Bit 3 - VID3 R - - 0 Bit 2 - VID2 R - - 0 Bit 1 - VID1 R - - 0 Bit 0 - VID0 R - - 1 Control Function Type 0 1 Default RID3 R - - 0 RID2 R - - 0 R - - 0 REVISION ID VENDOR ID SMBus Table: DEVICE ID Byte 5 Pin # Name Type 0 1 Default Bit 7 - DID7 R - - 0 Bit 6 - DID6 R - - 0 Bit 5 - DID5 R - - 0 Bit 4 - DID4 R - - 0 Bit 3 - DID3 R - - 0 Bit 2 - DID2 R - - 0 Bit 1 - DID1 R - - 0 Bit 0 - DID0 R - - 1 Control Function Device ID = 01 hex SMBus Table: Byte Count Register Byte 6 Pin # Name Type 0 1 Default Bit 7 - BC7 RW - - 0 Bit 6 - BC6 RW - - 0 Bit 5 - BC5 RW - - 0 Bit 4 - BC4 RW - - 0 Bit 3 - BC3 RW - - 0 Bit 2 - BC2 RW - - 1 Bit 1 - BC1 RW - - 1 Bit 0 - BC0 RW - - 1 Control Function Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 13 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: Reserved Register Byte 7 Pin # Bit 7 - Reserved 0 Bit 6 - Reserved 0 Bit 5 - Reserved 0 Bit 4 - Reserved 0 Bit 3 - Reserved 0 Bit 2 - Reserved 0 Bit 1 - Reserved 0 Bit 0 - Reserved 0 Name Control Function Type 0 1 Default SMBus Table: Reserved Register Byte 8 Pin # Bit 7 - Reserved 0 Bit 6 - Reserved 0 Bit 5 - Reserved 0 Bit 4 - Reserved 0 Bit 3 - Reserved 0 Bit 2 - Reserved 0 Bit 1 - Reserved 0 Bit 0 - Reserved 0 Name Control Function Type 0 1 Default SMBus Table: M/N Programming Enable Byte 9 Pin # Name Control Function Type 0 1 Default Bit 7 - M/N_Enable M/N Prog. Enable RW Disable Enable 0 Bit 6 - Bit 5 5 Bit 4 - Bit 3 Bit 2 Reserved REFOUT_En REFOUT Enable 1 RW Disable Enable 1 Reserved 0 - Reserved 0 - Reserved 0 Bit 1 - Reserved 0 Bit 0 - Reserved 0 SMBus Table: PLL Frequency Control Register Byte 10 Pin # Name Control Function Type Bit 7 - PLL N Div8 N Divider Prog bit 8 RW Bit 6 - PLL N Div9 N Divider Prog bit 9 RW Bit 5 - PLL M Div5 Bit 4 - PLL M Div4 Bit 3 - PLL M Div3 Bit 2 - PLL M Div2 Bit 1 - PLL M Div1 RW Bit 0 - PLL M Div0 RW RW RW M Divider Programming bit (5:0) IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 14 RW RW 0 1 Default The decimal representation of M and N Divider in Byte 10 and 11 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv(5:0)+2]. The user does NOT need to program these resgisters for standard frequencies. X X X X X X X X 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI SMBus Table: PLL Frequency Control Register Byte 11 Pin # Name Bit 7 - PLL N Div7 RW Bit 6 - PLL N Div6 RW Bit 5 - PLL N Div5 RW Bit 4 - PLL N Div4 Bit 3 - PLL N Div3 Bit 2 - PLL N Div2 RW Bit 1 - PLL N Div1 RW Bit 0 - PLL N Div0 RW Control Function N Divider Programming Byte11 bit(7:0) and Byte10 bit(7:6) Type RW RW 0 1 Default The decimal representation of M and N Divider in Byte 10 and 11 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv(5:0)+2]. The user does NOT need to program these resgisters for standard frequencies. X X X X X X X X SMBus Table: PLL Spread Spectrum Control Register Byte 12 Pin # Name Control Function Type Bit 7 - PLL SSP7 RW Bit 6 - PLL SSP6 RW Bit 5 - PLL SSP5 Bit 4 - PLL SSP4 Bit 3 - PLL SSP3 Bit 2 - PLL SSP2 RW Bit 1 - PLL SSP1 RW Bit 0 - PLL SSP0 RW RW Spread Spectrum Programming bit(7:0) RW RW 0 1 Default These Spread Spectrum bits in Byte 12 and 13 will program the spread pecentage of PLL. The user does not need to modify these settings unless nonstandard spread amounts are required. The part defaults to 0.5% spread when spread is enabled. X X X X X X X X SMBus Table: PLL Spread Spectrum Control Register Byte 13 Pin # Bit 7 - Bit 6 - PLL SSP14 RW Bit 5 - PLL SSP13 RW Bit 4 - PLL SSP12 Name Control Function Type 0 1 Default Reserved 0 RW Spread Spectrum Programming bit(14:8) Bit 3 - PLL SSP11 Bit 2 - PLL SSP10 RW Bit 1 - PLL SSP9 RW Bit 0 - PLL SSP8 RW IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 15 RW These Spread Spectrum bits in Byte 12 and 13 will program the spread pecentage of PLL. The user does not need to modify these settings unless nonstandard spread amounts are required. The part defaults to 0.5% spread when spread is enabled. X X X X X X X 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI 28-Pin SSOP Package Drawing and Dimensions 209 mil SSOP c N SYMBOL L E1 A A1 A2 b c D E E1 e L N α E INDEX AREA 1 2 α h x 45° D In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° VARIATIONS N A 28 -Cb D (inch) MAX 10.50 MIN .390 MAX .413 Reference Doc.: JEDEC Publication 95, MO-150 A1 e D mm. MIN 9.90 10-0033 SEATING PLANE .10 (.004) C IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 16 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI 28-Pin TSSOP Package Drawing and Dimensions 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) c N SYMBOL L E1 A A1 A2 b c D E E1 e L N α aaa E INDEX AREA 1 2 α D (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS A A2 N 28 D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 MAX .386 A1 - Ce b Reference Doc.: JEDEC Publication 95, MO-153 SEATING PLANE 10-0035 aaa C Ordering Information Part / Order Number Shipping Packaging 9FG430AFLF Tubes 9FG430AFLFT Tape and Reel 9FG430AFILF Tubes 9FG430AFILFT Tape and Reel 9FG430AGLF Tubes 9FG430AGLFT Tape and Reel 9FG430AGILF Tubes 9FG430AGILFT Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C “LF” suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant. “A” is the device revision designator (w ill not correlate w ith the datasheet revision). IDT® Four Output Differential Frequency Generator for PCIe Gen3 and QPI 17 1681D—04/04/17 9FG430 Four Output Differential Frequency Generator for PCIe Gen3 and QPI Revision History Rev. 0.1 A B C D Issue Date Who Description Page # 7/13/2010 RDW New datasheet. 7/13/2010 RDW Release 1. Added PPM tables to DS for both 25M and 14.318M inputs 7/20/2010 RDW 2. Added Test load figures 1. Updated/reformatted Electrical Tables 2. Corrected Features/Benefits and General Description 8/25/2010 RDW 3. Updated pull up ^ and pull down v indicators. 1, Various 4. Updated termination figures to include Fig. 5 for REF output, merged test load figures into these figures. 4/4/2017 RDW 1. Corrected Byte 5 Device ID from 43 hex to 01 hex 13 Innovate with IDT and accelerate your future networks. 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