DATASHEET
Eight Output Differential Frequency Generator
for PCIe Gen3 and QPI
9FG830
General Description:
Features/Benefits:
The 9FG830 is a Frequency Timing Generator that provides 8
HCSL differential output pairs. These outputs support PCI-Express
Gen3, and QPI applications. The part supports Spread Spectrum
and synthesizes several additional output frequencies from either
a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock.
The 9FG830 also outputs a copy of the reference clock. Complete
control of the device is available via strapping pins or via the
SMBus interface.
•
•
•
•
•
Recommended Application:
•
8 Output Differential Output Frequency Generator for PCIe Gen3
and QPI
Pin-to-Pin with 9FG108D; Easy upgrade to PCIe Gen3
Generates common frequencies from 14.318 MHz or 25
MHz; single part supports mulitple applications
Provides copy of reference output; eleminates need for
additional crystal or oscillator
Three spread spectrum modes: -0.5%, +/-0.25%, and off;
EMI reduction
Unused outputs may be disabled in Hi-Z; save system
power
Device may be configured by SMBus and/or strap pins;
can be used in systems without SMBus
Output Features:
Key Specifications:
•
•
•
•
•
•
•
8 - 0.7V current mode differential HCSL output pairs
1 - 3.3V LVTTL REF output
Cycle-to-cycle jitter: < 50ps with 25MHz input
Output-to-output skew: 200 mV
2
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
5
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Slew rate
Slew rate matching
Trf
∆Trf
Scope averaging on
Slew rate matching, Scope averaging on
1
4
20
Voltage High
VHigh
660
850
Voltage Low
VLow
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
∆-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
TYP
MAX UNITS NOTES
V/ns
%
1, 2, 3
1, 2, 4
1
mV
-150
150
1150
-300
300
250
550
140
1
1
1
1, 2
1, 5
1, 6
mV
mV
mV
mV
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA.
IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).
1
2
Measured from differential waveform
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope uses for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in a particular system. This is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
Electrical Characteristics - Current Consumption
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER
Operating Supply Current
DIF_STOP# Current
SYMBOL
CONDITIONS
I DD3.3
VDD, All outputs active @100MHz
VDDA, All outputs active @100MHz
VDD, All outputs active @400MHz
VDDA, All outputs active @400MHz
VDD, All DIF pairs stopped driven
VDDA, All DIF pairs stopped driven
VDD, All DIF pairs stopped Hi-Z
VDDA, All DIF pairs stopped Hi-Z
I DDA3.3OP
I DD3.3
I DDA3.3OP
I DD3.3DS
I DDA3.3DS
I DD3.3DZ
IDDA3.3DZ
MIN
TYP
MAX
250
28
200
28
190
28
38
28
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
I REF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
2
Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Duty Cycle
Skew, Output to Output
Jitter, Cycle to cycle
Jitter, Cycle to cycle
tDC
t sk3
Measured differentially, PLL Mode
VT = 50%
25M input
14.318M input
45
t jcyc-cyc
t jcyc-cyc
TYP
MAX
55
50
50
60
UNITS NOTES
%
ps
ps
ps
1
1
1,3
1,3
1
Guaranteed by design and characterization, not 100% tested in production.
I REF = VDD/(3xRR). For RR = 475Ω (1%), I REF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
3
Measured from differential waveform
2
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
6
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions
PARAMETER
Phase Jitter, PCI Express
SYMBOL
t jphPCIeG1
t jphPCIeG2
t jphPCIeG3
Phase Jitter, QPI/SMI
tjphQPI_SMI
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
MIN
TYP
MAX
86
3
3.1
1
0.5
0.3
0.2
UNITS Notes
ps (p-p) 1,2,3,6
ps
1,2,6
(rms)
ps
1,2,6
(rms)
ps
1,2,4,5,
(rms)
6
ps
1,5,6
(rms)
ps
1,5,6
(rms)
ps
1,5,6
(rms)
1
Guaranteed by design and characterization, not 100% tested in production.
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final radification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.3
6
Applies to all differential outputs
2
Electrical Characteristics - REF-14.318/25 MHz
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads for Loads for loading conditions.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0
Long Accuracy
ppm
see Tperiod min-max values
14.318MHz output nominal
69.8413
Clock period
Tperiod
25.000MHz output nominal
40
Clock period
Tperiod
1
2
Output High Voltage
VOH
I OH = -1 mA
Output Low Voltage
Output High Current
Output Low Current
Rise/Fall Time
VOL
I OH
I OL
t rf1
I OL = 1 mA
VOH @MIN = 1.0 V, VOH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
-29
29
0.5
45
Duty Cycle
dt1
VT = 1.5 V
Jitter
t jcyc-cyc
VT = 1.5 V
MAX
UNITS
ppm
ns
ns
Notes
1,2
1,2
1,2
V
1
V
mA
mA
ns
1
1
1
1
55
%
1
250
ps
1
2.4
0.4
-23
27
2
100
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 14.31818 or 25.00 MHz
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
7
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs
33
Rt
49.9
Unit
inch
inch
inch
ohm
ohm
Notes
1
1
1
1
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
(Test Load)
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
HCSL Output Buffer
Rt
Rt
L3'
PCI Express
Down Device
REF_CLK Input
L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
HCSL Output Buffer
Rs
Rt
Rt
L3'
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
PCI Express
Add-in Board
REF_CLK Input
L3
1680E—04/04/17
8
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Alternative
Vdiff
Vp-p
0.45v
0.22v
0.58
0.28
0.80
0.40
0.60
0.3
R1a = R1b = R1
R2a = R2b = R2
Termination for LVDS and other Common Differential Signals (Figure 3)
Vcm
R1
R2
R3
R4
Note
1.08
33
150
100
100
0.6
33
78.7
137
100
0.6
33
78.7
none
100
ICS874003i-02 input compatible
1.2
33
174
140
100
Standard LVDS
Figure 3
L2
L1
R3
R1a
R4
L4
L4'
L2'
L1'
R1b
HCSL Output Buffer
R2a
R2b
L3'
Down Device
REF_CLK Input
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6a
R6b
Cc
L4
L4'
Cc
PCIe Device
REF_CLK Input
Figure 5. REF Output Test Load
Zo = 50 ohms
33
5pF
9FGxxx REF Output
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680E—04/04/17
9
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Differential Clock Tolerances x1 - 25MHz
Clock Periods - Differential Outputs with Spread Spectrum Disabled
SSC OFF
or SSC +/- Synthesis
0.25%
Error
Center
(ppm)
Spread
DIF
0
0
0
10
0
6
10
0
1 Clock
Center
Freq.
MHz
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
1us
Measurement Window
0.1s
0.1s
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.95000
7.95000
7.45000
5.94994
4.95000
3.69998
2.94997
2.45000
10.00000
8.00000
7.50000
5.99994
5.00000
3.74998
2.99997
2.50000
1us
1 Clock
+SSC
+ ppm
0 ppm
Short- +c2c jitter Units
Long-Term
Period
Term
AbsPer
Average
Nominal
Average
Max
Max
Max
10.00000
10.00000
10.05000
ns
8.00000
8.00000
8.05000
ns
7.50000
7.50000
7.55000
ns
6.00000
6.00006
6.05006
ns
5.00000
5.00000
5.05000
ns
3.75000
3.75002
3.80002
ns
3.00000
3.00003
3.05003
ns
2.50000
2.50000
2.55000
ns
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1 Clock
SSC ON
-0.5%
Down
Spread
Synthesis
Error
(ppm)
Center
Freq.
MHz
DIF
96
19
96
10
96
-98
10
96
99.75
124.69
133.00
166.25
199.50
266.00
332.50
399.00
1us
Measurement Window
0.1s
0.1s
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.94910
7.94990
7.44933
5.94998
4.94955
3.70039
2.94999
2.44978
9.99910
7.99990
7.49933
5.99998
4.99955
3.75039
2.99999
2.49978
10.02410
8.01990
7.51808
6.01498
5.01205
3.75977
3.00749
2.50603
1us
1 Clock
+SSC
+ ppm
0 ppm
Short- +c2c jitter Units
Long-Term
Period
Term
AbsPer
Average
Nominal
Average
Max
Max
Max
10.02506
10.02603 10.05103 10.10103
ns
8.02005
8.02020
8.04020
8.09020
ns
7.51880
7.51952
7.53827
7.58827
ns
6.01504
6.01510
6.03010
6.08010
ns
5.01253
5.01301
5.02551
5.07551
ns
3.75940
3.75903
3.76841
3.81841
ns
3.00752
3.00755
3.01505
3.06505
ns
2.50627
2.50651
2.51276
2.56276
ns
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL
frequency.
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
10
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Differential Clock Tolerances x1 - 14.31818MHz
Clock Periods - Differential Outputs with Spread Spectrum Disabled
SSC OFF
or SSC +/- Synthesis
0.25%
Error
Center
(ppm)
Spread
DIF
35
-114
35
-104
35
42
-104
35
1 Clock
Center
Freq.
MHz
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
1us
Measurement Window
0.1s
0.1s
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.94965
7.95091
7.44974
5.95062
4.94983
3.69984
2.95031
2.44991
9.99965
8.00091
7.49974
6.00062
4.99983
3.74984
3.00031
2.49991
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
10.00000
8.00000
7.50000
6.00000
5.00000
3.75000
3.00000
2.50000
10.00035
7.99909
7.50026
5.99937
5.00018
3.75016
2.99969
2.50009
1us
1 Clock
+SSC
Short- +c2c jitter Units
Term
AbsPer
Average
Max
Max
10.05035
ns
8.04909
ns
7.55026
ns
6.04937
ns
5.05018
ns
3.80016
ns
3.04969
ns
2.55009
ns
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
1
1 Clock
SSC ON
-0.5%
Down
Spread
Synthesis
Error
(ppm)
Center
Freq.
MHz
DIF
199
-100
199
10
199
-140
10
199
99.75
124.69
133.00
166.25
199.50
266.00
332.50
399.00
1us
Measurement Window
0.1s
0.1s
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.94807
7.95085
7.44855
5.94998
4.94903
3.70055
2.94999
2.44952
9.99807
8.00085
7.49855
5.99998
4.99903
3.75055
2.99999
2.49952
10.02307
8.02085
7.51730
6.01498
5.01153
3.75992
3.00749
2.50577
1us
1 Clock
+SSC
+ ppm
Short- +c2c jitter Units
0 ppm
Long-Term
Term
Period
AbsPer
Average
Average
Nominal
Max
Max
Max
10.02506
10.02706 10.05206 10.10206
ns
8.02005
8.01925
8.03925
8.08925
ns
7.51880
7.52029
7.53904
7.58904
ns
6.01504
6.01510
6.03010
6.08010
ns
5.01253
5.01353
5.02603
5.07603
ns
3.75940
3.75887
3.76825
3.81825
ns
3.00752
3.00755
3.01505
3.06505
ns
2.50627
2.50676
2.51301
2.56301
ns
Notes
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the REF output is tuned to the exact target XTAL
frequency.
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
11
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
General SMBus serial interface information for the 9FG830
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address DC (H)
IDT clock will acknowledge
Controller (host) sends the begining byte location = N
IDT clock will acknowledge
Controller (host) sends the data byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controlle r (Host)
starT bit
T
Slave Address DC(H )
W Rite
WR
Controller (host) will send start bit.
Controller (host) sends the write address DC (H)
IDT clock will acknowledge
Controller (host) sends the begining byte
location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD (H)
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N + X -1
IDT clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controlle r (Host)
T
starT bit
Slave Address DC(H )
WR
W Rite
IDT (Sla ve /Re ce ive r)
IDT (Sla ve /Re ce ive r)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address DD(H )
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
12
Not acknowledge
stoP bit
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Pin #
Name
Control Function
Type
1
27
RW
Bit 7
FS3
1
5
RW
Bit 6
FS2
44
RW
Bit 5
FS11
7
RW
Bit 4
FS01
1
26
RW
Bit 3
Spread Enable
Bit 2
-
Enable Software Control of Frequency,
Spread Enable (Spread Type always
Software Control)
Bit 1
Bit 0
-
DIF_STOP# drive mode
Spread Type
RW
RW
RW
0
1
See Frequency
Selection Table.
Off
On
Hardware Software
Select
Select
Driven
Down
Default
Pin 27
Pin 5
Pin 44
Pin 7
Pin 26
0
Hi-Z
Center
0
0
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Default
1
1
1
1
1
1
1
1
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Pin #
Name
Control Function
Type
DIF_7 EN
Output Enable
RW
Bit 7
DIF_6 EN
Output Enable
RW
Bit 6
DIF_5 EN
Output Enable
RW
Bit 5
DIF_4 EN
Output Enable
RW
Bit 4
DIF_3
EN
Output
Enable
RW
Bit 3
DIF_2 EN
Output Enable
RW
Bit 2
DIF_1 EN
Output Enable
RW
Bit 1
DIF_0 EN
Output Enable
RW
Bit 0
Byte
1
sets
outputs
active
or
inactive,
not
the
conditons
set
by
the OE
Note:
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
inputs.
SMBus Table: Output Stop Mode Register
Byte 2
Pin #
Name
Control Function
DIF_7 STOP EN Free Run/ Stop Enable
Bit 7
DIF_6 STOP EN Free Run/ Stop Enable
Bit 6
DIF_5 STOP EN Free Run/ Stop Enable
Bit 5
DIF_4 STOP EN Free Run/ Stop Enable
Bit 4
DIF_3 STOP EN Free Run/ Stop Enable
Bit 3
DIF_2 STOP EN Free Run/ Stop Enable
Bit 2
DIF_1 STOP EN Free Run/ Stop Enable
Bit 1
DIF_0 STOP EN Free Run/ Stop Enable
Bit 0
0
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
13
Type
RW
RW
RW
RW
RW
RW
RW
RW
1
Default
Stop-able
0
Stop-able
0
Stop-able
0
Stop-able
0
Stop-able
0
Stop-able
0
Stop-able
0
Stop-able
0
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: Frequency Select Readback Register
Byte 3
Bit 7
27
SEL14M_25M#
Control Function
State of pin 27
Bit 6
6
FS21
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
44
45
26
Name
1
Type
R
State of pin 6
R
1
State of pin 44
R
1
State of pin 45
State of pin 26
Reserved
Reserved
Reserved
R
R
R
R
R
FS1
FS0
SPREAD1
0
1
Default
Pin 27
See Frequency
Selection Table.
Pin 44
Off
On
Reserved
Reserved
Reserved
Pin 45
Pin 26
X
X
X
Pin 6
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
Control Function
RID3
Bit 7
RID2
Bit 6
REVISION ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
1
-
Default
X
X
X
X
0
0
0
1
SMBus Table: DEVICE ID
Pin #
Name
Byte 5
DEVID7
Bit 7
DEVID6
Bit 6
DEVID5
Bit 5
DEVID4
Bit 4
DEVID3
Bit 3
DEVID2
Bit 2
DEVID1
Bit 1
DEVID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
1
0
0
0
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
Default
0
0
0
0
0
1
1
1
SMBus Table: Byte Count Register
Pin #
Name
Byte 6
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device ID = 10 hex
Control Function
Writing to this register
will configure how many
bytes will be read back,
default is 07 = 7 bytes.
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
14
1
-
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: Reserved Register
Pin #
Name
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
X
X
X
X
X
X
X
X
SMBus Table: Reserved Register
Pin #
Name
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
X
X
X
X
X
X
X
X
Type
0
1
Default
RW
Disable
Enable
0
RW
OE#
OE
1
RW
Disable
Enable
1
0
0
0
0
0
Type
RW
0
1
Default
X
SMBus Table: M/N Programming Enable
Byte 9
Pin #
Name
Control Function
PLL M/N Programming
M/N_EN
Bit 7
Enable
Select Polarity of OE
OE_Polarity
Bit 6
inputs
Enables/Disables
REF
5
REFOUT_En
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reserved
Bit 0
SMBus Table: PLL Frequency Control Register
Pin #
Name
Control Function
Byte 10
PLL N Div8
N Divider Prog bit 8
Bit 7
Bit 6
-
PLL N Div9
N Divider Prog bit 9
Bit 5
-
PLL M Div5
RW
Bit 4
-
PLL M Div4
RW
Bit 3
-
PLL M Div3
Bit 2
-
PLL M Div2
Bit 1
-
PLL M Div1
RW
Bit 0
-
PLL M Div0
RW
M Divider Programming
bit (5:0)
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
15
RW
RW
RW
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
X
X
X
X
X
X
X
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SMBus Table: PLL Frequency Control Register
Byte 11
Pin #
Name
Control Function
PLL N Div7
Bit 7
Type
RW
Bit 6
-
PLL N Div6
Bit 5
-
PLL N Div5
Bit 4
-
PLL N Div4
Bit 3
-
PLL N Div3
Bit 2
Bit 1
-
PLL N Div2
PLL N Div1
RW
RW
Bit 0
-
PLL N Div0
RW
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Byte 12
PLL SSP7
Bit 7
PLL SSP6
Bit 6
PLL SSP5
Bit 5
Spread Spectrum
PLL SSP4
Bit 4
Programming bit(7:0)
PLL SSP3
Bit 3
PLL SSP2
Bit 2
PLL SSP1
Bit 1
PLL SSP0
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
N Divider Programming
Byte11 bit(7:0) and
Byte10 bit(7:6)
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Byte 13
Reserved
Bit 7
PLL SSP14
Bit 6
PLL SSP13
Bit 5
PLL SSP12
Bit 4
Spread Spectrum
PLL SSP11
Bit 3
Programming bit(14:8)
PLL SSP10
Bit 2
PLL SSP9
Bit 1
PLL SSP8
Bit 0
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
16
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
0
1
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
0
1
0
1
Default
X
X
X
X
X
X
X
X
Default
X
X
These Spread
X
Spectrum bits in
X
Byte 13 and 14 will
X
program the spread
X
pecentage of PLL
X
X
Default
0
X
These Spread
X
Spectrum bits in
X
Byte 13 and 14 will
X
program the spread
X
pecentage of PLL
X
X
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
a
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
N
48
D mm.
MIN
15.75
D (inch)
MAX
16.00
MIN
.620
MAX
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
17
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
L SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
aaa
-0.10
-.004
c
N
E1
E
INDEX
AREA
1 2
α
D
A
A2
VARIATIONS
A1
N
- Ce
b
48
SEATING
PLANE
D mm.
MIN
MAX
12.40
12.60
D (inch)
MIN
.488
MAX
.496
Ref erence Doc.: JEDEC Publication 95, M O-153
10-0039
aaa C
Ordering Information
Part / Order Number Shipping Packaging
9FG830AFLF
Tubes
9FG830AFLFT
Tape and Reel
9FG830AFILF
Tubes
9FG830AFILFT
Tape and Reel
9FG830AGLF
Tubes
9FG830AGLFT
Tape and Reel
9FG830AGILF
Tubes
9FG830AGILFT
Tape and Reel
Package
48-pin SSOP
48-pin SSOP
48-pin SSOP
48-pin SSOP
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
Temperature
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
“LF” suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant.
“A” is the device revision designator (w ill not correlate w ith the datasheet revision).
IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
18
1680E—04/04/17
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
Revision History
Rev.
A
Issue Date
7/13/2010
B
7/20/2010
C
8/25/2010
D
7/3/2013
E
4/4/2017
Originator Description
RDW
Initial release. Move to final
1. Added PPM tables to DS for both 25M and 14.318M inputs
RDW
2. Added Test load figures
1. Updated/reformatted Electrical Tables
2. Corrected Features/Benefits and General Description
RDW
3. Updated termination figures to include Fig 5. for REF output
1. Update OE# Latency min/max values from 1 & 3 cycles to 2 & 5 cycles
respectively.
D. C.
2. Update VDDA max current from 28 to 30mA for 100MHz and 400MHz.
3. Added typical values to Phase Jitter Parameters table.
RDW
1. Corrected Byte 5 Device ID from 83hex to 10 hex.
Page #
Various
Various
14
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products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained
herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
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19
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