9FGL0241CKILFT

3.3V PCIe Gen1–5 Clock Generator Family 9FGL02x1/04x1/06x1/08x1 Datasheet Description Features The 9FGL02x1/04x1/06x1/08x1 devices comprise a family of 3.3V PCIe Gen1–5 clock generators. There are 2, 4, 6 and 8 outputs versions available and each differential output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35% power savings at optional 1.05V PCIe Clocking Architectures (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-selectable features allows optimization to customer ▪ Common Clocked (CC) ▪ Independent Reference (IR) with and without spread spectrum requirements: (SRIS, SRNS) Typical Applications ▪ ▪ ▪ ▪ ▪ Servers/High-Performance Computing nVME Storage Networking Accelerators Industrial Control ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Output Features ▪ 2, 4, 6, or 8 100MHz PCIe output pairs ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ ▪ ▪ ▪ 90fs RMS typical jitter (PCIe Gen5 CC) < 50ps cycle-to-cycle jitter on differential outputs < 50ps output-to-output skew on differential outputs ±0ppm synthesis error on differential outputs • Input polarity and pull-up/pull-downs • Output slew rate and amplitude • Output impedance (33Ω, 85Ω or 100Ω) for each output Contact factory for customized default configurations 25MHz input frequency OE# pins support PCIe CLKREQ# function Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread SMBus-selectable CC/SRIS -0.25% spread Clean switching between the CC/SRIS spread settings DIF outputs blocked until PLL is locked; clean system start-up 2 selectable SMBus addresses Space saving packages: • 4 × 4 mm 24-VFQFPN (9FGL02x1) • 5 × 5 mm 32-VFQFPN (9FGL04x1) • 5 × 5 mm 40-VFQFPN (9FGL06x1) • 6 × 6 mm 48-VFQFPN (9FGL08x1) Block Diagram VDDA vOE(n:0)# VDDREF VDDXTAL VDDDIG VDDO/ VDDIO n+1 REF3.3 XIN/CLKIN_25 DIFn# DIFn X2 vSADR ^vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 SCLK_3.3 SSC Capable PLL Control Logic GNDXTAL GNDREF ©2020 Renesas Electronics Corporation 2 to 8 outputs DIF0# DIF0 GNDDIG 1 GND EPAD November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9FGL02x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9FGL04x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9FGL06x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9FGL08x1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9FGL02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9FGL04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9FGL06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9FGL08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ©2020 Renesas Electronics Corporation 2 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Pin Assignments 9FGL02x1 Pin Assignment vOE1# VDD3.3 GND ^CKPWRGD_PD# ^vSS_EN_tri GNDXTAL Figure 1. Pin Assignments for 4 × 4 mm 24-VFQFPN Package – Top View 24 23 22 21 20 19 XIN/CLKIN_25 1 X2 2 18 DIF1# 17 DIF1 9FGL0241C 9FGL0251C EPAD is GND SCLK_3.3 16 VDDA3.3 15 GNDA 14 DIF0# 13 DIF0 9 10 11 12 vOE0# 8 VDD3.3 7 VDDDIG3.3 GNDREF 5 GNDDIG 6 GND vSADR/REF3.3 4 SDATA_3.3 VDDXTAL3.3 3 24-VFQFPN, 4 x 4 mm, 0.5mm pitch ^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull-down resistor ^v prefix indicates internal 120kOhm pull-up and pull-down resistors ©2020 Renesas Electronics Corporation 3 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet 9FGL04x1 Pin Assignment VDDO3.3 GND DIF3 DIF3# vOE3# GND ^CKPWRGD_PD# ^vSS_EN_tri Figure 2. Pin Assignments for 5 × 5 mm 32-VFQFPN Package – Top View 32 31 30 29 28 27 26 25 GNDXTAL 1 24 vOE2# 23 DIF2# XIN/CLKIN_25 2 X2 3 22 DIF2 21 VDDA3.3 9FGL0441C 9FGL0451C EPAD is GND VDDXTAL3.3 4 VDDREF3.3 5 vSADR/REF3.3 6 20 GNDA 19 DIF1# GNDREF 7 GNDDIG 8 18 DIF1 17 vOE1# VDDO3.3 GND DIF0# DIF0 vOE0# SDATA_3.3 SCLK_3.3 VDDDIG3.3 9 10 11 12 13 14 15 16 32-VFQFPN, 5 x 5 mm, 0.5mm pitch ^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull-down resistor ^v prefix indicates internal 120kOhm pull-up and pull-down resistors ©2020 Renesas Electronics Corporation 4 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet 9FGL06x1 Pin Assignment VDD3.3 VDDIO DIF4 DIF4# vOE4# DIF5 DIF5# vOE5# VDDIO ^CKPWRGD_PD# Figure 3. Pin Assignments for 5 × 5 mm 40-VFQFPN Package – Top View 40 39 38 37 36 35 34 33 32 31 ^vSS_EN_tri 1 30 vOE3# XIN/CLKIN_25 2 29 DIF3# X2 3 28 DIF3 VDDXTAL3.3 4 27 VDDIO 9FGL0641C 9FGL0651C EPAD is GND VDDREF3.3 5 vSADR/REF3.3 6 NC 7 26 VDDA3.3 25 NC 24 vOE2# GNDDIG 8 23 DIF2# SCLK_3.3 9 22 DIF2 SDATA_3.3 10 21 vOE1# NC DIF1# DIF1 VDDIO VDD3.3 DIF0# DIF0 vOE0# VDDIO VDDDIG3.3 11 12 13 14 15 16 17 18 19 20 40-VFQFPN, 5 x 5 mm, 0.4mm pitch ^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull-down resistor ^v prefix indicates internal 120kOhm pull-up and pull-down resistors ©2020 Renesas Electronics Corporation 5 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet 9FGL08x1 Pin Assignment vOE5# VDD3.3 VDDIO GND DIF6 DIF6# vOE6# DIF7 DIF7# vOE7# VDDIO ^CKPWRGD_PD# Figure 4. Pin Assignments for 6 × 6 mm 48-VFQFPN Package – Top View 48 47 46 45 44 43 42 41 40 39 38 37 ^vSS_EN_tri 1 36 DIF5# GNDXTAL 2 XIN/CLKIN_25 3 35 DIF5 34 vOE4# X2 4 VDDXTAL3.3 5 33 DIF4# 32 DIF4 9FGL0841C 9FGL0851C EPAD is GND VDDREF3.3 6 vSADR/REF3.3 7 GNDREF 8 GNDDIG 9 31 VDDIO 30 VDDA3.3 29 GNDA 28 vOE3# SCLK_3.3 10 SDATA_3.3 11 27 DIF3# 26 DIF3 VDDDIG3.3 12 25 vOE2# DIF2# DIF2 GND VDDIO VDD3.3 DIF1# DIF1 vOE1# DIF0# DIF0 vOE0# VDDIO 13 14 15 16 17 18 19 20 21 22 23 24 48-VFQFPN, 6 x 6 mm, 0.4mm pitch ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor ^v prefix indicates internal pull-up and pull-down resistors Pin Descriptions Table 1. Pin Descriptions Name Type Description 9FGL08x1 9FGL06x1 9FGL04x1 9FGL02x1 Pin No. Pin No. Pin No. Pin No. ^CKPWRGD_PD# Input Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. ^vSS_EN_tri Latched In Latched select input to select spread spectrum amount at initial power up. See Spread Selection table. 1 1 32 23 DIF0 Output Differential true clock output. 15 14 13 13 DIF0# Output Differential complementary clock output. 16 15 14 14 DIF1 Output Differential true clock output. 18 18 18 17 ©2020 Renesas Electronics Corporation 6 48 40 31 22 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 1. Pin Descriptions (Cont.) Description 9FGL08x1 9FGL06x1 9FGL04x1 9FGL02x1 Pin No. Pin No. Pin No. Pin No. Name Type DIF1# Output Differential complementary clock output. 19 19 19 18 DIF2 Output Differential true clock output. 23 22 22 — DIF2# Output Differential complementary clock output. 24 23 23 — DIF3 Output Differential true clock output. 26 28 27 — DIF3# Output Differential complementary clock output. 27 29 28 — DIF4 Output Differential true clock output. 32 33 — — DIF4# Output Differential complementary clock output. 33 34 — — DIF5 Output Differential true clock output. 35 36 — — DIF5# Output Differential complementary clock output. 36 37 — — DIF6 Output Differential true clock output. 41 — — — DIF6# Output Differential complementary clock output. 42 — — — DIF7 Output Differential true clock output. 44 — — — DIF7# Output Differential complementary clock output. 45 — — — EPAD GND Connect to ground. 49 41 33 25 GND GND Ground pin. 22 EPAD 15 10 GND GND Ground pin. 40 EPAD 26, 30 21 GNDA GND Ground pin for the PLL core. 29 EPAD 20 15 GNDDIG GND Ground pin for digital circuitry. 9 8 8 6 GNDREF GND Ground pin for the REF outputs. 8 — 7 5 GNDXTAL GND GND for XTAL. 2 EPAD 1 24 NC — No connect. — 7, 25 — — SCLK_3.3 Input Clock pin of SMBus circuitry, 3.3V tolerant. 10 9 10 8 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 11 10 11 9 VDD3.3 Power Power supply, nominally 3.3V. 20 16 16 11 VDD3.3 Power Power supply, nominally 3.3V. 38 31 25 20 VDDA3.3 Power 3.3V power for the PLL core. 30 26 21 16 VDDDIG3.3 Power 3.3V digital power (dirty power). 12 11 9 7 VDDIO Power Power supply for differential outputs. 13 12 — — VDDIO Power Power supply for differential outputs. 21 17 — — VDDIO Power Power supply for differential outputs. 31 27 — — VDDIO Power Power supply for differential outputs. 39 32 — — VDDIO Power Power supply for differential outputs. 47 39 — — VDDREF3.3 Power Power supply for REF output, nominally 3.3V. 6 5 5 — VDDXTAL3.3 Power Power supply for XTAL, nominally 3.3V. 5 4 4 3 ©2020 Renesas Electronics Corporation 7 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 1. Pin Descriptions (Cont.) Name Type 9FGL08x1 9FGL06x1 9FGL04x1 9FGL02x1 Pin No. Pin No. Pin No. Pin No. Description Input Active low input for enabling output 0. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 14 13 12 12 Input Active low input for enabling output 1. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 17 21 17 19 Input Active low input for enabling output 2. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 25 24 24 — Input Active low input for enabling output 3. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 28 30 29 — Input Active low input for enabling output 4. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 34 35 — — Input Active low input for enabling output 5. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 37 38 — — Input Active low input for enabling output 6. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 43 — — — vOE7# Input Active low input for enabling output 7. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 46 — — — vSADR/REF3.3 Latched I/O Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin. 7 6 6 4 X2 Output Crystal output. 4 3 3 2 XIN/CLKIN_25 Input Crystal input or Reference Clock input, nominally 25MHz. 3 2 2 1 vOE0# vOE1# vOE2# vOE3# vOE4# vOE5# vOE6# Table 2. Spread Selection ^vSS_EN_tri Pin B1[4:3] Spread% Note 0 00 0 — 01 -0.25 PCIe Common Clock or SRIS mode. M (VDD/2) 10 0 PCIe Common Clock or SRIS mode. 1 11 -0.50 PCIe Common Clock or SRIS mode. PCIe SRNS mode. If SRnS mode is desired, power up with ^vSS_EN_tri = '0'. Do not attempt to switch to the other modes via SMBus control in Byte 1 or a system reset will be required. If Common Clock (CC) or SRIS mode is desired, power up with ^vSS_EN_tri at either 'M' or '1'. The desired spread spectrum amount can then be selected via Byte 1 without a requiring a system reset. Once 'M' or '1' is latched at power up, do not attempt to enter SRnS mode or a system reset will be required. ©2020 Renesas Electronics Corporation 8 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 9FGL02x1/04x1/06x1/08x1 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3. Absolute Maximum Ratings Parameter Symbol Supply Voltage Minimum Maximum Units Notes VDDx -0.5 4.6 V 1,2 Input Voltage VIN -0.5 VDD + 0.5 V 1,3 Input High Voltage, SMBus VIHSMB 3.9 V 1 Storage Temperature Ts 150 °C 1 Junction Temperature Tj 125 °C 1 Input ESD Protection ESD prot V 1 1 Guaranteed 2 3 Conditions SMBus clock and data pins. -65 Human Body Model. 2500 by design and characterization, not 100% tested in production. Operation under these conditions is neither implied nor guaranteed. Not to exceed 4.6V. Thermal Characteristics Table 4. Thermal Characteristics Parameter 9FGL02 Thermal Resistance 9FGL04 Thermal Resistance 9FGL06 Thermal Resistance Symbol Conditions Package Typical Values Units Notes θJC Junction to case. 62 °C/W 1 θJb Junction to base. 5.4 °C/W 1 θJA0 Junction to air, still air. 50 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 43 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 39 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 38 °C/W 1 θJC Junction to case. 42 °C/W 1 θJb Junction to base. 2.4 °C/W 1 θJA0 Junction to air, still air. 39 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 33 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 28 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 27 °C/W 1 θJC Junction to case. 42 °C/W 1 θJb Junction to base. 2.4 °C/W 1 θJA0 Junction to air, still air. 39 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 33 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 28 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 27 °C/W 1 ©2020 Renesas Electronics Corporation NLG24 NLG32 NDG40 9 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 4. Thermal Characteristics (Cont.) Parameter 9FGL08 Thermal Resistance 1 EPAD Symbol Conditions Package Typical Values Units Notes θJC Junction to case. 33 °C/W 1 θJb Junction to base. 2.1 °C/W 1 θJA0 Junction to air, still air. 37 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 30 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 27 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 26 °C/W 1 NDG48 soldered to board. Electrical Characteristics TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions. Table 5. SMBus Parameters Parameter Symbol SMBus Input Low Voltage VILSMB VDDSMB = 3.3V. SMBus Input High Voltage VIHSMB VDDSMB = 3.3V. SMBus Output Low Voltage VOLSMB At IPULLUP. SMBus Sink Current IPULLUP At VOL. Nominal Bus Voltage VDDSMB SCLK/SDATA Rise Time tRSMB SCLK/SDATA Fall Time SMBus Operating Frequency 1 2 Conditions Minimum Typical 2.1 Maximum Units 0.8 V 3.6 V 0.4 V 4 Notes mA 2.7 3.6 V (Max. VIL - 0.15V) to (Min. V IH + 0.15V). 1000 ns 1 tFSMB (Min. VIH + 0.15V) to (Max. VIL - 0.15V). 300 ns 1 fSMB SMBus operating frequency. 500 kHz 2 Notes Guaranteed by design and characterization, not 100% tested in production. The device must be powered up for the SMBus to function. Table 6. Input/Supply/Common Parameters – Normal Operating Conditions Parameter Symbol Conditions Minimum Typical Maximum Units Supply Voltage VDDxxx Supply voltage for core, analog and single-ended LVCMOS outputs. 3.135 3.3 3.465 V IO Supply Voltage VDDIO Supply voltage for differential low power outputs. 0.9975 1.05–3.3 3.465 V Ambient Operating Temperature TAMB Industrial range. -40 25 85 °C Input High Voltage VIH 0.75 x VDDx VDDx + 0.3 V Input Low Voltage VIL -0.3 0.25 x VDDx V Input High Voltage VIHtri 0.8 x VDDx VDDx + 0.3 V Input Mid Voltage VIMtri 0.6 x VDDx V Input Low Voltage VILtri 0.20 x VDDx V Single-ended inputs, except SMBus. Single-ended tri-level inputs ('_tri' suffix). ©2020 Renesas Electronics Corporation 0.4 x VDDx -0.3 10 0.5 x VDDx November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 6. Input/Supply/Common Parameters – Normal Operating Conditions (Cont.) Parameter Symbol Conditions Minimum Typical Maximum Units IIN Single-ended inputs, VIN = GND, VIN = V DD. -5 -0.05 5 μA IINP Single-ended inputs. VIN = 0V; inputs with internal pull-up resistors. VIN = VDD; inputs with internal pull-down resistors. -50 7 50 μA Input Frequency FIN XTAL or X1 input. Pin Inductance Lpin Input Current CIN Capacitance 25 Logic inputs, except DIF_IN. Notes MHz 4 7 nH 1 5 pF 1 6 pF 1 0.3 1.8 ms 1,2 1.5 COUT Output pin capacitance. CLK Stabilization tSTAB From VDD power-up and after input clock stabilization or deassertion of PD# to 1st clock. SS Modulation Frequency fMOD Triangular modulation. 30 31.6 33 kHz 1 OE# Latency tLATOE# DIF start after OE# assertion. DIF stop after OE# deassertion. 1 2 3 clocks 1,3 Tdrive_PD# tDRVPD DIF output enable after PD# de-assertion. 300 μs 1,3 1 2 3 4 Fall Time tF Fall time of single-ended control inputs. 5 ns 1,2 Rise Time tR Rise time of single-ended control inputs. 5 ns 1,2 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. Time from deassertion until outputs are > 200mV. Contact the factory for other frequencies. Table 7. Differential Low-Power HCSL Outputs Parameter Symbol Slew Rate Trf Crossing Voltage (abs) Vcross_abs Scope averaging off. Crossing Voltage (var) Δ-Vcross Scope averaging off. Avg. Clock Period Accuracy Conditions Minimum Typical Maximum Units Notes Scope averaging on, fast setting. 2 2.7 4 V/ns 2,3 Scope averaging, slow setting. 1 1.9 3 V/ns 2,3 250 409 550 mV 1,4,5 14 140 mV 1,4,9 0 0 +2500 ppm 2,10,12,13 9.95 10 10.0503 ns 2,6 16 50 ps 2 660 761 850 mV 1 -150 -7 150 mV 1 9FGL0xxx devices have 0 ppm TPERIOD_AVG synthesis error. The maximum occurs with -0.5% SSC. Absolute Period TPERIOD_ABS Jitter, Cycle to Cycle tjcyc-cyc Voltage High VHIGH Voltage Low VLOW ©2020 Renesas Electronics Corporation Includes jitter and spread spectrum modulation. Statistical measurement on single-ended signal using oscilloscope math function (scope averaging on). 11 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 7. Differential Low-Power HCSL Outputs (Cont.) Parameter Symbol Conditions Absolute Maximum Voltage VMIN Absolute Minimum Voltage VMAX Measurement on single-ended signal using absolute value (scope averaging off). Duty Cycle tDC Slew Rate Matching ΔTrf Skew, Output to Output tsk3 1 Measured 2 Minimum Typical Maximum Units Notes 819 1150 mV 1,7,15 -300 -46 1,8,15 45 49 55 % 2 Single-ended measurement. 6 20 % 1,14 Averaging on, VT = 50%. 12 50 ps 2 from single-ended waveform.  Measured from differential waveform. 3 Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through 4 5 the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum 7 8 9 modulation. Defined as the maximum instantaneous voltage including overshoot. Defined as the minimum instantaneous voltage including undershoot. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in VCROSS for any particular system. 10 11 12 Refer to Section 8.6.2 of the PCI Express Base Specification, Revision 5.0 for information regarding PPM considerations. System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single-ended probes must be used for measurements requiring single ended measurements. Either single-ended probes with math or differential probe can be used for differential measurements. Test load CL = 2pF. PCIe Gen1 through Gen4 specify ±300ppm frequency tolerances. PCIe Gen5 reduces the allowable tolerance to ±100ppm without spread spectrum. 13 “ppm” refers to 14 15 parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly or 100Hz. For 100ppm, then we have an error budget of 100Hz/ppm × 100ppm = 10kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±100ppm applies to systems that do not employ Spread Spectrum clocking, or that use common clock source. For systems employing Spread Spectrum clocking, there is an additional 2,500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,600ppm for Common Clock architectures. Separate Reference Clock architectures may have a lower allowed spread percentage. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. At default SMBus amplitude settings. Table 8. 12kHz–20MHz Phase Jitter of Differential Outputs Parameter Symbol Phase Jitter, 12kHz–20MHz tjph12k20M ©2020 Renesas Electronics Corporation Conditions Differential outputs when device is set to PCIe SRnS mode (Byte1[4:3] = 00). 12 Minimum Typical Maximum Units 1.9 2 ps (rms) November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 9. Current Consumption – 9FGL02 Parameter Symbol Operating Supply Current IDDAOP VDDA, all outputs active at 100MHz. 13 17 mA IDDOP All VDD, except V DDA, all outputs active at100MHz. 18 23 mA Wake-on-LAN Current (Power down state and Byte 3, bit 5 = '1') IDDAPD VDDA, DIF outputs off, REF output running. 0.9 1.5 mA 1 IDDPD All VDD, except V DDA, DIF outputs off, REF output running. 5.7 8 mA 1 Power Down Current (Power down state and Byte 3, bit 5 = '0') IDDAPD VDDA, all outputs off. 0.9 1.5 mA IDDPD All VDD, except V DDA, all outputs off. 1.7 2.5 mA 1 Conditions Minimum Typical Maximum Units Notes This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1). Table 10. Current Consumption – 9FGL04 Parameter Symbol Conditions Minimum Typical Maximum Units Notes IDDAOP VDDA, all outputs active at 100MHz. 13 17 mA IDDOP All other VDD, except V DDA, all outputs active at100MHz. 30 39 mA Wake-on-LAN Current (Power down state and Byte 3, bit 5 = '1') IDDAPD VDDA, DIF outputs off, REF output running. 0.9 1.5 mA 1 IDDPD All other VDD, except V DDA, DIF outputs off, REF output running. 5.9 8.0 mA 1 Power Down Current (Power down state and Byte 3, bit 5 = '0') IDDAPD VDDA, all outputs off. 0.9 1.5 mA IDDPD All other VDD, except V DDA, all outputs off. 1.5 2.5 mA Operating Supply Current 1 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1). Table 11. Current Consumption – 9FGL06 Parameter Operating Supply Current Wake-on-LAN Current (Power down state and Byte 3, bit 5 = '1') Symbol Conditions Minimum Typical Maximum Units Notes IDDAOP VDDA, all outputs active at 100MHz. 14 17 mA IDDOP All VDD, except V DDA and VDDIO, all outputs active at100MHz. 16 20 mA IDDIOOP VDDIO, all outputs active at100MHz. 27 32 mA IDDAPD VDDA, DIF outputs off, REF output running. 0.9 1.5 mA 1 IDDPD All VDD, except V DDA and VDDIO, DIF outputs off, REF output running. 6 8 mA 1 0.04 0.05 mA 1 IDDIOOP VDDIO, DIF outputs off, REF output running. ©2020 Renesas Electronics Corporation 13 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 11. Current Consumption – 9FGL06 Parameter Power Down Current (Power down state and Byte 3, bit 5 = '0') 1 Symbol Conditions Minimum Typical Maximum Units Notes IDDAPD VDDA, all outputs off. 0.9 1.5 mA IDDPD All VDD, except V DDA and VDDIO, all outputs off. 1.8 2.5 mA VDDIO, all outputs off. 0.04 0.08 mA IDDIOOP This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1). Table 12. Current Consumption – 9FGL08 Parameter Operating Supply Current Wake-on-LAN Current (Power down state and Byte 3, bit 5 = '1') Power Down Current (Power down state and Byte 3, bit 5 = '0') 1 Symbol Conditions Minimum Typical Maximum Units Notes IDDAOP VDDA, all outputs active at 100MHz. 14 19 mA IDDOP All VDD, except V DDA and VDDIO, all outputs active at100MHz. 18 24 mA IDDIOOP VDDIO, all outputs active at100MHz. 30 37 mA IDDAPD VDDA, DIF outputs off, REF output running. 0.9 1.5 mA 1 IDDPD All VDD, except V DDA and VDDIO, DIF outputs off, REF output running. 5.2 8 mA 1 IDDIOOP VDDIO, DIF outputs off, REF output running. 0.04 0.1 mA 1 IDDAPD VDDA, all outputs off. 0.9 1.5 mA IDDPD All VDD, except V DDA and VDDIO, all outputs off. 1.7 2.3 mA VDDIO, all outputs off. 0.04 0.1 mA IDDIOOP This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1). Table 13. PCIe Phase Jitter of Differential Outputs TAMB = over the specified operating range. Supply voltages per normal operation conditions. See Test Loads for loading conditions. Parameter PCIe Phase Jitter (Common Clocked Architecture) PCIe Phase Jitter (SRIS Architecture) Symbol Conditions Units Notes tjphPCIeG1-CC PCIe Gen1 (2.5 GT/s) 18 28 86 ps (p-p) 1,2,7 PCIe Gen2 Hi Band (5.0 GT/s) 0.9 1.6 3 ps (RMS) 1,2,7 PCIe Gen2 Lo Band (5.0 GT/s) 0.4 0.6 3.1 ps (RMS) 1,2, tjphPCIeG3-CC PCIe Gen3 (8.0 GT/s) 0.25 0.4 1 ps (RMS) 1,2,3,7 tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) 0.25 0.4 0.5 ps (RMS) 1,2,3,4,7 tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) 0.09 0.11 0.15 ps (RMS) 1,2,3,5,7 tjphPCIeG1-SRIS PCIe Gen1 (2.5 GT/s) 4 6 ps (RMS) 1,2,6,8 tjphPCIeG2-SRIS PCIe Gen2 (5.0 GT/s) 0.8 1.1 ps (RMS) 1,2,6,8 tjphPCIeG3-SRIS PCIe Gen3 (8.0 GT/s) 0.3 0.4 ps (RMS) 1,2,6,8 tjphPCIeG4-SRIS PCIe Gen4 (16.0 GT/s) 0.3 0.35 ps (RMS) 1,2,6,8 tjphPCIeG5-SRIS PCIe Gen5 (32.0 GT/s) 0.15 0.19 ps (RMS) 1,2,6,8 tjphPCIeG2-CC ©2020 Renesas Electronics Corporation Minimum 14 Typical Maximum Limit N/A November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet 1 2 3 4 5 6 7 8 The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. Values for the Common Clock architecture are calculated for CC/SRIS spread off and spread on at -0.5%. SRIS values are calculated for CC/SRIS spread off and spread on at ≤-0.3%. If oscilloscope data is used, equipment noise is removed from all results. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specification limits, hence the N/A in the “Limit” column. SRIS values are informative only. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by √2. An additional consideration is the value for which to divide by √2. The conservative approach is to divide the ref clock jitter limit, and the case can be made for dividing the channel simulation values by √2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A “rule-of-thumb” SRIS limit would be either 0.5ps RMS/√2 = 0.35ps RMS, or 0.7ps RMS/√2 = 0.5ps RMS. Calculated for Byte1[4:3] spread settings of 01, 10 and 11. Calculated for Byte1[4:3] spread settings of 01, and 10. ©2020 Renesas Electronics Corporation 15 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 14. REF Output Parameter Symbol Long Accuracy ppm Clock Period Conditions Minimum Typical Maximum Units Notes See Tperiod min-max values. 0 ppm 1,2 Tperiod REF output. 40 ns 2 High Output Voltage VHIGH IOH = -2mA. Low Output Voltage VLOW IOL = 2mA. 0.8 x VDDREF V 0.2 x VDDREF V trf1 Byte 3 = 1F, VOH = 0.8 × VDD, VOL = 0.2 × VDD. 0.5 0.9 1.5 V/ns 1 trf1 Byte 3 = 5F, VOH = 0.8 × VDD, VOL = 0.2 × VDD. 1.0 1.5 2.5 V/ns 1,3 trf1 Byte 3 = 9F, VOH = 0.8 × VDD, VOL = 0.2 × VDD. 1.5 2.1 3.1 V/ns 1 trf1 Byte 3 = DF, VOH = 0.8 × VDD, VOL = 0.2 × VDD. 2.0 2.7 3.8 V/ns 1 Duty Cycle dt1X VT = VDD/2 V. 45 49.7 55 % 1,4 Jitter, Cycle to Cycle tjcyc-cyc VT = VDD/2 V. 35 125 ps 1,4 tjdBc1k 1kHz offset. -145 -135 dBc 1,4 tjdBc10k 10kHz offset to Nyquist. -150 -140 dBc 1,4 12kHz to 5MHz, DIF SSC off. 0.13 0.3 ps (rms) 1,4 12kHz to 5MHz, DIF SSC on. 1.4 1.5 ps (rms) 1,4,5 Rise/Fall Slew Rate Noise Floor Jitter, Phase 1 Guaranteed 2 All 3 4 5 tjphREF by design and characterization, not 100% tested in production. Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00MHz. Default SMBus value. When driven by a crystal. Does not apply to the 9FGL06x1 devices. ©2020 Renesas Electronics Corporation 16 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Power Management Table 15. Power Management 3 Differential Output CKPWRGD_PD# SMBus OE bit OEx# Pin True O/P Comp. O/P REF 0 X X Low 1 Low 1 Hi-Z 2 1 1 0 Running 1 1 1 The 2 REF 3 1 1 0 X Running Disabled 1 Disabled 1 Running Disabled 1 Running Disabled 1 Disabled 4 output state is set by B11[1:0] (Low/Low default). is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is disabled unless Byte3[5] = 1, in which case REF is running. Input polarities defined at default values. 4 See SMBus description for Byte 3, bit 4. Table 16. SMBus Address Selection SADR Address + Read/Write Bit 0 1101000 X 1 1101010 X State of SADR on first application of CKPWRGD_PD# Test Loads Figure 5. Single-ended Output Test Load Test Point L DUT REFCLK Zo Rs CL Table 17. Terminations for Single-ended Output Clock Source Device Under Test (DUT) Rs (Ω) Zo (Ω) L (cm) CL (pF) N/A 9FGL0nxx 33 50 12.7 4.7 ©2020 Renesas Electronics Corporation 17 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Figure 6. Test Load for AC/DC Measurements CL CK+ L Test Points for High Impedance Probe Zo (differential) DUT CK- CL Table 18. Terminations for AC/DC Measurements Clock Source Device Under Test (DUT) Rs (Ω) Zo (Ω) L (cm) CL (pF) N/A 9FGL0x41 Internal 100 12.7 2 N/A 9FGL0x51 Internal 85 12.7 2 Figure 7. Test Setup for PCIe Clock Phase Jitter Measurements Oscillocope (≥20GS/s) L CKIN+ CK+ Zo (differential) DUT CKIN- Coax Cables 0.1uF CK- 50 SMA Connectors 50 Table 19. Terminations for PCIe Clock Phase Jitter Measurements Clock Source Device Under Test (DUT) Rs (Ω) Zo (Ω) L (cm) CL (pF) N/A 9FGL0x41 Internal 100 12.7 N/A N/A 9FGL0x51 Internal 85 12.7 N/A Alternate Terminations The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's “Universal” Low-Power HCSL Outputs” for details. ©2020 Renesas Electronics Corporation 18 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Crystal Characteristics Table 20. Recommended Crystal Characteristics 1 Parameter Value Units Frequency1 25 MHz Resonance Mode Fundamental — Frequency Tolerance @ 25°C ±20 ppm maximum Frequency Stability, reference at 25°C over operating temperature range ±20 ppm maximum Temperature Range (industrial) -40 to +85 °C Temperature Range (commercial) 0 to +70 °C Equivalent Series Resistance (ESR) 50 Ω maximum Shunt Capacitance (CO) 7 pF maximum Load Capacitance (CL) 8 pF maximum Drive Level 0.1 mW maximum Aging per year ±5 ppm maximum When driven by an external oscillator via the XIN/CLKIN_25 pin, X2 should be floating. ©2020 Renesas Electronics Corporation 19 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet General SMBus Serial Interface Information How to Write How to Read ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Controller (host) sends a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) sends the byte count = X Renesas clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 Renesas clock will acknowledge each byte one at a time Controller (host) sends a stop bit Index Block Write Operation Controller (Host) Renesas (Slave/Receiver) Controller (host) will send a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Renesas clock will acknowledge Renesas clock will send the data byte count = X Renesas clock sends Byte N+X-1 Renesas clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit T starT bit Slave Address WR WRite Index Block Read Operation ACK Beginning Byte = N ACK Controller (Host) starT bit Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X Beginning Byte N X Byte O O O Renesas T ACK ACK O O O RT RD Byte N + X - 1 Repeat starT Slave Address ReaD ACK ACK P stoP bit Data Byte Count=X ACK Note: Address is latched on SADR pin. Beginning Byte N O O O X Byte ACK O O O Byte N + X - 1 N P ©2020 Renesas Electronics Corporation 20 Not acknowledge stoP bit November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 21. Byte 0: Output Enable Register Byte 01 Control Function Type Bit7 Bit6 Output Enable Output Enable RW RW Bit5 Bit4 Output Enable Output Enable RW RW Bit3 Bit2 Bit1 Bit0 Output Enable Output Enable Output Enable RW 0 See B11[1:0] 1 OE# Pin Controls Output Output Enable RW RW RW 9FGL08 Name OE7 OE6 OE5 OE4 OE3 OE2 OE1 OE0 9FGL08 Default 1 1 1 1 1 1 1 1 9FGL06 Name OE5 OE4 Reserved OE3 OE2 OE1 Reserved OE0 9FGL06 Default 1 1 x 1 1 1 x 1 9FGL04 Name Reserved Reserved Reserved Reserved OE3 OE2 OE1 OE0 9FGL04 Default x x x x 1 1 1 1 9FGL02 Name Reserved Reserved Reserved Reserved Reserved OE1 OE0 Reserved 9FGL02 Default x x x x x 1 1 x 1A low on these bits will override the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default) Table 22. Byte 1: Spread Spectrum with VHIGH Control Register Byte 1 Bit7 Control Function Type Bit6 SS Enable SS Enable Readback Bit1 Readback Bit0 R R 0 See Spread Selection table 1 Bit5 Bit4 Bit3 Enable software control of spread spectrum SS Software Control Bit1 SS Software Control Bit0 Controls Output Amplitude RW RW1 RW1 RW RW 00 = 0.6V 10 = 0.75V 01 = 0.68V 11 = 0.85V SS controlled by latch (B1[7:6]) Values in B1[4:3] control SS amount Reserved Bit1 Bit0 See Spread Selection table Name SSENRB1 SSENRB1 SSEN_SWCNTRL SSENSW1 SSENSW0 Default Latch Latch 0 0 0 1 See Bit2 AMPLITUDE 1 AMPLITUDE 0 x 1 0 notes on Spread Selection table. B1[5] must be set to a 1 in order to use B1[4:3]. ©2020 Renesas Electronics Corporation 21 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 23. Byte 2: DIF Slew Selection Register Byte 2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Control Function Select fast or slow slew rate Select fast or slow slew rate Select fast or slow slew rate Select fast or slow slew rate Select fast or slow slew rate Select fast or slow slew rate Select fast or slow slew rate Select fast or slow slew rate Type RW RW RW RW RW RW RW RW 0 Slow Slew Rate 1 Fast Setting 9FGL08 Name DIF7_slew DIF6_slew DIF5_slew DIF4_slew DIF3_slew DIF2_slew DIF1_slew DIF0_slew 9FGL08 Default 1 1 1 1 1 1 1 1 9FGL06 Name DIF5_slew DIF4_slew Reserved DIF3_slew DIF2_slew DIF1_slew Reserved DIF0_slew 9FGL06 Default 1 1 x 1 1 1 x 1 9FGL04 Name Reserved Reserved Reserved Reserved DIF3_slew DIF2_slew DIF1_slew DIF0_slew 9FGL04 Default x x x x 1 1 1 1 9FGL02 Name Reserved Reserved Reserved Reserved Reserved DIF1_slew DIF0_slew Reserved 9FGL02 Default x x x x x 1 1 x Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Wake-on-Lan Enable for REF REF Output Enable Reserved Reserved Reserved Reserved x x x x 1 See Differential Low-Power HCSL Outputs table for slew rates. Table 24. Byte 3: REF Slew Rate Control Register Byte 3 Bit7 Control Function Bit6 Slew Rate Control Type RW RW RW RW 0 00 = Slowest 10 = Fast REF disabled in Power Down Disabled1 1 01 = Slow 11 = Fastest REF runs in Power Down Enabled REF Power Down Function REF OE 0 1 Name REF Slew Rate [1:0] Default 1 The 0 1 disabled state depends on Byte11[1:0]. '00' = Low, '01'= HiZ, '10' = Low, '11' = High. Byte 4 is Reserved ©2020 Renesas Electronics Corporation 22 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 25. Byte 5: Revision and Vendor ID Register Byte 5 Bit7 Bit6 Control Function Type Bit4 Bit3 Bit2 Revision ID R R R R R C rev = 0010 1 RID3 RID2 Bit1 Bit0 R R VENDOR ID R 0 Name Bit5 0001 = Renesas RID1 RID0 VID3 VID2 VID1 VID0 Bit4 Bit3 Bit2 Bit1 Bit0 R R R Table 26. Byte 6: Device Type/Device ID Register Byte 6 Bit7 Control Function Type Bit6 Bit5 Device Type R Device ID R R R 9FGL08 = 0b00100 9FGL06 = 0b00110 9FGL04 = 0b00100 9FGL02 = 0b00010 0 00 = FGL 1 Name Device Type1 R Device Type0 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0 Bit4 Bit3 Bit2 Bit1 Bit0 RW RW Table 27. Byte 7: Byte Count Register Byte 7 Bit7 Bit6 Bit5 Control Function Type 0 Byte Count Programming Reserved Reserved Reserved RW RW RW Writing to this register will configure how many bytes will be read back. 1 Name Default x x x BC4 BC3 BC2 BC1 BC0 0 1 0 0 0 Bytes 8 and 9 are Reserved ©2020 Renesas Electronics Corporation 23 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 28. Byte 10: PLL MN Enable, PD_Restore Register Byte 10 Bit7 Bit6 Control Function M/N Programming Enable Restore Default Config. In PD Type RW RW 0 M/N Prog. Disabled Clear Config in PD 1 M/N Prog. Enabled Keep Config in PD Name PLL M/N En Power-Down (PD) Restore Default 0 1 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reserved Reserved Reserved Reserved Reserved Reserved x x x x x x Table 29. Byte 11: Stop State Control Register Byte 11 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Control Function Type 0 Bit0 True/Complement DIF Output Disable State Reserved Reserved Reserved Reserved Reserved Reserved 1 RW RW 00 = Low/Low 01 = HiZ/HiZ 10 = High/Low 11 = Low/High Name Default Bit1 x x x STP[1] STP[0] x x x 0 0 Bit4 Bit3 Bit2 Bit1 Bit0 Table 30. Byte 12: Impedance Control Register 1 Byte 12 Control Function Type Bit7 Bit6 Output impedance control [1:0] RW RW 0 Output impedance control [1:0] RW RW DIF3_imp[1] DIF3_imp[0] DIF2_imp[1] DIF2_imp[1] DIF2_imp[0] DIF1_imp[1] RW RW RW DIF2_imp[0] DIF1_imp[1] DIF1_imp[0] DIF0_imp[1] DIF0_imp[0] DIF1_imp[0] Reserved Reserved DIF0_imp[1] DIF0_imp[0] DIF0_imp[0] Reserved Reserved 9FGL0641 defaults to 0b1010xx10 9FGL0651 defaults to 0b0101xx01 9FGL06 Default 9FGL04 Name RW Output impedance control [1:0] 9FGL0841 defaults to 0b10101010 9FGL0851 defaults to 0b01010101 9FGL08 Default 9FGL06 Name Output impedance control [1:0] 00 = 33ohm DIF Zout, 01 = 85ohm DIF Zout 10 = 100ohm DIF Zout, 11 = Reserved 1 9FGL08 Name Bit5 DIF1_imp[1] DIF1_imp[0] ©2020 Renesas Electronics Corporation Reserved Reserved 24 DIF0_imp[1] November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 30. Byte 12: Impedance Control Register 1 (Cont.) Byte 12 Bit7 Bit6 Bit5 Bit4 Bit2 Bit1 Bit0 Reserved Reserved Reserved Bit2 Bit1 Bit0 9FGL0441 defaults to 0b10xx10xx 9FGL0451 defaults to 0b01xx01xx 9FGL04 Default 9FGL02 Name Bit3 DIF0_imp[1] DIF0_imp[0] Reserved Reserved Reserved 9FGL0241 defaults to 0b10xxxxxx 9FGL0251 defaults to 0b01xxxxxx 9FGL02 Default Table 31. Byte 13: Impedance Control Register 2 Byte 13 Control Function Type Bit7 Bit6 Output impedance control [1:0] RW RW 0 Bit4 Output impedance control [1:0] RW RW DIF7_imp[1] DIF7_imp[0] DIF6_imp[1] DIF5_imp[1] DIF5_imp[0] DIF4_imp[1] Reserved Reserved DIF3_imp[1] RW RW RW DIF6_imp[0] DIF5_imp[1] DIF5_imp[0] DIF4_imp[1] DIF4_imp[0] DIF4_imp[0] Reserved Reserved DIF3 Zout DIF3 Zout DIF3_imp[0] DIF2_imp[1] DIF2_imp[0] Reserved Reserved DIF1_imp[0] Reserved Reserved 9FGL0441 defaults to 0bxx1010xx 9FGL0451 defaults to 0bxx0101xx 9FGL04 Default 9FGL02 Name RW Output impedance control [1:0] 9FGL0641 defaults to 0b1010xx10 9FGL0651 defaults to 0b0101xx01 9FGL06 Default 9FGL04 Name Output impedance control [1:0] 9FGL0841 defaults to 0hAA 9FGL0851 defaults to 0h55 9FGL08 Default 9FGL06 Name Bit3 00 = 33ohm DIF Zout, 01 = 85ohm DIF Zout 10 = 100ohm DIF Zout, 11 = Reserved 1 9FGL08 Name Bit5 Reserved Reserved 9FGL02 Default ©2020 Renesas Electronics Corporation Reserved Reserved DIF1_imp[1] 9FGL0241 defaults to 0bxxxx10xx 9FGL0251 defaults to 0bxxxx01xx 25 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 32. Byte 14: Pull-up Pull-down Control Register 1 Byte 14 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Control Function Pull-up(pu)/ Pull-down(pd) control Pull-up(pd)/ Pull-down(pd) control Pull-up(pd)/ Pull-down(pd) control Pull-up(pd)/ Pull-down(pd) control Type RW RW RW RW RW RW RW RW 0 00 = None 01 = pd 00 = None 01 = pd 00 = None 01 = pd 00 = None 01 = pd 1 10 = pu 11 = pu+pd 10 = pu 11 = pu+pd 10 = pu 11 = pu+pd 10 = pu 11 = pu+pd 9FGL08 Name OE3_pu/pd[1] OE3_pu/pd[0] OE2_pu/pd[1] OE2_pu/pd[0] OE1_pu/pd[1] OE1_pu/pd[0] OE0_pu/pd[1] OE0_pu/pd[0] 9FGL08 Default 0 1 0 1 0 1 0 1 9FGL06 Name OE2_pu/pd[1] OE2_pu/pd[0] OE1_pu/pd[1] OE1_pu/pd[0] Reserved Reserved OE0_pu/pd[1] OE0_pu/pd[0] 9FGL06 Default 0 1 0 1 x x 0 1 9FGL04 Name OE1_pu/pd[1] OE1_pu/pd[0] Reserved Reserved OE0_pu/pd[1] OE0_pu/pd[0] Reserved Reserved 9FGL04 Default 0 1 x x 0 1 x x 9FGL02 Name OE0_pu/pd[1] OE0_pu/pd[0] Reserved Reserved Reserved Reserved Reserved Reserved 9FGL02 Default 0 1 x x x x x x Bit3 Bit2 Bit1 Bit0 Table 33. Byte 15: Pull-up Pull-down Control Register 2 Byte 15 Bit7 Bit6 Control Function Pull-up(pd)/ Pull-down(pd) control Pull-up(pd)/ Pull-down(pd) control Pull-up(pd)/ Pull-down(pd) control Pull-up(pd)/ Pull-down(pd) control Type RW RW RW RW RW RW RW RW 0 00 = None 01 = pd 00 = None 01 = pd 00 = None 01 = pd 00 = None 01 = pd 1 10 = pu 11 = pu+pd 10 = pu 11 = pu+pd 10 = pu 11 = pu+pd 10 = pu 11 = pu+pd 9FGL08 Name OE7_pu/pd[1] OE7_pu/pd0] OE6_pu/pd[1] OE6_pu/pd[0] OE5_pu/pd[1] OE5_pu/pd[0] OE4_pu/pd[1] OE4_pu/pd[0] 9FGL08 Default 0 1 0 1 0 1 0 1 9FGL06 Name OE5_pu/pd[1] OE5_pu/pd[0] OE4_pu/pd[1] OE4_pu/pd[0] Reserved Reserved OE3_pu/pd[1] OE3_pu/pd[0] 9FGL06 Default 0 1 0 1 0 1 0 1 9FGL04 Name Reserved Reserved OE3_pu/pd[1] OE3_pu/pd[0] OE2_pu/pd[1] OE2_pu/pd[0] Reserved Reserved ©2020 Renesas Electronics Corporation Bit5 Bit4 26 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 33. Byte 15: Pull-up Pull-down Control Register 2 (Cont.) Byte 15 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 9FGL04 Default 0 1 0 1 0 1 0 1 9FGL02 Name Reserved Reserved Reserved Reserved OE1_pu/pd[1] OE1_pu/pd[0] Reserved Reserved 9FGL02 Default 0 1 0 1 0 1 0 1 Bit3 Bit2 Bit1 Bit0 Table 34. Byte 16: Pull-up Pull-down Control Register 3 Byte 16 Bit7 Bit6 Bit5 Bit4 Pull-up(pd)/ Pull-down(pd) control Control Function Type RW RW 00 = None 01 = pd 1 10 = pu 11 = pu+pd Name CKPWRGD_ PD_pu/pd[1] CKPWRGD_ PD_pu/pd[0] 1 0 0 Default Reserved 0 Reserved 0 Reserved 1 Reserved 0 Reserved 0 Reserved 1 Byte 17 is Reserved ©2020 Renesas Electronics Corporation 27 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Table 35. Byte 18: Polarity Control Register 2 Byte 18 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Control Function Sets OE pin polarity Sets OE pin polarity Sets OE pin polarity Sets OE pin polarity Sets OE pin polarity Sets OE pin polarity Sets OE pin polarity Sets OE pin polarity Type RW RW RW RW RW RW RW RW 0 Output enabled when OE pin is low 1 Output enabled when OE pin is high 9FGL08 Name OE7_polarity OE6_polarity OE5_polarity OE4_polarity OE3_polarity OE2_polarity OE1_polarity OE0_polarity 9FGL08 Default 0 0 0 0 0 0 0 0 9FGL06 Name OE5_polarity OE4_polarity Reserved OE3_polarity OE2_polarity OE1_polarity Reserved OE0_polarity 9FGL06 Default 0 0 0 0 0 0 0 0 9FGL04 Name Reserved OE3_polarity OE2_polarity Reserved OE1_polarity Reserved OE0_polarity Reserved 9FGL04 Default 0 0 0 0 0 0 0 0 9FGL02 Name Reserved Reserved OE1_polarity Reserved OE0_polarity Reserved Reserved Reserved 9FGL02 Default 0 0 0 0 0 0 0 0 Bit4 Bit3 Bit2 Bit1 Bit0 Table 36. Byte 19: Polarity Control Register 1 Byte 19 Bit7 Bit6 Bit5 Control Function Sets CKPWRGD_ PD polarity Type RW 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Power Down when Low 1 Power Down when High Name CKPWRGD_ PD_polarity Default 0 0 ©2020 Renesas Electronics Corporation 0 0 28 0 0 0 0 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. 9FGL02: www.idt.com/document/psc/nlnlg24p1-package-outline-40-x-40-mm-body-05-mm-pitch-qfn-epad-size-245-x-245-mm 9FGL04: www.idt.com/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1 9FGL06: www.idt.com/document/psc/ndndg40-package-outline-50-x-50-mm-bodyepad-350mm-sq-040-mm-pitch-qfn 9FGL08: www.idt.com/document/psc/48-vfqfpn-package-outline-drawing-60-x-60-x-090-mm-body-epad-42-x-42-mm-040mm-pitch-ndg48p2 Marking Diagrams 9FGL02 ▪ Line 1:“LOT” denotes the lot number. ▪ Line 2: truncated part number. ▪ Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. 9FGL04 ▪ ▪ ▪ ▪ ©2020 Renesas Electronics Corporation Lines 1 and 2: truncated part number Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. Line 4: “COO” denotes country of origin. Line 5: “LOT” denotes the lot number. 29 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet 9FGL06 9FGL08 ▪ ▪ ▪ ▪ Lines 1 and 2: truncated part number Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. Line 4: “COO” denotes country of origin. Line 5: “LOT” denotes the lot number. ▪ ▪ ▪ ▪ Lines 1 and 2: truncated part number Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. Line 4: “COO” denotes country of origin. Line 5: “LOT” denotes the lot number. ©2020 Renesas Electronics Corporation 30 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Ordering Information Table 37. Ordering Information Number of Output Clock Outputs Impedance 100 2 85 100 4 85 100 6 85 100 8 85 Orderable Part Number Temperature Range Package Part Number Suffix and Shipping Method 9FGL0241CKILF 9FGL0241CKILFT 9FGL0251CKILF 24-VFQFPN 9FGL0251CKILFT 9FGL0441CKILF 9FGL0441CKILFT 9FGL0451CKILF 32-VFQFPN None = Trays 9FGL0451CKILFT -40°C to +85°C 9FGL0641CKILF 9FGL0641CKILFT 9FGL0651CKILF 40-VFQFPN “T” = Tape and Reel, Pin 1 Orientation: EIA-481C (see Table 38 for more details) 9FGL0651CKILFT 9FGL0841CKILF 9FGL0841CKILFT 9FGL0851CKILF 48-VFQFPN 9FGL0851CKILFT “C” is the device revision designator (will not correlate with the datasheet revision). “LF” denotes Pb-free configuration, RoHS compliant. Table 38. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION T CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED ©2020 Renesas Electronics Corporation 31 November 17, 2020 9FGL02x1/04x1/06x1/08x1 Datasheet Revision History Revision Date Description of Change November 17, 2020 ▪ Updated DIF5# pin numbers for 9FGL06x1. ▪ Rebranded to Renesas. October 10, 2019 Initial release. ©2020 Renesas Electronics Corporation 32 November 17, 2020 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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