DATASHEET
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
General Description
Features/Benefits
The 9FGP202A is a peripheral clock for Intel Server. It is
driven with a 25MHz crystal and generates CPU outputs up
to 400MHz. An SMBus interface allows full control of the
device.
• Selectable SMBus Address – D0/D1 or C0/C1
• Spread Spectrum capability on CPU and DOT 96MHz
clocks
• SMBus Control:
Recommended Application
– M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
Peripheral Clock for Intel Server
– Outputs can be disabled via pins or SMBus
Output Features
•
•
•
•
•
•
Key Specifications
1 - 0.7V current-mode differential CPU pair
8 - 50MHz output
1 - DOT 96MHz output
1 - 33.33MHz output
1 - 32.768KHz output
2 - 25MHz REF outputs
• Exact synthesis on CPU, RMII and 33.33MHz clocks
• +/- 100ppm frequency accuracy on remaining clocks
Block Diagram
25MHz(1:0)
X1_25
X2_25
XTAL
VttPwr_GD/PD#
CPU PLL
(SPREAD
CAPABLE)
CPUCLK
DOT PLL
(SPREAD
CAPABLE)
DOT96SS
OE_CPU
OE_96
OE_RMIIA
OE_RMIIB
CONTROL
LOGIC
33.33MHz
FIXED
PLL
DIVIDERS
8
RMII(7:0)
SMBADR
SMBDAT
SMBCLK
DIVIDERS
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
1
32.768KHz
9FGP202A
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9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
OE_RMIIA
RMII3
RMII2
VDDRMII
GNDRMII
RMII1
RMII0
SMBCLK
SMBDAT
VttPwr_GD/PD#
Pin Configuration
40 39 38 37 36 35 34 33 32 31
GND
VDD96
DOT96SST
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
9FGP202
OE_RMIIB
RMII4
RMII5
GND RMII
VDDRMII
RMII6
RMII7
VDD33
33.33MHZ/**SMBADR
GND 33
X2_25
X1_25
GNDREF
25MHz_0
25MHZ_1
VDDREF
GND32K
32.768KHz
VDD32K
IREF
11 12 13 14 15 16 17 18 19 20
40-MLF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
SMBus Address Selection
SMBADR
*SMBADR = 0
SMBADR = 1
D0/D1
C0/C1
* Default value
Power Supply Pins
Pin Number
Description
VDD
GND
9
10
CPUCLK output
2
1
DOT96SS output
26,34
27,35
50 MHz RMII outputs
23
21
33.33MHz output
12
14
32.768KHz output
15
18
XTAL, REF outputs
Note: All VDD should be connected to a common power rail with proper filtering
and decoupling.
Functionality
CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS
MHz
MHz
Byte0 Bit2 Byte0 Bit1 Byte0 Bit0
0
0
0
266.67
96.00
0
0
1
133.33
96.00
0
1
0
200.00
96.00
0
1
1
166.67
96.00
1
0
0
333.33
96.00
1
0
1
100.00
96.00
1
1
0
400.00
96.00
1
1
1
Reserved
96.00
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
RMII
MHz
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
25
MHz
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
32.768
KHz
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
P ower up default is highlighted.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
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9FGP202A
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
1
2
3
4
GND
VDD96
DOT96SST
DOT96SSC
PWR
PWR
OUT
OUT
5
OE_96
IN
6
OE_CPU
IN
7
CPUCLKT0
OUT
8
CPUCLKC0
OUT
9
10
VDDCPU
GNDCPU
PWR
PWR
11
IREF
OUT
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VDD32K
32.768KHz
GND32K
VDDREF
25MHz_0
25MHZ_1
GNDREF
X1_25
X2_25
GND33
33.33MHZ/**SMBADR
VDD33
RMII7
RMII6
VDDRMII
GNDRMII
RMII5
RMII4
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
OUT
PWR
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
30
OE_RMIIB
IN
31
OE_RMIIA
IN
32
33
34
35
36
37
38
39
RMII3
RMII2
VDDRMII
GNDRMII
RMII1
RMII0
SMBCLK
SMBDAT
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
40
VttPwr_GD/PD#
IN
DESCRIPTION
Ground pin.
Power pin for the DOT96 cloc ks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock .
Complement clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
Ac tive high input for enabling 96Hz outputs.
1 = enable output(s ), 0 = tri-state output(s)
Ac tive high input for enabling CPU DIFF pairs.
1 = enable output(s ), 0 = tri-state output(s)
True clock of differential pair CPU outputs. These are c urrent mode outputs. External resistors are
required for voltage bias .
Complementary c lock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision res istor tied to ground in order to establish the appropriate current. 475
ohms is the standard v alue.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Ground pin for the REF outputs .
Crystal input, Nominally 25.00MHz.
Crystal output, Nominally 25.00MHz .
Ground pin for the 33.33MHz outputs
33.33MHz clock output / SMBus address select bit.
Power pin for the 33.33MHz outputs , nominal 3.3V
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Ac tive high input for enabling RMII(7:4) outputs.
1 = enable output(s ), 0 = low
Ac tive high input for enabling RMII(3:0) outputs.
1 = enable output(s ), 0 = low
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and
are ready to be sampled. This is an active high input. / Asynchronous activ e low input pin used to
power down the devic e into a low power state.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Drive Strengths
9FGP202A
The singled-ended outputs of the 9FGP202A default to either a drive strength of 2 loads or a drive strength of 1 load.
Alternate drive strengths can be selected via the SMBus. Using the correct resistor value can properly terminate the output
to the transmission line without having to change the default drive strengths via the SMBus. The default drive strengths for
the single ended outputs are show below, as are the suggested termination resistors for the above topologies. All values
assume Zo = 50 ohms:
Default Drive Strength Table
Default Drive
RMII
1 Load
33.33MHz
2 Loads
25Mhz
2 Loads
32.768KHz
2 Loads
Optional Drive
2 Loads
1 Load
1 Load
1 Load
Series Termination Resistor Values
Series Resistor Series Resistor
Output Drive (Rs) for driving 1 (Rs) for driving 2
Load
Loads
Strength
1 Load
33 ohms
N/A
2 Loads
43 ohms
22 ohms
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Truth Table 1: VttPwr_GD/PD# and OE_96
VttPwr_GD/PD#
OE_96
Clocks
Pin 40
Pin 5
0
0
All clocks are powered down
0
1
All clocks are powered down
1
0
All clocks are enabled except DOT96SS
1
1
*All clocks are enabled including DOT96SS
*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)
Truth Table 2: VttPwr_GD/PD# and OE_CPU
VttPwr_GD/PD#
OE_CPU
Clocks
Pin 40
Pin 6
0
0
All clocks are powered down
0
1
All clocks are powered down
1
0
All clocks are enabled except CPUCLK
1
1
*All clocks are enabled including CPUCLK
*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)
Table 1: CPU Spread and Frequency Selection
CPU
SS_EN
Byte 0
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CPU
FS2
Byte 0
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CPU
FS1
Byte 0
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CPU
FS0
Byte 0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
Down
Spread %
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
0%
0%
0%
0%
0%
0%
0%
0%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Table2: DOT96 Spread and Frequency Selection Table
DOT96
SS_EN
Byte 0
bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
FS2
FS1
FS0
Byte 3
bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Byte 3
bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Byte 3
bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Byte 3
bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
DOT96SS
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
Spread %
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
+/-0.25
+/-0.5
+/-0.75
+/-1.0
-0.25
-0.50
-0.75
-1.0
-1.25
-1.50
-1.75
-2.0
-2.25
-2.5
-2.75
-3.00
6
Center
Center
Center
Center
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
9FGP202A
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGP202A. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
P ARAMETE R
SYMB OL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
3.3V Supply Voltage
Maxi mum difference across all
VDD pins
Storage Temperature
VDDxxx
-
GND - 0.5
3.3V
GND + 4.5
V
1
VDDdelta
-
0.5
V
1
Ts
-
-65
°
1
Ambient Operating Temp
Tambient
-
0
70
C
°C
Junction Temperature
Tj
-
125
°C
1
Input ESD protection HBM
ESD pro t
-
V
1
150
2000
1
1
Guaranteed by desig n and characterization, not 100% tested in production.
Electrical Characteristics–DOT96SS 0.7V Current Mode Differential Pair
P ARAMETE R
SYMB OL
CONDITIONS*
MIN
Current Source Output Impedance
Zo
VO = Vx
3000
Voltage High
VHigh
VLow
Statistical measu rement on singl e
ended signal
660
Voltage Low
-150
Measurement on single ended
signal using absolute value.
-300
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs)
Vx(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
TYP
MAX
250
UNITS
Notes
Ω
1
850
mV
1,3
150
mV
1,3
1150
mV
1
mV
1
550
mV
1
140
mV
1
V ariation of crossing over a ll
edges
see Tperiod min-max values
-100
100
ppm
1,2
96.00MHz nominal
10.4135
10.4198
ns
2
96.00MHz spread
10.4135
10.4722
ns
2
10.1635
10.7222
ns
1,2
Average period
Tperiod
Absolute min period
Tabsmin
96.00MHz no minal/spread
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
V OH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-t r
VOL = 0.175V, VOH = 0.525V
Fall Time Variati on
d-t f
V OH = 0.525V VOL = 0.175V
Measure ment from differential
dt3
45
Duty Cycle
wavefrom
Measure ment from differential
t jcyc -cyc
Jitter, Cycle to cycle
wavefrom
*T A = 0 - 70°C; V DD = 3.3 V +/-5% ; CL =2pF, R S=33.2ohms, R P=49.9ohms, I REF = 475ohms
125
ps
1
125
ps
1
55
%
1
250
ps
1
1
Guaranteed by desig n and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.00MHz
3
I REF = V DD/(3xR R). For R R = 475ohms (1%), I REF = 2.32mA. IOH = 6 x IR EF and V OH = 0.7V @ Z O=50ohms.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Electrical Characteristics–Input/Supply/Common Output Parameters
P ARAMETE R
SYMB OL
CONDITIONS*
MIN
MAX
UNITS
Notes
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
VIL
3.3 V +/-5%
VS S - 0.3
0.8
V
1
Input High Current
I IH
VIN = V DD
-5
5
uA
1
I IL 1
VIN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
I IL 2
VIN = 0 V ; Inputs with pull-up
resistors
-200
uA
1
VIH_ FS
3.3 V +/-5%
0.7
VDD + 0.3
V
1
V IL _FS
3.3 V +/-5%
VS S - 0.3
0.35
V
1
Input L ow Current
Low Thresh old InputHigh Voltage
Low Thresh old InputLow Voltage
Operating Current
I DD 3.3OP
Powerdown Current
IDD 3.3PD
Input Frequency
Fi
Pin Inductance
Lpi n
Input Capacitance
Clk Stabiliza tion
TYP
all outputs driven
200
mA
1
all diff pairs driven
30
mA
1
all differential pairs tri-stated
8
mA
1
MHz
2
VD D = 3.3 V
25.00000
7
nH
1
4
pF
1
C IN
Logic Inputs
C OU T
Output pin capacitance
5
pF
1
C INX
X1 & X 2 pins
5
pF
1
T STAB
From V DD Power-Up or deassertion of PD to 1st clock
2.5
ms
1
33
kHz
1
300
us
1
Modulation Frequency
Triangular Modulation
Tdrive_PD
CP U output enable after
PD de-assertion
30
Tfall_ PD
PD fall time of
5
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
VD D
Low-level Output Voltage
VOL
Current sinking at
VOL = 0.4 V
IPU LLU P
S CLK/SDATA
Clock/Data Rise Time
T RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
S CLK/SDATA
Clock/Data Fall Time
T FI2 C
(Min V IH + 0.15) to
(Max VIL - 0.15)
2.7
@ I PUL LUP
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
4
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by desig n and characterization, not 100% tested in production.
Input frequ ency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs.
2
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Electrical Characteristics–CPU 0.7V Current Mode Differential Pair
P ARAMETE R
SYMB OL
CONDITIONS*
MIN
Current Source Output Impedance
Zo
VO = V x
3000
Voltage High
VHigh
VLow
Statistical measu rement on singl e
ended signal
660
Voltage Low
-150
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs)
Vx(abs)
Crossing Voltage (var)
d-Vx
Long Accuracy
ppm
Average period
Absolute min/ma x period
Tperiod
T ab smin /ma x
Measurement on single ended
signal using absolute value.
TYP
MAX
UNITS
NOTES
Ω
1
850
mV
1,3
150
mV
1,3
1150
mV
1
-300
250
mV
1
550
mV
1
140
mV
1
1,2
V ariation of crossing over a ll
edges
see Tperiod min-max values
-100
0
100
ppm
400MHz nomin al
2.4998
2.5000
2.5003
ns
2
400MHz sp rea d
2.4998
2.5128
ns
2
333.33MHz nominal
2.9997
3.0003
ns
2
333.33MHz spread
2.9997
3.0154
ns
2
266.66MHz nominal
3.7496
3.7504
ns
2
266.66MHz spread
3.7496
3.7692
ns
2
200MHz nomin al
4.9995
200MHz sp rea d
4.9995
166.66MHz nominal
5.9994
166.66MHz spread
5.9994
133.33MHz nominal
7.4993
133.33MHz spread
7.4993
100.00MHz nominal
9.9990
3.0000
3.7500
5.0000
5.0005
ns
2
5.0256
ns
2
6.0006
ns
2
6.0307
ns
2
7.5000
7.5008
ns
2
7.5385
ns
2
10.0000
10.0010
ns
2
6.0000
100.00MHz spread
9.9990
10.0513
ns
2
400MHz nominal/spread
2.4148
2.5978
ns
1,2
333.33MHz nominal/spread
2.9147
3.1004
ns
1,2
266.66MHz nominal/spread
3.6646
3.8542
ns
1,2
200MHz nominal/spread
4.9145
5.1106
ns
1,2
166.66MHz nominal/spread
5.9144
6.1157
ns
1,2
133.33MHz nominal/spread
7.4143
7.6235
ns
1,2
100.00MHz nominal/spread
9.9140
10.1363
ns
1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
V OH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-t r
VOL = 0.175V, VOH = 0.525V
V OH = 0.525V VOL = 0.175V
Measure ment from differential
Duty Cycle
dt3
45
wavefrom
Measure ment from differential
Jitter, Cycle to cycle
t jcyc -cyc
wavefrom, CPUCLK
*T A = 0 - 70°C; V DD = 3.3 V +/-5% ; CL =2pF, R S=33.2ohms, R P=49.9ohms, IR EF = 475ohms
Fall Time Variati on
d-t f
125
ps
1
125
ps
1
55
%
1
85
ps
1
1
Guaranteed by desig n and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000MHz
3
I REF = V DD/(3xR R). For R R = 475ohms (1%), I REF = 2.32mA. IOH = 6 x IR EF and V OH = 0.7V @ Z O=50ohms.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
9
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Electrical Characteristics–RMII - 50MHz
P ARAMETE R
SYMB OL
CONDITIONS*
MIN
TYP
MAX
UNITS
NOTES
Long Accuracy
ppm
see Tperiod min-max values
-50
0
50
ppm
1,2
Clock period
Tperiod
VOH
50.00MHz output nominal
I OH = -1 mA
19.990
20.000
20.010
ns
1
Output High Voltage
V
1
Output Low Voltage
VOL
I OL = 1 mA
V
OH @ MIN = 1.0 V
Output High Current
IOH
Output Low Current
I OL
Rise Time
tr
VOL = 0.4 V , VOH = 2.4 V
Fall Time
tf
Duty Cycle
dt1
t skew _3 V50(3 :0)
Group S kew
2.4
0.4
-33
VOH @MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
V
1
mA
1
mA
1
mA
1
38
mA
1
1
3
ns
1
VOH = 2.4 V , VOL = 0.4 V
1
3
ns
1
VT = 1.5 V
35
65
%
1
V T = 1.5 V,
for each group of 4 outputs
200
ps
1
V OL @ MAX = 0.4 V
t skew _3 V50(7 :4)
Jitter, Long Term
tj abs
VT = 1.5 V, 10 ∪sec interva l
500
ps
1
Ji tter, Peak
t jpe ak
VT = 1.5 V
100
ps
1,3
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown i n the termination table (unless otherwise specified)
1
Guaranteed by desig n and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.00MHz
3
1/2 of the peak-to-peak jitte r. (Lg+ + |Lg-|)/2
Electrical Characteristics–33.33MHz
P ARAMETE R
SYMB OL
CONDITIONS*
MIN
TYP
MAX
UNITS
NOTES
Long Accuracy
ppm
see Tperiod min-max values
-1 00
0
100
ppm
1
Clock period
Tperiod
33.33MHz output non-spread
29.970
33.33MHz output non-spread
I OH = -1 mA
29.720
ns
1
1
Output High Voltage
Tabs
VOH
30.030
30.280
ns
Absolute min/ma x period
30.000
30.000
V
1
Output Low Voltage
VOL
I OL = 1 mA
0.4
V
1
Output High Current
IOH
mA
1
V
OH @MIN
= 1.0 V
2.4
-33
VOH @MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
mA
1
mA
1
Output Low Current
I OL
38
mA
1
Rise Time
tr
VOL = 0.4 V , VOH = 2.4 V
0.5
2
ns
1
Fall Time
tf
VOH = 2.4 V , VOL = 0.4 V
0.5
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
t jcyc -cyc
VT = 1.5 V
250
ps
1
V OL @ MAX = 0.4 V
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown i n the termination table (unless otherwise specified)
1
Guaranteed by desig n and characterization, not 100% tested in production.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
10
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Electrical Characteristics–32.768kHz
P ARAMETE R
SYMB OL
CONDITIONS*
MIN
Long Accuracy
ppm
see Tperiod min-max values
-1 00
Clock period
Output High Voltage
Tperiod
VOH
32.768KHz output nominal
I OH = -1 mA
Output Low Voltage
VOL
I OL = 1 mA
Output High Current
IOH
V
OH @ MIN
= 1.0 V
TYP
Output Low Current
I OL
Rise Time
tr
VOL = 0.4 V , VOH = 2.4 V
UNITS
100
ppm
1
us
1
30.518
2.4
0.4
-33
VOH @MAX = 3.135 V
VOL @ MIN = 1.95 V
MAX
-33
1
V
1
V
1
mA
1
mA
1
mA
1
38
mA
1
4
ns
1
1
30
V OL @ MAX = 0.4 V
NOTES
Fall Time
tf
VOH = 2.4 V , VOL = 0.4 V
1
4
ns
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
t jcyc -cyc
VT = 1.5 V
500
ps
1
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown i n the termination table (unless otherwise specified)
1
Guaranteed by desig n and characterization, not 100% tested in production.
Electrical Characteristics–REF - 25MHz
P ARAMETE R
SYMB OL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
-50
Clock period
T pe rio d
25.00MHz output nominal
39.980
Outp ut High Volta ge
VOH
I OH = -1 mA
2.4
Output Low Voltage
V OL
I OL = 1 mA
V
OH @MIN
= 1.0 V
TYP
40.000
MAX
UNITS
Notes
50
ppm
1,2
40.020
ns
2
V
1
V
1
0.4
-29
mA
1
mA
1
mA
1
Output High Current
IOH
Output Low Current
I OL
27
mA
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
1
2
ns
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
2
ns
1
500
ps
1
55
%
1
500
ps
1
VOH @MAX = 3.135 V
VOL @ MIN = 1.95 V
-23
29
V OL @ MAX = 0.4 V
Skew
tsk1
VT = 1.5 V
Duty Cycle
dt1
VT = 1.5 V
Ji tter
t jcyc -cyc
VT = 1.5 V
45
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown i n the termination table (unless otherwise specified)
1
Guaranteed by desig n and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.000MHz
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
11
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
ACK
WR
WRite
ACK
Beginning Byte = N
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
RT
Slave Address
Beginning Byte N
ACK
X Byte
O
O
O
Repeat starT
RD
ReaD
ACK
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
O
O
Read Address
Write Address
*D1(H)
*D0(H)
* By default, SMBADR = 0,
therefore, SMBus WRITE/READ address is D0/D1.
O
X Byte
P
O
O
O
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Please see SMBus Address Selection table on page 2.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
12
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
SMBus Table: CPU Frequency Select and Spread Spectrum Control Register
Pin #
Byte 0
Name
Control Function
Reserved
Reserved
Bit 7
Reserved
Reserved
Bit 6
Reserved
Reserved
Bit 5
DOT96 SS_EN
DOT96 Spread Spectrum Enable
Bit 4
CPU SS_EN
CPU Spread Spectrum Enable
Bit 3
CPU FS2
CPU Freq Select Bit 2
Bit 2
CPU FS1
CPU Freq Select Bit 1
Bit 1
CPU FS0
CPU Freq Select Bit 0
Bit 0
SMBus Table: RMII Output Control Register
Pin #
Byte 1
Name
24
RMII_7 Enable
Bit 7
25
Bit 6
RMII_6 Enable
28
Bit 5
RMII_5 Enable
29
Bit 4
RMII_4 Enable
32
Bit 3
RMII_3 Enable
33
Bit 2
RMII_2 Enable
36
Bit 1
RMII_1 Enable
37
Bit 0
RMII_0 Enable
Type
RW
Rev 0.20
RW
RW
RW
RW
RW
RW
Control Function
RMII_7 Output Control
RMII_6 Output Control
RMII_5 Output Control
RMII_4 Output Control
RMII_3 Output Control
RMII_2 Output Control
RMII_1 Output Control
RMII_0 Output Control
SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register
Pin #
Byte 2
Name
Control Function
7,8
CPUCLK PD Drive Mode
Driven in PD
Bit 7
0
1
Reserved
Reserved
Reserved
Disable
Enable
See Table 1:
CPU Frequency Selection Table
PWD
0
0
0
0
0
0
1
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
Type
RW
0
Driven
1
Hi-Z
PWD
0
Bit 6
3,4
DOT96SS PD Drive Mode
Driven in PD
RW
Driven
Hi-Z
0
Bit
Bit
Bit
Bit
Bit
Bit
22
17
16
13
6
5
33.33MHz Enable
25MHz_1 Enable
25MHz_0 Enable
32.768kHz Enable
CPUCLK Enable
DOT96SS Enable
33.33MHz Output Control
25MHz_1 Output Control
25MHz_0 Output Control
32.768KHz Output Control
CPUCLK Output Control
DOT96SS Output Control
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register
Pin #
Byte 3
Name
Control Function
Reserved
Reserved
Bit 7
Reserved
Reserved
Bit 6
Reserved
Reserved
Bit 5
Reserved
Reserved
Bit 4
Bit 3
DOT96SS FS3
DOT96 Freq Select Bit 3
Bit 2
DOT96SS FS2
DOT96 Freq Select Bit 2
Bit 1
DOT96SS FS1
DOT96 Freq Select Bit 1
DOT96SS FS0
DOT96 Freq Select Bit 0
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: RMII Strength Control Register
Pin #
Byte 4
Name
RMII_7 Str
24
Bit 7
RMII_6 Str
25
Bit 6
RMII_5 Str
28
Bit 5
RMII_4 Str
29
Bit 4
RMII_3 Str
32
Bit 3
RMII_2 Str
33
Bit 2
RMII_1 Str
36
Bit 1
37
RMII_0 Str
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
PWD
0
0
0
0
0
0
0
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Reserved
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
Reserved
Reserved
1
PWD
0
0
1
1
1
1
0
0
5
4
3
2
1
0
Control Function
RMII_7 Strength Control
RMII_6 Strength Control
RMII_5 Strength Control
RMII_4 Strength Control
RMII_3 Strength Control
RMII_2 Strength Control
RMII_1 Strength Control
RMII_0 Strength Control
SMBus Table: 32.768KHz, 25Mhz and 33.33MHz Strength Control Register
Byte 5
Name
Control Function
Pin #
Bit 7
Reserved
Reserved
Bit 6
Reserved
Reserved
22
Bit 5
33.33MHz Str
33.33MHz Strength Control
17
Bit 4
25MHz_1 Str
25MHz_1 Strength Control
16
Bit 3
25MHz_1 Strength Control
25MHz_0 Str
13
Bit 2
32.768kHz Str
32.768kHz Strength Control
Bit 1
Reserved
Reserved
Bit 0
Reserved
Reserved
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
13
Reserved
Reserved
Reserved
Reserved
See Table 2:
DOT Frequency Selection Table
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
SMBus Table: Vendor & Revision ID Register
Pin #
Byte 6
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: Device ID
Byte 7
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
-
PWD
X
X
X
X
0
0
0
1
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
SMBus Table: CPU PLL VCO Frequency Control Register
Pin #
Byte 11
Name
Bit 7
N Div8
Bit 6
N Div 9
Bit 5
M Div5
Bit 4
M Div4
Bit 3
M Div3
Bit 2
M Div2
Bit 1
M Div1
M Div0
Bit 0
0
-
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
0
0
1
0
0
0
1
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
0
0
1
0
0
1
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
0
0
0
0
0
0
0
0
Control Function
PLLs M/N Programming Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
0
Disable
1
Enable
PWD
0
0
0
0
0
0
0
0
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
VENDOR ID
Control Function
Device ID
Control Function
Writing to this register configures how
many bytes will be read back.
Name
SMBus Table: PLLs M/N Programming Enable Register
Byte 10
Name
Pin #
M/N_EN
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
REVISION ID
Name
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0 (LSB)
SMBus Table: Byte Count Register
Pin #
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Reserved
Pin #
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
M Divider Programming bits
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
The decimal representation of M and N
Divier in Byte 11 and 12 will configure
the VCO frequency. Default at power up
= latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
SMBus Table: CPU PLL VCO Frequency Control Register
Pin #
Byte 12
Name
N Div7
Bit 7
N Div6
Bit 6
N Div5
Bit 5
N Div4
Bit 4
N Div3
Bit 3
N Div2
Bit 2
N Div1
Bit 1
N Div0
Bit 0
Control Function
N Divider Programming b(7:0)
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte 13
Name
Control Function
Pin #
SSP7
Bit 7
SSP6
Bit 6
SSP5
Bit 5
Spread Spectrum Programming
SSP4
Bit 4
SSP3
b(7:0)
Bit 3
SSP2
Bit 2
SSP1
Bit 1
Bit 0
SSP0
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte 14
Name
Control Function
Pin #
Reserved
Bit 7
Bit 6
SSP14
Bit 5
SSP13
Bit 4
SSP12
Spread Spectrum Programming
Bit 3
SSP11
b(14:8)
Bit 2
SSP10
Bit 1
SSP9
Bit 0
SSP8
SMBus Table: DOT PLL VCO Frequency Control Register
Pin #
Byte 15
Name
N Div8
Bit 7
N Div9
Bit 6
M Div5
Bit 5
M Div4
Bit 4
M Div3
Bit 3
M Div2
Bit 2
M Div1
Bit 1
M Div0
Bit 0
SMBus Table: DOT PLL VCO Frequency Control Register
Byte 16
Name
Pin #
N Div7
Bit 7
N Div6
Bit 6
N Div5
Bit 5
N Div4
Bit 4
N Div3
Bit 3
N Div2
Bit 2
N Div1
Bit 1
Bit 0
N Div0
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
M Divider Programming bits
Control Function
N Divider Programming b(7:0)
SMBus Table: DOT PLL Spread Spectrum Control Register
Pin #
Byte 17
Name
Control Function
Bit 7
SSP7
Bit 6
SSP6
Bit 5
SSP5
Spread Spectrum Programming
Bit 4
SSP4
b(7:0)
Bit 3
SSP3
Bit 2
SSP2
Bit 1
SSP1
SSP0
Bit 0
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
15
0
1
The decimal representation of M and N
Divier in Byte 11 and 12 will configure
the VCO frequency. Default at power up
= latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
0
1
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
0
1
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
0
1
The decimal representation of M and N
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power up
= Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
0
1
The decimal representation of M and N
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power up
= Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
0
1
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
9FGP202A
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
PWD
0
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
X
X
X
X
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
SMBus Table: DOT PLL Spread Spectrum Control Register
Pin #
Byte 18
Name
Control Function
Reserved
Bit 7
SSP14
Bit 6
SSP13
Bit 5
SSP12
Bit 4
Spread Spectrum Programming
SSP11
Bit 3
b(14:8)
SSP10
Bit 2
SSP9
Bit 1
SSP8
Bit 0
SMBus Table: Reserved
Pin #
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Reserved
Pin #
Byte 20
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Reserved
Pin #
Byte 21
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
PWD
0
X
X
X
X
X
X
X
Name
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
0
0
0
0
0
0
0
0
Name
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
0
0
0
0
0
0
0
0
Name
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
0
0
0
0
0
0
0
0
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
16
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Package Outline and Package Dimensions (40-pin MLF)
Seating Plane
A1
Index Area
N
1
2
(Ref)
ND & NE
Even
(ND-1)x e
(Ref)
L
A3
e
N
Anvil
Singulation
1
(Typ)
If ND & NE
2
are Even
2
E
-- or -Top View
E2
Sawn
Singulation
A
D
0.08 C
E2
(NE-1)x e
(Ref)
2
(Ref)
ND & NE
Odd
b
e
C
Symbol
Millimeters
Min
Max
A
A1
A3
b
e
D x E BASIC
D2 MIN./MAX.
E2 MIN./MAX.
L MIN./MAX.
ND
NE
0.8
1.0
0
0.05
0.25 Reference
0.18
0.3
0.50 BASIC
6.00 x 6.00
2.75
3.00
2.75
3.00
0.3
0.5
10
10
Thermal Base
D2
2
D2
Ordering Information
Part / Order Number
9FGP202AKLF
9FGP202AKLFT
Shipping Packaging
Trays
Tape and Reel
Package
40-pin MLF
40-pin MLF
Temperature
0 to +70°C
0 to +70°C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
17
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Revision History
Rev.
D
Issue Date
7/5/2011
Who
D. Chan
Description
Updated datasheet template
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Page #
18
9FGP202A
REV D 070511
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
SYNTHESIZERS
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Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or
registered trademarks used to identify products or services of their respective owners.
Printed in USA
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