2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
9FGU0231
DATASHEET
Description
Features/Benefits
The 9FGU0231 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 2output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
• LP-HCSL outputs; save 4 resistors compared to standard
•
•
•
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
•
Output Features
•
• 2 - 100MHz Low-Power (LP) HCSL DIF pairs
• 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
•
support
•
Key Specifications
•
•
•
•
•
DIF cycle-to-cycle jitter = 0.8xVDDSMB
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9FGU0231 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
1
2
SYMBOL
Slew rate
Trf
Slew rate matching
ΔTrf
Voltage High
VHIGH
CONDITIONS
MIN
TYP
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
1.1
0.9
2.2
1.7
3
600
735
Voltage Low
VLOW
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
MAX UNITS NOTES
V/ns 1,2,3
3.3
V/ns 1,2,3
2.6
%
20
1,2,4
850
7
mV
-150
-16
150
779
-45
1503
405
12
1150
-300
300
250
550
140
7
7
7
1,2,7
1,5,7
1,6,7
mV
mV
mV
mV
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7
At default SMBus amplitude settings.
Electrical Characteristics–DIF Output Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
tjphPCIeG1
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
tjphPCIeG2
Phase Jitter, PLL Mode
tjphPCIeG3
tjphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
MIN
TYP
MAX
27.7
40
IND.
LIMIT
86
1.0
1.3
3
1.9
2.2
3.1
0.4
0.6
1
0.4
0.6
0.7
UNITS
Notes
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
1,2,3,5
ps
(rms)
1,2,3,5
1,2,3,5
1,2,3,5
1,2,3,5
1
Guaranteed by design and characterization, not 100% tested in production.
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Calculated from Intel-supplied Clock Jitter Tool
5
Applies to all differential outputs
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2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
9FGU0231 DATASHEET
Electrical Characteristics–REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
25 MHz output
Clock period
Tperiod
Rise/Fall Slew Rate
trf1
Byte 3 = 1F, 20% to 80% of VDDREF
0.3
Byte 3 = 5F, 20% to 80% of VDDREF
0.5
Rise/Fall Slew Rate
trf1
Byte 3 = 9F, 20% to 80% of VDDREF
0.77
Rise/Fall Slew Rate
trf1
Byte 3 = DF, 20% to 80% of VDDREF
0.84
Rise/Fall Slew Rate
trf1
Duty Cycle
dt1X
VT = VDD/2 V
45
0
TYP
0
40
0.7
1.0
1.3
1.4
47.1
MAX
1.1
1.6
1.9
2.0
55
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
Notes
1,2
2
1
1,3
1
1
1,4
Duty Cycle Distortion
dtcd
VT = VDD/2 V, when driven by XIN/CLKIN_25 pin
2.0
4
%
1,5
Jitter, cycle to cycle
Noise floor
Noise floor
tjcyc-cyc
tjdBc1k
tjdBc10k
VT = VDD/2 V
1kHz offset
10kHz offset to Nyquist
51.2
-126
-139
250
-105
-110
1,4
1,4
1,4
Jitter, phase
tjphREF
12kHz to 5MHz
1.11
3
ps
dBc
dBc
ps
(rms)
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
2
3
Default SMBus Value
When driven by a crystal.
4
5
X2 should be floating.
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94900
9.99900
10.00000
10.00100
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100
ns
1,2
Clock Periods–Differential Outputs with -0.5% Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94906
9.99906
10.02406
10.02506
10.02607
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107
ns
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
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General SMBus Serial Interface Information
How to Write
•
•
•
•
•
•
•
•
•
•
How to Read
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
WR
ACK
WRite
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
Data Byte Count = X
RT
ACK
Beginning Byte N
RD
ACK
X Byte
O
O
O
Repeat starT
Slave Address
ReaD
ACK
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
X Byte
P
O
Note: Read/Write address is determined by SADR latch.
O
O
O
O
O
Byte N + X - 1
OCTOBER 18, 2016
9
N
Not acknowledge
P
stoP bit
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
9FGU0231 DATASHEET
SMBus Table: Output Enable Register
Byte 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DIF OE1
Bit 2
DIF OE0
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Output Enable
Output Enable
Reserved
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Name
Control Function
SSENRB1
SS Enable Readback Bit1
Bit 7
SSENRB1
SS Enable Readback Bit0
Bit 6
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
SSENSW1
SS Enable Software Ctl Bit1
Bit 4
SSENSW0
SS Enable Software Ctl Bit0
Bit 3
Reserved
Bit 2
AMPLITUDE 1
Bit 1
Controls Output Amplitude
AMPLITUDE 0
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 2
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 1
Reserved
Bit 0
SMBus Table: REF Control Register
Byte 3
Name
Bit 7
REF
Bit 6
Bit 5
REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Control Function
Slew Rate Control
Wake-on-Lan Enable for REF
REF Output Enable
Reserved
Reserved
Reserved
Reserved
Type
0
1
RW
RW
Low/Low
Low/Low
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
Type
0
1
00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
R
RW
SS control locked
Values in B1[4:3]
control SS amount.
RW 1
RW 1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW
RW
00 = 0.55V
10= 0.7V
01 = 0.65V
11 = 0.8V
Type
0
1
RW
RW
Slow Setting
Slow Setting
Fast Setting
Fast Setting
Type
RW
RW
Default
Latch
Latch
0
0
0
1
1
0
Default
1
1
1
1
1
1
1
1
0
1
00 = Slowest
01 = Slow
10 = Fast
11 = Faster
REF does not run in REF runs in Power
RW
Power Down
Down
RW
Low
Enabled
Default
0
1
0
1
1
1
1
1
Byte 4 is reserved and reads back 'hFF'.
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
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9FGU0231 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Revision ID
VENDOR ID
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
R
R
R
R
R
R
R
R
0
A rev = 0000
0001 = IDT
Type
R
R
R
R
R
R
R
R
0
1
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
00010 binary or 02 hex
Type
RW
RW
RW
RW
RW
1
0
1
Writing to this register will configure how
many bytes will be read back, default is
= 8 bytes.
Default
0
0
0
0
0
0
0
1
Default
0
0
0
0
0
0
1
0
Default
0
0
0
0
1
0
0
0
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Load Capacitance (CL)
Drive Level
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
25
Fundamental
±20
MHz
PPM Max
1
1
1
±20
PPM Max
1
0~70
-40~85
50
7
8
0.3
±5
°C
°C
Ω Max
pF Max
pF Max
mW Max
PPM Max
1
2
1
1
1
1
1
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2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
9FGU0231 DATASHEET
Thermal Characteristics
PARAMETER
SYMBOL
CONDITIONS
Thermal Resistance
θJC
θJb
θJA0
θJA1
θJA3
θJA5
Junction to Case
Junction to Base
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
TYP
UNITS NOTES
VALUE
62
°C/W
1
C/W
5.4
°
1
50
°C/W
1
NLG24
C/W
43
°
1
39
°C/W
1
38
°C/W
1
PKG
1
ePad soldered to board
Marking Diagrams
LOT
U31AL
YYWW
LOT
U31AIL
YYWW
Notes:
1. “LOT” is the lot number.
2. “YYWW” is the last two digits of the year and week that the part was assembled.
3. “L” denotes RoHS compliant package.
4. “I” denotes industrial temperature grade.
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
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9FGU0231 DATASHEET
Package Outline and Package Dimensions (NLG24)
Seating Plane
A1
Index Area
N
(Ref)
ND & NE
Even
(ND-1)x e
(Ref)
L
A3
e
N
Anvil
Singulation
1
(Typ)
If ND & NE
2
are Even
2
E
-- or -Top View
E2
Sawn
Singulation
A
(NE-1)x e
(Ref)
2
(Ref)
ND & NE
Odd
D
0.08 C
E2
b
e
C
Symbol
Millimeters
Min
Max
A
A1
A3
b
e
D x E BASIC
D2 MIN./MAX.
E2 MIN./MAX.
L MIN./MAX.
N
ND
0.80
1.00
0
0.05
0.25 Reference
0.18
0.30
0.50 BASIC
4.00 x 4.00
2.3
2.60
2.3
2.60
0.30
0.50
24
6
Thermal Base
D2
2
D2
Ordering Information
Part / Order Number Shipping Packaging
9FGU0231AKLF
Tubes
9FGU0231AKLFT
Tape and Reel
9FGU0231AKILF
Tubes
9FGU0231AKILFT
Tape and Reel
Package
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
OCTOBER 18, 2016
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2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
9FGU0231 DATASHEET
Revision History
Rev.
Issue Date
Intiator
A
9/24/2014
RDW
B
10/18/2016
RDW
Description
1. Updated electrical tables with latest versions for release
2. Updated SMBus nomenclature for consistency with the family
3. Removed references to Suspend Mode. This is replaced by Power
Down with Wake-on-LAN Modes in the current consumption table.
4. Updated GenDes tab for front page consistency
5. All Electrical tables updated with characterization data.
6. Move to final.
Removed IDT crystal part number
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
14
Page #
Various
OCTOBER 18, 2016
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
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