6-Output Very Low-Power PCIe Gen 1-2-3-4
Clock Generator
9FGV0631C
DATASHEET
Description
Features
The 9FGV0631C is a member of IDT's SOC-Friendly 1.8V
very low-power PCIe clock family. The device has 6 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off, and 2 selectable SMBus
addresses.
• LP-HCSL outputs; save 12 resistors compared to standard
Typical Applications
•
•
•
•
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
•
Output Features
•
• 6 100MHz Low-Power (LP) HCSL DIF pairs
• 1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
•
support
•
Key Specifications
•
•
•
•
•
DIF cycle-to-cycle jitter = 0.65xVDDSMB.
2
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
6
JUNE 6, 2019
9FGV0631C DATASHEET
Electrical Characteristics–DIF Low Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Slew rate
Trf
Slew rate matching
ΔTrf
Voltage High
VHIGH
Voltage Low
VLOW
CONDITIONS
MIN
TYP
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
1.8
1.4
2.7
2.1
4
4.4
3.4
20
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
660
793
850
-150
16
150
831
-95
1555
429
12
1150
-300
300
250
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Measurement on single ended signal using
Vmin
absolute value. (Scope averaging off)
Vswing
Scope averaging off
Vcross_abs
Scope averaging off
Scope averaging off
Δ-Vcross
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
MAX UNITS NOTES
550
140
V/ns
V/ns
%
1,2,3
1,2,3
1,2,4
7
mV
7
mV
mV
mV
mV
7
7
1,2,7
1,5,7
1,6,7
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
7
At default SMBus amplitude settings.
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SYMBOL
PARAMETER
CONDITIONS
t jphPCIeG1-CC
PCIe Gen 1
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
t jphPCIeG2-CC
PCIe Gen 2 High Band
Phase Jitter,
1.5MHz
< f < Nyquist (50MHz)
PLL Mode
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 3
t jphPCIeG3-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
PCIe Gen 4
t jphPCIeG4-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
Notes on PCIe Filtered Phase Jitter Table
1
Applies to all differential outputs, guaranteed by design and characterization.
2
Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.
3
Specification
UNITS NOTES
Limit
86
ps (p-p) 1, 2, 3
MIN
TYP
MAX
21
25
35
0.9
0.9
1.1
3
ps
(rms)
1, 2
1.5
1.6
1.9
3.1
ps
(rms)
1, 2
0.3
0.37
0.44
1
0.3
0.37
0.44
0.5
ps
(rms)
ps
(rms)
1, 2
1, 2
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.
JUNE 6, 2019
7
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0631C DATASHEET
Electrical Characteristics–REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Tperiod
25 MHz output
Rise/Fall Slew Rate
t rf1
Byte 3 = 1F, 20% to 80% of VDDREF
0.6
Rise/Fall Slew Rate
trf1
Byte 3 = 5F, 20% to 80% of VDDREF
0.9
Rise/Fall Slew Rate
trf1
Byte 3 = 9F, 20% to 80% of VDDREF
1.1
Rise/Fall Slew Rate
trf1
Byte 3 = DF, 20% to 80% of VDDREF
1.1
Duty Cycle
dt1X
VT = VDD/2 V
45
Duty Cycle Distortion
dtcd
VT = VDD/2 V
0
Jitter, cycle to cycle
t jcyc-cyc
VT = VDD/2 V
Noise floor
tjdBc1k
1kHz offset
Noise floor
tjdBc10k
10kHz offset to Nyquist
Jitter, phase
12kHz to 5MHz
t jphREF
TYP
0
40
1
1.4
1.7
1.8
49.1
2
19.1
-129.8
-143.6
MAX
0.63
1.5
1.6
2.2
2.7
2.9
55
4
250
-105
-115
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
%
ps
dBc
dBc
ps
(rms)
Notes
1,2
2
1
1,3
1
1
1,4
1,5
1,4
1,4
1,4
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3
Default SMBus Value
4
When driven by a crystal.
5
When driven by an external oscillator via the X1 pin, X2 should be floating.
2
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
- ppm
+ ppm
0 ppm
-c2c jitter
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94900
9.99900
10.00000
10.00100
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100
ns
1,2
Clock Periods–Differential Outputs with Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
- ppm
+ ppm
0 ppm
-c2c jitter
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94906
9.99906
10.02406
10.02506
10.02607
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107
ns
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
2
Clock Periods–Single-ended Outputs
1 Clock
SSC OFF
Center
Freq.
MHz
REF
25.000
1us
0.1s
Measurement Window
0.1s
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
39.79880
40.00000
40.00120
39.99880
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
8
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
40.20120
ns
1,2
JUNE 6, 2019
9FGV0631C DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a stop bit
•
•
•
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
WR
ACK
WRite
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
Data Byte Count = X
RT
ACK
Beginning Byte N
RD
ACK
X Byte
O
O
O
Repeat starT
Slave Address
ReaD
ACK
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
X Byte
P
O
O
O
O
O
Note: Read/Write address is latched on SADR pin.
JUNE 6, 2019
O
Byte N + X - 1
9
N
Not acknowledge
P
stoP bit
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0631C DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
DIF OE5
Output Enable
RW
Low/Low
Bit 7
DIF OE4
Output Enable
RW
Low/Low
Bit 6
Reserved
Bit 5
DIF OE3
Output Enable
RW
Low/Low
Bit 4
DIF OE2
Output Enable
RW
Low/Low
Bit 3
DIF OE1
Output Enable
RW
Low/Low
Bit 2
Reserved
Bit 1
DIF OE0
Output Enable
RW
Low/Low
Bit 0
1. A low on these bits will override the OE# pin and force the differential output Low/Low
SMBus Table: SS Readback and Control Register
Byte 1
Name
Control Function
SSENRB1
SS Enable Readback Bit1
Bit 7
SSENRB1
SS Enable Readback Bit0
Bit 6
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
SSENSW1
SS Enable Software Ctl Bit1
Bit 4
SSENSW0
SS Enable Software Ctl Bit0
Bit 3
Reserved
Bit 2
AMPLITUDE 1
Bit 1
Controls Output Amplitude
AMPLITUDE 0
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
Bit 7
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
Bit 6
Reserved
Bit 5
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
Bit 4
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 3
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 2
Reserved
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 0
REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Wake-on-Lan Enable for REF
REF Output Enable
Reserved
Reserved
Reserved
Reserved
Enabled
Enabled
Enabled
Enabled
Type
0
1
00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
R
RW
Values in B1[7:6] Values in B1[4:3]
control SS amount control SS amount.
RW 1
RW 1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW
RW
00 = 0.6V
10= 0.8V
01 = 0.7V
11 = 0.9V
Type
RW
RW
0
Slow Setting
Slow Setting
1
Fast Setting
Fast Setting
RW
RW
RW
Slow Setting
Slow Setting
Slow Setting
Fast Setting
Fast Setting
Fast Setting
RW
Slow Setting
Fast Setting
SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register
Byte 3
Name
Control Function
Type
RW
Bit 7
REF
Slew Rate Control
RW
Bit 6
Bit 5
1
Enabled
Enabled
0
1
00 = Slowest
01 = Slow
10 = Fast
11 = Faster
REF does not run in REF runs in Power
RW
Power Down
Down
RW
Low
Enabled
Default
1
1
1
1
1
1
1
1
Default
Latch
Latch
0
0
0
1
1
0
Default
1
1
1
1
1
1
1
1
Default
0
1
0
1
1
1
1
1
Byte 4 is Reserved
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
10
JUNE 6, 2019
9FGV0631C DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
RID3
Bit 7
RID2
Bit 6
Revision ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
RW
RW
RW
RW
RW
0
1
C rev = 0001
0001 = IDT
0
1
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
000110 binary or 06 hex
0
Default
0
0
0
1
0
0
0
1
Default
0
0
0
0
0
1
1
0
1
Default
0
0
0
0
1
Writing to this register will configure how
0
many bytes will be read back, default is
0
= 8 bytes.
0
Recommended Crystal Characteristics (3225 package)
PARAMETER
Frequency
Resonance Mode
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commercial)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Load Capacitance (CL)
Drive Level
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
JUNE 6, 2019
VALUE
UNITS
NOTES
25
Fundamental
±20
MHz
PPM Max
1
1
1
±20
PPM Max
1
0~70
-40~85
50
7
8
0.3
±5
°C
°C
Ω Max
pF Max
pF Max
mW Max
PPM Max
1
2
1
1
1
1
1
11
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0631C DATASHEET
Thermal Characteristics
PARAMETER
SYMBOL
Thermal Resistance
θJC
θJb
θJA0
θJA1
θJA3
θJA5
CONDITIONS
PKG
Junction to Case
Junction to Base
Junction to Air, still air
NDG40
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
TYP.
42
2.4
39
33
28
27
UNITS
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
NOTES
1
1
1
1
1
1
1
ePad soldered to board
Marking Diagrams
ICS
V0631CIL
YYWW
COO
LOT
ICS
GV0631CL
YYWW
COO
LOT
Notes:
1. Line 2: truncated part number.
2. “I” denotes industrial temperature.
3. “L” denotes RoHS compliant package.
4. “YYWW” is the last two digits of the year and week that the part was assembled.
5. “COO” denotes country of origin.
6. “LOT” is the lot number.
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
12
JUNE 6, 2019
9FGV0631C DATASHEET
Package Outline and Dimensions (5 x 5 mm 40-VFQFPN)
JUNE 6, 2019
13
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0631C DATASHEET
Package Outline and Dimensions (5 x 5 mm 40-VFQFPN), cont.
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
14
JUNE 6, 2019
9FGV0631C DATASHEET
Ordering Information
Part / Order Number Shipping Packaging
9FGV0631CKLF
Trays
9FGV0631CKLFT
Tape and Reel
9FGV0631CKILF
Trays
9FGV0631CKILFT
Tape and Reel
Package
40-pin VFQFPN
40-pin VFQFPN
40-pin VFQFPN
40-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“C” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Issue Date
Description
1. Updated front page text and block diagram.
2. Updated pin out to remove references to VDD Suspend pins. Using the part with collapsible
power supplies did not save power and complicated board design. NO pins were changed.
September 29, 2014 3. Updated SMBus Descriptions
4. Simplified footnote 2 on PPM table.
5. Updated all electrical tables
6. Move to final
October 18, 2016
Removed IDT crystal part number
Updated front page Gendes to reflect the PCIe Gen4 updates.
June 23, 2017
Updated Electrical Characteristics - Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures and added PCIe Gen4 Data
June 6, 2019
Changed Input Current minimum and maximum values from -200/200uA to -20/20uA.
JUNE 6, 2019
15
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
9FGV0631C JUNE 6, 2019
16
©2019 Integrated Device Technology, Inc.
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.