8-Output Very Low-Power PCIe Gen1–4
Clock Generator with Zo = 100ohms
9FGV0841
Datasheet
Description
Features
The 9FGV0841 is a member of IDT's SOC-friendly 1.8V very
low-power PCIe clock family. It has integrated output terminations
providing Zo = 100Ω for direction connection to 100Ω transmission
lines. The device has 8 output enables for clock management, 2
different spread spectrum levels in addition to spread off, and 2
selectable SMBus addresses.
▪ Direct connection to 100Ω transmission lines; saves 32
resistors compared to standard PCIe devices
▪ 62mW typical power consumption; reduced thermal concerns
▪ Outputs can optionally be supplied from any voltage between
1.05V and 1.8V; maximum power savings
▪ OE# pins; support DIF power management
▪ LP-HCSL differential clock outputs; reduced power and board
Typical Applications
▪
▪
▪
▪
▪
▪
space
PCIe Gen1–4 clock generation for Riser Cards
Storage
Networking
JBOD
Communications
Access Points
▪ Programmable slew rate for each output; allows tuning for
various line lengths
▪ Programmable output amplitude; allows tuning for various
application environments
▪ DIF outputs blocked until PLL is locked; clean system start-up
▪ Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
Output Features
▪ External 25MHz crystal; supports tight ppm with 0 ppm
▪ Eight 100MHz Low-Power HCSL (LP-HCSL) DIF pairs with
synthesis error
Zo = 100Ω
▪ Configuration can be accomplished with strapping pins; SMBus
▪ One 1.8V LVCMOS REF output with Wake-On-LAN (WOL)
interface not required for device control
support
▪ 3.3V tolerant SMBus interface works with legacy controllers
▪ Selectable SMBus addresses; multiple devices can easily
Key Specifications
▪
▪
▪
▪
share an SMBus segment
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF phase jitter is PCIe Gen1–4 compliant
REF phase jitter is < 1.5ps RMS
▪ Space saving 6 × 6 mm 48-VFQFPN; minimal board space
▪ Available in Commercial (0° to +70°C), Industrial (-40°C to
+85°C) and Automotive Grade 2 (-40°C to +105°C)
temperature ranges
Block Diagram
vOE(7:0)#
XIN/CLKIN_25
8
REF1.8
OSC
DIF7
X2
DIF6
DIF5
SS Capable PLL
DIF3
vSADR
DIF2
vSS_EN_tri
^CKPWRGD_PD#
DIF4
Control Logic
DIF1
SDATA_3.3
SCLK_3.3
©2021 Renesas Electronics Corporation
DIF0
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9FGV0841 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ITest Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
©2021 Renesas Electronics Corporation
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9FGV0841 Datasheet
Pin Assignments
vOE5#
VDD1.8
VDDIO
GND
DIF6
DIF6#
vOE6#
DIF7
DIF7#
vOE7#
VDDIO
^CKPWRGD_PD#
Figure 1. Pin Assignments for 6 × 6 mm 48-VFQFPN Package – Top View
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri
GNDXTAL
X1_25
X2
VDDXTAL1.8
VDDREF1.8
vSADR/REF1.8
GNDREF
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
9FGV0841
DIF5#
DIF5
vOE4#
DIF4#
DIF4
VDDIO
VDDA1.8
GNDA
vOE3#
DIF3#
DIF3
vOE2#
DIF2#
DIF2
GND
VDDIO
VDD1.8
DIF1#
DIF1
vOE1#
DIF0#
DIF0
vOE0#
VDDIO
13 14 15 16 17 18 19 20 21 22 23 24
6 x 6 mm 48-VFQFPN, 0.4mm pitch
vv prefix indicates internal 60kOhm pull-down resistor
v prefix indicates internal 120kOhm pull-down resistor
^ prefix indicates internal 120kOhm pull-up resistor
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type
Description
Latched select input to select spread spectrum amount at initial power-up:
1 = -0.5% spread, M = -0.25%, 0 = spread off
1
vSS_EN_tri
Latched In
2
GNDXTAL
GND
Ground for XTAL.
3
X1_25
Input
Crystal input, nominally 25.00MHz.
4
X2
Output
Crystal output.
5
VDDXTAL1.8
Power
Power supply for XTAL, nominal 1.8V.
6
VDDREF1.8
Power
VDD for REF output, nominal 1.8V.
7
vSADR/REF1.8
8
GNDREF
GND
Ground pin for the REF outputs.
9
GNDDIG
GND
Ground pin for digital circuitry.
10
SCLK_3.3
Input
Clock pin of SMBus circuitry, 3.3V tolerant.
11
SDATA_3.3
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
12
VDDDIG1.8
Power
1.8V digital power (dirty power).
13
VDDIO
Power
Power supply for differential outputs.
Latched I/O
©2021 Renesas Electronics Corporation
Latch to select SMBus address/1.8V LVCMOS copy of X1/REFIN pin.
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9FGV0841 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
Name
Type
Input
Description
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
14
vOE0#
15
DIF0
Output
Differential true clock output.
16
DIF0#
Output
Differential complementary clock output.
17
vOE1#
Input
18
DIF1
Output
Differential true clock output.
19
DIF1#
Output
Differential complementary clock output.
20
VDD1.8
Power
Power supply, nominal 1.8V.
21
VDDIO
Power
Power supply for differential outputs.
22
GND
GND
Ground pin.
23
DIF2
Output
Differential true clock output.
24
DIF2#
Output
Differential complementary clock output.
25
vOE2#
Input
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26
DIF3
OUT
Differential true clock output.
27
DIF3#
OUT
Differential complementary clock output.
28
vOE3#
Input
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
29
GNDA
GND
Ground pin for the PLL core.
30
VDDA1.8
Power
1.8V power for the PLL core.
31
VDDIO
Power
Power supply for differential outputs.
32
DIF4
Output
Differential true clock output.
33
DIF4#
Output
Differential complementary clock output.
34
vOE4#
Input
35
DIF5
Output
Differential true clock output.
36
DIF5#
Output
Differential complementary clock output.
37
vOE5#
Input
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
38
VDD1.8
Power
Power supply, nominal 1.8V.
39
VDDIO
Power
Power supply for differential outputs.
40
GND
GND
Ground pin.
41
DIF6
Output
Differential true clock output.
42
DIF6#
Output
Differential complementary clock output.
43
vOE6#
Input
44
DIF7
Output
©2021 Renesas Electronics Corporation
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output.
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9FGV0841 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
Name
Type
Description
45
DIF7#
Output
Differential complementary clock output.
46
vOE7#
Input
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
47
VDDIO
Power
Power supply for differential outputs.
48
^CKPWRGD_PD#
Input
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal pull-up resistor.
Power Management
Table 2. Power Management
CKPWRGD_PD#
SMBus OE bit
0
DIFx
REF
OEx#
True Output
Complementary Output
X
X
Low
Low
Hi-Z[a]
1
1
0
Running
Running
Running
1
0
1
Low
Low
Low
[a] REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is Low.
Table 3. SMBus Address Selection
State of SADR on first application of CKPWRGD_PD#
SADR
Address
+ Read/Write Bit
0
1101000
X
1
1101010
X
Table 4. Power Connections
Pin Number
VDD
VDDIO
GND
Description
5
2
XTAL OSC
6
8
REF Power
12
9
Digital (dirty) Power
22, 29, 40
DIF Outputs
29
PLL Analog
20, 38
13, 21, 31, 39, 47
30
©2021 Renesas Electronics Corporation
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9FGV0841 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 9FGV0841 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 5. Absolute Maximum Ratings[a][b][c]
Parameter
Symbol
Supply Voltage
VDDxx
Input Voltage
VIN
Input High Voltage, SMBus
VIHSMB
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection
ESD prot
Conditions
Applies to all VDD pins.
Minimum
Typical
Maximum
Units
-0.5
2.5
V
-0.5
VDD + 0.5V
V
3.6V
V
150
°C
125
°C
SMBus clock and data pins.
-65
Human Body Model.
2000
V
[a] Guaranteed by design and characterization, not 100% tested in production.
[b] Operation under these conditions is neither implied nor guaranteed.
[c] Not to exceed 2.5V.
Thermal Characteristics
Table 6. Thermal Characteristics[a]
Parameter
Thermal Resistance
Symbol
Conditions
Package
Typical Values
Units
θJC
Junction to case.
33
°C/W
θJb
Junction to base.
2.1
°C/W
θJA0
Junction to air, still air.
37
°C/W
θJA1
Junction to air, 1 m/s air flow.
30
°C/W
θJA3
Junction to air, 3 m/s air flow.
27
°C/W
θJA5
Junction to air, 5 m/s air flow.
26
°C/W
NDG48
[a] EPAD soldered to board.
©2021 Renesas Electronics Corporation
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9FGV0841 Datasheet
Electrical Characteristics
TA = TAMB; supply voltages per normal operation conditions. See ITest Loads for loading conditions
Table 7. Common Electrical Characteristics
Parameter
Symbol
Conditions
Supply voltage for core, analog and single-ended
LVCMOS outputs.
Supply Voltage
VDDxx
Output Supply Voltage
VDDIO Supply voltage for differential Low Power outputs.
Commercial range.
Minimum
Typical
Maximum
Units
1.7
1.8
1.9
V
0.9975
1.05–1.8
1.9
V
0
25
70
°C
-40
25
85
°C
VDD + 0.3
V
0.6 VDD
V
0.25 VDD
V
Ambient Operating
Temperature
TAMB
Input High Voltage
VIH
Single-ended inputs, except SMBus.
0.75 VDD
Input Mid Voltage
VIM
Single-ended tri-level inputs ('_tri' suffix).
0.4 VDD
Input Low Voltage
VIL
Single-ended inputs, except SMBus.
-0.3
Output High Voltage
VOH
Single-ended outputs, except SMBus.
IOH = -2mA
VDD-0.45
Output Low Voltage
VOL
Single-ended outputs, except SMBus.
IOL = -2mA
IIN
Single-ended inputs, VIN = GND, V IN
= VDD.
IINP
Single-ended inputs.
VIN = 0 V; Inputs with internal pull-up
resistors.
VIN = VDD; Inputs with internal
pull-down resistors.
IIN
Single-ended inputs, VIN = GND, V IN
= VDD.
IINP
Single-ended inputs.
[b]
VIN = 0 V; Inputs with internal pull-up Automotive
resistors.
VIN = VDD; Inputs with internal
pull-down resistors.
-25
Fin
XTAL, or X1 input.
23
Input Current
Input Frequency
Pin Inductance
[c]
Capacitance[c]
Industrial range.
0.5 VDD
V
0.45
-5
5
Industrial[a]
μA
-20
20
-5
5
μA
25
25
27
MHz
7
nH
5
pF
6
pF
0.6
1.8
ms
Lpin
CIN
Logic Inputs, except DIF_IN.7
V
1.5
COUT
Output pin capacitance.
Clk Stabilization[c][d]
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock.
SS Modulation Frequency[c]
fMOD
Allowable Frequency.
(Triangular Modulation)
30
31.6
33
kHz
1
3
3
clocks
20
300
us
OE# Latency[c][e]
tLATOE#
DIF start after OE# assertion.
DIF stop after OE# deassertion
Tdrive_PD#[c][e]
tDRVPD
DIF output enable after PD# de-assertion.
©2021 Renesas Electronics Corporation
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9FGV0841 Datasheet
Table 7. Common Electrical Characteristics (Cont.)
Parameter
Symbol
Tfall[d]
Trise
[d]
SMBus Input Low Voltage
Conditions
Minimum
5
ns
tR
Rise time of single-ended control inputs.
5
ns
0.6
V
3.6
V
0.4
V
VILSMB
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V.
SMBus Output Low Voltage
VOLSMB At IPULLUP.
SMBus Sink Current
IPULLUP At VOL.
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time[c]
SMBus Operating
Frequency[c]
Units
Fall time of single-ended control inputs.
VIHSMB VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V.
[c]
Maximum
tF
SMBus Input High Voltage[f]
Nominal Bus Voltage
Typical
2.1
4
mA
1.7
VDDSMB
3.6
V
tRSMB
(Max VIL - 0.15V) to (Min VIH + 0.15V).
1000
ns
tFSMB
(Min VIH + 0.15V) to (Max V IL - 0.15V).
300
ns
fMAXSMB Maximum SMBus operating frequency.
400
kHz
[a] 9FGV0841AKLF, 9FGV0841AKLFT, 9FGV0841AKILF, and 9FGV0841AKILFT.
[b] 9FGV0841ANDG2 and 9FGV0841ANDG28.
[c] Guaranteed by design and characterization, not 100% tested in production.
[d] Control input must be monotonic from 20% to 80% of input swing.
[e] Time from deassertion until outputs are > 200mV.
[f] For VDDSMB < 3.3V, VIHSMB > = 0.65 x VDDSMB.
Table 8. DIF Low-Power HCSL (LP-HCSL) Outputs
Parameter
Slew Rate
Symbol
[a][b][c]
Trf
Conditions
Scope averaging on fast setting.
Industrial[d]
Automotive
[e]
Scope averaging on slow setting.
[a][b][f]
Slew Rate Matching
ΔTrf
[g]
VHIGH
Voltage Low[g]
VLOW
Max Voltage[g]
Vmax
Voltage[g]
Vmin
Voltage High
Min
Vswing[a][b][g]
Crossing Voltage
(abs)[a][g][h]
Crossing Voltage (var)[a][g][i]
Minimum
Typical
1.6
2.3
3.5
2.4
3.2
4.2
1.3
1.9
2.9
V/ns
7
20
%
660
784
850
-150
-33
150
816
1150
Slew rate matching, scope averaging on.
Statistical measurement on single-ended signal
using oscilloscope math function (scope averaging
on).
Maximum Units
V/ns
mV
Measurement on single-ended signal using absolute
value (scope averaging off).
-300
-42
Scope averaging off.
300
1634
Vcross_abs Scope averaging off.
250
427
550
mV
12
140
mV
Vswing
Δ-Vcross
Scope averaging off.
mV
mV
[a] Guaranteed by design and characterization, not 100% tested in production.
[b] Measured from differential waveform.
[c] Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a ±150mV window around differential 0V.
[d] 9FGV0841AKLF, 9FGV0841AKLFT, 9FGV0841AKILF, and 9FGV0841AKILFT.
[e] 9FGV0841ANDG2 and 9FGV0841ANDG28.
©2021 Renesas Electronics Corporation
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9FGV0841 Datasheet
[f] Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use
for the edge rate calculations.
[g] At default SMBus amplitude settings.
[h] VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
[i] The total variation of all Vcross measurements in any particular system. Note that this is a subset of VCROSS_min/max (VCROSS absolute)
allowed. The intent is to limit VCROSS induced modulation by setting Δ-VCROSS to be smaller than VCROSS absolute
Table 9. Current Consumption[a]
Parameter
Operating Supply Current
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')[d]
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
Symbol
Conditions
Minimum
Typical
Maximum
Units
6
9
mA
Industrial[b]
12
16
Automotive[c]
12
20
IDDAOP
VDDA, All outputs active at100MHz.
IDDOP
All VDD, except VDDA and VDDIO, All
outputs active at100MHz.
IDDIOOP
VDDIO, All outputs active at100MHz.
28
35
mA
IDDAPD
VDDA, DIF outputs off, REF output running.
0.4
1
mA
IDDPD
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running.
Industrial [b]
5.3
8
Automotive[c]
5.3
12
mA
mA
IDDIOPD
VDDIO, DIF outputs off, REF output running.
0.04
0.1
mA
IDDAPD
VDDA, all outputs off.
0.4
1
mA
IDDPD
All VDD, except VDDA and VDDIO, all outputs off.
0.6
1
mA
0.0005
0.1
mA
Minimum
Typical
Maximum
Units
45
50
55
%
Industrial [c]
43
50
Automotive[d]
43
67
14
50
VDDIO, all outputs off.
IDDIOPD
[a] Guaranteed by design and characterization, not 100% tested in production.
[b] 9FGV0841AKLF, 9FGV0841AKLFT, 9FGV0841AKILF, and 9FGV0841AKILFT.
[c] 9FGV0841ANDG2 and 9FGV0841ANDG28.
[d] This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1).
Table 10. DIF Output Duty Cycle, Jitter, and Skew Characteristics
Parameter
Symbol
Conditions
Duty Cycle [a][b]
tDC
Measured differentially, PLL
Mode.
Skew, Output to Output [a][b]
tsk3
Averaging on, VT = 50%.
Jitter, Cycle to Cycle[a][b]
tjcyc-cyc
ps
ps
[a] Guaranteed by design and characterization, not 100% tested in production.
[b] Measured from differential waveform.
[c] 9FGV0841AKLF, 9FGV0841AKLFT, 9FGV0841AKILF, and 9FGV0841AKILFT.
[d] 9FGV0841ANDG2 and 9FGV0841ANDG28.
©2021 Renesas Electronics Corporation
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August 20, 2021
9FGV0841 Datasheet
Table 11. Filtered Phase Jitter Parameters – PCIe Common Clocked (CC) Architectures
Parameter
Specification
Units
Limits
Symbol
Conditions
Minimum
Typical
Maximum
tjphPCIeG1-CC
PCIe Gen1.
21
25
35
86
ps
(p-p)
1,2,3
PCIe Gen2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5–16MHz, 8–16MHz,
CDR = 5MHz).
0.9
0.9
1.1
3
ps
(rms)
1,2
PCIe Gen2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5–16MHz, 8–16MHz,
CDR = 5MHz).
1.5
1.6
1.9
3.1
ps
(rms)
1,2
tjphPCIeG3-CC
PCIe Gen3
(PLL BW of 2–4MHz, 2–5MHz,
CDR = 10MHz).
0.3
0.37
0.44
1
ps
(rms)
1,2
tjphPCIeG4-CC
PCIe Gen4
(PLL BW of 2–4MHz, 2–5MHz,
CDR = 10MHz).
0.3
0.37
0.44
0.5
ps
(rms)
1,2
tjphPCIeG2-CC
Phase Jitter,
PLL Mode
Notes
Table 12. REF
Parameter
Symbol
Long Accuracy[a][b]
ppm
Clock Period[b]
Rise/Fall Slew Rate
[a]
Rise/Fall Slew Rate
[a][c]
Rise/Fall Slew Rate[a]
Rise/Fall Slew Rate
[a]
Duty Cycle [a][d]
Duty Cycle Distortion
Jitter, Cycle to
[a][e]
Cycle[a][d]
Noise Floor[a][d]
Noise Floor
[a][d]
Jitter, Phase
[a][d]
Tperiod
Conditions
See Tperiod min–max values.
Minimum
Typical
Maximum
0
25MHz output.
Units
ppm
40
ns
trf1
Byte 3 = 1F, 20% to 80% of VDDREF.
0.6
1
1.6
V/ns
trf1
Byte 3 = 5F, 20% to 80% of VDDREF.
0.9
1.4
2.2
V/ns
trf1
Byte 3 = 9F, 20% to 80% of VDDREF.
1.1
1.7
2.7
V/ns
trf1
Byte 3 = DF, 20% to 80% of VDDREF.
1.1
1.8
2.9
V/ns
dt1X
VT = VDD/2 V.
45
49.1
55
%
dtcd
VT = VDD/2 V.
0
2
4
%
tjcyc-cyc
VT = VDD/2 V.
19.1
250
ps
tjdBc1k
1kHz offset.
-129.8
-105
dBc
tjdBc10k
10kHz offset to Nyquist.
-143.6
-115
dBc
tjphREF
12kHz to 5MHz.
0.63
1.5
ps (rms)
[a] Guaranteed by design and characterization, not 100% tested in production.
[b] All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00MHz.
[c] Default SMBus value.
[d] When driven by a crystal.
[e] When driven by an external oscillator via the X1 pin, X2 should be floating.
©2021 Renesas Electronics Corporation
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August 20, 2021
9FGV0841 Datasheet
Clock Periods
Table 13. Clock Periods - Differential Outputs with Spread Spectrum Disabled
Measurement Window
SSC OFF
Center
Frequency
(MHz)
DIF[a] [b]
100.00
1 Clock
1μs
0.1s
0.1s
0.1s
1μs
1 Clock
-c2cjitter
AbsPer
Min
-SSC
Short-Term
Average
Min
-ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2cjitter
AbsPer
Max
9.94900
—
9.99900
10.00000
10.00100
—
10.05100
Units
ns
[a] Guaranteed by design and characterization, not 100% tested in production.
[b] All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 0ppm.
Table 14. Clock Periods - Differential Outputs with Spread Spectrum Enabled
Measurement Window
SSC ON
Center
Frequency
(MHz)
DIF[a][b]
99.75
1 Clock
1μs
0.1s
0.1s
0.1s
1μs
1 Clock
-c2cjitter
AbsPer
Min
-SSC
Short-Term
Average
Min
-ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2cjitter
AbsPer
Max
9.94906
9.99906
10.02406
10.02506
10.02607
10.05107
10.10107
Units
ns
[a] Guaranteed by design and characterization, not 100% tested in production.
[b] All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 0ppm.
©2021 Renesas Electronics Corporation
11
August 20, 2021
9FGV0841 Datasheet
Crystal Characteristics
Table 15. Recommended Crystal Characteristics
Parameter
Value
Units
Frequency
25
MHz
Resonance Mode
Fundamental
–
Frequency Tolerance at 25°C
±20
ppm maximum
Frequency Stability, REF at 25°C Over Operating Temperature Range
±20
ppm maximum
Temperature Range (commercial)
0–70
°C
Temperature Range (industrial)
-40–85
°C
Equivalent Series Resistance (ESR)
50
Ω maximum
Shunt Capacitance (CO)
7
pF maximum
Load Capacitance (CL)
8
pF maximum
Drive Level
0.1
mW maximum
Aging Per Year
±5
ppm maximum
ITest Loads
Figure 2. Low-Power HCSL (LP-HCSL) Differential Output Test Load
5 inches
Rs
Zo = 100ohm
2pF
Rs
2pF
Device
Figure 3. REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
©2021 Renesas Electronics Corporation
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August 20, 2021
9FGV0841 Datasheet
Alternate Terminations
Figure 4. Driving LVDS
3.3V
Driving LVDS
Cc
R7a
R7b
R8a
R8b
Rs
Zo
Cc
Rs
LVDS Clock input
Device
Table 16. Driving LVDS Inputs
Component
Value
Receiver has termination
Receiver does not have termination
R7a, R7b
10kΩ
140Ω
R8a, R8b
5.6kΩ
75Ω
Cc
0.1uF
0.1uF
Vcm
1.2 Volts
1.2 Volts
©2021 Renesas Electronics Corporation
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August 20, 2021
9FGV0841 Datasheet
General SMBus Serial Interface Information
How to Write
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
T
starT bit
Slave Address
WR
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
O
O
O
O
O
O
Byte N + X - 1
ACK
P
stoP bit
Note: SMBus address is latched on SADR pin.
©2021 Renesas Electronics Corporation
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August 20, 2021
9FGV0841 Datasheet
How to Read
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address
WR
WRite
IDT (Slave/Receiver)
ACK
Beginning Byte = N
ACK
RT
RD
Repeat starT
Slave Address
ReaD
ACK
Data Byte Count=X
ACK
Beginning Byte N
O
O
O
X Byte
ACK
O
O
O
Byte N + X - 1
N
P
Not acknowledge
stoP bit
©2021 Renesas Electronics Corporation
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August 20, 2021
9FGV0841 Datasheet
SMBus Table: Output Enable Register
Byte 0
Name[a]
Control Function
Type
0
1
Default
Bit 7
DIF OE7
Output Enable
RW
Low/Low
Enabled
1
Bit 6
DIF OE6
Output Enable
RW
Low/Low
Enabled
1
Bit 5
DIF OE5
Output Enable
RW
Low/Low
Enabled
1
Bit 4
DIF OE4
Output Enable
RW
Low/Low
Enabled
1
Bit 3
DIF OE3
Output Enable
RW
Low/Low
Enabled
1
Bit 2
DIF OE2
Output Enable
RW
Low/Low
Enabled
1
Bit 1
DIF OE1
Output Enable
RW
Low/Low
Enabled
1
Bit 0
DIF OE0
Output Enable
RW
Low/Low
Enabled
1
[a] A low on these bits will override the OE# pin and force the differential output Low/Low.
SMBus Table: SS Readback and Control Register
Byte 1
Name
Control Function
Type
Bit 7
SSENRB1
SS Enable Readback Bit1
R
Bit 6
SSENRB1
SS Enable Readback Bit0
R
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
RW
Bit 4
SSENSW1
SS Enable Software Ctl Bit1
RW[a]
SS Enable Software Ctl Bit0
[a]
Bit 3
SSENSW0
RW
0
1
Default
00' for SS_EN_tri = 0, '01' for SS_EN_tri =
'M', '11 for SS_EN_tri = '1'
Values in B1[7:6]
control SS amount
Values in B1[4:3]
control SS amount.
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
Reserved
Bit 2
Bit 1
AMPLITUDE 1
Bit 0
AMPLITUDE 0
Controls Output Amplitude
Latch
Latch
0
0
0
1
RW
00 = 0.6V
01 = 0.7V
1
RW
10= 0.8V
11 = 0.9V
0
[a] B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Type
0
1
Default
Bit 7
SLEWRATESEL DIF7
Adjust Slew Rate of DIF7
RW
Slow Setting
Fast Setting
1
Bit 6
SLEWRATESEL DIF6
Adjust Slew Rate of DIF6
RW
Slow Setting
Fast Setting
1
Bit 5
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
RW
Slow Setting
Fast Setting
1
Bit 4
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
RW
Slow Setting
Fast Setting
1
Bit 3
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
RW
Slow Setting
Fast Setting
1
Bit 2
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
RW
Slow Setting
Fast Setting
1
Bit 1
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
RW
Slow Setting
Fast Setting
1
Bit 0
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
RW
Slow Setting
Fast Setting
1
©2021 Renesas Electronics Corporation
16
August 20, 2021
9FGV0841 Datasheet
SMBus Table: Nominal VHIGH Amplitude Control / REF Control Register
Byte 3
Name
Control Function
REF
Slew Rate Control
Bit 5
REF Power
Down Function
Bit 4
REF OE
Bit 7
Bit 6
Type
0
1
Default
RW
00 = Slowest
01 = Slow
0
RW
10 = Fast
11 = Faster
1
Wake-on-Lan Enable for REF
RW
REF does not run in Power Down
REF runs in Power Down
0
REF Output Enable
RW
Low
Enabled
1
Bit 3
Reserved
1
Bit 2
Reserved
1
Bit 1
Reserved
1
Bit 0
Reserved
1
Byte 4 is Reserved.
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
Type
0
1
Default
Bit 7
RID3
Bit 6
RID2
Bit 5
RID1
Bit 4
RID0
R
1
Bit 3
VID3
R
0
Bit 2
VID2
Bit 1
VID1
Bit 0
VID0
R
R
Revision ID
R
0
Industrial: 0001 (revision A)
Automotive; 1000 (revision A)
R
VENDOR ID
0
0
0001 = IDT
R
0
0
R
1
SMBus Table: Device Type/Device ID Register
Byte 6
Name
Bit 7
Device Type1
Bit 6
Device Type0
Bit 5
Device ID5
R
0
Bit 4
Device ID4
R
0
Bit 3
Device ID3
Bit 2
Device ID2
Bit 1
Device ID1
R
0
Bit 0
Device ID0
R
0
©2021 Renesas Electronics Corporation
Control Function
Type
R
Device Type
R
R
Device ID
R
17
0
1
Default
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
001000 binary or 08 hex
0
0
1
0
August 20, 2021
9FGV0841 Datasheet
SMBus Table: Revision and Vendor ID Register
Byte 7
Name
Control Function
Type
0
1
Default
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
BC4
RW
Bit 3
BC3
RW
Bit 2
BC2
Bit 1
BC1
RW
Bit 0
BC0
RW
Byte Count Programming
RW
0
Writing to this register will configure
how many bytes will be read back,
default is = 8 bytes.
1
0
0
0
Package Outline Drawings
The package outline drawings are appended at the end of this document and are also accessible from the links below. The package
information is the most current data available and is subject to change without notice or revision of this document.
▪ Commercial and Industrial Devices:
www.idt.com/document/psc/48-vfqfpn-package-outline-drawing-60-x-60-x-090-mm-body-epad-42-x-42-mm-040mm-pitch-ndg48p2
▪ Automotive Devices:
www.idt.com/document/psc/48-vfqfpn-package-outline-drawing-48-vfqfpn-package-outline-drawing-ndg48s1-wettable-flank
Marking Diagrams
Commercial
▪
▪
▪
▪
▪
▪
Industrial
Automotive
Lines 1 and 2: truncated part number
“YYWW” denotes the last digits of the year and work week the part was assembled.
“#” denotes the stepping sequence.
“$” denotes mark code.
“COO” denotes country of origin/
“LOT” denotes the lot number.
©2021 Renesas Electronics Corporation
18
August 20, 2021
9FGV0841 Datasheet
Ordering Information
Orderable Part Number[a][b]
Package
Carrier Type
Temperature
9FGV0841AKLF
6 × 6 mm, 0.4mm pitch 48-VFQFPN
Tray
0 to +70°C
9FGV0841AKLFT
6 × 6 mm, 0.4mm pitch 48-VFQFPN
Reel
0 to +70°C
9FGV0841AKILF
6 × 6 mm, 0.4mm pitch 48-VFQFPN
Tray
-40 to +85°C
9FGV0841AKILFT
6 × 6 mm, 0.4mm pitch 48-VFQFPN
Reel
-40 to +85°C
9FGV0841ANDG2
6 × 6 mm, 0.4mm pitch 48-VFQFPN (wettable flank)
Tray
-40 to +105°C[c]
9FGV0841ANDG28
6 × 6 mm, 0.4mm pitch 48-VFQFPN (wettable flank)
Reel
-40 to +105°C[c]
[a] “LF” indicates Pb-free, RoHS compliant.
[b] “A” is the device revision designator (will not correlate to with the datasheet revision).
[c] AEC-Q100 Grade 2.
Revision History
Revision Date
August 20, 2021
November 26, 2019
Description of Change
Rebranded to Renesas.
Initial release of production datasheet. Key changes include the addition of automotive electrical
characteristics to Table 7 to Table 10; however, no changes were made to industrial-grade parameters.
©2021 Renesas Electronics Corporation
19
August 20, 2021
48-VFQFPN Package Outline Drawing
6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch
NDG48P2, PSC-4212-02, Rev 03, Page 1
© Renesas Electronics Corporation
48-VFQFPN Package Outline Drawing
6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch
NDG48P2, PSC-4212-02, Rev 03, Page 2
Package Revision History
© Renesas Electronics Corporation
Description
Date Created
Rev No.
July 24, 2018
Rev 02 New Format Change QFN to VFQFPN, Recalculate Land Pattern
Feb 25, 2020
Rev 03 Tolerance Format Change
48-VFQFPN, Package Outline Drawing
6.00 x 6.00 x 0.90 mm Body, 0.4mm Pitch, Epad Size 4.10 x 4.10 mm
NDG48S1, Wettable Flank, PSC-4212-04, Rev 01, Page 1
© Renesas Electronics Corporation
48-VFQFPN, Package Outline Drawing
6.00 x 6.00 x 0.90 mm Body, 0.4mm Pitch, Epad Size 4.10 x 4.10 mm
NDG48S1, Wettable Flank, PSC-4212-04, Rev 01, Page 2
Package Revision History
© Renesas Electronics Corporation
Description
Date Created
Rev No.
Aug 27, 2021
Rev 01
Update Dimensions of Wettable Flank & Add Land Pattern Note 3.
May 3, 2019
Rev 00
Initial Release
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