9FGV1001BQ506LTGI

9FGV1001 Low Phase-Noise, Low-Power Programmable PhiClock™ Generator Description Features The 9FGV1001 is a member of IDT's PhiClock™ programmable clock generator family. The 9FGV1001 provides four non-spread spectrum copies of a single output frequency and two copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I2C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components. ▪ ▪ ▪ ▪ Typical Applications ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ HPC Storage 10G/25G Ethernet Fiber Optic Modules SSDs ▪ ▪ ▪ Output Features Datasheet 1.8V–3.3V core VDD and VDDREF Individual 1.8V–3.3V VDDO for each programmable output pair Supports HCSL, LVDS and LVCMOS I/O standards Supports LVPECL and CML logic with easy AC coupling – see application note AN-891 for alternate terminations HCSL utilizes IDT's LP-HCSL technology for improved performance, lower power and higher integration: • Programmable output impedance of 85 or 100Ω On-board OTP supports up to 4 complete configurations Configuration selected via strapping pins or I2C < 125mW at 1.8V, < 230mW at 3.3V with outputs running at 100MHz 4 programmable I2C addresses: D0/D1, D2/D3, D4/D5, D6/D7 read/write Supported by IDT Timing Commander™ software 4 × 4 mm 24-VFQFPN; minimal board space Key Specifications ▪ 4 programmable output pairs plus 2 LVCMOS REF outputs ▪ 1 integer output frequency per configuration ▪ 10MHz–325MHz output frequency (LVDS or LP-HCSL output configuration) ▪ 10MHz–200MHz output frequency (LVCMOS output configuration) ▪ 259fs rms typical phase jitter outputs at 156.25MHz (12kHz– 20MHz) ▪ PCIe Gen1–4 compliant PCIe Clocking Architectures Supported ▪ Common Clocked (CC) ▪ Independent Reference without spread spectrum (SRnS) Block Diagram VDDDp XIN/CLKIN XO OTP_VPP REF1 REF0 VDDREFp OSC INT PLL vSEL_I2C# ^SEL0/SCL ^SEL1/SDA ^OEB ^OEA VDDAp SMBus Engine INT DIV OUT3# OUT3 VDDO3 OUT2# OUT2 VDDO2 OUT1# OUT1 VDDO1 Factory Configuration OUT0# OUT0 VDDO0 Control Logic Internal terminations are available when LP -HCSL output format is selected . EPAD/GND ©2018 Integrated Device Technology, Inc. 1 July 5, 2018 9FGV1001 Datasheet Table 1. OE Mapping OE[B:A] OUT0 OUT1 OUT2 OUT3 REF0 REF1 00 Running Stopped Stopped Stopped Running Running 01 Running Running Stopped Stopped Running Running 10 Running Running Running Stopped Running Running 11 Running Running Running Running Running Running Pin Assignments OUT3 OUT3# VDDO3 VDDAp vREF0_SEL_I2C# VDDREFp Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View 24 23 22 21 20 19 XIN/CLKIN 1 XO 2 18 VDDO2 17 OUT2 9FGV1001 connect EPAD to GND REF1 3 ^SEL0/SCL 4 ^SEL1/SDA 5 16 OUT2# 15 VDDO1 14 OUT1 ^OEA 6 13 OUT1# OUT0 VDDO0 9 10 11 12 OUT0# ^OEB 8 OTP_VPP VDDDp 7 4 × 4 mm 24-VFQFPN, 0.5mm pitch ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor Note: The order of OUT3 is reversed from OUT[0:2] Pin Descriptions Table 2. Pin Descriptions Number Name Type Input Description 1 XIN/CLKIN 2 XO Output Crystal output. 3 REF1 Output LVCMOS reference output. 4 ^SEL0/SCL Input 5 ^SEL1/SDA I/O 6 ^OEA Input ©2018 Integrated Device Technology, Inc. Crystal input or reference clock input. Select pin for internal frequency configurations/I2C clock pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-up. Select pin for internal frequency configurations/I2C data pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-up. Active high input for enabling outputs. This pin has an internal pull-up resistor. 0 = disable outputs, 1 = enable outputs. 2 July 5, 2018 9FGV1001 Datasheet Table 2. Pin Descriptions (Cont.) Number Name Type Description 7 VDDDp Power Digital power. 1.8V to 3.3V. VDDAp and VDDDp should be connected to the same power supply. 8 ^OEB Input Active high input for enabling outputs. This pin has an internal pull-up resistor. 0 = disable outputs, 1 = enable outputs. 9 OTP_VPP Power Voltage for programming OTP. During normal operation, this pin should be connected to the same power rail as VDDD. 10 OUT0# Output Complementary output clock 0. 11 OUT0 Output Output clock 0. 12 VDDO0 Power Power supply for output 0. 13 OUT1# Output Complementary output clock 1. 14 OUT1 Output Output clock 1. 15 VDDO1 Power Power supply for output 1. 16 OUT2# Output Complementary output clock 2. 17 OUT2 Output Output clock 2. 18 VDDO2 Power Power supply for output 2. 19 OUT3 Output Output clock 3. 20 OUT3# Output Complementary output clock 3. 21 VDDO3 Power Power supply for output 3. 22 VDDAp Power Power supply for analog circuits. VDDAp and VDDDp should be connected to the same power supply. Programmable for nominal voltages of 1.8V, 2.5V or 3.3V. Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the state of the I2C pins. After power-up, the pin acts as an LVCMOS reference output. This pin Latched has an internal pull-down. I/O 1 = SEL0/SEL1. 0 = SCL/SDA. 23 vREF0_SEL_I2C# 24 VDDREFp Power Power supply for REF0 and REF1 and the internal XO. Programmable to 1.8V, 2.5V or 3.3V. 25 EPAD GND Connect to ground. Note: Unused outputs can be programmed off and left floating. VDDREF and VDDO0 have to be connected. ©2018 Integrated Device Technology, Inc. 3 July 5, 2018 9FGV1001 Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 9FGV1001 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3. Absolute Maximum Ratings Parameter Rating Supply Voltage, VDDA, VDDD, VDDO 3.465V Storage Temperature, TSTG -65°C to 150°C ESD Human Body Model 2000V Junction Temperature 125°C Inputs XIN/CLKIN 0V to 1.2V voltage swing Other Inputs -0.5V to VDDD Outputs Outputs, VDDO (LVCMOS) -0.5V to VDDO + 0.5V Outputs, IO (SDA) 10mA Thermal Characteristics Table 4. Thermal Characteristics Parameter Thermal Resistance (devices with external crystal) 1 Symbol Conditions Package Typical Values Units Notes θJC Junction to case. 52 °C/W 1 θJb Junction to base. 2.3 °C/W 1 θJA0 Junction to air, still air. 44 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 37 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 33 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 32 °C/W 1 NBG24 EPAD soldered to board. ©2018 Integrated Device Technology, Inc. 4 July 5, 2018 9FGV1001 Datasheet Recommended Operating Conditions Table 5. Recommended Operating Conditions Symbol Minimum Typical Power supply voltage for supporting 1.8V outputs. 1.71 1.8 1.89 V Power supply voltage for supporting 2.5V outputs. 2.375 2.5 2.625 V Power supply voltage for supporting 3.3V outputs. 3.135 3.3 3.465 V VDDD Power supply voltage for core logic functions. 1.71 3.465 V VDDA Analog power supply voltage. Use filtered analog power supply if available. 1.71 3.465 V TA Operating temperature, ambient. -40 85 °C CL Maximum load capacitance (3.3V LVCMOS only). 15 pF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic). 5 ms VDDOx Parameter Maximum Units 0.05 Electrical Characteristics VDDx = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Table 6. Common Electrical Characteristics Parameter Input Frequency Output Frequency Symbol fIN fOUT Conditions Minimum Typical Maximum Units Notes Crystal input frequency. 8 50 MHz 1 CLKIN input frequency. 1 240 MHz 5 Differential clock output (LVDS/LP-HCSL). 10 325 MHz Single-ended clock output (LVCMOS). 10 200 MHz 2600 MHz VCO Frequency fVCO VCO operating frequency range. 2400 Loop Bandwidth fBW Input frequency = 25MHz. 0.06 0.9 MHz Input High Voltage VIH SEL[1:0]. 0.7 x VDDD VDDD + 0.3 V Input Low Voltage VIL SEL[1:0]. GND - 0.3 0.8 V Input High Voltage VIH REF/SEL_I2C#. 0.65 x VDDREF VDDREF + 0.3 V Input Low Voltage VIL REF/SEL_I2C#. -0.3 0.4 V Input High Voltage VIH XIN/CLKIN. 0.8 1.2 V Input Low Voltage VIL XIN/CLKIN. -0.3 0.4 V 300 ns 3 7 pF Input Rise/Fall Time TR/TF 2500 SEL1/SDA, SEL0/SCL. Input Capacitance CIN SEL[1:0]. Internal Pull-up Resistor RUP SEL[1:0] at 25°C. 200 237 300 kΩ REF/SEL_I2C#. 200 237 300 kΩ Internal Pull-down Resistor RDOWN ©2018 Integrated Device Technology, Inc. 5 July 5, 2018 9FGV1001 Datasheet Table 6. Common Electrical Characteristics (Cont.) Parameter Symbol Programmable Capacitance at XIN and XO (XIN in parallel with XO) CL XIN/CLKIN, XO. 0 Input Duty Cycle t2 CLKIN, measured at VDDREF/2. 40 LVCMOS, fOUT > 156.25MHz. Output Duty Cycle t3 Clock Jitter t6 Conditions Minimum Typical Maximum Units 8 pF 50 60 % 40 50 60 % LVCMOS, fOUT < 156.25MHz. 45 50 55 % LVDS, LP-HCSL outputs. 45 50.3 55 % Notes Cycle-to-cycle jitter (peak-to-peak). See “Test Frequencies for Jitter Measurements in Common Electrical Characteristics” for configurations. 28 ps 4 Reference clock RMS phase jitter (12kHz to 5MHz integration range). See “Test Frequencies for Jitter Measurements in Common Electrical Characteristics” for configurations. 338 fs rms 4 OUTx RMS phase jitter (12kHz to 20MHz integration range) differential output. See “Test Frequencies for Jitter Measurements in Common Electrical Characteristics” for configurations. 259 fs rms 4 105 ps Output Skew t7 Skew between the same frequencies, with outputs using the same driver format. Lock Time t8 PLL lock time from power-up. 1 Practical lower frequency is determined by loop filter settings. 2 Includes loading the configuration bits from OTP to registers. 5 3 Actual PLL lock time depends on the loop configuration. 4 Actual jitter is configuration dependent. These values are representative of what the device can achieve. 5 Input doubler off. Maximum input frequency with input doubler on is 160MHz. 10 ms 2,3 Table 7. Test Frequencies for Jitter Measurements in Common Electrical Characteristics Table Device 9FGV1001 XIN/CLKIN OUT0 OUT1 OUT2 50 156.25 50 100 1 This configuration used for 12kHz–20MHz phase jitter measurement. 2 This configuration used for PCIe filtered phase jitter measurements. 3 Outputs configured as LP-HCSL or LVDS with REF output off unless noted. ©2018 Integrated Device Technology, Inc. 6 OUT3 Unit MHZ Notes 1,3 2,3 July 5, 2018 9FGV1001 Datasheet Table 8. LVCMOS Output Electrical Characteristics Parameter Symbol Slew Rate SR Conditions Minimum Typical Maximum 3.3V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 2.5 3.7 4.6 2.5V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 1.5 2.4 4.6 1.8V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 0.8 1.7 3.5 Units Notes V/ns IOH = -15mA at 3.3V. Output High Voltage VOH IOH = -12mA at 2.5V. 0.8 x VDDO VDDO V 0.22 0.4 V IOH = -8mA at 1.8V. IOL = 15mA at 3.3V. Output Low Voltage VOL IOL = 12mA at 2.5V. IOL = 8mA at 1.8V. Output Leakage Current (OUT[0:1]) IOZDD Programmable outputs, tri-state, VDDO = 3.465V. 0 5 μA Output Leakage Current (REF) IOZDD REF outputs, tri-state, VDDO = 3.465V. 0 5 μA CMOS Output Driver Impedance ROUT TA = 25°C. 17 Ω Table 9. LVDS Output Electrical Characteristics Parameter Symbol Minimum Typical Maximum Units Differential Output Voltage for the TRUE Binary State VOT (+) 247 328 454 mV Differential Output Voltage for the FALSE Binary State VOT (-) -454 -332 -247 mV Change in VOT between Complementary Output States ΔVOT 50 mV Output Common Mode Voltage (Offset Voltage) at 3.3V +5% & 2.5V +5% VOS 1.125 1.19 1.55 V Output Common Mode Voltage (Offset Voltage) at 1.8V +5% VOS 0.8 0.86 0.95 V Change in VOS between Complementary Output States ΔVOS 0 50 mV Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD IOS 6 12 mA Differential Outputs Short Circuit Current, VOUT+ = VOUT- IOSD 3 12 mA Rise Times Tested at 20% – 80% TR 257 400 ps Fall Times Tested at 80% – 20% TF 287 400 ps ©2018 Integrated Device Technology, Inc. 7 Notes July 5, 2018 9FGV1001 Datasheet Table 10. Low-Power (LP) Push-Pull HCSL Differential Outputs VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol Slew Rate TR/F Slew Rate Matching ΔTR/F Conditions Scope averaging on. Crossing Voltage (abs) VCROSS Scope averaging off. Crossing Voltage (var) ΔVCROSS Scope averaging off. Minimum Typical Maximum Units Notes 1 2.5 4 V/ns 2,3,16 9 20 % 1,14,16 424 550 mV 1,4,5,16 16 140 mV 1,4,9,16 250 Voltage High VHIGH 660 785 850 mV 1 Voltage Low VLOW -150 13 150 mV 1 Absolute Maximum Voltage VMAX 808 1150 mV 1,7,15 Absolute Minimum Voltage VMIN mV 1,8,15 -300 -54 1 Measured from single-ended waveform. 2 Measured from differential waveform. 3 Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. 4 Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. 5 Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. 7 Defined as the maximum instantaneous voltage including overshoot. 8 Defined as the minimum instantaneous voltage including undershoot. 9 Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum allowed variance in VCROSS for any particular system. 10 Refer to section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information regarding ppm considerations. 11 System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL = 2pF. 12 T STABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to droop back into the VRB ±100mV differential range. 13 ppm refers to parts per million and is a DC absolute period accuracy specification. 1 ppm is 1/1,000,000th of 100.000000MHz exactly or 100Hz. For 300ppm, then we have an error budget of 100Hz/ppm × 300 ppm = 30kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±300 ppm applies to systems that do not employ spread spectrum clocking, or that use common clock source. For systems employing spread spectrum clocking, there is an additional 2,500 ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 ppm. 14 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of REFCLK+ should be compared to the fall edge rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. 15 At default amplitude settings. 16 Guaranteed by design and characterization. ©2018 Integrated Device Technology, Inc. 8 July 5, 2018 9FGV1001 Datasheet Table 11. Filtered Phase Jitter Parameters – PCIe Common Clocked (CC) Architectures TAMB = over the specified operating range. Supply Voltages per normal operation conditions; see Test Loads for loading conditions. Parameter Industry Limits Units Notes 18 86 ps (p-p) 1,2,3 0.1 0.14 3 ps (rms) 1,2 PCIe Gen2 High Band 1.5MHz < f < Nyquist (50MHz) (PLL BW of 5–16MHz, 8–16MHz, CDR = 5MHz). 1.1 1.5 3.1 ps (rms) 1,2 tjphPCIeG3-CC PCIe Gen3 (PLL BW of 2–4MHz, 2–5MHz, CDR = 10MHz). 0.27 0.37 1 ps (rms) 1,2 tjphPCIeG4-CC PCIe Gen4 (PLL BW of 2–4MHz, 2–5MHz, CDR = 10MHz). 0.27 0.37 0.5 ps (rms) 1,2 Symbol Conditions tjphPCIeG1-CC PCIe Gen1. 11 PCIe Gen2 Low Band 10kHz < f < 1.5MHz (PLL BW of 5–16MHz, 8–16MHz, CDR = 5MHz). tjphPCIeG2-CC PCIe Phase Jitter Minimum Typical Maximum Table 12. Filtered Phase Jitter Parameters – PCIe Independent Reference (IR) Architectures TAMB = over the specified operating range. Supply Voltages per normal operation conditions; see Test Loads for loading conditions. Parameter PCIe Phase Jitter Symbol Conditions Minimum tjphPCIeG2-SRIS PCIe Gen2 (PLL BW of 16MHz, CDR = 5MHz). 1.1 tjphPCIeG3-SRIS PCIe Gen3 (PLL BW of 2–4MHz, CDR = 10MHz). 0.28 Industry Limits Units Notes 1.34 2 ps (rms) 1,4,5 0.39 0.7 ps (rms) 1,4,5 Typical Maximum Notes for PCIe Filtered Phase Jitter Parameters tables: 1 Applies to all differential outputs, guaranteed by design and characterization. 2 Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisig.com for latest specifications. 3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12. 4 IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock architectures. 5 According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates. ©2018 Integrated Device Technology, Inc. 9 July 5, 2018 9FGV1001 Datasheet Table 13. Current Consumption VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol Conditions Minimum Typical Maximum Units Notes VDDREF Supply Current IDDREF 25MHz REFCLK. 4 7 mA Core Supply Current IDDCORE 2500MHz VCO, 25MHz REFCLK. 23 31 mA 3 LVDS, 325MHz. 20 26 mA 2 LP-HCSL, 100MHz. 18 24 mA 2 LVCMOS, 50MHz. 15 20 mA 1,2 LVCMOS, 200MHz. 24 39 mA 1,2 LVDS, 325MHz. 7 11 mA 2 LP-HCSL, 100MHz. 6 10 mA 2 LVCMOS, 50MHz. 4 7 mA 1,2 LVCMOS, 200MHz. 13 25 mA 1,2 Programmable outputs in HCSL mode, B37[6,0] = 0. 9 13 mA 2 Programmable outputs in LVDS mode, B37[6,0] = 0. 24 31 mA 2 Programmable outputs in LVCMOS1 mode, B37[6,0] = 0. 4 7 mA 2 Output Buffer Supply Current (VDDO2) Output Buffer Supply Current (VDDO0, VDDO1, VDDO3–per output) Total Power Down Current IDDOx IDDOx IDDPD 1 Single CMOS driver active for each output pair. 2 See Test Loads for details. 3 IDDCORE = IDDA + IDDDIG. ©2018 Integrated Device Technology, Inc. 10 July 5, 2018 9FGV1001 Datasheet I2C Bus Characteristics Table 14. I2C Bus DC Characteristics Parameter Symbol Conditions Minimum Input High Level VIH — 0.7 x VDDD Input Low Level VIL — VHYS — 0.05 x VDDD Input Leakage Current IIN — -1 Output Low Voltage VOL Hysteresis of Inputs Typical Maximum Units V 0.3 x VDDD V V IOL = 3mA. 30 μA 0.4 V Maximum Units 400 kHz Table 15. I2C Bus AC Characteristics Parameter Symbol Conditions Minimum FSCLK — 10 tBUF — 1.3 μs Setup Time, START tSU:START — 0.6 μs Hold Time, START tHD:START — 0.6 μs Setup Time, Data Input (SDA) tSU:DATA — 0.1 μs Hold Time, Data Input (SDA) tHD:DATA — 0 μs Output Data Valid from Clock tOVD — 0.9 μs Capacitive Load for Each Bus Line CB — 400 pF Rise Time, Data and Clock (SDA, SCL) tR — 20 + 0.1 x CB 300 ns Fall Time, Data and Clock (SDA, SCL) tF — 20 + 0.1 x CB 300 ns High Time, Clock (SCL) tHIGH — 0.6 μs Low Time, Clock (SCL) tLOW — 1.3 μs tSU:STOP — 0.6 μs Serial Clock Frequency (SCL) Bus free time between STOP and START Setup Time, STOP Typical Note: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. ©2018 Integrated Device Technology, Inc. 11 July 5, 2018 9FGV1001 Datasheet Crystal Characteristics Table 16. Recommended Crystal Characteristics Parameter Value Units Frequency 8–50 MHz Resonance Mode Fundamental – Frequency Tolerance at 25°C ±20 ppm maximum Frequency Stability, REF at 25°C Over Operating Temperature Range ±20 ppm maximum Temperature Range (commercial) 0–70 °C Temperature Range (industrial) -40–85 °C Equivalent Series Resistance (ESR) 50 Ω maximum Shunt Capacitance (CO) 7 pF maximum Load Capacitance (CL) 8 pF maximum Drive Level 0.1 mW maximum Aging per year ±5 ppm maximum ©2018 Integrated Device Technology, Inc. 12 July 5, 2018 9FGV1001 Datasheet Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-075-mm-body-05mm-pitch-epad-26-x-26-mm-nbnbg24p2 Marking Diagram 1. Line 1 and 2: truncated part number 2. “#” denotes stepping number. 9FGV100 1BnnnGI #YWW**$ 3. “YWW” denotes the last digits of the year and week the part was assembled. 4. “**” denotes lot number. 5. “$” denotes mark code. Ordering Information Orderable Part Number Package Carrier Type Temperature 9FGV1001BnnnNBGI 4 × 4 mm, 0.5mm pitch 24-VFQFPN Tray -40 to +85°C 9FGV1001BnnnNBGI8 4 × 4 mm, 0.5mm pitch 24-VFQFPN Reel -40 to +85°C “G” indicates RoHS 6.6 compliance. “nnn” are decimal digits indicating a specific configuration. Revision History Revision Date Description of Change July 5, 2018 Removed “120kOhm” text from pin assignment notes. March 28, 2018 Updated pin 23 descriptions and Output Features on front page. February 6, 2018 Updated pin 23 descriptions. January 31, 2018 ▪ Updated drive level parameter in Crystal Characteristics table. ▪ Updated Package Outline Drawings text and added hyperlink to document. October 5, 2017 Initial release. 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All rights reserved. ©2018 Integrated Device Technology, Inc. 13 July 5, 2018 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm NB/NBG24P2, PSC-4313-02, Rev 01, Page 1 TOP VIEW BOTTOM VIEW SIDE VIEW 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm NB/NBG24P2, PSC-4313-02, Rev 01, Page 2 Package Revision History Description Date Created Rev No. Jan 24, 2018 Rev 01 Change QFN to VFQFPN and New Format May 11, 2016 Rev 00 Initial Release IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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All rights reserved. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Renesas Electronics: 9FGV1001A000NBGI 9FGV1001A000NBGI8 9FGV1001B001NBGI 9FGV1001B001NBGI8 9FGV1001B002NBGI 9FGV1001B002NBGI8 9FGV1001B003NBGI 9FGV1001B003NBGI8 9FGV1001B004NBGI 9FGV1001B004NBGI8 9FGV1001BQ505LTGI8 9FGV1001BQ506LTGI 9FGV1001BQ500LTGI 9FGV1001BQ505LTGI 9FGV1001BQ506LTGI8 9FGV1001BQ500LTGI8 9FGV1001BQ507LTGI 9FGV1001BQ507LTGI8 9FGV1001BQ508LTGI 9FGV1001BQ508LTGI8