Low Phase-Noise, Low-Power
Programmable PhiClock™
Generators
Description
Features
The 9FGV1001C / 9FGV1005C are members of the Renesas
PhiClock™ programmable clock generator family. The devices are
optimized for low phase noise in non-spread spectrum
applications such as Ethernet or PCI Express. Four user-defined
configurations may be selected via two hardware select pins or
two I2C bits, allowing easy software selection of the desired
configuration.
▪
▪
▪
▪
▪ Supports LVPECL and CML logic with easy AC coupling. See
application note AN-891 for alternate terminations
▪
▪
▪
▪
▪
▪
▪
High-performance Computing (HPC)
Enterprise Storage including eSSDs
10G / 25G / 100G Ethernet
Data Center Accelerators
Multiple XO replacement
PCIe Clocking Architectures
▪ Common Clocked (CC)
▪ Independent Reference without spread spectrum (SRnS)
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
Internal crystal load capacitors
< 125mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1001C)
< 100mW at 1.8V, LP-HCSL outputs at 100MHz (9FGV1005C)
4 programmable I2C addresses: D0, D2, D4, D6
Easily configured with Renesas Timing Commander™ software
or Web Configuration tool
▪ 4 × 4 mm 24-VFQFPN (9FGV1001)
▪ 3 × 3 mm 16-LGA (9FGV1005)
▪ Integrated crystal option available
Output Features
▪
▪
▪
▪
▪
1.8V to 3.3V power supplies
Individual 1.8V to 3.3V VDDO for each output pair
Supports HCSL, LVDS and LVCMOS I/O standards
HCSL utilizes Renesas’ LP-HCSL technology for improved
performance, lower power and higher integration:
• Programmable output impedance of 85Ω or 100Ω
Typical Applications
▪
▪
▪
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9FGV1001C / 9FGV1005C
Datasheet
9FGV1001: 4 programmable output pairs plus 2 REF outputs
9FGV1005: 2 programmable output pairs plus 1 REF output
1 integer output frequency per configuration
1MHz–325MHz differential outputs
1MHz–200MHz single-ended outputs
Key Specifications
▪ 261fs RMS 12kHz–20MHz typical phase jitter at 156.25M Hz
▪ PCIe Gen5 jitter (CC) < 0.08ps RMS
▪ PCIe Gen5 jitter (SRNS) < 0.07ps RMS
Block Diagram
VDDREFp
9FGV1001
REF1
vREF0_SEL_I2C#
Consult factory if design requires REF1.
XIN/CLKIN
XO
OSC
9FGV1001CQ and
9FGV1005CQ integrate the
crystal
INT
PLL
vSEL0/SCL
vSEL1/SDA
9FGV1001
^OEB
^OEA
©2020 Renesas Electronics Corporation
SMBus
Engine
INT
DIV
Factory
Configuration
Control
Logic
1
Prog.
Output
OUT3#
OUT3
VDDO3
Prog.
Output
OUT2#
OUT2
VDDO2
Prog.
Output
OUT1#
OUT1
VDDO1
Prog.
Output
OUT0#
OUT0
VDDO0
9FGV1001
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
9FGV1001 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
9FGV1005 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Standard Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
©2020 Renesas Electronics Corporation
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9FGV1001C / 9FGV1005C Datasheet
9FGV1001 Pin Assignments and Descriptions
24 23 22 21 20 19
OUT3
OUT3#
VDDO3
VDDAp
8
9
16 OUT2#
15 VDDO1
14 OUT1
13 OUT1#
10 11 12
VDDO0
7
OUT0
vSEL1/SDA 5
^OEA 6
OUT0#
14 OUT1
13 OUT1#
18 VDDO2
17 OUT2
9FGV1001CQ
Connect
EPAD to GND
OTP_VPP
REF1 3
vSEL0/SCL 4
VDDO0
OUT0
^OEB
16 OUT2#
15 VDDO1
9 10 11 12
OUT0#
8
OTP_VPP
7
VDDDp
vSEL1/SDA 5
^OEA 6
NC 1
NC 2
^OEB
9FGV1001C
Connect
EPAD to GND
REF1 3
vSEL0/SCL 4
24 23 22 21 20 19
18 VDDO2
17 OUT2
VDDDp
XIN/CLKIN 1
XO 2
vREF0_SEL_I2C#
VDDREFp
OUT3
OUT3#
VDDO3
VDDAp
VDDREFp
vREF0_SEL_I2C#
Figure 1. Pin Assignments for 9FGV1001C 4 x 4 mm 24-VFQFPN and 24-LGA Packages – Top View
4 × 4 mm 24-LGA, 0.5mm pitch
4 × 4 mm 24-VFQFPN, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
Table 1. 9FGV1001C Pin Descriptions[a]
Number
Name
Type
Description
1[b]
XIN/CLKIN
2[b]
XO
Output
Crystal output.
3
REF1
Output
LVCMOS reference output.
4
vSEL0/SCL
Input
Select pin for internal frequency configurations/I2C clock pin. Function is determined by state of
SEL_I2C# upon power-up. This pin has an internal pull-down.
5
vSEL1/SDA
I/O
Select pin for internal frequency configurations/I2C data pin. Function is determined by state of
SEL_I2C# upon power-up. This pin has an internal pull-down.
6
^OEA
Input
Active high input for enabling outputs. This pin has an internal pull-up resistor.
0 = disable outputs, 1 = enable outputs.
7
VDDDp
Power
Digital power. Connect to 1.8V, 2.5V or 3.3V.
8
^OEB
Input
Active high input for enabling outputs. This pin has an internal pull-up resistor.
0 = disable outputs, 1 = enable outputs.
9
OTP_VPP
Power
Voltage for programming OTP. During normal operation, this pin should be connected to the
same power rail as VDDD.
10
OUT0#
Output
Complementary output clock 0.
11
OUT0
Output
Output clock 0.
12
VDDO0
Power
Power supply for output 0.
13
OUT1#
Output
Complementary output clock 1.
Input
©2020 Renesas Electronics Corporation
Crystal input or reference clock input.
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 1. 9FGV1001C Pin Descriptions[a] (Cont.)
Number
Name
Type
Description
14
OUT1
Output
Output clock 1.
15
VDDO1
Power
Power supply for output 1.
16
OUT2#
Output
Complementary output clock 2.
17
OUT2
Output
Output clock 2.
18
VDDO2
Power
Power supply for output 2.
19
OUT3
Output
Output clock 3.
20
OUT3#
Output
Complementary output clock 3.
21
VDDO3
Power
Power supply for output 3.
22
VDDAp
Power
Analog power. Connect to same voltage as VDDDp, with proper filtering.
Latched
I/O
Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the state of
the I2C pins. After power-up, the pin acts as an LVCMOS reference output. This pin has an
internal pull-down.
1 = SEL0/SEL1.
0 = SCL/SDA.
23
vREF0_SEL_I2C#
24
VDDREFp
Power
Power supply for REF outputs and the internal XO. Nominal voltages are 1.8V, 2.5V or 3.3V.
25
EPAD
GND
Connect to ground.
[a] Unused outputs can be programmed off and left floating. Output supplies VDDREF and VDDO2 have to be connected. If OUT0 is used, VDDO1 must
also be connected.
[b] These pins are 'No Connect' on 9FGV1001CQ integrated quartz versions and should have no stubs.
Table 2. 9FGV1001 OE Mapping
OE[B:A]
OUT0
OUT1
OUT2
OUT3
REF0
REF1
00
Running
Stopped
Stopped
Stopped
Running
Running
01
Running
Running
Stopped
Stopped
Running
Running
10
Running
Running
Running
Stopped
Running
Running
11
Running
Running
Running
Running
Running
Running
©2020 Renesas Electronics Corporation
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
9FGV1005 Pin Assignments and Descriptions
16 15 14 13
8
OUT0#
OUT0
VDDO1
VDDAp
9FGV1005CQ
10 NC
9 VDDO0
vSEL0/SCL 3
vSEL1/SDA 4
EPAD = GND
16-LGA 3 x 3 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
12 OUT1
11 OUT1#
10 NC
9 VDDO0
5
6
7
8
OUT0
7
NC 2
OUT0#
6
NC 1
OTP_VPP
5
OTP_VPP
vSEL0/SCL 3
vSEL1/SDA 4
EPAD = GND
VDDDp
XO 2
9FGV1005C
16 15 14 13
12 OUT1
11 OUT1#
VDDDp
XIN/CLKIN 1
vREF0_SEL_I2C#
VDDREFp
VDDO1
VDDAp
VDDREFp
vREF0_SEL_I2C#
Figure 2. Pin Assignments for 9FGV1005C 3 x 3 mm 16-LGA Package – Top View
16-LGA 3 x 3 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
Table 3. 9FGV1005C Pin Descriptions[a]
Number
1[b]
2
[b]
Name
XIN/CLKIN
XO
Type
Input
Output
Description
Crystal input or reference clock input.
Crystal output.
vSEL0/SCL
Input
Select pin for internal frequency configurations/I2C Clock pin. Function is determined by
state of SEL_I2C# upon power-up. This pin has an internal pull-down.
4
vSEL1/SDA
I/O
Select pin for internal frequency configurations/I2C Data pin. Function is determined by
state of SEL_I2C# upon power-up. This pin has an internal pull-down.
5
VDDDp
Power
Digital power. Connect to 1.8V, 2.5V or 3.3V.
OTP_VPP
Power
Voltage for programming OTP. During normal operation, this pin should be connected to the
same power rail as VDDD.
7
OUT0#
Output
Complementary output clock 0.
8
OUT0
Output
Output clock 0.
9
VDDO0
Power
Power supply for output 0.
10
NC
11
OUT1#
Output
Complementary output clock 1.
12
OUT1
Output
Output clock 1.
13
VDDO1
Power
Power supply for output 1.
14
VDDAp
Power
Analog power. Connect to same voltage as VDDDp, with proper filtering.
3
6
N/A
©2020 Renesas Electronics Corporation
No connection.
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 3. 9FGV1005C Pin Descriptions[a] (Cont.)
Number
Name
Type
Description
Latched
I/O
Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the
state of the I2C pins. After power-up, the pin acts as an LVCMOS reference output. This pin
has an internal pull-down.
1 = SEL0/SEL1.
0 = SCL/SDA.
15
vREF0_SEL_I2C#
16
VDDREFp
Power
Power supply for REF outputs and the internal XO. Nominal voltages are 1.8V, 2.5V or
3.3V.
17
EPAD
GND
Connect to ground.
[a] Unused outputs can be programmed off and left floating. Output supplies VDDREF and VDDO1 have to be connected. This means that if only one
output is to be used, it must be OUT1. If OUT0 is used, pin 10 must be connected. They may share the same power filter.
[b] These pins are 'No Connect' on 9FGV1005CQ integrated quartz version and should have no stubs.
©2020 Renesas Electronics Corporation
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Phase Noise Plots
Figure 3. 9FGV1001C Phase Noise Plot, 3.3V, 25°C
Figure 4. 9FGV1005C Phase Noise Plot, 3.3V, 25°C
©2020 Renesas Electronics Corporation
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 9FGV1001C / 9FGV1005C at absolute maximum ratings is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
Table 4. Absolute Maximum Ratings
Parameter
Rating
Supply Voltage, V DDA, VDDD, VDDO
3.9V
Storage Temperature, T STG
-65°C to 150°C
ESD Human Body Model
2000V
Junction Temperature
125°C
Inputs
XIN/CLKIN
0V to 1.2V voltage swing
Other Inputs
-0.5V to VDDD
Outputs
Outputs, VDDO (LVCMOS)
-0.5V to VDDO + 0.5V
Outputs, IO (SDA)
10mA
Recommended Operating Conditions
Table 5. Recommended Operating Conditions[a]
Symbol
Minimum
Typical
Maximum
Units
Power supply voltage for supporting 1.8V outputs.
1.71
1.8
1.89
V
Power supply voltage for supporting 2.5V outputs.
2.375
2.5
2.625
V
Power supply voltage for supporting 3.3V outputs.
3.135
3.3
3.465
V
VDDD
Power supply voltage for core logic functions.
1.71
–
3.465
V
VDDA
Analog power supply voltage. Use filtered analog power supply if
available.
1.71
–
3.465
V
TA
Operating temperature, ambient.
-40
–
85
°C
CL
Maximum load capacitance (3.3V LVCMOS only).
–
–
15
pF
tPU
Power-up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic).
0.05
–
5
ms
VDDOx
Parameter
[a] All electrical characteristics are specified over these conditions unless noted.
©2020 Renesas Electronics Corporation
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Electrical Characteristics
Table 6. Common Electrical Characteristics
Symbol
fIN
Parameter
Input Frequency
Conditions
Minimum
Typical
Maximum
Units
Crystal input frequency [a].
8
–
50
MHz
[b].
1
–
240
MHz
Differential clock output
(LVDS/LP-HCSL).
1
–
325
MHz
Single-ended clock output (LVCMOS).
1
–
200
MHz
CLKIN input frequency
fOUT
Output Frequency
fVCO
VCO Frequency
VCO operating frequency range.
2400
2500
2600
MHz
fBW
Loop Bandwidth
Input frequency = 25MHz.
0.06
–
0.9
MHz
VIH
Input High Voltage
SEL[1:0].
0.7 x VDDD
–
VDDD + 0.3
V
VIL
Input Low Voltage
SEL[1:0].
GND - 0.3
–
0.8
V
VIH
Input High Voltage
REF/SEL_I2C#.
0.65 x VDDREF
–
VDDREF + 0.3
V
VIL
Input Low Voltage
REF/SEL_I2C#.
-0.3
–
0.4
V
VIH
Input High Voltage
XIN/CLKIN.
0.8
–
1.2
V
VIL
Input Low Voltage
XIN/CLKIN.
-0.3
–
0.4
V
OEA, OEB (when present).
–
–
10
SEL1/SDA, SEL0/SCL.
–
–
300
SEL[1:0].
–
3
7
pF
TR/TF
Input Rise/Fall Time
ns
CIN
Input Capacitance
RUP
Internal Pull-up Resistor
200
237
300
kΩ
Internal Pull-down Resistor
200
237
300
kΩ
8
pF
RDOWN
CL
Programmable Capacitance at
XIN and XO (XIN in parallel with
XO)
XIN/CLKIN, XO.
0
t2
Input Duty Cycle
CLKIN, measured at V DDREF/2.
40
50
60
%
LVCMOS, fOUT > 156.25MHz.
40
50
60
%
LVCMOS, fOUT < 156.25MHz.
45
50
55
%
LVDS, LP-HCSL outputs.
45
50.2
55
%
Cycle-to-cycle jitter (Peak-to-Peak), See
Test Frequencies for Jitter
Measurements for configurations.
–
28
–
ps
Reference clock RMS phase jitter
(12kHz to 20MHz integration range).
See Test Frequencies for Jitter
Measurements for configurations.
–
338
–
fs
rms
OUTx RMS phase jitter(12kHz to 20MHz
integration range) differential output.
See Test Frequencies for Jitter
Measurements for configurations.
–
261
–
fs
rms
t3
t6
Output Duty Cycle
Clock Jitter (9FGV1001)[c]
©2020 Renesas Electronics Corporation
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 6. Common Electrical Characteristics (Cont.)
Symbol
Parameter
Clock Jitter (9FGV1005)[c]
t6
t7
Output Skew
t8a
t8b
Lock Time [d] [e]
Conditions
Minimum
Typical
Maximum
Units
Cycle-to-cycle jitter (Peak-to-Peak). See
Test Frequencies for Jitter
Measurements for configurations.
–
30
–
ps
Reference clock RMS phase jitter
(12kHz to 5MHz integration range). See
Test Frequencies for Jitter
Measurements for configurations.
–
357
–
fs
rms
OUTx RMS phase jitter(12kHz to 20MHz
integration range) differential output.
See Test Frequencies for Jitter
Measurements for configurations.
–
284
–
fs
rms
All outputs using the same driver format
and VDDO voltage. (9FGV1001).
–
105
135
All outputs using the same driver format
and VDDO voltage. (9FGV1005).
–
37
50
PLL outputs valid from V DDs > 1.5V.
–
5
10
REF outputs valid from VDDs > 1.5V.
–
5
11
ps
ms
[a] Practical lower frequency is determined by loop filter settings.
[b] Input doubler off. Maximum input frequency with input doubler on is 160MHz.
[c] Actual jitter is configuration dependent. These values are representative of what the device can achieve.
[d] Includes loading the configuration bits from OTP to registers.
[e] Actual PLL output valid time depends on the loop configuration.
Table 7. Test Frequencies for Jitter Measurements
XIN/CLKIN
OUT0
50
OUT1
OUT2
OUT3
Unit
156.25 [a] [b]
MHZ
100 [a] [c] [d]
MHZ
[a] Outputs configured as LP-HCSL or LVDS with REF output off unless noted.
[b] This configuration used for 12kHz-20MHz OUT phase jitter measurement. REF off, SSC off.
[c] This configuration used for 12kHz-20MHz REF phase jitter measurement, SSC Off.
[d] This configuration used for PCIe RefClk phase jitter measurements.
©2020 Renesas Electronics Corporation
10
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 8. PCIe Refclk Phase Jitter[a]
[b] [c]
Conditions
Minimum
Typical
Maximum
Specification
Limits
Units
PCIe Gen1 (2.5 GT/s)
–
2.35
4.84
86
ps (p-p)
PCIe Gen2 Hi Band (5.0 GT/s)
–
0.13
0.22
3
ps (RMS)
PCIe Gen2 Lo Band (5.0 GT/s)
–
0.05
0.08
3.1
ps (RMS)
PCIe Gen3 (8.0 GT/s) [d]
–
0.07
0.12
1
ps (RMS)
tjphPCIeG4-CC
PCIe Gen4 (16.0 GT/s) [d] [e]
–
0.07
0.12
0.5
ps (RMS)
tjphPCIeG5-CC
PCIe Gen5 (32.0 GT/s) [d] [f]
–
0.03
0.05
0.15
ps (RMS)
tjphPCIeG1-IR
PCIe Gen1 (2.5 GT/s)
–
0.24
0.34
N/A
ps (RMS)
tjphPCIeG2-IR
PCIe Gen2 (5.0 GT/s)
–
0.18
0.28
N/A
ps (RMS)
PCIe Gen3 (8.0 GT/s)
–
0.05
0.08
N/A
ps (RMS)
PCIe Gen4 (16.0 GT/s)
–
0.05
0.08
N/A
ps (RMS)
PCIe Gen5 (32.0 GT/s)
–
0.04
0.07
N/A
ps (RMS)
Symbol
Parameter
tjphPCIeG1-CC
tjphPCIeG2-CC
tjphPCIeG3-CC
tjphPCIeG3-IR
tjphPCIeG4-IR
PCIe Phase Jitter
(Common Clocked
Architecture)
PCIe Phase Jitter
(IR Architecture) [g]
tjphPCIeG5-IR
[a] See Test Loads for details.
[b] The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads
section of the data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table. Equipment
noise is removed from all measurements.
[c] Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample
rate of 20GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no
extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and
integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency)
below the Nyquist frequency. For PNA measurements for the 2.5GT/s data rate, the RMS jitter is converted to peak to peak jitter using a
multiplication factor of 8.83.
[d] SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC
content.
[e] Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system.
[f] Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system.
[g] The PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate IR jitter values, however, it does not provide
specification limits, hence the “N/A” in the Limit column. IR values are informative only. In general, a clock operating in an IR system must be
twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by Ö2.
And additional consideration is the value for which to divide by 2. The conservative approach is to divide the CC ref clock jitter limits, and the
case can be made for dividing the CC channel simulation values by 2, if the ref clock is close to the clock input. An example for Gen4 is as
follows: A rule-of-thumb IR limit would be either 0.5ps RMS/2 = 0.35ps RMS, or 0.7ps RMS/2 = 0.5ps RMS, depending on the distance
between the clock generator and the Tx or Rx clock input.
Table 9. Low-Power (LP) HCSL Differential Output Electrical Characteristics[a]
Symbol
Parameter
TR/F
Slew Rate
ΔTR/F
Slew Rate Matching
VCROSS
Crossing Voltage (abs)
©2020 Renesas Electronics Corporation
Conditions
Scope averaging on. [b] [c]
[d] [e]
Scope averaging
off.[d] [e] [f]
11
Minimum
Typical
Maximum
Units
1.25
2.5
4
V/ns
–
9
20
%
250
424
550
mV
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 9. Low-Power (LP) HCSL Differential Output Electrical Characteristics[a] (Cont.)
Symbol
ΔVCROSS
Parameter
Crossing Voltage (var)
TPERIOD_AVG Average Clock Period Accuracy
Conditions
Minimum
Typical
Maximum
Units
–
16
140
mV
Outputs set to 100MHz for PCIe
applications. SSC off.[b] [h] [i] [j]
-100
0
+100
660
808
1150
mV
-300
-54
150
mV
Scope averaging off.[d] [e] [g]
VMAX
Absolute Maximum Voltage
Includes 300mV of overshoot (Vovs).[d] [k] [l]
VMIN
Absolute Minimum Voltage
[m]
Includes -300mV of undershoot (Vuds). [d] [l]
[a] System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single
ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe
can be used for differential measurements.See Test Loads for details.
[b] Measured from differential waveform.
[c] Measured from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
[d] Measured from single-ended waveform.
[e] Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the
median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations. The rise edge rate of REFCLK+ should be compared to the fall edge rate of REFCLK-; the
maximum allowed difference should not exceed 20% of the slowest edge rate.
[f] Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
[g] Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum allowed variance in VCROSS
for any particular system.
[h] Refer to Section 8.6 of the PCI Express Base Specification, Revision 5.0 for information regarding PPM considerations.
[i] PCIe Gen1 through Gen4 specify ±300ppm frequency tolerances. PCIe Gen5 specifies ±100ppm frequency tolerances and the 9FGV100x devices
already meet this.
[j] “ppm” refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly or 100Hz.
For 100ppm, then we have an error budget of 100Hz/ppm × 100ppm = 10kHz. The period is to be measured with a frequency counter with
measurement window set to 100ms or greater. The ±100ppm applies to systems that do not employ Spread Spectrum clocking, or that use
common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500ppm nominal shift in maximum period
resulting from the 0.5% down spread resulting in a maximum average period specification of +2,600ppm for Common Clock architectures.
Separate Reference Clock architectures may have a lower allowed spread percentage.
[k] Defined as the maximum instantaneous voltage including overshoot.
[l] At default amplitude settings.
[m] Defined as the minimum instantaneous voltage including undershoot.
©2020 Renesas Electronics Corporation
12
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 10. 9FGV1001C Current Consumption[a]
Symbol
Parameter
IDDREF
VDDREF Supply Current
IDDCORE
Core Supply Current
[b]
Output Buffer Supply Current
VDDO2 (includes output divider)
IDDOx
Output Buffer Supply Current
(VDDO0, VDDO1, VDDO3 – per output)
Conditions
Minimum
Typical
Maximum
50MHz REFCLK.
–
4
6
2500MHz VCO, 50MHz REFCLK.
–
23
29
LVDS, 325MHz.
–
19
24
–
16
20
–
15
19
LVCMOS, 200MHz [c].
–
24
37
LVDS, 325MHz.
–
7
10
LP-HCSL, 100MHz.
–
6
8
LVCMOS, 50MHz [c].
–
4
7
–
13
24
Programmable outputs, HCSL
mode, B37[0] = 0.
–
9
12
Programmable outputs in LVDS
mode, B37[0] = 0.
–
24
30
Programmable outputs in
LVCMOS1 mode, B37[0] = 0.
–
4
7
LP-HCSL, 100MHz.
LVCMOS, 50MHz
[c].
LVCMOS, 200MHz
IDDPD
Total Power Down Current [b]
[c].
Units
mA
[a] See Test Loads for details.
[b] IDDCORE = IDDA+ IDDDIG.
[c] Single CMOS driver active for each output pair.
©2020 Renesas Electronics Corporation
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 11. 9FGV1005C Current Consumption
Symbol
[a]
Parameter
IDDREF
VDDREF Supply Current
IDDCORE
Core Supply Current
Conditions
[b]
Minimum
Typical
Maximum
50MHz REFCLK.
–
5
8
2500MHz VCO, 50MHz REFCLK.
–
24
30
LVDS, 325MHz.
–
22
27
–
17
23
–
15
19
LVCMOS, 200MHz [c].
–
25
39
LVDS, 325MHz.
–
8
11
LP-HCSL.
–
6
9
–
4
7
–
13
25
Programmable outputs in HCSL
mode, B37[0] = 0.
–
7
10
Programmable outputs in LVDS
mode, B37[0] = 0.
–
16
20
Programmable outputs in
LVCMOS1 mode, B37[0] = 0.
–
5
7
LP-HCSL, 100MHz.
Output Buffer Supply Current
VDDO1 (includes output divider)
LVCMOS, 50MHz
IDDOx
Output Buffer Supply Current – VDDO0
[c].
LVCMOS, 50MHz [c].
LVCMOS, 200MHz
IDDPD
Total Power Down Current[b]
[c].
Units
mA
[a] See Test Loads for details.
[b] IDDCORE = IDDA + IDDD + IDDAO.
[c] Single CMOS driver active for each output pair.
Table 12. LVCMOS Output Electrical Characteristics[a]
Symbol
SR
Parameter
Slew Rate
Conditions
Minimum
Typical
Maximum
Units
3.3V ±5%, 20% to 80% of VDDO (output
load = 4.7pF).
2.6
3.7
4.7
2.5V ±5%, 20% to 80% of VDDO (output
load = 4.7pF).
1.5
2.4
4.7
1.8V ±5%, 20% to 80% of VDDO (output
load = 4.7pF).
1.0
1.7
3.2
0.8 x VDDO
–
VDDO
V
0.22
0.4
V
V/ns
IOH = -15mA at 3.3V.
VOH
Output High Voltage
IOH = -12mA at 2.5V.
IOH = -8mA at 1.8V.
VOL
Output Low Voltage
IOL = 15mA at 3.3V.
–
IOL = 12mA at 2.5V.
–
IOL = 8mA at 1.8V.
–
IOZDD
Output Leakage Current
Outputs, tri-stated,
VDDO, VDDREF = 3.465V.
–
0
5
μA
ROUT
CMOS Output Driver Impedance
TA = 25°C.
–
17
–
Ω
[a] See Test Loads for details.
©2020 Renesas Electronics Corporation
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October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 13. LVDS Output Electrical Characteristics[a]
Symbol
Parameter
Minimum
Typical
Maximum
Units
VOT (+)
Differential Output Voltage for the TRUE Binary State
247
328
454
mV
VOT (-)
Differential Output Voltage for the FALSE Binary State
-454
-332
-247
mV
ΔVOT
Change in VOT between Complementary Output States
–
–
50
mV
VOS
Output Common Mode Voltage (Offset Voltage) at 3.3V +5% and 2.5V +5%
1.125
1.19
1.55
V
VOS
Output Common Mode Voltage (Offset Voltage) at 1.8V +5%
0.8
0.86
0.95
V
ΔVOS
Change in VOS between Complementary Output States
–
0
50
mV
IOS
Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD
–
6
12
mA
IOSD
Differential Outputs Short Circuit Current, VOUT+ = VOUT-
–
3
12
mA
TR
Rise Times Tested at 20%–80%
–
257
375
ps
TF
Fall Times Tested at 80%–20%
–
287
375
ps
[a] See Test Loads for details.
I2C Bus Characteristics
Table 14. I2C Bus DC Characteristics
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Level
–
0.7 x VDDD
–
–
V
VIL
Input Low Level
–
–
–
0.3 x VDDD
V
Hysteresis of Inputs
–
0.05 x VDDD
–
–
V
IIN
Input Leakage Current
–
-1
–
30
μA
VOL
Output Low Voltage
IOL = 3mA.
–
–
0.4
V
VHYS
Table 15. I2C Bus AC Characteristics[a]
Symbol
Conditions
Minimum
Typical
Maximum
Units
Serial Clock Frequency (SCL)
–
10
–
400
kHz
Bus Free Time between STOP and START
–
1.3
–
μs
tSU:START
Setup Time, START
–
0.6
–
μs
tHD:START
Hold Time, START
–
0.6
–
μs
tSU:DATA
Setup Time, Data Input (SDA)
–
0.1
–
μs
tHD:DATA
Hold Time, Data Input (SDA)
–
0
–
μs
tOVD
Output Data Valid from Clock
–
–
–
0.9
μs
CB
Capacitive Load for Each Bus Line
–
–
–
400
pF
tR
Rise Time, Data and Clock (SDA, SCL)
–
20 + 0.1 x CB
–
300
ns
tF
Fall Time, Data and Clock (SDA, SCL)
–
20 + 0.1 x CB
–
300
ns
FSCLK
tBUF
Parameter
©2020 Renesas Electronics Corporation
15
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 15. I2C Bus AC Characteristics[a] (Cont.)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
tHIGH
HIGH Time, Clock (SCL)
–
0.6
–
–
μs
tLOW
LOW Time, Clock (SCL)
–
1.3
–
–
μs
Setup Time, STOP
–
0.6
–
–
μs
tSU:STOP
[a] A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
Test Loads
Figure 5. LVCMOS AC/DC Test Load
Test
Point
L
Zo
Rs
CL
Rs
Zo
L
CL
33Ω
50Ω
5 inches
4.7pF
Figure 6. LP-HCSL AC/DC Test Load
(Standard PCIe source-terminated test load)
Rs
CL
L
Test
Points
Differential Zo
CL
Rs
Rs
Zo
L
CL
Internal
100Ω
5 inches
2pF
Internal
85Ω
5 inches
2pF
©2020 Renesas Electronics Corporation
16
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Figure 7. LVDS AC/DC Test Load
L
Differential Zo
100ohm
Rs
Zo
L
CL
N/A
100Ω
5 inches
N/A
Test
Points
Figure 8. Test Setup for PCIe Measurement Using a Phase Noise Analyzer
SMA
Connectors
L
CK+
0.1uF
CK-
50
Rs
Zo
L
CL
Internal
100Ω
5 inches
N/A
©2020 Renesas Electronics Corporation
Coax
Cables
Balun
Zo (differential)
DUT
Phase Noise Analyzer
17
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Crystal Characteristics
Table 16. Recommended Crystal Characteristics
Parameter
Value
Units
Frequency
8–50
MHz
Resonance Mode
Fundamental
–
Frequency Tolerance at 25°C
±20
ppm maximum
Frequency Stability, REF at 25°C Over Operating Temperature Range
±20
ppm maximum
Temperature Range (commercial)
0–70
°C
Temperature Range (industrial)
-40 to 85
°C
Equivalent Series Resistance (ESR)
50
Ω maximum
Shunt Capacitance (CO)
7
pF maximum
Load Capacitance (CL)
8
pF maximum
Drive Level
0.1
mW maximum
Aging Per Year
±5
ppm maximum
Package Outline Drawings
Are accessible from the links below. The package information is the most current data available and is subject to change without notice or
revision of this document.
9FGV1001C:
www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-075-mm-body-05mm-pitch-epad-26-x-26-mm-nbnbg24p2
www.idt.com/document/psc/24-lga-package-outline-drawing-40-x-40-x-140-mm-body-05mm-pitch-ltg24t2
9FGV1005C:
www.idt.com/document/psc/16-lga-package-outline-drawing-30-x-30-x-110-mm-body-05mm-pitch-ltg16p1
©2020 Renesas Electronics Corporation
18
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Thermal Characteristics
Table 17. Thermal Resistance
Parameter
Thermal Resistance
(devices with external crystal)
Thermal Resistance Q-series
(devices with internal crystal)
[a]
Symbol
Conditions
Package
Typical Values
θJC
Junction to case.
52
θJb
Junction to base.
2.3
θJA0
Junction to air, still air.
θJA1
Junction to air, 1 m/s air flow.
θJA3
Junction to air, 3 m/s air flow.
33
θJA5
Junction to air, 5 m/s air flow.
32
θJC
Junction to case.
66
θJb
Junction to base.
5.1
θJA0
Junction to air, still air.
θJA1
Junction to air, 1 m/s air flow.
θJA3
Junction to air, 3 m/s air flow.
51
θJA5
Junction to air, 5 m/s air flow.
49
θJC
Junction to case.
57.3
θJb
Junction to base.
24.3
θJA0
Junction to air, still air.
θJA1
Junction to air, 1 m/s air flow.
θJA3
Junction to air, 3 m/s air flow.
69.9
θJA5
Junction to air, 5 m/s air flow.
67.3
θJC
Junction to case.
82.1
θJb
Junction to base.
42.3
θJA0
Junction to air, still air.
θJA1
Junction to air, 1 m/s air flow.
87.1
θJA3
Junction to air, 3 m/s air flow.
83.3
NBG24
LTG16
LTG24
LTG16
Units
44
37
63
56
°C/W
79.8
73.9
93.6
[a] EPAD soldered to board.
©2020 Renesas Electronics Corporation
19
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Marking Diagrams
Figure 9. 9FGV1001C Marking Diagrams
▪ Lines 1 and 2: truncated part number:
9FGV100
1CnnnGI
#YWW**$
• “nnn” denotes the decimal digits indicating a specific configuration.
• “aa” denotes the alphanumeric digits indicating a specific Q5 configuration.
1001C
Q5aaI
YWW**$
▪ Line 3:
• “#” denotes the stepping number.
• “YWW” denotes the last digits of the year and week the part was assembled.
• “**” denotes the lot sequence; “$” denotes the mark code.
Figure 10. 9FGV1005C Marking Diagrams
▪ Line 1: truncated part number
5Cnnn
YWW$
XXX
• “nnn” denotes the decimal digits indicating a specific configuration.
• “aa” denotes the alphanumeric digits indicating a specific Q5 configuration.
5CQ5aa
YWW$
XXX
▪ Line 2: “YWW” denotes the last digits of the year and week the part was
assembled; “$” denotes mark code.
▪ Line 3: “XXX” denotes the last three characters of the lot number.
Standard Configurations
Table 18. 9FGV1001C / 9FGV1005C Standard Configurations
Supply Voltage–all
pins (V)
Output Impedance
(ohms)
Number of PCIe
Clock Outputs
4
3.3
100
2
4
1.8
100
2
XTAL Frequency
(MHz)
Orderable Part Number
(Bulk)
Orderable Part Number
(Tape and Reel)
25 – external
9FGV1001C001NBGI
9FGV1001C001NBGI8
50 – internal
9FGV1001CQ505LTGI
9FGV1001CQ505LTGI8
25 – external
9FGV1005C001LTGI
9FGV1005C001LTGI8
50 – internal
9FGV1005CQ505LTGI
9FGV1005CQ505LTGI8
25 – external
9FGV1001C002NBGI
9FGV1001C002NBGI8
50 – internal
9FGV1001CQ506LTGI
9FGV1001CQ506LTGI8
25 – external
9FGV1005C002LTGI
9FGV1005C002LTGI8
50 – internal
9FGV1005CQ506LTGI
9FGV1005CQ506LTGI8
Table 19. Common Features of 9FGV1001C / 9FGV1005C Standard Configurations
These common features are collaborative with Table 18.
Configuration
Output Frequency (MHz)
0
50
1
100
2
125
3
156.25
©2020 Renesas Electronics Corporation
20
Output Type
Ref Outputs
LP-HCSL
OFF
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Table 20. 9FGV1001C / 9FGV1005C Standard Configurations (with 39.0625MHz crystal frequency)
Supply
Voltage–all pins
(V)
Output Impedance
(ohms)
3.3
100
1.8
100
Number of PCIe
Clock Outputs
XTAL Frequency
(MHz)
Orderable Part Number
(Bulk)
Orderable Part Number
(Tape and Reel)
4
39.0625 – external
9FGV1001C011NBGI
9FGV1001C011NBGI8
2
39.0625 – external
9FGV1005C011LTGI
9FGV1005C011LTGI8
4
39.0625 – external
9FGV1001C012NBGI
9FGV1001C012NBGI8
2
39.0625 – external
9FGV1005C012LTGI
9FGV1005C012LTGI8
Table 21. Common Features of 9FGV1001C / 9FGV1005C Standard Configurations (with 39.0625MHz
crystal frequency)
These common features are collaborative with Table 20.
Configuration
Output Frequency (MHz)
0
156.25
1
161.1328125
2
312.5
3
322.265625
Output Type
Ref Outputs
LP-HCSL
OFF
Ordering Information
Orderable Part Number
9FGV1001CnnnNBGI
9FGV1001CnnnNBGI8
9FGV1001CQ5aaLTGI
9FGV1001CQ5aaLTGI8
Package
Carrier Type
4 × 4 mm, 0.5mm pitch 24-VFQFPN
4 × 4 mm, 0.5mm pitch 24-LGA
Tray
Tray
Tape and Reel
Tray
9FGV1005CnnnLTGI8
Tape and Reel
3 × 3 mm, 0.5mm pitch 16-LGA
9FGV1005CQ5aaLTGI8
Tray
Tape and Reel
Crystal
External
Tape and Reel
9FGV1005CnnnLTGI
9FGV1005CQ5aaLTGI
Temperature
50MHz Internal
-40 to +85°C
External
50MHz Internal
“G” indicates RoHS 6.6 compliance.
“nnn” are decimal digits indicating a specific configuration.
“aa” are alphanumeric digits indicating a specific configuration.
“Q5” indicates internal 50MHz crystal.
©2020 Renesas Electronics Corporation
21
October 29, 2020
9FGV1001C / 9FGV1005C Datasheet
Revision History
Revision Date
Description of Change
October 29, 2020
Updated pin descriptions for VDDAp and VDDDp.
September 28, 2020
Added Standard Configurations section and tables.
September 18, 2020
Corrected typo in Features section from 3 x 3 mm 16-LGA (9FGV1006) to 3 x 3 mm 16-LGA (9FGV1005).
August 18, 2020
Updated 9FGV1005CQ marking diagram.
August 14, 2020
Updated Slew Rate 1.8V minimum value from 0.8 to 1.0V/ns.
August 13, 2020
Updated Carrier Type in Ordering Information table from “Cut-Tape” to “Tray”.
July 21, 2020
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Merge 9FGV1001 and 9FGV1005 into single data sheet.
Update to device Rev C, SEL0 and SEL1 lines now have internal pull-down resistors.
Add PCIe Gen5 performance specifications.
Updated electrical tables to latest format.
©2020 Renesas Electronics Corporation
22
October 29, 2020
24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm
NB/NBG24P2, PSC-4313-02, Rev 01, Page 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
24-VFQFPN, Package Outline Drawing
4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm
NB/NBG24P2, PSC-4313-02, Rev 01, Page 2
Package Revision History
Description
Date Created
Rev No.
Jan 24, 2018
Rev 01
Change QFN to VFQFPN and New Format
May 11, 2016
Rev 00
Initial Release
24-LGA Package Outline Drawing
4.0 x 4.0 x 1.40 mm Body, 0.5mm Pitch
LTG24T2, PSC-4481-02, Rev 00, Page 1
24-LGA Package Outline Drawing
4.0 x 4.0 x 1.40 mm Body, 0.5mm Pitch
LTG24T2, PSC-4481-02, Rev 00, Page 2
Package Revision History
Date Created
Rev No.
Sept 15, 2017
Rev 00
Description
Initial Release
16-LGA Package Outline Drawing
3.0 x 3.0 x 1.10 mm Body, 0.5mm Pitch
LTG16P1, PSC-4651-01, Rev 02, Page 1
16-LGA Package Outline Drawing
3.0 x 3.0 x 1.10 mm Body, 0.5mm Pitch
LTG16P1, PSC-4651-01, Rev 02, Page 2
Package Revision History
Description
Date Created
Rev No.
Nov 6, 2017
Rev 02
Modify Solder Mask & Epad Chamfer
Sept 29, 2017
Rev 01
Modify Land Pattern
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