9FGV1006CQ515LTGI

PCIe Gen1–5 Low-Power Programmable PhiClock™ Generators Description Features The 9FGV1002C / 9FGV1006C are members of the Renesas PhiClock™ programmable clock generator family. These devices are optimized for low phase noise spread-spectrum applications such as PCIe Express. The 9FGV1002C is a four-output device while the 9FGV1006C is a smaller two-output version. Four user-defined configurations may be selected via two hardware select pins or two I2C bits, allowing easy software selection of the desired configuration. Any one of the four OTP configurations may be specified as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components. ▪ ▪ ▪ ▪ 1.8V to 3.3V power supplies Individual 1.8V to 3.3V VDDO for each output pair Supports HCSL, LVDS and LVCMOS I/O standards HCSL utilizes Renesas’ LP-HCSL technology for improved performance, lower power and higher integration: • Programmable output impedance of 85Ω or 100Ω ▪ Supports LVPECL and CML logic with easy AC coupling – see application note AN-891 for alternate terminations ▪ ▪ ▪ ▪ Typical Applications ▪ ▪ ▪ ▪ ▪ 9FGV1002C / 9FGV1006C Datasheet High-performance Computing (HPC) Enterprise Storage including eSSDs 10G / 25G / 100G Ethernet Fiber Optic Modules NVLink On-board OTP supports up to 4 complete configurations Configuration selected via strapping pins or I2C Internal crystal load capacitors < 125mW at 1.8V with LP-HCSL outputs at 100MHz (9FGV1002C) ▪ < 100mW at 1.8V with LP-HCSL outputs at 100MHz (9FGV1006C) ▪ 4 programmable I2C addresses: D0, D2, D4, D6 ▪ Easily configured with Renesas Timing Commander™ software or Web Configuration tool PCIe Clocking Architectures ▪ 4 × 4 mm 24-VFQFPN with integrated crystal option ▪ Common Clocked (CC) ▪ Independent Reference without spread spectrum (SRnS) ▪ Independent Reference with spread spectrum (SRIS) (9FGV1002CQ) ▪ 3 × 3 mm 16-LGA with integrated crystal option (9FGV1006CQ) ▪ Programmable spread spectrum modulation frequency and Output Features amount ▪ 9FGV1002: 4 programmable output pairs plus 2 LVCMOS REF Key Specifications ▪ 9FGV1006: 2 programmable output pairs plus 1 LVCMOS REF ▪ 12kHz–20MHz typical phase jitter at 156.25M (SSC off) 276ps ▪ 1 integer, fractional or spread spectrum output frequency per ▪ PCIe Gen4 jitter (CC) < 0.23ps RMS ▪ PCIe Gen5 jitter (CC) < 0.08ps RMS ▪ PCIe Gen5 jitter (SRIS) < 0.07ps RMS outputs RMS output configuration ▪ 1MHz–325MHz LVDS or LP-HCSL outputs ©2020 Renesas Electronics Corporation 1 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet 9FGV1002C / 9FGV1006C Block Diagram VDDREFp 9FGV1002 REF1 vREF0_SEL_I2C# Consult factory if design requires REF1. XIN/CLKIN XO OSC 9FGV1002CQ and 9FGV1006CQ integrate the crystal FRAC PLL (SSC) vSEL0/SCL vSEL1/SDA 9FGV1002 SMBus Engine ^OEB ^OEA INT DIV Factory Configuration Control Logic Prog. Output OUT3# OUT3 VDDO3 Prog. Output OUT2# OUT2 VDDO2 Prog. Output OUT1# OUT1 VDDO1 Prog. Output OUT0# OUT0 VDDO0 9FGV1002 Table 1. OE Mapping OE[B:A] OUT0 OUT1 OUT2 OUT3 REF0 REF1 00 Running Stopped Stopped Stopped Running Running 01 Running Running Stopped Stopped Running Running 10 Running Running Running Stopped Running Running 11 Running Running Running Running Running Running ©2020 Renesas Electronics Corporation 2 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9FGV1002C / 9FGV1006C Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9FGV1002C Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9FGV1006C Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Standard Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ©2020 Renesas Electronics Corporation 3 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Pin Assignments 24 23 22 21 20 19 10 11 12 7 OUT3 OUT3# VDDO3 VDDAp 8 9 16 OUT2# 15 VDDO1 14 OUT1 13 OUT1# 10 11 12 VDDO0 vSEL1/SDA 5 ^OEA 6 OUT0 14 OUT1 13 OUT1# 18 VDDO2 17 OUT2 9FGV1002CQ Connect EPAD to GND OUT0# OTP_VPP REF1 3 vSEL0/SCL 4 OTP_VPP ^OEB 16 OUT2# 15 VDDO1 VDDO0 9 OUT0 8 OUT0# 7 VDDDp vSEL1/SDA 5 ^OEA 6 NC 1 NC 2 ^OEB 9FGV1002C Connect EPAD to GND REF1 3 vSEL0/SCL 4 24 23 22 21 20 19 18 VDDO2 17 OUT2 VDDDp XIN/CLKIN 1 XO 2 vREF0_SEL_I2C# VDDREFp OUT3 OUT3# VDDO3 VDDAp vREF0_SEL_I2C# VDDREFp Figure 1. Pin Assignments for 9FGV1002C 4 x 4 mm 24-VFQFPN and 24-LGA Packages – Top View 4 × 4 mm 24-QFN, 0.5mm pitch 4 × 4 mm 24-LGA, 0.5mm pitch ^ prefix indicates internal pull-up v prefix indicates internal pull-down resistor Note: The order of OUT3 is reversed from OUT[0:2] ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor Note: The order of OUT3 is reversed from OUT[0:2] OUT0# OUT0 vSEL0/SCL 3 vSEL1/SDA 4 VDDO1 5 6 7 8 12 OUT1 11 OUT1# 10 VDDO0 9 VDDO0 16-LGA 3 x 3 mm, 0.5mm pitch ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor 16-LGA 3 x 3 mm, 0.5mm pitch ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor ©2020 Renesas Electronics Corporation 9FGV1006CQ EPAD = GND OUT0 8 10 VDDO0 9 VDDO0 NC 2 OUT0# 7 NC 1 OTP_VPP 6 12 OUT1 11 OUT1# VDDDp 5 VDDDp vSEL0/SCL 3 vSEL1/SDA 4 9FGV1006C EPAD = GND OTP_VPP XO 2 VDDAp 16 15 14 13 16 15 14 13 XIN/CLKIN 1 vREF0_SEL_I2C# VDDREFp VDDO1 VDDAp vREF0_SEL_I2C# VDDREFp Figure 2. Pin Assignments for 9FGV1006C 3 x 3 mm 16-LGA Package – Top View 4 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet 9FGV1002C Pin Descriptions Note: Unused outputs can be programmed off and left floating. Output supplies VDDREF and VDDO2 have to be connected. If OUT0 is used, V DDO1 must also be connected. Table 2. 9FGV1002C Pin Descriptions Number 1[a] Name XIN/CLKIN Type Input Description Crystal input or reference clock input. [a] XO Output Crystal output. 3 REF1 Output LVCMOS reference output. 4 vSEL0/SCL Input Select pin for internal frequency configurations/I2C clock pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-down. 5 vSEL1/SDA I/O Select pin for internal frequency configurations/I2C data pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-down. 6 ^OEA Input Active high input for enabling outputs. This pin has an internal pull-up resistor. 0 = disable outputs, 1 = enable outputs. 7 VDDDp Power Digital power. Connect to 1.8V, 2.5V or 3.3V. 8 ^OEB Input Active high input for enabling outputs. This pin has an internal pull-up resistor. 0 = disable outputs, 1 = enable outputs. 9 OTP_VPP Power Voltage for programming OTP. During normal operation, this pin should be connected to the same power rail as VDDD. 10 OUT0# Output Complementary output clock 0. 11 OUT0 Output Output clock 0. 12 VDDO0 Power Power supply for output 0. 13 OUT1# Output Complementary output clock 1. 14 OUT1 Output Output clock 1. 15 VDDO1 Power Power supply for output 1. 16 OUT2# Output Complementary output clock 2. 17 OUT2 Output Output clock 2. 18 VDDO2 Power Power supply for output 2. 19 OUT3 Output Output clock 3. 20 OUT3# Output Complementary output clock 3. 21 VDDO3 Power Power supply for output 3. 22 VDDAp Power Analog power. Connect to same voltage as VDDDp, with proper filtering. 2 Latched I/O Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the state of the I2C pins. After power-up, the pin acts as an LVCMOS reference output. This pin has an internal pull-down. 1 = SEL0/SEL1. 0 = SCL/SDA. 23 vREF0_SEL_I2C# 24 VDDREFp Power Power supply for REF outputs and the internal XO. Nominal voltages are 1.8V, 2.5V or 3.3V. 25 EPAD GND Connect to ground. [a] These pins are 'No Connect' on 9FGV1002Q integrated quartz versions and should have no stubs. ©2020 Renesas Electronics Corporation 5 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet 9FGV1006C Pin Descriptions Note: Unused outputs can be programmed off and left floating. Output supplies VDDREF and VDDO1 have to be connected. This means that if only one output is to be used, it must be OUT1. If OUT0 is used, both pins 9 and 10 must be connected. They may share the same power filter. Table 3. 9FGV1006C Pin Descriptions Number 1[a] 2 [a] Name XIN/CLKIN XO Type Input Output Description Crystal input or reference clock input. Crystal output. vSEL0/SCL Input Select pin for internal frequency configurations/I2C Clock pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-down. 4 vSEL1/SDA I/O Select pin for internal frequency configurations/I2C Data pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-down. 5 VDDDp Power Digital power. Connect to 1.8V, 2.5V or 3.3V. OTP_VPP Power Voltage for programming OTP. During normal operation, this pin should be connected to the same power rail as VDDD. 7 OUT0# Output Complementary output clock 0. 8 OUT0 Output Output clock 0. 9 VDDO0 Power Power supply for output 0. 10 VDDO0 Power Power supply for output 0. 11 OUT1# Output Complementary output clock 1. 12 OUT1 Output Output clock 1. 13 VDDO1 Power Power supply for output 1. 14 VDDAp Power Analog power. Connect to same voltage as VDDDp, with proper filtering. 3 6 Latched I/O Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the state of the I2C pins. After power-up, the pin acts as an LVCMOS reference output. This pin has an internal pull-down. 1 = SEL0/SEL1. 0 = SCL/SDA. 15 vREF0_SEL_I2C# 16 VDDREFp Power Power supply for REF outputs and the internal XO. Nominal voltages are 1.8V, 2.5V or 3.3V. 17 EPAD GND Connect to ground. [a] These pins are 'No Connect' on 9FGV1006Q integrated quartz version and should have no stubs. ©2020 Renesas Electronics Corporation 6 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Phase Noise Plots Figure 3. 9FGV1002C Phase Noise Plot1, 3.3V, 25°C. 1 See Test Frequencies for Jitter Measurements table for details. ©2020 Renesas Electronics Corporation 7 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Figure 4. 9FGV1006C Phase Noise Plot1, 3.3V, 25°C. 1 See Test Frequencies for Jitter Measurements table for details. ©2020 Renesas Electronics Corporation 8 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 9FGV1002C / 9FGV1006C at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 4. Absolute Maximum Ratings Parameter Rating Supply Voltage, V DDA, VDDD, VDDO 3.9V Storage Temperature, T STG -65°C to 150°C ESD Human Body Model 2000V Junction Temperature 125°C Inputs XIN/CLKIN 0V to 1.2V voltage swing Other Inputs -0.5V to VDDD Outputs Outputs, VDDO (LVCMOS) -0.5V to VDDO + 0.5V Outputs, IO (SDA) 10mA Thermal Characteristics Table 5. Thermal Characteristics for 24-pin Devices Parameter Thermal Resistance (devices with external crystal) Thermal Resistance Q-series (devices with internal crystal) 1 Symbol Conditions Package Typical Values Units Notes θJC Junction to case. 52 °C/W 1 θJb Junction to base. 2.3 °C/W 1 θJA0 Junction to air, still air. 44 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 37 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 33 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 32 °C/W 1 θJC Junction to case. 57.3 °C/W 1 θJb Junction to base. 24.3 °C/W 1 θJA0 Junction to air, still air. 79.8 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 73.9 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 69.9 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 67.3 °C/W 1 NBG24 LTG24 EPAD soldered to board. ©2020 Renesas Electronics Corporation 9 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Table 6. Thermal Characteristics for 16-pin devices Parameter Thermal Resistance (devices with external crystal) Thermal Resistance Q-series (devices with internal crystal) 1 Symbol Conditions Package Typical Values Units Notes θJC Junction to case. 66 °C/W 1 θJb Junction to base. 5.1 °C/W 1 θJA0 Junction to air, still air. 63 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 56 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 51 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 49 °C/W 1 θJC Junction to case. 82.1 °C/W 1 θJb Junction to base. 42.3 °C/W 1 θJA0 Junction to air, still air. 93.6 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 87.1 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 83.3 °C/W 1 LTG16 LTG16 EPAD soldered to board. Recommended Operating Conditions Table 7. Recommended Operating Conditions Symbol Minimum Typical Maximum Units Power supply voltage for supporting 1.8V outputs. 1.71 1.8 1.89 V Power supply voltage for supporting 2.5V outputs. 2.375 2.5 2.625 V Power supply voltage for supporting 3.3V outputs. 3.135 3.3 3.465 V VDDD Power supply voltage for core logic functions. 1.71 3.465 V VDDA Analog power supply voltage. Use filtered analog power supply if available. 1.71 3.465 V TA Operating temperature, ambient. -40 85 °C CL Maximum load capacitance (3.3V LVCMOS only). 15 pF tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic). 5 ms VDDOx Parameter ©2020 Renesas Electronics Corporation 10 0.05 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Electrical Characteristics VDDx = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Table 8. Common Electrical Characteristics Parameter Input Frequency Symbol fIN Conditions Minimum Typical Maximum Units Notes Crystal input frequency. 8 50 MHz 1 CLKIN input frequency. 1 240 MHz 5 Differential clock output (LVDS/LP-HCSL). 1 325 MHz Single-ended clock output (LVCMOS). 1 200 MHz 2600 MHz Output Frequency fOUT VCO Frequency fVCO VCO operating frequency range. 2400 Loop Bandwidth fBW Input frequency = 25MHz. 0.06 0.9 MHz Input High Voltage VIH SEL[1:0]. 0.7 x VDDD VDDD + 0.3 V Input Low Voltage VIL SEL[1:0]. GND - 0.3 0.8 V Input High Voltage VIH REF/SEL_I2C#. 0.65 x VDDREF VDDREF + 0.3 V Input Low Voltage VIL REF/SEL_I2C#. -0.3 0.4 V Input High Voltage VIH XIN/CLKIN. 0.8 1.2 V Input Low Voltage VIL XIN/CLKIN. -0.3 0.4 V Input Rise/Fall Time TR/TF Input Capacitance CIN Internal Pull-up Resistor RUP RDOWN Internal Pull-down Resistor 2500 OEA, OEB (when present) 10 SEL1/SDA, SEL0/SCL 300 SEL[1:0]. ns 3 7 pF 200 237 300 kΩ 200 237 300 kΩ 8 pF Programmable Capacitance at XIN and XO (XIN in parallel with XO) CL XIN/CLKIN, XO. 0 Input Duty Cycle t2 CLKIN, measured at VDDREF/2. 40 50 60 % LVCMOS, fOUT > 156.25MHz. 40 50 60 % LVCMOS, fOUT < 156.25MHz. 45 50 55 % LVDS, LP-HCSL outputs. 45 50.2 55 % Output Duty Cycle Clock Jitter t3 t6 Cycle-to-cycle jitter (Peak-to-Peak), See Test Frequencies for Jitter Measurements for configurations. 24 ps 4 Reference clock RMS phase jitter (12kHz to 20MHz integration range). See Test Frequencies for Jitter Measurements for configurations. 245 fs rms 4 OUTx RMS phase jitter(12kHz to 20MHz integration range) differential output. See Test Frequencies for Jitter Measurements for configurations. 276 fs rms 4 ©2020 Renesas Electronics Corporation 11 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Table 8. Common Electrical Characteristics (Cont.) Parameter Output Skew Lock Time 1 2 3 Typical Maximum All outputs using the same driver format same VDDO voltage. (9FGV1006C). 38 60 All outputs using the same driver format and same VDDO voltage. (9FGV1002C). 62 100 t8a PLL outputs valid from VDDs reaching 1.5V. 5 10 ms 2,3 t8b REF outputs valid from VDDs reaching 1.5V. 5 11 ms 2,3 Units Notes t7 Conditions Minimum Units Notes ps Practical lower frequency is determined by loop filter settings. Includes loading the configuration bits from OTP to registers. Actual PLL lock time depends on the loop configuration. 4 Actual 5 Symbol jitter is configuration dependent. These values are representative of what the device can achieve. Input doubler off. Maximum input frequency with input doubler on is 160MHz. Table 9. Test Frequencies for Jitter Measurements VDDx = 3.3V±5%, 2.5V±5%, 1.8V±5%, TA = -40°C to +85°C unless stated otherwise XIN/CLKIN OUT0 OUT1 50 1 4 OUT3 Unit Notes 156.25 MHZ 3,4 100 MHZ 1,2,3 This configuration is used for 12kHz–20MHz REF phase jitter measurement, SSC off. 2 This 3 OUT2 configuration is used for PCIe filtered phase jitter measurements with SSC on and off. Outputs configured as LP-HCSL or LVDS with REF output off, unless noted. This configuration is used for 12kHz–20MHz OUT phase jitter measurement. REF off, SSC off. Table 10. LVCMOS Output Electrical Characteristics Parameter Slew Rate Symbol SR Conditions Minimum Typical Maximum 3.3V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 2.6 3.7 4.7 2.5V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 1.5 2.4 4.7 1.8V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 1.0 1.7 3.2 V/ns IOH = -15mA at 3.3V. Output High Voltage VOH IOH = -12mA at 2.5V. 0.8 x VDDO VDDO V IOH = -8mA at 1.8V. ©2020 Renesas Electronics Corporation 12 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Table 10. LVCMOS Output Electrical Characteristics (Cont.) Parameter Symbol Conditions Minimum Typical Maximum Units 0.22 0.4 V 5 μA Notes IOL = 15mA at 3.3V. Output Low Voltage VOL IOL = 12mA at 2.5V. IOL = 8mA at 1.8V. Output Leakage Current IOZDD Outputs, tri-stated, VDDO, VDDREF = 3.465V. 0 CMOS Output Driver Impedance ROUT TA = 25°C. 17 Ω Table 11. LVDS Output Electrical Characteristics Parameter Symbol Minimum Typical Maximum Units Differential Output Voltage for the TRUE Binary State VOT (+) 247 328 454 mV Differential Output Voltage for the FALSE Binary State VOT (-) -454 -332 -247 mV Change in VOT between Complementary Output States ΔV OT 50 mV Output Common Mode Voltage (Offset Voltage) at 3.3V +5% and 2.5V +5% VOS 1.125 1.19 1.55 V Output Common Mode Voltage (Offset Voltage) at 1.8V +5% VOS 0.8 0.86 0.95 V Change in VOS between Complementary Output States ΔVOS 0 50 mV Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or V DD IOS 6 12 mA Differential Outputs Short Circuit Current, VOUT+ = VOUT- IOSD 3 12 mA Rise Times Tested at 20%–80% TR 257 375 ps Fall Times Tested at 80%–20% TF 287 375 ps ©2020 Renesas Electronics Corporation 13 Notes November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Table 12. Low-Power (LP) Push-Pull HCSL Differential Outputs VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol Slew Rate TR/F Slew Rate Matching ΔTR/F Conditions Scope averaging on. Crossing Voltage (abs) VCROSS Scope averaging off. Crossing Voltage (var) ΔVCROSS Scope averaging off. Average Clock Period Accuracy TPERIOD_AVG Absolute Period TPERIOD_ABS Includes jitter and spread modulation. Minimum Typical Maximum Units Notes 1.25 2.5 4 V/ns 2,3,16 9 20 % 1,14,16 424 550 mV 1,4,5,16 16 140 mV 1,4,9,16 -100 0 +2600 2,10,12,13 9.949 10 10.101 2,6 250 Outputs set to 100MHz for PCIe applications. Absolute Maximum Voltage VMAX Includes 300mV of overshoot (Vovs). 660 808 1150 mV 1,7,15 Absolute Minimum Voltage VMIN Includes -300mV of undershoot (Vuds). -300 -54 150 mV 1,8,15 1 Measured 2 Measured 3 Measured 4 5 6 7 8 from single-ended waveform. from differential waveform. from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. Defined as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. Defined as the maximum instantaneous voltage including overshoot. Defined as the minimum instantaneous voltage including undershoot. 9 Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum allowed variance in VCROSS for any particular system. 10 11 12 Refer to Section 8.6 of the PCI Express Base Specification, Revision 4.0 for information regarding PPM considerations. System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load CL = 2pF. PCIe Gen1 through Gen4 specify ±300ppm frequency tolerances. The PhiClock devices already meet the tighter ±100ppm frequency tolerances proposed for PCIe Gen5 and required by most servers. 13 “ppm” refers to 14 15 16 parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly or 100Hz. For 100ppm, then we have an error budget of 100Hz/ppm × 100ppm = 10kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±100ppm applies to systems that do not employ Spread Spectrum clocking, or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,600ppm for Common Clock architectures. Separate Reference Clock architectures may have a lower allowed spread percentage. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of REFCLK+ should be compared to the fall edge rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. At default amplitude settings. Guaranteed by design and characterization. ©2020 Renesas Electronics Corporation 14 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Table 13. Filtered PCIe Phase Jitter Parameters TAMB = over the specified operating range. Supply Voltages per normal operation conditions; see Test Loads for loading conditions. Parameter PCIe Phase Jitter7 (Common Clocked Architecture) 7 PCIe Phase Jitter (SRIS Architecture) 1 2 3 4 5 6 7 Specification Units Limits Symbol Conditions Minimum Typical Maximum tjphPCIeG1-CC PCIe Gen1 (2.5 GT/s) SSC ≤ -0.5% 0.28 6.80 24 86 ps (p-p) 1,2 PCIe Gen2 Hi Band (5.0 GT/s) SSC ≤ -0.5% 0.11 0.36 0.64 3 ps (rms) 1,2 PCIe Gen2 Lo Band (5.0 GT/s) SSC ≤ -0.5% 0.00 0.02 0.07 3.1 ps (rms) 1,2 tjphPCIeG3-CC PCIe Gen3 (8.0 GT/s) SSC ≤ -0.5% 0.03 0.13 0.23 1 ps (rms) 1,2 tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) SSC ≤ -0.5% 0.03 0.13 0.23 0.5 ps 1,2,3,4 (rms) tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) SSC ≤ -0.5% 0.01 0.04 0.083 0.15 ps 1,2,3,5 (rms) tjphPCIeG2-SRIS PCIe Gen2 (5.0 GT/s) SSC ≤ -0.3% 0.29 0.39 0.505 ps (rms) 1,2,6 tjphPCIeG3-SRIS PCIe Gen3 (8.0 GT/s) SSC ≤ -0.3% 0.09 0.19 0.273 ps (rms) 1,2,6 tjphPCIeG4-SRIS PCIe Gen4 (16.0 GT/s) SSC ≤ -0.3% 0.10 0.14 0.184 ps (rms) 1,2,6 tjphPCIeG5-SRIS PCIe Gen5 (32.0 GT/s) SSC ≤ -0.3% 0.03 0.05 0.071 ps (rms) 1,2,6 tjphPCIeG2-CC N/A Notes The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all measurements. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. While the PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, it does not provide specification limits, hence the n/a in the Limit column. SRIS values are informative only. SRIS is not defined for PCIe Gen1. 9FGV1002C or 9FGV1006C with 001/015 or Q505/Q515 configurations. See the 9FGV1002C/9FGV1006C Standard Configurations table for details and a selection of off-the-shelf configurations supporting PCIe Gen5. ©2020 Renesas Electronics Corporation 15 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Table 14. 9FGV1002C Current Consumption VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol Conditions Minimum Typical Maximum Units Notes VDDREF Supply Current IDDREF 50MHz REFCL, subtract 3mA for 25MHz REFCLK. 7 11 mA Core Supply Current IDDCORE 2400MHz VCO. 37 49 mA 3 LVDS, 325MHz. 7 9 mA 2 LP-HCSL, 100MHz. 6 7 mA 2 LVCMOS, 50MHz. 4 6 mA 1,2 LVCMOS, 200MHz. 12 21 mA 1,2 LVDS, 325MHz. 19 24 mA 2 LP-HCSL, 100MHz. 16 20 mA 2 LVCMOS, 50MHz. 14 18 mA 1,2 LVCMOS, 200MHz. 23 35 mA 1,2 LVDS, 325MHz. 7 10 mA 2 LP-HCSL, 100MHz. 7 10 mA 2 LVCMOS, 50MHz. 8 14 mA 1,2 LVCMOS, 200MHz. 9 15 mA 1,2 LVDS, 325MHz. 6 9 mA 2 LP-HCSL, 100MHz. 5 7 mA 2 LVCMOS, 50MHz. 3 6 mA 1,2 LVCMOS, 200MHz. 12 22 mA 1,2 Programmable outputs in HCSL mode, B37[0] = 0. 20 27 mA 2 Programmable outputs in LVDS mode, B37[0] = 0. 33 45 mA 2 Programmable outputs in LVCMOS1 mode, B37[0] = 0. 16 22 mA 2 Output Buffer Supply Current VDDO3 Output Buffer Supply Current VDDO2 (includes output divider) IDDOx Output Buffer Supply Current VDDO1 (this pin must be connected if OUT0 is used) Output Buffer Supply Current VDDO0 Total Power Down Current 1 2 3 IDDPD Single CMOS driver active for each output pair. See Test Loads for details. IDDCORE = IDDA + IDDD. For integer, fractional or spread spectrum PLL. ©2020 Renesas Electronics Corporation 16 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Table 15. 9FGV1006C Current Consumption VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol Conditions Minimum Typical Maximum Units Notes VDDREF Supply Current IDDREF 50MHz REFCLK. 3 7 mA Core Supply Current IDDCORE 2400MHz VCO. 37 48 mA 3 LVDS, 350MHz. 19 24 mA 2 LP-HCSL, 100MHz. 16 20 mA 2 LVCMOS, 50MHz. 14 19 mA 1,2 LVCMOS, 200MHz. 22 34 mA 1,2 LVDS, 350MHz. 7 11 mA 2 LP-HCSL, 100MHz. 8 10 mA 2 LVCMOS, 50MHz. 8 13 mA 1,2 LVCMOS, 200MHz. 8 14 mA 1,2 Programmable outputs in HCSL mode, B37[0] = 0. 19 25 mA 2 Programmable outputs in LVDS mode, B37[0] = 0. 25 34 mA 2 Programmable outputs in LVCMOS1 mode, B37[0] = 0. 16 22 mA 2 Minimum Typical Maximum Units PCIe Compliant -0.5% spread modulation. 30 31.5 33 kHz Modulation frequency. 30 31.5 63 kHz Amount of spread value (programmable) – down spread. -0.1 -0.5 -3.0 Amount of spread value (programmable) – center spread. ±0.05 Output Buffer Supply Current (VDDO1) IDDOx Output Buffer Supply Current (VDDO0 – the total for pins 9 and 10) Total Power Down Current 1 2 IDDPD Single CMOS driver active for each output pair. See Test Loads for details. 3I DDCORE = IDDA + IDDD + IDDAO. Table 16. Spread Spectrum Generation Specifications Parameter Symbol Mod Frequency fMODPCIe Mod Frequency fMOD Spread% SSC% Conditions ©2020 Renesas Electronics Corporation 17 ±1.5 % November 30, 2020 9FGV1002C / 9FGV1006C Datasheet I2C Bus Characteristics Table 17. I2C Bus DC Characteristics Parameter Symbol Conditions Minimum Input High Level VIH — 0.7 x VDDD Input Low Level VIL — VHYS — 0.05 x VDDD Input Leakage Current IIN — -1 Output Low Voltage VOL IOL = 3mA. Hysteresis of Inputs Typical Maximum Units V 0.3 x VDDD V V 30 μA 0.4 V Maximum Units 400 kHz Table 18. I2C Bus AC Characteristics Parameter Symbol Conditions Minimum FSCLK — 10 tBUF — 1.3 μs Setup Time, START tSU:START — 0.6 μs Hold Time, START tHD:START — 0.6 μs Setup Time, Data Input (SDA) tSU:DATA — 0.1 μs Hold Time, Data Input (SDA) 1 tHD:DATA — 0 μs Output Data Valid from Clock tOVD — 0.9 μs Capacitive Load for Each Bus Line CB — 400 pF Rise Time, Data and Clock (SDA, SCL) tR — 20 + 0.1 x CB 300 ns Fall Time, Data and Clock (SDA, SCL) tF — 20 + 0.1 x CB 300 ns HIGH Time, Clock (SCL) tHIGH — 0.6 μs LOW Time, Clock (SCL) tLOW — 1.3 μs tSU:STOP — 0.6 μs Serial Clock Frequency (SCL) Bus free time between STOP and START Setup Time, STOP Typical Note: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. ©2020 Renesas Electronics Corporation 18 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Test Loads Figure 5. LVCMOS AC/DC Test Load Test Point L Zo Rs CL Rs Zo L CL 33Ω 50Ω 5 inches 4.7pF Figure 6. LP-HCSL AC/DC Test Load (Standard PCIe source-terminated test load) Rs CL L Test Points Differential Zo CL Rs Rs Zo L CL Internal 100Ω 5 inches 2pF Internal 85Ω 5 inches 2pF Figure 7. LVDS AC/DC Test Load L Differential Zo 100ohm Rs Zo L CL N/A 100Ω 5 inches N/A ©2020 Renesas Electronics Corporation 19 Test Points November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Figure 8. Test Setup for PCIe Measurement Using a Real-Time Scope Real Time Scope SMA Connectors Rs Coax Cables L Differential Zo 0.1µF 50 50 Rs Rs Zo L CL Internal 100Ω 5 inches N/A Figure 9. Test Setup for PCIe Measurement Using a Phase Noise Analyzer SMA Connectors L CK+ 0.1uF CK- 50 Rs Zo L CL Internal 100Ω 5 inches N/A ©2020 Renesas Electronics Corporation Coax Cables Balun Zo (differential) DUT Phase Noise Analyzer 20 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Crystal Characteristics Table 19. Recommended Crystal Characteristics Parameter Value Units Frequency 8–50 MHz Resonance Mode Fundamental – Frequency Tolerance at 25°C ±20 ppm maximum Frequency Stability, REF at 25°C Over Operating Temperature Range ±20 ppm maximum Temperature Range (commercial) 0–70 °C Temperature Range (industrial) -40–85 °C Equivalent Series Resistance (ESR) 50 Ω maximum Shunt Capacitance (CO) 7 pF maximum Load Capacitance (CL) 8 pF maximum Drive Level 0.1 mW maximum Aging Per Year ±5 ppm maximum Package Outline Drawings The package outline drawings are appended at the end of this document and are also accessible from the link below. The package information is the most current data available and is subject to change without notice or revision of this document. 9FGV1002C: www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-075-mm-body-05mm-pitch-epad-26-x-26-mm-nbnbg24p2 www.idt.com/document/psc/24-lga-package-outline-drawing-40-x-40-x-140-mm-body-05mm-pitch-ltg24t2 9FGV1006C: www.idt.com/document/psc/16-lga-package-outline-drawing-30-x-30-x-110-mm-body-05mm-pitch-ltg16p1 Marking Diagrams Figure 10. 9FGV1002C Marking Diagrams ▪ Lines 1 and 2 are the truncated part number: 9FGV100 2CnnnGI #YWW**$ 1002C Q5aaI YWW**$ ©2020 Renesas Electronics Corporation • “nnn” denotes the decimal digits indicating a specific configuration. • “aa” denotes the alphanumeric digits indicating a specific Q5 configuration. ▪ Line 3: • “#” denotes the stepping number. • “YWW” denotes the last digits of the year and week the part was assembled. • “**” denotes the lot sequence; “$” denotes the mark code. 21 November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Figure 11. 9FGV1006C Marking Diagrams ▪ Line 1: truncated part number 6Cnnn YWW$ XXX 6CQ5aa YWW$ XXX • “nnn” denotes the decimal digits indicating a specific configuration. • “aa” denotes the alphanumeric digits indicating a specific Q5 configuration. ▪ Line 2: “YWW” denotes the last digits of the year and week the part was assembled; “$” denotes mark code. ▪ Line 3: “XXX” denotes the last three characters of the lot number. Standard Configurations Table 20. 9FGV1002C/9FGV1006C Standard Configurations Supply Voltage–all pins (V) Output Impedance (ohms) Number of PCIe Clock Outputs 4 100 2 3.3 4 85 2 4 1.8 100 2 XTAL Frequency (MHz) Orderable Part Number (Bulk) Orderable Part Number (Tape and Reel) 25 – external 9FGV1002C001NBGI 9FGV1002C001NBGI8 50 – internal 9FGV1002CQ505LTGI 9FGV1002CQ505LTGI8 25 – external 9FGV1006C001LTGI 9FGV1006C001LTGI8 50 – internal 9FGV1006CQ505LTGI 9FGV1006CQ505LTGI8 25 – external 9FGV1002C015NBGI 9FGV1002C015NBGI8 50 – internal 9FGV1002CQ515LTGI 9FGV1002CQ515LTGI8 25 – external 9FGV1006C015LTGI 9FGV1006C015LTGI8 50 – internal 9FGV1006CQ515LTGI 9FGV1006CQ515LTGI8 25 – external 9FGV1002C002NBGI 9FGV1002C002NBGI8 50 – internal 9FGV1002CQ506LTGI 9FGV1002CQ506LTGI8 25 – external 9FGV1006C002LTGI 9FGV1006C002LTGI8 50 – internal 9FGV1006CQ506LTGI 9FGV1006CQ506LTGI8 Table 21. Common Features of 9FGV1002C/9FGV1006C Standard Configurations Output Freq (MHz) 100 Output Type LP-HCSL ©2020 Renesas Electronics Corporation REF Outputs Off 22 Configuration SSC amount (%) Notes 0 0 CC, SRNS 1 -0.1 CC, SRIS 2 -0.3 CC, SRIS 3 -0.5 CC November 30, 2020 9FGV1002C / 9FGV1006C Datasheet Ordering Information Orderable Part Number Package Carrier Type Temperature Crystal 9FGV1002CnnnNBGI 4 × 4 mm, 0.5mm pitch 24-VFQFPN Tray -40 to +85°C External 9FGV1002CnnnNBGI8 4 × 4 mm, 0.5mm pitch 24-VFQFPN Tape and Reel -40 to +85°C External 9FGV1002CQ5aaLTGI 4 × 4 mm, 0.5mm pitch 24-LGA Tray -40 to +85°C 50MHz Internal 9FGV1002CQ5aaLTGI8 4 × 4 mm, 0.5mm pitch 24-LGA Tape and Reel -40 to +85°C 50MHz Internal 9FGV1006CnnnLTGI 3 × 3 mm, 0.5mm pitch 16-LGA Tray -40 to +85°C External 9FGV1006CnnnLTGI8 3 × 3 mm, 0.5mm pitch 16-LGA Tape and Reel -40 to +85°C External 9FGV1006CQ5aaLTGI 3 × 3 mm, 0.5mm pitch 16-LGA Tray -40 to +85°C 50MHz Internal 9FGV1006CQ5aaLTGI8 3 × 3 mm, 0.5mm pitch 16-LGA Tape and Reel -40 to +85°C 50MHz Internal “G” indicates RoHS 6.6 compliance. “nnn” are decimal digits indicating a specific configuration. “aa” are alphanumeric digits indicating a specific configuration. “Q5” indicates internal 50MHz crystal. Revision History Revision Date Description of Change November 30, 2020 Removed “Output Frequency” parameter from Spread Spectrum Generation Specifications table. October 29, 2020 Updated pin descriptions for VDDAp and VDDDp. October 9, 2020 Added a condition and values for REF outputs to the Lock Time parameter. September 28, 2020 Removed “PCIe Gen5’ from the standard configuration tables titles and the relative heading title. August 18, 2020 Updated 9FGV1006CQ marking diagram. August 14, 2020 Updated Slew Rate 1.8V minimum value from 0.8 to 1.0V/ns. August 13, 2020 Updated Carrier Type in Ordering Information table from “Cut-Tape” to “Tray”. July 16, 2020 Corrected internal resistors on SEL0/SCL and SEL1/SDA to be pull-downs. July 10, 2020 Initial release. ©2020 Renesas Electronics Corporation 23 November 30, 2020 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm NB/NBG24P2, PSC-4313-02, Rev 01, Page 1 TOP VIEW BOTTOM VIEW SIDE VIEW 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm NB/NBG24P2, PSC-4313-02, Rev 01, Page 2 Package Revision History Description Date Created Rev No. Jan 24, 2018 Rev 01 Change QFN to VFQFPN and New Format May 11, 2016 Rev 00 Initial Release 24-LGA Package Outline Drawing 4.0 x 4.0 x 1.40 mm Body, 0.5mm Pitch LTG24T2, PSC-4481-02, Rev 00, Page 1 24-LGA Package Outline Drawing 4.0 x 4.0 x 1.40 mm Body, 0.5mm Pitch LTG24T2, PSC-4481-02, Rev 00, Page 2 Package Revision History Date Created Rev No. Sept 15, 2017 Rev 00 Description Initial Release 16-LGA Package Outline Drawing 3.0 x 3.0 x 1.10 mm Body, 0.5mm Pitch LTG16P1, PSC-4651-01, Rev 02, Page 1 16-LGA Package Outline Drawing 3.0 x 3.0 x 1.10 mm Body, 0.5mm Pitch LTG16P1, PSC-4651-01, Rev 02, Page 2 Package Revision History Description Date Created Rev No. Nov 6, 2017 Rev 02 Modify Solder Mask & Epad Chamfer Sept 29, 2017 Rev 01 Modify Land Pattern IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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