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9FGV1008C000LTGI

9FGV1008C000LTGI

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    TFLGA-16

  • 描述:

    IC CLOCK GENERATOR LGA

  • 数据手册
  • 价格&库存
9FGV1008C000LTGI 数据手册
Low Phase-Noise, Low-Power Programmable PhiClock™ Generator Description Features The 9FGV1004C/9FGV1008C are members of Renesas’ PhiClock™ programmable clock generator family. The 9FGV1004 provides 1 copy each of 2 integer-related frequencies, 2 copies of a fractional or spread-spectrum frequency. The 9FGV1008 provided 1 integer frequency and 1 copy of a fractional or spread-spectrum frequency. Four user-defined configurations may be selected via two hardware select pins or two I2C bits, allowing easy software selection of the desired configuration. Any one of the four OTP configurations may be specified as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components. ▪ ▪ ▪ ▪ High-performance Computing (HPC) eSSDs 10G/25G/100G Ethernet Fiber Optic Modules Data Center Accelerators Output Features ▪ 9FGV1004: 4 programmable output pairs plus 2 LVCMOS REF outputs ▪ 9FGV1008 2 programmable output pairs plus 1 LVCMOS REF output ▪ 2 integer and 1 fractional/spread spectrum output frequency per configuration ▪ 1MHz–325MHz LVDS or LP-HCSL outputs ▪ 1MHz–200MHz LVCMOS outputs ▪ 1MHz–156.25MHz spread spectrum or fractional output Key Specifications ▪ 12kHz–20MHz typical phase jitter at156.25M Hz (SSC off or on) 224fs RMS (9FGV1008 OUT1) ▪ 12kHz–20MHz typical phase jitter at156.25MHz (SSC off or on) 267fs RMS (9FGV1004 OUT3) ▪ PCIe Gen1–4 compliant (spread spectrum off) ▪ PCIe Gen1–3 compliant (spread spectrum on) ▪ See AN1001 for generating PCIe Gen5 clocks from the 9FGV1004C/9FGV1008C PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference without spread spectrum (SRnS) ▪ See AN1001 for Independent Reference with spread-spectrum (SRIS) applications ©2020 Renesas Electronics Corporation 1.8V, 2.5V or 3.3V power supplies Individual VDDO for each programmable output pair Supports HCSL, LVDS and LVCMOS I/O standards Low-Power HCSL technology for improved performance, lower power and higher integration: • Programmable output impedance of 85Ω or 100Ω ▪ Supports LVPECL and CML logic with easy AC coupling – see AN-891 for alternate terminations ▪ On-board OTP supports up to 4 complete configurations selectable via strapping pins or I2C ▪ Internal crystal load capacitors ▪ Programmable spread-spectrum modulation frequency and amount ▪ < 150mW at 1.8V with LP-HCSL outputs at 100MHz (9FGV1004) ▪ < 135mW at 1.8V with LP-HCSL outputs at 100MHz (9FGV1008) ▪ 4 programmable I2C addresses: D0, D2, D4, D6 ▪ Easily configured with Renesas Timing Commander™ software or Web Configurator ▪ Space saving 4 × 4 mm 24-VFQFPN, 24-LGA (9FGV1004) and 3 × 3 mm 16-LGA (9FGV1008) packages ▪ Integrated crystal option (9FGV1004CQ, 9FGV1008CQ) Typical Applications ▪ ▪ ▪ ▪ ▪ 9FGV1004C/9FGV1008C Datasheet 1 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Standard Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ©2020 Renesas Electronics Corporation 2 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Block Diagram VDDREFp 9FGV1004 REF1 vREF0_SEL_I2C# Consult factory if design requires REF1. XIN/CLKIN XO OSC 9FGV1004CQ and 9FGV1008CQ integrate the crystal INT DIV Prog. Output OUT3# OUT3 VDDO3 9FGV1004 INT DIV Prog. Output OUT2# OUT2 VDDO2 OUT1/1# VDDO1 on 9FGV1008 Prog. Output OUT1# OUT1 VDDO1 Prog. Output OUT0# INT PLL vSEL0/SCL vSEL1/SDA 9FGV1004 ^OEB ^OEA SMBus Engine Factory Configuration FODSSC Control Logic 9FGV1004 OUT0 VDDO0 Table 1. OE Mapping OE[B:A] OUT0 OUT1 OUT2 OUT3 REF0 REF1 00 Running Stopped Running Stopped Running Running 01 Running Running Stopped Stopped Running Running 10 Stopped Stopped Running Running Running Running 11 Running Running Running Running Running Running ©2020 Renesas Electronics Corporation 3 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Pin Assignments OUT3 OUT3# VDDO3 VDDAp vREF0_SEL_I2C# VDDREFp Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View 24 23 22 21 20 19 XIN/CLKIN 1 XO 2 18 VDDO2 17 OUT2 16 OUT2# 15 VDDO1 14 OUT1 13 OUT1# VDDO0 10 11 12 OUT0 9 OUT0# 7 VDDDp 8 OTP_VPP vSEL1/SDA 5 ^OEA 6 ^OEB 9FGV1004C Connect EPAD to GND REF1 3 vSEL0/SCL 4 4 × 4 mm 24-VFQFPN, 0.5mm pitch ^ prefix indicates internal pull-up v prefix indicates internal pull-down resistor Note: The order of OUT3 is reversed from OUT[0:2] OUT3 OUT3# VDDO3 VDDAp vREF0_SEL_I2C# VDDREFp Figure 2. Pin Assignments for 4 x 4 mm 24-LGA Package – Top View 24 23 22 21 20 19 NC 1 NC 2 18 VDDO2 17 OUT2 9FGV1004CQ Connect EPAD to GND 9 ^OEB OTP_VPP 16 OUT2# 15 VDDO1 14 OUT1 13 OUT1# 10 11 12 VDDO0 8 OUT0 7 VDDDp vSEL1/SDA 5 ^OEA 6 OUT0# REF1 3 vSEL0/SCL 4 4 × 4 mm 24-LGA, 0.5mm pitch ^ prefix indicates internal pull-up resistor v prefix indicates internal pull-down resistor Note: The order of OUT3 is reversed from OUT[0:2] ©2020 Renesas Electronics Corporation 4 October 29, 2020 9FGV1004C/9FGV1008C Datasheet OUT0# OUT0 vSEL0/SCL 3 vSEL1/SDA 4 VDDO1 5 6 7 8 12 OUT1 11 OUT1# 10 VDDAO0p 9 VDDO0 3 x 3 mm 16-LGA , 0.5mm pitch ^ prefix indicates internal pull-up v prefix indicates internal pull-down 3 x 3 mm 16-LGA , 0.5mm pitch ^ prefix indicates internal pull-up v prefix indicates internal pull-down ©2020 Renesas Electronics Corporation 9FGV1008CQ EPAD = GND OUT0 8 10 VDDAO0p 9 VDDO0 NC 2 OUT0# 7 12 OUT1 11 OUT1# OTP_VPP 6 NC 1 VDDDp 5 OTP_VPP vSEL0/SCL 3 vSEL1/SDA 4 9FGV1008C EPAD = GND VDDDp XO 2 VDDAp 16 15 14 13 16 15 14 13 XIN/CLKIN 1 vREF0_SEL_I2C# VDDREFp VDDO1 VDDAp vREF0_SEL_I2C# VDDREFp Figure 3. Pin Assignments for 3 x 3 mm 16-LGA Package – Top View 5 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Pin Descriptions Table 2. 9FGV1004 Pin Descriptions Number Name Type Description 1[a] XIN/CLKIN 2a] XO Output Crystal output. 3 REF1 Output LVCMOS reference output. 4 vSEL0/SCL Input Select pin for internal frequency configurations/I2C clock pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-down. vSEL1/SDA I/O Select pin for internal frequency configurations/I2C data pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-down. 5 6 Input Crystal input or reference clock input. ^OEA Input Active high input for enabling outputs. This pin has an internal pull-up resistor. 0 = disable outputs, 1 = enable outputs. VDDDp Power Digital power. Connect to 1.8V, 2.5V or 3.3V. ^OEB Input Active high input for enabling outputs. This pin has an internal pull-up resistor. 0 = disable outputs, 1 = enable outputs. OTP_VPP Power Voltage for programming OTP. During normal operation, this pin should be connected to the same power rail as VDDD. 10 OUT0# Output Complementary output clock 0. 11 OUT0 Output Output clock 0. 12 VDDO0 Power Power supply for output 0. 13 OUT1# Output Complementary output clock 1. 14 OUT1 Output Output clock 1. 15 VDDO1 Power Power supply for output 1. 16 OUT2# Output Complementary output clock 2. 17 OUT2 Output Output clock 2. 18 VDDO2 Power Power supply for output 2. 19 OUT3 Output Output clock 3. 20 OUT3# Output Complementary output clock 3. 21 VDDO3 Power Power supply for output 3. 22 VDDAp Power Analog power. Connect to same voltage as VDDDp, with proper filtering. 7 8 9 Latched I/O Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the state of the I2C pins. After power-up, the pin acts as an LVCMOS reference output. This pin has an internal pull-down. 1 = SEL0/SEL1. 0 = SCL/SDA. 23 vREF0_SEL_I2C# 24 VDDREFp Power Power supply for REF0 and REF1 and the internal XO. Programmable to 1.8V, 2.5V or 3.3V. 25 EPAD GND Connect to ground. Note: Unused outputs can be programmed off and left floating. VDDREF and VDDO0 have to be connected. [a] These pins are 'No Connect' on 9FGV100xQ integrated quartz versions and should have no stubs. ©2020 Renesas Electronics Corporation 6 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Table 3. 9FGV1008 Pin Descriptions Number 1[a] 2 [a] 3 Name XIN/CLKIN XO Type Input Output Description Crystal input or reference clock input. Crystal output. vSEL0/SCL Input Select pin for internal frequency configurations/I2C clock pin. Function is determined by state of SEL_I2C# upon power up. This pin has an internal pull-down. 4 vSEL1/SDA I/O Select pin for internal frequency configurations/I2C data pin. Function is determined by state of SEL_I2C# upon power-up. This pin has an internal pull-down. 5 VDDDp Power Digital power. Connect to 1.8V, 2.5V or 3.3V. OTP_VPP Power Voltage for programming OTP. During normal operation, this pin should be connected to the same power rail as VDDD. 7 OUT0# Output Complementary output clock 0. 8 OUT0 Output Output clock 0. 9 VDDO0 Power Power supply for output 0. 10 VDDAO0p Power Analog power supply for output 0. This pin should be connected to the same power rail as output 0 and filtered appropriately. Nominal voltages are 1.8V, 2.5V or 3.3V. 11 OUT1# Output Complementary output clock 1. 12 OUT1 Output Output clock 1. 13 VDDO1 Power Power supply for output 1. 14 VDDAp Power Analog power. Connect to same voltage as VDDDp, with proper filtering. 6 Latched I/O Latched input/LVCMOS Output. At power-up, the state of this pin is latched to select the state of the I2C pins. After power-up, the pin acts as a LVCMOS reference output. This pin has an internal pull-down. 1 = SEL0/SEL1. 0 = SCL/SDA. 15 vREF0_SEL_I2C# 16 VDDREFp Power Power supply for REF outputs and the internal XO. Nominal voltages are 1.8V, 2.5V or 3.3V. 17 EPAD GND Connect to ground. Note: Unused outputs can be programmed off and left floating. VDDREF and VDDO0 have to be connected. [a] These pins are 'No Connect' on 9FGV100xQ integrated quartz versions and should have no stubs. ©2020 Renesas Electronics Corporation 7 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 9FGV1004C/9FGV1008C at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 4. Absolute Maximum Ratings Parameter Rating Supply Voltage, V DDA, VDDD, VDDO 3.9V Storage Temperature, T STG -65°C to 150°C ESD Human Body Model 2000V Junction Temperature 125°C Inputs XIN/CLKIN 0V to 1.2V voltage swing Other Inputs -0.5V to VDDD Outputs Outputs, VDDO (LVCMOS) -0.5V to VDDO + 0.5V Outputs, IO (SDA) 10mA Thermal Characteristics Table 5. Thermal Characteristics–24-pin Devices Parameter Thermal Resistance (devices with external crystal) Thermal Resistance Q-series (devices with internal crystal) 1 Symbol Conditions Package Typical Values Units Notes θJC Junction to case 52 °C/W 1 θJb Junction to base 2.3 °C/W 1 θJA0 Junction to air, still air 44 °C/W 1 θJA1 Junction to air, 1 m/s air flow 37 °C/W 1 θJA3 Junction to air, 3 m/s air flow 33 °C/W 1 θJA5 Junction to air, 5 m/s air flow 32 °C/W 1 θJC Junction to case 57.3 °C/W 1 θJb Junction to base 24.3 °C/W 1 θJA0 Junction to air, still air 79.8 °C/W 1 θJA1 Junction to air, 1 m/s air flow 73.9 °C/W 1 θJA3 Junction to air, 3 m/s air flow 69.9 °C/W 1 θJA5 Junction to air, 5 m/s air flow 67.3 °C/W 1 NBG24 LTG24 EPAD soldered to board. ©2020 Renesas Electronics Corporation 8 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Table 6. Thermal Characteristics–16-pin Devices Parameter Thermal Resistance (devices with external crystal) Thermal Resistance Q-series (devices with internal crystal) 1 Symbol Conditions Package Typical Values Units Notes θJC Junction to case 66 °C/W 1 θJb Junction to base 5.1 °C/W 1 θJA0 Junction to air, still air 63 °C/W 1 θJA1 Junction to air, 1 m/s air flow 56 °C/W 1 θJA3 Junction to air, 3 m/s air flow 51 °C/W 1 θJA5 Junction to air, 5 m/s air flow 49 °C/W 1 θJC Junction to case 82.1 °C/W 1 θJb Junction to base 42.3 °C/W 1 θJA0 Junction to air, still air 93.6 °C/W 1 θJA1 Junction to air, 1 m/s air flow 87.1 °C/W 1 θJA3 Junction to air, 3 m/s air flow 83.3 °C/W 1 θJA5 Junction to air, 5 m/s air flow 66 °C/W 1 LTG16 LTG16 EPAD soldered to board. Recommended Operating Conditions Table 7. Recommended Operating Conditions Symbol Minimum Typical Maximum Units Power supply voltage for supporting 1.8V outputs. 1.71 1.8 1.89 V Power supply voltage for supporting 2.5V outputs. 2.375 2.5 2.625 V Power supply voltage for supporting 3.3V outputs. 3.135 3.3 3.465 V VDDD Power supply voltage for core logic functions. 1.71 3.465 V VDDA Analog power supply voltage. Use filtered analog power supply if available. 1.71 3.465 V TA Operating temperature, ambient. -40 85 °C CL Maximum load capacitance (3.3V LVCMOS only). 15 pF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic). 5 ms VDDOx Parameter ©2020 Renesas Electronics Corporation 9 0.05 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Electrical Characteristics VDDx = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Table 8. Common Electrical Characteristics Parameter Input Frequency Output Frequency (OUT[3:0]) Output Frequency (OUT[1:0]) Symbol fIN fOUT Conditions Minimum Typical Maximum Units Notes Crystal input frequency. 8 50 MHz 1 CLKIN input frequency. 1 240 MHz 5 Differential clock output (LVDS/LP-HCSL). 1 325 MHz Single-ended clock output (LVCMOS). 1 200 MHz Spread spectrum or fractional configuration. 1 156.25 MHz 2600 MHz VCO Frequency fVCO VCO operating frequency range. 2400 Loop Bandwidth fBW Input frequency = 25MHz. 0.06 0.9 MHz Input High Voltage VIH SEL[1:0]. 0.7 x VDDD VDDD + 0.3 V Input Low Voltage VIL SEL[1:0]. GND - 0.3 0.8 V Input High Voltage VIH REF/SEL_I2C#. 0.65 x VDDREF VDDREF + 0.3 V Input Low Voltage VIL REF/SEL_I2C#. -0.3 0.4 V Input High Voltage VIH XIN/CLKIN. 0.8 1.2 V Input Low Voltage VIL XIN/CLKIN. -0.3 0.4 V OEA, OEB (24-pin device only) 10 ns SEL1/SDA, SEL0/SCL. 300 ns 3 7 pF Input Rise/Fall Time TR/TF SEL[1:0]. 2500 Input Capacitance CIN Internal Pull-up Resistor RUP 200 237 300 kΩ RDOWN 200 237 300 kΩ 8 pF Internal Pull-down Resistor Programmable capacitance at XIN and XO (XIN in parallel with XO) CL XIN/CLKIN, XO. 0 Input Duty Cycle t2 CLKIN, measured at VDDREF/2. 40 50 60 % LVCMOS, fOUT > 156.25MHz. 40 50 60 % LVCMOS, fOUT < 156.25MHz. 45 50 55 % LVDS, LP-HCSL outputs. 45 50 55 % Output Duty Cycle t3 ©2020 Renesas Electronics Corporation 10 6 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Table 8. Common Electrical Characteristics (Cont.) Parameter Symbol 3 6 7 Units Notes 4 Reference clock RMS phase jitter (12kHz to 5MHz integration range). See “Test Frequencies for Jitter Measurements” for configurations. 250 fs rms 4 OUTx RMS phase jitter(12kHz to 20MHz integration range) differential output. See “Test Frequencies for Jitter Measurements” for configurations. 267 fs rms 4 Cycle-to-cycle jitter (Peak-to-Peak), See “Test Frequencies for Jitter Measurements” for configurations. 27 ps 4 Reference clock RMS phase jitter (12kHz to 5MHz integration range). See “Test Frequencies for Jitter Measurements” for configurations. 317 fs rms 4 OUTx RMS phase jitter(12kHz to 20MHz integration range) differential output. See “Test Frequencies for Jitter Measurements” for configurations. 224 fs rms 4 t7 Skew between the same frequencies, with outputs using the same driver format. 34 ps 7 t8a PLL outputs valid from VDDs reaching 1.5V. 5 10 ms 2,3 t8b REF outputs valid from VDDs reaching 1.5V. 5 11 ms 2,3 t6 t6 Practical lower frequency is determined by loop filter settings. Includes loading the configuration bits from OTP to registers. Actual PLL lock time depends on the loop configuration. 4 Actual 5 Maximum ps Output Skew (9FGV1004) 2 Typical 27 Clock Jitter (9FGV1008) 1 Minimum Cycle-to-cycle jitter (Peak-to-Peak), See “Test Frequencies for Jitter Measurements” for configurations. Clock Jitter (9FGV1004) Lock Time Conditions jitter is configuration dependent. These values are representative of what the device can achieve. Input doubler off. Maximum input frequency with input doubler on is 160MHz. With internal low pass filter enabled. When disabled, maximum frequency is 325MHz. 9FGV1004 OUT0 and OUT1. ©2020 Renesas Electronics Corporation 11 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Table 9. Test Frequencies for Jitter Measurements Device XIN/CLKIN 9FGV1004 9FGV1004Q5 50 100 Device XIN/CLKIN OUT0 9FGV1008 9FGV1008Q5 50 100 1 All 2 3 OUT0 OUT1 OUT2 OUT3 Unit Notes 125.00 156.25 MHZ 1,2,3 OUT1 Unit Notes 156.25 MHZ 1,2,3 outputs measured with 100MHz outputs both spreading and non-spreading. Outputs configured as LP-HCSL or LVDS with REF output off unless noted. This configuration used for 12kHz–20MHz OUT phase jitter measurement. REF off, SSC off. Table 10. LVCMOS Output Electrical Characteristics Parameter Symbol Slew Rate SR Conditions Minimum Typical Maximum Units 3.3V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 2.6 3.7 4.7 V/ns 2.5V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 1.5 2.4 4.7 V/ns 1.8V ±5%, 20% to 80% of VDDO (output load = 4.7pF). 1.0 1.7 3.2 V/ns VDDO V 0.22 0.4 V 5 μA Output High Voltage VOH IOH = -15mA at 3.3V. IOH = -12mA at 2.5V. IOH = -8mA at 1.8V. Output Low Voltage VOL IOL = 15mA at 3.3V. IOL = 12mA at 2.5V. IOL = 8mA at 1.8V. 0.8 x VDDO Output Leakage Current IOZDD Outputs tri-stated, VDDO, VDDREF = 3.465V. 0 CMOS Output Driver Impedance ROUT TA = 25°C. 17 Notes Ω Table 11. LVDS Output Electrical Characteristics Parameter Symbol Minimum Typical Maximum Units Differential Output Voltage for the TRUE Binary State VOT (+) 247 328 454 mV Differential Output Voltage for the FALSE Binary State VOT (-) -454 -332 -247 mV Change in VOT between Complementary Output States ΔV OT 50 mV Output Common Mode Voltage (Offset Voltage) at 3.3V +5% and 2.5V +5% VOS 1.125 1.19 1.55 V Output Common Mode Voltage (Offset Voltage) at 1.8V +5% VOS 0.8 0.86 0.95 V Change in VOS between Complementary Output States ΔVOS 0 50 mV Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or V DD IOS 6 12 mA Differential Outputs Short Circuit Current, VOUT+ = VOUT- IOSD 3 12 mA ©2020 Renesas Electronics Corporation 12 Notes October 29, 2020 9FGV1004C/9FGV1008C Datasheet Table 11. LVDS Output Electrical Characteristics (Cont.) Parameter Symbol Minimum Typical Maximum Units Rise Times Tested at 20% – 80% TR 257 375 ps Fall Times Tested at 80% – 20% TF 287 375 ps Notes Table 12. Low-Power (LP) Push-Pull HCSL Differential Outputs VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol Slew Rate TR/F Slew Rate Matching ΔTR/F Conditions Scope averaging on. Minimum Typical Maximum Units 1 Crossing Voltage (abs) VCROSS Scope averaging off. Crossing Voltage (var) ΔVCROSS Scope averaging off. Average Clock Period Accuracy TPERIOD_AVG Absolute Period TPERIOD_ABS Includes jitter and spread modulation. 2.5 4 V/ns 2,3,16 9 20 % 1,14,16 424 550 mV 1,4,5,16 16 140 mV 1,4,9,16 -100 0 +2600 ppm 2,10,12,13 9.949 10 10.101 ns 2,6 250 Outputs set to 100MHz for PCIe applications. Notes Absolute Maximum Voltage VMAX Includes 300mV of overshoot (Vovs). 660 808 1150 mV 1,7,15 Absolute Minimum Voltage VMIN Includes -300mV of undershoot (Vuds). -300 -54 150 mV 1,8,15 1  Measured from single-ended waveform. 2 Measured 3 Measured 4 from differential waveform. from -150mV to +150mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-. 5 Refers to the total variation from the lowest crossing point to the 6 7 8 9 measurement. highest, regardless of which edge is crossing. Refers to all crossing points for this Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative ppm tolerance, and spread spectrum modulation. Defined as the maximum instantaneous voltage including overshoot. Defined as the minimum instantaneous voltage including undershoot. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the maximum allowed variance in VCROSS for any particular system. 10 11 Refer to Section 8.6 of the PCI Express Base Specification, Revision 4.0 for information regarding PPM considerations. System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single-ended probes must be used for measurements requiring single-ended measurements. Either single-ended probes with math or differential probe can be used for differential measurements. Test load CL = 2pF. 12 PCIe Gen1 through Gen4 specify ±300ppm frequency tolerances. The PhiClock devices already meet the tighter ±100ppm frequency tolerances proposed for PCIe Gen5 and required by most servers. 13 “ppm” refers to parts per million and is a DC absolute period accuracy specification. 1ppm is 1/1,000,000th of 100.000000MHz exactly or 100Hz. For 100ppm, then we have an error budget of 100Hz/ppm × 100ppm = 10kHz. The period is to be measured with a frequency counter with measurement window set to 100ms or greater. The ±100ppm applies to systems that do not employ Spread Spectrum Clocking, or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,600ppm for Common Clock Architectures. Separate Reference Clock Architectures may have a lower allowed spread percentage. ©2020 Renesas Electronics Corporation 13 October 29, 2020 9FGV1004C/9FGV1008C Datasheet 14 15 16 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge rate of REFCLK+ should be compared to the fall edge rate of REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate. At default amplitude settings. Guaranteed by design and characterization. Table 13. Filtered Phase Jitter Parameters – PCIe Common Clocked (CC) Architectures TAMB = over the specified operating range. Supply Voltages per normal operation conditions; see Test Loads for loading conditions. Parameter Typical Maximum Industry Limits Units Notes PCIe Gen1. 24 43 86 ps (p-p) 1,2,3 PCIe Gen2 Low Band 10kHz < f < 1.5MHz (PLL BW of 5–16MHz, 8–16MHz, CDR = 5MHz). 0.7 1.4 3 ps (rms) 1,2 PCIe Gen2 High Band 1.5MHz < f < Nyquist (50MHz) (PLL BW of 5–16MHz, 8–16MHz, CDR = 5MHz). 1.8 2.6 3.1 ps (rms) 1,2 tjphPCIeG3-CC PCIe Gen3 (PLL BW of 2–4MHz, 2–5MHz, CDR = 10MHz). 0.44 0.65 1 ps (rms) 1,2 tjphPCIeG4-CC PCIe Gen4 (SSC off) (PLL BW of 2–4MHz, 2–5MHz, CDR = 10MHz). 0.30 0.44 0.5 ps (rms) 1,2,6,7 Symbol Conditions tjphPCIeG1-CC tjphPCIeG2-CC PCIe Phase Jitter Minimum Table 14. Filtered Phase Jitter Parameters – PCIe Independent Reference (IR) Architectures TAMB = over the specified operating range. Supply Voltages per normal operation conditions; see Test Loads for loading conditions. Parameter PCIe Phase Jitter Typical Maximum Industry Limits Units Notes PCIe Gen2 (-0.5% SSC) (PLL BW of 16MHz, CDR = 5MHz). 1.2 1.53 2 ps (rms) 1,2,4,5 PCIe Gen3 (SSC off) (PLL BW of 2–4MHz, CDR = 10MHz). 0.37 0.45 0.7 ps (rms) 1,2,4, 5,6 Symbol Conditions tjphPCIeG2-SRnS tjphPCIeG3-SRnS Minimum Notes for all PCIe Filtered Phase Jitter tables: 1 2 3 4 5 Applies to all differential outputs, guaranteed by design and characterization. Based on PCIe Base Specification Rev4.0 version 1.0. See http://www.pcisig.com for latest specifications. Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12. IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock architectures. According to the PCIe Base Specification Rev4.0 version 1.0, the jitter transfer functions and corresponding jitter limits are not defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this table. The PCIe Base Specification Rev5.0 is expected to resolve this. ©2020 Renesas Electronics Corporation 14 October 29, 2020 9FGV1004C/9FGV1008C Datasheet 6 7 For improved PCIe performance, including PCIe Gen5, see application note AN1001. SSC off. Table 15. Current Consumption–9FGV1004 VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol Conditions VDDREF Supply Current IDDREF Core Supply Current IDDCORE Output Buffer Supply Current (VDDO3) Output Buffer Supply Current (VDDO2) IDDOx Output Buffer Supply Current (VDDO1) Output Buffer Supply Current (VDDO0) Total Power Down Current 1 2 3 IDDPD Minimum Typical Maximum Units Notes 50MHz REFCLK, subtract 3mA for 25MHz REFCLK. 7 11 mA 2500MHz VCO, 50MHz REFCLK. 30 42 mA 3 LVDS, 325MHz 18 24 mA 2 LP-HCSL, 100MHz 12 21 mA 2 LVCMOS, 50MHz 14 19 mA 1,2 LVCMOS, 200MHz 21 35 mA 1,2 LVDS, 325MHz 18 24 mA 2 LP-HCSL, 100MHz 16 21 mA 2 LVCMOS, 50MHz 14 19 mA 1,2 LVCMOS, 200MHz 21 35 mA 1,2 LVDS, 325MHz, SSC Off 8 11 mA 2 LP-HCSL, 100MHz, SSC Off 6 8 mA 2 LP-HCSL, 100MHz, SSC On 14 18 mA 2 LVCMOS, 50MHz, SSC Off 5 7 mA 1,2 LVCMOS, 50MHz, SSC On 9 12 mA 1,2 LVCMOS, 200MHz, SSC Off 13 24 mA 1,2 LVDS, 325MHz 16 21 mA 2 LP-HCSL, 100MHz 15 18 mA 2 LVCMOS, 50MHz 13 17 mA 1,2 LVCMOS, 200MHz 21 34 mA 1,2 Programmable outputs in HCSL mode, B37[0] = 0. 20 26 mA 1,2 Programmable outputs in LVDS mode, B37[0] = 0. 31 43 mA 1,2 Programmable outputs in LVCMOS1 mode, B37[0] = 0. 16 20 mA 1,2 Single CMOS driver active for each output pair. See Test Loads for details. IDDCORE = IDDA + IDDD. ©2020 Renesas Electronics Corporation 15 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Table 16. Current Consumption–9FGV1008 VDDO = 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, TA = -40°C to +85°C unless stated otherwise. Parameter Symbol VDDREF Supply Current IDDREF Core Supply Current IDDCORE Output Buffer Supply Current (VDDO1) IDDOx Output Buffer Supply Current (VDDO0) Total Power Down Current 1 2 3 IDDPD Conditions Minimum Typical Maximum Units Notes 50MHz REFCLK. 5 7 mA 2500MHz VCO, SSC off. 32 45 mA 3 2500MHz VCO, SSC on. 39 56 mA 3 LVDS, 325MHz. 18 22 mA 2 LP-HCSL, 100MHz. 16 21 mA 2 LVCMOS, 50MHz. 14 18 mA 1,2 LVCMOS, 200MHz. 22 34 mA 1,2 LVDS, 325MHz. 16 21 mA 2 LP-HCSL. 16 20 mA 2 LVCMOS, 50MHz. 13 18 mA 1,2 LVCMOS, 200MHz. 21 33 mA 1,2 Programmable outputs in HCSL mode, B37[0] = 0. 19 25 mA 1,2 Programmable outputs in LVDS mode, B37[0] = 0. 25 35 mA 1,2 Programmable outputs in LVCMOS1 mode, B37[0] = 0. 17 23 mA 1,2 Single CMOS driver active for each output pair. See Test Loads for details. IDDCORE = IDDA + IDDD + IDDAO. Table 17. 9FGV1004C/9FGV1008C Spread Spectrum Programmability Parameter Symbol Mod Frequency fMODPCIe Mod Frequency fMOD Conditions Minimum Typical Maximum Units PCIe Compliant -0.5% spread modulation. 30 31.5 33 kHz Modulation frequency. 30 63 kHz Spread% SSC% Spread amount – down spread. -0.1 -3 % Spread% SSC% Spread amount – center spread. ±0.05 ±1.5 % ©2020 Renesas Electronics Corporation 16 October 29, 2020 9FGV1004C/9FGV1008C Datasheet I2C Bus Characteristics Table 18. I2C Bus DC Characteristics Parameter Symbol Conditions Minimum Input High Level VIH — 0.7 x VDDD Input Low Level VIL — VHYS — 0.05 x VDDD Input Leakage Current IIN — -1 Output Low Voltage VOL IOL = 3mA. Hysteresis of Inputs Typical Maximum Units V 0.3 x VDDD V V 30 μA 0.4 V Maximum Units 400 kHz Table 19. I2C Bus AC Characteristics Parameter Symbol Conditions Minimum FSCLK — 10 tBUF — 1.3 μs Setup Time, START tSU:START — 0.6 μs Hold Time, START tHD:START — 0.6 μs Setup Time, Data Input (SDA) tSU:DATA — 0.1 μs 1 tHD:DATA — 0 μs tOVD — 0.9 μs Capacitive Load for Each Bus Line CB — 400 pF Rise Time, Data and Clock (SDA, SCL) tR — 20 + 0.1 x CB 300 ns Fall Time, Data and Clock (SDA, SCL) tF — 20 + 0.1 x CB 300 ns High Time, Clock (SCL) tHIGH — 0.6 μs Low Time, Clock (SCL) tLOW — 1.3 μs tSU:STOP — 0.6 μs Serial Clock Frequency (SCL) Bus free time between STOP and START Hold Time, Data Input (SDA) Output Data Valid from Clock Setup Time, STOP Typical 1 A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. ©2020 Renesas Electronics Corporation 17 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Test Loads Figure 4. LVCMOS AC/DC Test Load Test Point L Zo Rs CL Rs Zo L CL 33Ω 50Ω 5 inches 4.7pF Figure 5. LP-HCSL AC/DC Test Load (Standard PCIe source-terminated test load) Rs CL L Test Points Differential Zo CL Rs Rs Zo L CL Internal 100Ω 5 inches 2pF Internal 85Ω 5 inches 2pF Figure 6. LVDS AC/DC Test Load L Differential Zo 100ohm Rs Zo L CL N/A 100Ω 5 inches N/A ©2020 Renesas Electronics Corporation 18 Test Points October 29, 2020 9FGV1004C/9FGV1008C Datasheet Figure 7. Test Setup for PCIe Measurement Using a Real-Time Scope Real Time Scope SMA Connectors Rs Coax Cables L Differential Zo 0.1µF 50 50 Rs Rs Zo L CL Internal 100Ω 5 inches N/A Figure 8. Test Setup for PCIe Measurement Using a Phase Noise Analyzer SMA Connectors L CK+ 0.1uF CK- 50 Rs Zo L CL Internal 100Ω 5 inches N/A ©2020 Renesas Electronics Corporation Coax Cables Balun Zo (differential) DUT Phase Noise Analyzer 19 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Crystal Characteristics Table 20. Recommended Crystal Characteristics Parameter Value Units Frequency 8 – 50 MHz Resonance Mode Fundamental — Frequency Tolerance at 25°C ±20 ppm maximum Frequency Stability, REF at 25°C Over Operating Temperature Range ±20 ppm maximum Temperature Range (commercial) 0 to +70 °C Temperature Range (industrial) -40 to +85 °C Equivalent Series Resistance (ESR) 50 Ω maximum Shunt Capacitance (CO) 7 pF maximum Load Capacitance (CL) 8 pF maximum Drive Level 0.1 mW maximum Aging per year ±5 ppm maximum Package Drawings The package outline drawings are appended at the end of this document and are also accessible from the link below. The package information is the most current data available and is subject to change without notice or revision of this document. 9FGV1004C: www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-075-mm-body-05mm-pitch-epad-26-x-26-mm-nbnbg24p2 www.idt.com/us/en/document/psc/lga24l-package-outline-drawing-40-x-40-x-155-mm-body-050mm-pitch-ltg24t1 9FGV1008C: www.idt.com/us/en/document/psc/16-lga-package-outline-drawing30-x-30-x-110-mm-body-05mm-pitchltg16p1 ©2020 Renesas Electronics Corporation 20 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Marking Diagrams 24-VFQFPN 9FGV100 4CnnnGI #YWW**$ ▪ Lines 1 and 2 are the truncated part number. ▪ Line 3: • “#” denotes the stepping number. • “YWW” denotes the last digits of the year and week the part was assembled. • “**” denotes the lot sequence. • “$” denotes the mark code. 24-LGA (with internal crystal) 1004C Q5aa YWW**$ ▪ Lines 1 and 2 are the truncated part number. ▪ Line 3: • “YWW” denotes the last digits of the year and week the part was assembled. • “**” denotes the lot sequence. • “$” denotes the mark code. 16-LGA 8Cnnn YWW$ XXX ▪ Line 1 is the truncated part number. ▪ Line 2: • “YWW” denotes the last digits of the year and week the part was assembled. • “$” denotes the mark code. ▪ Line 3: • “XXX” denotes the last three characters of the assembly lot number. 16-LGA (with internal crystal) 8CQ5aa YWW$ XXX ▪ Line 1 is the truncated part number. ▪ Line 2: • “YWW” denotes the last digits of the year and week the part was assembled. • “$” denotes the mark code. ▪ Line 3: • “XXX” denotes the last three characters of the assembly lot number. ©2020 Renesas Electronics Corporation 21 October 29, 2020 9FGV1004C/9FGV1008C Datasheet Standard Configurations Table 21. 9FGV1004C/9FGV1008C Standard Configurations Supply Voltage–all pins (V) Output Impedance (ohms) Number of PCIe Clock Outputs 4 3.3 and 1.8 100 (LP-HCSL) 2 XTAL Frequency (MHz) Orderable Part Number (Bulk) Orderable Part Number (Tape and Reel) 50 – external 9FGV1004C001NBGI 9FGV1004C001NBGI8 50 – internal 9FGV1004CQ501LTGI 9FGV1004CQ501LTGI8 50 – external 9FGV1008C001LTGI 9FGV1008C001LTGI8 50 – internal 9FGV1008CQ501LTGI 9FGV1008CQ501LTGI8 Table 22. Common Features of 9FGV1004C/9FGV1008C Standard Configurations Configuration 0 1 2 3 9FGV1004 Output 9FGV1008 Output OUT0 OUT0 100 1.8 LP-HCSL OUT1 — 100 1.8 LP-HCSL OUT2 OUT1 125 1.8 LVDS OUT3 — 50 1.8 LP-HCSL OUT0 OUT0 100 1.8 LP-HCSL OUT1 — 100 1.8 LP-HCSL OUT2 OUT1 156.25 1.8 LVDS OUT3 — 50 1.8 LP-HCSL OUT0 OUT0 100 3.3 LP-HCSL OUT1 — 100 3.3 LP-HCSL OUT2 OUT1 125 3.3 LVDS OUT3 — 50 3.3 LP-HCSL OUT0 OUT0 100 3.3 LP-HCSL OUT1 — 100 3.3 LP-HCSL OUT2 OUT1 156.25 3.3 LVDS OUT3 — 50 3.3 LP-HCSL ©2020 Renesas Electronics Corporation Output Frequency (MHz) Supply Voltage (V) 22 Output Type Ref Outputs OFF OFF OFF OFF October 29, 2020 9FGV1004C/9FGV1008C Datasheet Ordering Information Orderable Part Number Package Carrier Type Temperature Crystal 9FGV1004CnnnNBGI 4 × 4 mm, 0.5mm pitch 24-VFQFPN Tray -40 to +85°C External 9FGV1004CnnnNBGI8 4 × 4 mm, 0.5mm pitch 24-VFQFPN Tape and Reel -40 to +85°C External 9FGV1004CQ5aaLTGI 4 × 4 mm, 0.5mm pitch 24-LGA Tray -40 to +85°C 50MHz Internal 9FGV1004CQ5aaLTGI8 4 × 4 mm, 0.5mm pitch 24-LGA Tape and Reel -40 to +85°C 50MHz Internal 9FGV1008CnnnLTGI 3 × 3 mm, 0.5mm pitch 16-LGA Tray -40 to +85°C External 9FGV1008CnnnLTGI8 3 × 3 mm, 0.5mm pitch 16-LGA Tape and Reel -40 to +85°C External 9FGV1008CQ5aaLTGI 3 × 3 mm, 0.5mm pitch 16-LGA Tray -40 to +85°C 50MHz Internal 9FGV1008CQ5aaLTGI8 3 × 3 mm, 0.5mm pitch 16-LGA Tape and Reel -40 to +85°C 50MHz Internal “G” indicates RoHS 6.6 compliance. “nnn” are decimal digits indicating a specific configuration. “aa” are alphanumeric digits indicating a specific configuration. “Q5” indicates internal 50MHz crystal. Revision History Revision Date Description of Change October 29, 2020 Updated pin descriptions for VDDAp and VDDDp. October 20, 2020 Added Test Loads section and diagrams. September 28, 2020 Added Standard Configurations section and tables. September 22, 2020 Correct all fOUT minimum frequencies from 10MHz to 1MHz in Common Electrical Characteristics table. August 18, 2020 Updated 9FGV1008CQ (16-LGA with internal crystal) marking diagram. August 14, 2020 Updated Slew Rate 1.8V minimum value from 0.8 to 1.0V/ns. August 13, 2020 Updated Carrier Type in Ordering Information table from “Trays” to “Tray”. July 20, 2020 Corrected internal resistors from pull-up to pull-down on SEL0/SCL and SEL1/SDA pins. April 16, 2020 Initial release. ©2020 Renesas Electronics Corporation 23 October 29, 2020 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm NB/NBG24P2, PSC-4313-02, Rev 01, Page 1 TOP VIEW BOTTOM VIEW SIDE VIEW 24-VFQFPN, Package Outline Drawing 4.0 x 4.0 x 0.75 mm Body, 0.5mm Pitch, Epad 2.6 x 2.6 mm NB/NBG24P2, PSC-4313-02, Rev 01, Page 2 Package Revision History Description Date Created Rev No. Jan 24, 2018 Rev 01 Change QFN to VFQFPN and New Format May 11, 2016 Rev 00 Initial Release 16-LGA Package Outline Drawing 3.0 x 3.0 x 1.10 mm Body, 0.5mm Pitch LTG16P1, PSC-4651-01, Rev 02, Page 1 16-LGA Package Outline Drawing 3.0 x 3.0 x 1.10 mm Body, 0.5mm Pitch LTG16P1, PSC-4651-01, Rev 02, Page 2 Package Revision History Description Date Created Rev No. Nov 6, 2017 Rev 02 Modify Solder Mask & Epad Chamfer Sept 29, 2017 Rev 01 Modify Land Pattern IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.
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