ICS9LPRS365
Integrated
Circuit
Systems, Inc.
Advance Information
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
Output Features:
•
2 - CPU differential low power push-pull pairs
•
9 - SRC differential low power push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull pair
•
1 - SRC/DOT selectable differential low power push-pull pair
•
5 - PCI, 33MHz
•
1 - PCI_F, 33MHz free running
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
•
Does not require external pass transistor for voltage
regulator
•
Integrated 33ohm series resistors on differential outputs,
Zo=50Ω
• Supports spread spectrum modulation, default is 0.5% down
spread
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Pin Configuration
PCI0/CR#_A
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_Select
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
SRCT0/DOTT_96
SRCC0/DOTC_96
GND
VDDPLL3
27MHz_NonSS/SRCT1/SE1
27MHz_SS/SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
SRCT3/CR#_C
SRCC3/CR#_D
VDDSRC_IO
SRCT4
SRCC4
GNDSRC
SRCT9
SRCC9
SRCC11/CR#_G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
9LPRS365
Recommended Application:
CK505 compliant clock with fully integrated voltage regulator
and Internal series resistor on differential outputs
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0
CPUC0
GNDCPU
CPUT1_F
CPUC1_F
VDDCPU_IO
NC
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
VDDSRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
GNDSRC
SRCT6
SRCC6
VDDSRC
PCI_STOP#
CPU_STOP#
VDDSRC_IO
SRCC10
SRCT10
SRCT11/CR#_H
64-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
64-TSSOP
27_Select (power on latch)
Pin13/14 & Pin17/18
Selectable between one SRC differential push-pull pair
and two single-ended outputs
0
1
DOT96, LCD_SS
SRC0, 27MHz Non SS & SS
Byte1 bit7 = 1.
Byte1 bit7 = 0.
Table 1: CPU Frequency Select Table
2
FSLC
B0b7
0
0
0
0
1
1
1
1
1
FSLB
B0b6
0
0
1
1
0
0
1
1
1
FSLA
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
1218—09/09/09
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS9LPRS365
Advance Information
TSSOP Pin Description
PIN #
PIN NAME
1
PCI0/CR#_A
2
VDDPCI
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_Select
TYPE
DESCRIPTION
I/O
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair
0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first
be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
PWR
Power supply pin for the PCI outputs, 3.3V nominal
I/O
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair
1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first
be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
I/O
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as
follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
OUT
I/O
I/O
3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on this pin
determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the function table for the
pin17 and pin18.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the
PCI_STOP# pin. On powerup, the state of this pin determines whether pins 46 and 47 are an ITP or SRC
pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
7
PCI_F5/ITP_EN
8
GNDPCI
PWR
Ground for PCI clocks.
9
VDD48
PWR
10
USB_48MHz/FSLA
11
GND48
PWR
Power supply for USB clock, nominal 3.3V.
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
Ground pin for the 48MHz outputs.
12
VDD96_IO
PWR
1.05V to 3.3V from external power supply
13
DOTT_96/SRCT0
OUT
True clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0,
0=DOT96
14
DOTC_96/SRCC0
OUT
I/O
15
GND
PWR
Complement clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0,
0=DOT96
Ground pin for the DOT96 clocks.
16
VDD
PWR
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
1218—09/09/09
2
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
19
GND
PWR
True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the power-up
default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. See table 2 for more
information.
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the
power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential clock. See table 2 for
more information.
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
20
VDDPLL3_IO
PWR
1.05V to 3.3V from external power supply
21
SRCT2/SATAT
OUT
True clock of differential SRC/SATA clock pair.
22
SRCC2/SATAC
OUT
Complement clock of differential SRC/SATA clock pair.
23
GNDSRC
PWR
24
SRCT3/CR#_C
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
17
27MHz_NonSS/SRCT1/SE1
OUT
18
27MHz_SS/SRCC1/SE2
OUT
25
SRCC3/CR#_D
26
VDDSRC_IO
27
SRCT4
I/O
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4
pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
PWR
1.05V to 3.3V from external power supply
I/O
True clock of differential SRC clock pair 4
I/O
Complement clock of differential SRC clock pair 4
28
SRCC4
29
GNDSRC
PWR
Ground pin for SRC clocks.
30
SRCT9
OUT
True clock of differential SRC clock pair.
31
SRCC9
OUT
32
SRCC11/CR#_G
I/O
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
1218—09/09/09
3
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
I/O
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
33
SRCT11/CR#_H
34
SRCT10
OUT
True clock of differential SRC clock pair.
35
SRCC10
OUT
Complement clock of differential SRC clock pair.
36
VDDSRC_IO
PWR
37
CPU_STOP#
IN
38
PCI_STOP#
39
VDDSRC
PWR
1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
VDD pin for SRC Pre-drivers, 3.3V nominal
40
SRCC6
OUT
Complement clock of low power differential SRC clock pair.
41
SRCT6
OUT
True clock of low power differential SRC clock pair.
42
GNDSRC
PWR
43
SRCC7/CR#_E
IN
I/O
44
SRCT7/CR#_F
I/O
45
VDDSRC_IO
PWR
46
CPUC2_ITP/SRCC8
OUT
47
CPUT2_ITP/SRCT8
OUT
48
NC
N/A
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function
of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as
follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
1218—09/09/09
4
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
49
VDDCPU_IO
PWR
1.05V to 3.3V from external power supply
50
CPUC1_F
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
51
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
52
GNDCPU
PWR
Ground Pin for CPU Outputs
53
CPUC0
OUT
Complement clock of low power differential CPU clock pair.
54
CPUT0
OUT
True clock of low power differential CPU clock pair.
55
VDDCPU
PWR
56
CK_PWRGD/PD#
IN
57
FSLB/TEST_MODE
IN
58
GNDREF
PWR
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and
Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in
test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
59
X2
OUT
Crystal output, nominally 14.318MHz.
60
X1
IN
Crystal input, Nominally 14.318MHz.
61
VDDREF
62
REF0/FSLC/TEST_SEL
I/O
63
SDATA
I/O
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable
test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
64
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
PWR
Power Supply 3.3V nominal.
1218—09/09/09
5
ICS9LPRS365
Advance Information
GNDREF
1
CPUC1_F
VDDCPU_IO
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
VDDSRC_IO
SRCC7/CR#_E
GNDSRC
56 55 54
53
52 51 50
49
X2
2
X1
3
VDDREF
4
REF0/FSLC/TEST_SEL
5
SDATA
6
SRCT7/CR#_F
CPUT1_F
57
NC
CPUC0
60 59 58
GNDCPU
CPUT0
61
CK_PWRGD/PD#
64 63 62
FSLB/TEST_MODE
VDDCPU
Pin Configuration
48 SRCT6
47 SRCC6
46 VDDSRC
45 PCI_STOP#
44 CPU_STOP#
43 VDDSRC_IO
SCLK 7
PCI0/CR#_A 8
VDDPCI 9
PCI1/CR#_B 10
PCI2/TME 11
42 SRCC10
41 SRCT10
40 SRCT11/CR#_H
39 SRCC11/CR#_G
9LPRS365
38 SRCC9
37 SRCT9
PCI3 12
PCI4/27_Select 13
36 GNDSRC
35 SRCC4
PCI_F5/ITP_EN 14
GNDPCI 15
34 SRCT4
33 VDDSRC_IO
29 30 31
32
SRCT0/DOTT_96
SRCC0/DOTC_96
GND
27MHz_NonSS/SRCT1/SE1
27MHz_SS/SRCC1/SE2
GND
SRCT2/SATAT
SRCC2/SATAC
SRCC3/CR#_D
SRCT3/CR#_C
28
GNDSRC
25 26 27
VDDPLL3_IO
24
VDDPLL3
21 22 23
VDD96_IO
20
USB_48MHz/FSLA
17 18 19
GND48
VDD48 16
64-pin MLF
64-MLF
27_Select (power on latch)
Pin20/21 & Pin24/25
0
1
DOT96, LCD_SS
SRC0, 27MHz Non SS & SS
Byte1 bit7 = 1
Byte1 bit7= 0.
1218—09/09/09
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ICS9LPRS365
Advance Information
MLF Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
PWR
OUT
IN
PWR
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level
latched input to enable test mode. Refer to Test Clarification Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
1
2
3
4
GNDREF
X2
X1
VDDREF
5
REF0/FSLC/TEST_SEL
I/O
6
7
SDATA
SCLK
I/O
IN
8
PCI0/CR#_A
9
VDDPCI
10
PCI1/CR#_B
I/O
PWR
I/O
11
PCI2/TME
I/O
12
PCI3
13
PCI4/27_Select
I/O
14
PCI_F5/ITP_EN
I/O
15
16
GNDPCI
VDD48
OUT
PWR
PWR
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control
of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control
of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on
power-up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin24, 25 strap. On powerup, the logic value on
this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the
function talbe for the pin24 and pin25.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the
state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 53 and
54 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground for PCI clocks.
Power supply for USB clock, nominal 3.3V.
1218—09/09/09
7
ICS9LPRS365
Advance Information
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
17
USB_48MHz/FSLA
18
19
GND48
VDD96_IO
PWR
PWR
20
DOTT_96/SRCT0
OUT
21
DOTC_96/SRCC0
OUT
22
23
GND
VDD
PWR
PWR
24
27MHz_NonSS/SRCT1/SE1
OUT
25
27MHz_SS/SRCC1/SE2
OUT
26
27
28
29
30
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
PWR
PWR
OUT
OUT
PWR
31
32
SRCT3/CR#_C
SRCC3/CR#_D
I/O
DESCRIPTION
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values.
Ground pin for the 48MHz outputs.
1.05V to 3.3V from external power supply
True clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0,
0=DOT96
Complement clock of SRC or DOT96. The power-up default function depends on 27_Select,1=
SRC0, 0=DOT96
Ground pin for the DOT96 clocks.
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the
power-up default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. See
table 2 for more information.
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select
determines the power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential
clock. See table 2 for more information.
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
I/O
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1
or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
1218—09/09/09
8
ICS9LPRS365
Advance Information
MLF Pin Description (Continued)
PIN #
33
34
35
36
37
38
39
PIN NAME
VDDSRC_IO
SRCT4
SRCC4
GNDSRC
SRCT9
SRCC9
SRCC11/CR#_G
TYPE
DESCRIPTION
PWR
I/O
I/O
PWR
OUT
OUT
1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
I/O
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of
SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte
6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
I/O
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of
SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using
byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
40
SRCT11/CR#_H
41
42
43
SRCT10
SRCC10
VDDSRC_IO
OUT
OUT
PWR
44
CPU_STOP#
IN
45
PCI_STOP#
IN
46
47
48
VDDSRC
SRCC6
SRCT6
PWR
OUT
OUT
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are
shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted
in from the ICH to set the FSC, FSB, FSA values
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
1218—09/09/09
9
ICS9LPRS365
Advance Information
MLF Pin Description (Continued)
PIN #
49
50
PIN NAME
GNDSRC
SRCC7/CR#_E
TYPE
DESCRIPTION
PWR
Ground for SRC clocks
I/O
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of
SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte
6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
I/O
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of
SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair
must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte
6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
51
SRCT7/CR#_F
52
VDDSRC_IO
PWR
53
CPUC2_ITP/SRCC8
OUT
54
CPUT2_ITP/SRCT8
OUT
55
56
NC
VDDCPU_IO
N/A
PWR
57
CPUC1_F
OUT
58
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
59
60
61
62
63
GNDCPU
CPUC0
CPUT0
VDDCPU
CK_PWRGD/PD#
PWR
OUT
OUT
PWR
IN
64
FSLB/TEST_MODE
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N
divider mode while in test mode. Refer to Test Clarification Table.
IN
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential SRC pair.
The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on
powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is
as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be free-running
during iAMT.
1218—09/09/09
10
ICS9LPRS365
Advance Information
General Description
ICS9LPRS365 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS9LPRS365 is driven with a 14.318MHz crystal. It also provides a tight
ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
X1
REF
R EF
X2
OSC
CPU(1:0)
SRC8/CPU_ITP
CPU
CPU PLL1
SS
SRC
SRC(11-9,4:3, 7:6)
SR C _M A IN
PCI33MHz
SRC
PLL3
SS
PCIF5 (4:0)
PCI33MHz
SRC2/SATA
FSLA
CKPWRGD/PD#
PCI_STOP#
27MHz/SRC1/SE(2:1)
CPU_STOP#
CR#_(A:H)
27_Select
Control
Logic
Differential Output
SE Outputs
TME, ITP_EN
7
FSLC/TESTSEL
FSLB/TESTMODE
27MHz_NonSS
PLL2
Non-SS
SRC0/DOT96
SATA
DOT96MHz
48MHz
48MHz
Power Groups
Pin Number
VDD
GND
49
52
55
52
26, 36, 45
23, 29, 42
39
23, 29, 42
20
19
16
19
12
11
9
11
61
58
2
8
Description
CPUCLK
Low power outputs
Master Clock, Analog
Low power outputs
SRCCLK
PLL 1
Low power outputs
PLL3/SE
PLL 3
DOT 96Mhz
Low power outputs
USB 48
Xtal, REF
PCICLK
1218—09/09/09
11
ICS9LPRS365
Advance Information
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
MAX
UNITS
Maximum Supply Voltage
VDDxxx
Core/Logic Supply
4.6
V
1,2
Maximum Supply Voltage
VDDxxx_IO
Low Voltage Differential I/O Supply
3.8
V
1,2
Maximum Input Voltage
VIH
3.3V LVCMOS Inputs
V
1,2,3
Minimum Input Voltage
VIL
Any Input
GND - 0.5
Storage Temperature
Ts
-
-65
Case Temperature
Tcase
-
Input ESD protection
ESD prot
Human Body Model
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied, nor guaranteed.
3
Maximum input voltage is not to exceed maximum VDD
MIN
4.6
Notes
V
1,2
150
°
1,2
115
°C
1,2
V
1,2
2000
C
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Ambient Operating Temp
Tambient
-
0
70
°C
1
Supply Voltage
VDDxxx
Supply Voltage
3.135
3.465
V
1
Notes
1
Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
1
3.465
V
Input High Voltage
VIHSE
Single-ended inputs
2
VDD + 0.3
V
1
Input Low Voltage
VILSE
Single-ended inputs
VSS - 0.3
0.8
V
1
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
5
uA
1
Input Leakage Current
IINRES
Inputs with pull or pull down resistors
VIN = VDD , VIN = GND
-200
200
uA
1
Output High Voltage
VOHSE
Single-ended outputs, IOH = -1mA
2.4
V
1
Output Low Voltage
VOLSE
Single-ended outputs, IOL = 1 mA
Output High Voltage
VOHDIF
Differential Outputs, IOH = TBD mA
Output Low Voltage
Low Threshold InputHigh Voltage (Test Mode)
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
VOLDIF
Differential Outputs, IOL = TBD mA
VIH_FS_TEST
3.3 V +/-5%
VIH_FS
VIL_FS
Operating Supply Current
Power Down Current
0.4
V
1
0.9
V
1
0.4
V
1
2
VDD + 0.3
V
1
3.3 V +/-5%
0.7
1.5
V
1
3.3 V +/-5%
VSS - 0.3
0.35
V
1
0.7
IDD_DEFAULT
3.3V supply, PLL3 off
95
250
mA
1
IDD_PLL3DIF
3.3V supply, PLL3 Differential Out
106
250
mA
1
IDD_PLL3SE
3.3V supply, PLL3 Single-ended Out
101
250
mA
1
32
80
mA
1
IDD_PD3.3
0.8V supply, Differential IO current,
all outputs enabled
3.3V supply, Power Down Mode
26
30
mA
1
IDD_PDIO
0.8V IO supply, Power Down Mode
0.23
0.5
mA
1
IDD_IO
25
IDD_iAMT3.3
3.3V supply, iAMT Mode
47
80
mA
1
IDD_iAMT0.8
0.8V IO supply, iAMTMode
5
10
mA
1
Input Frequency
Fi
VDD = 3.3 V
14.318
MHz
1
Pin Inductance
Lpin
7
nH
1
CIN
Logic Inputs
5
pF
1
Input Capacitance
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
fSSMOD
Triangular Modulation
33
kHz
1
iAMT Mode Current
Spread Spectrum Modulation
Frequency
*TA = 0 - 70°C; VDD = 3.3 V +/-5%
1
TYPICAL
Guaranteed by design and characterization, not 100% tested in production.
1218—09/09/09
12
1.5
30
ICS9LPRS365
Advance Information
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
SMBus Voltage
VDD
CONDITIONS
@ IPULLUP
Low-level Output Voltage
VOLSMB
Current sinking at
IPULLUP
SMB Data Pin
VOLSMB = 0.4 V
(Max VIL - 0.15) to
SCLK/SDATA
TRI2C
(Min VIH + 0.15)
Clock/Data Rise Time
(Min VIH + 0.15) to
SCLK/SDATA
TFI2C
(Max VIL - 0.15)
Clock/Data Fall Time
Maximum SMBus Operating
FSMBUS
Block Mode
Frequency
1
Guaranteed by design and characterization, not 100% tested in production.
MIN
MAX
UNITS
2.7
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
100
kHz
1
MAX
UNITS
Notes
1.8
ms
1
15
ns
1,2
300
us
1
10
ns
1,2
5
ns
1,2
5
ns
1,2
4
Notes
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
SYMBOL
Clk Stabilization
TSTAB
Tdrive_SRC
TDRSRC
Tdrive_PD#
T DRPD
Tdrive_CPU
TDRSRC
Tfall_PD#
TFALL
Trise_PD#
TRISE
CONDITIONS
From VDD Power-Up or deassertion of PD# to 1st clock
SRC output enable after
PCI_STOP# de-assertion
Differential output enable after
PD# de-assertion
CPU output enable after
CPU_STOP# de-assertion
MIN
Fall/rise time of PD#, PCI_STOP#
and CPU_STOP# inputs
1
Guaranteed by design and characterization, not 100% tested in production.
2
Optional. Only applies when PCI_STOP# and/or CPU_STOP# is present.
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
NOTES
Rising Edge Slew Rate
tSLR
Differential Measurement
2.5
8
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
2.5
8
V/ns
1,2
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
VHIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
VSWING
Differential Measurement
300
mV
1
300
550
mV
1,3,4
140
mV
1,3,5
55
%
1
Crossing Point Voltage
VXABS
Single-ended Measurement
Crossing Point Variation
VXABSVAR
Single-ended Measurement
Duty Cycle
DCYC
Differential Measurement
CPU Jitter - Cycle to Cycle
CPUJ C2C
Differential Measurement
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJ C2C
Differential Measurement
125
ps
1
DOT Jitter - Cycle to Cycle
DOTJ C2C
Differential Measurement
250
ps
1
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC[10:0] Skew
SRCSKEW
Differential Measurement
TBD
ps
1
45
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =5pF, RS=22Ω (unless specified otherwise.)
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#.
5
1218—09/09/09
13
ICS9LPRS365
Advance Information
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
NOTES
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
30.00900
ns
2
30.15980
ns
2
30.65980
ns
2
V
1
V
1
33.33MHz output nominal
Clock period
Tperiod
Absolute min/max period
Tabs
33.33MHz output nominal/spread
29.49100
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
Output High Current
IOH
Output Low Current
IOL
33.33MHz output spread
29.99100
IOL = 1 mA
V OH @MIN = 1.0 V
0.4
-33
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
VOL @ MAX = 0.4 V
mA
1
mA
1
mA
1
38
mA
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Skew
tskew
VT = 1.5 V
250
ps
1
Intentional PCI-PCI delay
tdelay
VT = 1.5 V
ps
1,3
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
ps
1
200 nominal
500
*TA = 0 - 70°C; VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
See PCI Clock-to-Clock Delay Figure
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
1218—09/09/09
14
ICS9LPRS365
Advance Information
Electrical Characteristics - USB48MHz
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
MIN
-100
MAX
100
UNITS
ppm
NOTES
Clock period
T period
48.00MHz output nominal
20.83125
20.83542
ns
2
Absolute min/max period
Tabs
48.00MHz output nominal
20.48130
21.18540
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
V OH @MIN = 1.0 V
IOH
Output Low Current
IOL
0.4
-29
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
-23
V
1
mA
1
mA
1
mA
1
27
mA
1
29
VOL @ MAX = 0.4 V
1,2
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
2
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
2
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
350
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - SE 24.576MHz
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
MIN
-300
MAX
300
UNITS
ppm
NOTES
Clock period
T period
24.576MHz output nominal
40.70231
40.67790
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
Output Low Current
IOL
V OH @MIN = 1.0 V
0.4
-29
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
-23
V
1
mA
1
mA
1
mA
1
27
mA
1
1
29
VOL @ MAX = 0.4 V
1,2
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
500
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
1218—09/09/09
15
ICS9LPRS365
Advance Information
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
Clock period
T period
14.318MHz output nominal
69.8203
69.8622
ns
2
Absolute min/max period
Tabs
14.318MHz output nominal
69.8203
70.86224
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
1
-33
-33
mA
1
30
38
mA
1
VOH @MIN = 1.0 V,
Output High Current
IOH
Output Low Current
IOL
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
Jitter
tjcyc-cyc
VT = 1.5 V
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
55
%
1
1000
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Preferred drive strengths using CK505 clock sources.
Transmission lines to load do not share series resistors.
Desktop (Zo=50Ω) and mobile (Zo=55Ω) have the same drive strength.
Number of Loads
to Drive
D.C.Drive
Strength
1
2
3
Number of Loads Actually Driven.
[Zo=55Ω]
Match Point for N & P
Voltage / Current
(mA)
1 Load Rs = 2 Loads Rs= 3 Loads Rs =
0.56 / 33
(17Ω)
33Ω [39Ω]
-
-
0.92 / 66
(14Ω)
1.15 / 99
(11.6Ω)
39Ω [43Ω]
22Ω [27Ω]
-
43Ω [43Ω]
27Ω [33Ω]
15Ω [22Ω]
1218—09/09/09
16
ICS9LPRS365
Advance Information
Table 1: CPU Frequency Select Table
2
1
FSLC
B0b7
0
0
0
0
1
1
1
1
FSLB
B0b6
0
0
1
1
0
0
1
1
1
FSLA
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 2: PLL3 Quick Configuration
B1b4
B1b3
B1b2
B1b1
Pin17 (TSSOP) Pin18 (TSSOP)
/ Pin24 (MLF) / Pin25 (MLF)
MHz
MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
100.00
100.00
100.00
100.00
100.00
100.00
N/A
24.576
24.576
98.304
27.000
25.000
N/A
N/A
100.00
100.00
100.00
100.00
100.00
100.00
N/A
24.576
98.304
98.304
27.000
25.000
N/A
N/A
1
1
1
1
N/A
N/A
1218—09/09/09
17
Spread
Comment
%
PLL 3 disabled
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0.5% Down Spread
Only SRCCLK1 from PLL3
1% Down Spread
Only SRCCLK1 from PLL3
1.5% Down Spread
Only SRCCLK1 from PLL3
2% Down Spread
Only SRCCLK1 from PLL3
2.5% Down Spread
Only SRCCLK1 from PLL3
N/A
N/A
None
24.576Mhz on SE1 and SE2
None
24.576Mhz on SE1, 98.304Mhz on SE2
None
98.304Mhz on SE1 and SE2
None
27Mhz on SE1 and SE2
None
25Mhz on SE1 and SE2
N/A
N/A
N/A
N/A
N/A
N/A
ICS9LPRS365
Advance Information
Table 3: IO_Vout select table
B9b2
B9b1
B9b0 IO_Vout
0.3V
0
0
0
0.4V
0
0
1
0.5V
0
1
0
0.6V
0
1
1
0.7V
1
0
0
0.8V
1
0
1
0.9V
1
1
0
1.0V
1
1
1
CPU Power Management Table
PCI_STOP#
CR#
SMBus
Register OE
CPU1
CPU1#
CPU(0,2)
CPU(0,2)#
1
X
1
X
X
Enable
Running
Running
Running
Running
X
Enable
Low/20K
Low
Low/20K
Low
0
X
X
X
Enable
High
Low
High
Low
X
X
Disable
Low/20K
Low
Low/20K
Low
Running
Running
Low/20K
Low
SRC/LCD
SRC#/LCD#
PD# CPU_STOP#
1
0
1
1
M1
SRC, LCD, DOT Power Management Table
PD# CPU_STOP#
SMBus
Register OE
PCI_STOP#
CR#
1
X
0
X
Enable
Running
Running
Enable
Low/20K
Low
X
Enable
Running
1
X
Enable
Running
Disable
1
X
0
1
X
X
1
X
0
X
1
X
X
M1
Free-Run
SRC/LCD SRC#/LCD#
PCI Stoppable/CR
Selected
Running
Running
1
X
0
1
X
X
1
X
Running
Running
Low
Low/20K
Low
Running
High
Low
Running
Running
Running
Low/20K
Low
Running
Running
Low/20K
Low
Low/20K
Low
Low/20K
Low
Low/20K
Low
Low/20K
Low
Low/20K
Low
USB
REF
Running
PCI_STOP#
CR#
SMBus
Register OE
PCIF/PCI
PCIF/PCI
Free-run
Stoppable
1
X
X
Enable
Running
Running
Running
X
Enable
Low
Low
Low
Low
0
X
X
Enable
Running
Low
Running
Running
X
Disable
Low
Low
Low
Low
Low
Low
Low
Low
M1
DOT#
Low/20K
Singled-ended Power Management Table
PD# CPU_STOP#
DOT
1218—09/09/09
18
ICS9LPRS365
Advance Information
General SMBus serial interface information for the ICS9LPRS365
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
1218—09/09/09
19
Not acknowledge
stoP bit
ICS9LPRS365
Advance Information
Byte 0 FS Readback and PLL Selection Register
Bit
7
6
5
Pin
-
Name
FSLC
FSLB
FSLA
4
-
iAMT_EN
3
2
-
Reserved
SRC_Main_SEL
1
-
SATA_SEL
0
-
PD_Restore
Description
CPU Freq. Sel. Bit (Most Significant)
CPU Freq. Sel. Bit
CPU Freq. Sel. Bit (Least Significant)
Type
0
1
R
See Table 1 : CPU Frequency Select
R
Table
R
RW
Set via SMBus or dynamically by CK505 if detects
(Sticky
Legacy Mode
iAMT Enabled
dynamic M1
Bit)
Reserved
RW
Select source for SRC Main
RW SRC Main = PLL1 SRC Main = PLL3
SATA =
Select source for SATA clock
RW
SATA = PLL2
SRC_Main
If config saved, on deassert return to last known
Configuration Not
Configuration
state else clear all config as if cold power on and go RW
Saved
Saved
to latches open state
Default
Latch
Latch
Latch
0
0
0
0
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit
7
6
5
4
3
2
1
0
Pin
13/14
17/18
Name
SRC0_SEL
PLL1_SSC_SEL
Reserved
PLL3_CF3
PLL3_CF2
PLL3_CF1
PLL3_CF0
PCI_SEL
Description
Select SRC0 or DOT96
Select 0.5% down or center SSC
PLL3 Quick Config Bit
PLL3 Quick Config Bit
PLL3 Quick Config Bit
PLL3 Quick Config Bit
PCI_SEL
3
2
1
0
Type
R
RW
RW
RW
RW
RW
RW
RW
0
SRC0
Down spread
1
DOT96
Center spread
PCI from PLL1
PCI from PLL3
Default
Note 1
0
0
0
0
1
0
1
Type
0
1
Default
RW
Output Disabled
Output Enabled
1
RW
RW
RW
RW
RW
RW
RW
Output
Output
Output
Output
Output
Output
Output
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Output
Output
Output
Output
Output
Output
Output
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
1
1
1
1
1
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Output
Output
Output
Output
Output
Output
Output
Output
0
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Output
Output
Output
Output
Output
Output
Output
Output
1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
See Table 2: pin17, 18 Configuration
Only applies if Byte 0, bit 2 = 0.
Note 1 : When 27_Select pin = 0, B1b7 PWD = 1, , when 27_Select pin = 1, PWD = 0
Byte 2 Output Enable Register
Bit
Pin
Name
7
REF_OE
6
5
4
3
2
1
0
USB_OE
PCIF5_OE
PCI4_OE
PCI3_OE
PCI2_OE
PCI1_OE
PCI0_OE
Description
Output enable for REF, if disabled output is tristated
Output enable for USB
Output enable for PCI5
Output enable for PCI4
Output enable for PCI3
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
Byte 3 Output Enable Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
SRC11_OE
SRC10_OE
SRC9_OE
SRC8/ITP_OE
SRC7_OE
SRC6_OE
Reserved
SRC4_OE
Description
Output enable for SRC11
Output enable for SRC10
Output enable for SRC9
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Reserved
Output enable for SRC4
1218—09/09/09
20
ICS9LPRS365
Advance Information
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
SRC3_OE
SATA/SRC2_OE
SRC1_OE
SRC0/DOT96_OE
CPU1_OE
CPU0_OE
PLL1_SSC_ON
PLL3_SSC_ON
Description
Output enable for SRC3
Output enable for SATA/SRC2
Output enable for SRC1
Output enable for SRC0/DOT96
Output enable for CPU1
Output enable for CPU0
Enable PLL1's spread modulation
Enable PLL3's spread modulation
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Spread Disabled
Spread Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Spread Enabled
Spread Enabled
Default
1
1
1
1
1
1
1
1
Byte 5 Clock Request Enable/Configuration Register
Bit
Pin
Name
Description
Type
0
1
Default
7
CR#_A_EN
Enable CR#_A (clk req),
PCI0_OE must be = 0 for this bit to take effect
RW
Disable CR#_A
Enable CR#_A
0
6
5
4
3
2
1
0
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
CR#_D_EN
CR#_D_SEL
Sets CR#_A to control either SRC0 or SRC2
Enable CR#_B (clk req)
Sets CR#_B -> SRC1 or SRC4
Enable CR#_C (clk req)
Sets CR#_C -> SRC0 or SRC2
Enable CR#_D (clk req)
Sets CR#_D -> SRC1 or SRC4
RW
RW
RW
RW
RW
RW
RW
CR#_A -> SRC0
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
0
0
0
0
0
0
0
1
Enable CR#_E
Enable CR#_F
Enable CR#_G
Enable CR#_H
Default
0
0
0
0
0
0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit
7
6
5
4
3
2
Pin
Name
CR#_E_EN
CR#_F_EN
CR#_G_EN
CR#_H_EN
Reserved
Reserved
SSCD_STP_CRTL
1
0
SRC_STP_CRTL
Description
Enable CR#_E (clk req) -> SRC6
Enable CR#_F (clk req) -> SRC8
Enable CR#_G (clk req) -> SRC9
Enable CR#_H (clk req) -> SRC10
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
0
Disable CR#_E
Disable CR#_F
Disable CR#_G
Disable CR#_H
If set, LCD_SS stops with PCI_STOP#
RW
Free Running
If set, SRCs stop with PCI_STOP#
RW
Free Running
Description
Type
R
R
R
R
R
R
R
R
0
Stops with
PCI_STOP#
assertion
Stops with
PCI_STOP#
assertion
0
0
Byte 7 Vendor ID/ Revision ID
Bit
7
6
5
4
3
2
1
0
Pin
Name
Rev Code Bit
Rev Code Bit
Rev Code Bit
Rev Code Bit
Vendor ID bit
Vendor ID bit
Vendor ID bit
Vendor ID bit
3
2
1
0
3
2
1
0
Revision ID
Vendor ID
ICS is 0001, binary
1218—09/09/09
21
1
Vendor specific
Default
0
0
1
0
0
0
0
1
ICS9LPRS365
Advance Information
Byte 8 Device ID and Output Enable Register
Bit
7
6
5
4
3
2
Pin
Name
Device_ID3
Device_ID2
Device_ID1
Device_ID0
Reserved
Reserved
Description
0
Reserved
Reserved
Type
R
R
R
R
RW
RW
-
-
SE1_OE
Output enable for SE1
RW
Disabled
Enabled
SE2_OE
Output enable for SE2
RW
Disabled
Enabled
Name
Description
Type
0
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of
PCI_STOP#
RW
Free running
6
5
4
TME_Readback
REF Strength
Test Mode Select
Truested Mode Enable (TME) strap status
Sets the REF output drive strength
Allows test select, ignores REF/FSC/TestSel
R
RW
RW
normal operation
1X (2Loads)
Outputs HI-Z
1
Stops with
PCI_STOP#
assertion
no overclocking
2X (3 Loads)
Outputs = REF/N
3
Test Mode Entry
Allows entry into test mode, ignores FSB/TestMode
RW
Normal operation
Test mode
0
2
1
0
IO_VOUT2
IO_VOUT1
IO_VOUT0
IO Output Voltage Select (Most Significant Bit)
IO Output Voltage Select
IO Output Voltage Select (Least Significant Bit)
RW
RW
RW
See Table 3: V_IO Selection
(Default is 0.8V)
1
0
1
Table of Device identifier codes, used for
differentiating between CK505 package options,
etc.
1
See Device ID Table
1
0
Default
1
1
0
1
0
0
27_Select
power on
latch
27_Select
power on
latch
Byte 9 Output Control Register
Bit
Pin
Default
0
0
1
0
Byte 10 Free-Running Control Register
Bit
Pin
7
6
5
4
3
2
1
0
Name
27_Selec Latch read
back
Reserved
Reserved
CPU1_AMT_EN
Reserved
CPU 2 Stop Enable
CPU 1 Stop Enable
CPU 0 Stop Enable
Description
Type
Readback of 27_Select latch
R
Reserved
Reserved
M1 mode clk enable
Reserved
Enables control of CPU2 with CPU_STOP#
Enables control of CPU1 with CPU_STOP#
Enables control of CPU 0 with CPU_STOP#
RW
RW
RW
RW
RW
RW
RW
0
Dot96/ LCD_SS
/SE
Disable
Free Running
Free Running
Free Running
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1x
1x
1x
1x
1x
1x
1x
-
1
Enable
Stoppable
Stoppable
Stoppable
Default
27_Select
latch
1
1
1
1
1
1
1
1
2x
2x
2x
2x
2x
2x
2x
-
Default
0
0
0
0
0
0
0
0
SRC0/ 27MHz
Byte 11 Strength Control Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
48MHz
PCIF5
PCI4
PCI3
PCI2
PCI1
PCI0
Reserved
Description
Reserved
Reserved
1218—09/09/09
22
ICS9LPRS365
Advance Information
Byte 12 Byte Count Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
Reserved
Reserved
BC5
BC4
BC3
BC2
BC1
BC0
Description
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
0
0
0
0
1
1
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Type
RW
RW
RW
The decimal representation of N Div (9:0) is equal to
RW
VCO divider value. Default at power up = latch-in or
RW
Byte 0 Rom table.
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
0
x
X
X
X
X
X
X
Read Back byte count register,
max bytes = 32
Byte 13 VCO Frequency Control Register PLL1
Bit
7
6
5
4
3
2
1
0
Pin
Name
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Description
N Divider 8
N Divider 9
The decimal representation of M Div (5:0) is equal
to reference divider value. Default at power up =
latch-in or Byte 0 Rom table.
Byte 14 VCO Frequency Control Register PLL1
Bit
7
6
5
4
3
2
1
0
Pin
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Description
Byte 15 Spread Spectrum Control Register PLL1
Bit
7
6
5
4
3
2
1
0
Pin
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Description
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
Byte 16 Spread Spectrum Control Register PLL1
Bit
7
6
5
4
3
2
1
0
Pin
Name
Reserved
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Description
Reserved
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
1218—09/09/09
23
ICS9LPRS365
Advance Information
Byte 17 VCO Frequency Control Register PLL3
Bit
7
6
5
4
3
2
1
0
Pin
Name
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Description
N Divider 8
N Divider 9
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Type
RW
RW
RW
The decimal representation of N Div (9:0) is equal to
RW
VCO divider value. Default at power up = latch-in or
RW
Byte 0 Rom table.
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
0
x
X
X
X
X
X
X
The decimal representation of M Div (5:0) is equal
to reference divider value. Default at power up =
latch-in or Byte 0 Rom table.
Byte 18 VCO Frequency Control Register PLL3
Bit
7
6
5
4
3
2
1
0
Pin
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Description
Byte 19 Spread Spectrum Control Register PLL3
Bit
7
6
5
4
3
2
1
0
Pin
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Description
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
Byte 20 Spread Spectrum Control Register PLL3
Bit
7
6
5
4
3
2
1
0
Pin
Name
Reserved
SSP14
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Description
Reserved
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
Byte 21 M/N Enables
Bit
7
6
5
4
3
2
Pin
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
RW
RW
RW
RW
RW
RW
RW
0
1
Default
0
0
0
0
0
0
M/N Enable
CPU PLL M/N Enable
RW
Disable
Enable
0
RW
Disable
Enable
0
0
M/N Enable
SRC/PCI PLL M/N Enable
*These bits are disabled if TME is latched to 1
1218—09/09/09
24
ICS9LPRS365
Advance Information
Test Clarification Table
HW
Comments
FSLC/
TEST_SEL
HW PIN
SW
FSLB/
TEST
TEST_MODE ENTRY BIT
HW PIN
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
X
0
0
1
0
X
X
X
0
0
1
0
NORMAL
HI-Z
REF/N
REF/N
>2.0V
1
X
1
REF/N
2.0V then use TEST_SEL
If power-up w/ Vlow Vth input
TEST_MODE is a real time input
2.0V
>2.0V
>2.0V
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
1218—09/09/09
25
ICS9LPRS365
Advance Information
c
N
L
E1
INDEX
AREA
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
E
1 2
a
D
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
-1.20
-.047
0.05
0.15
.002
.006
0.80
1.05
.032
.041
0.17
0.27
.007
.011
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
-0.10
-.004
A
A2
VARIATIONS
A1
N
-Ce
b
SEATING
PLANE
aaa C
64
D mm.
MIN
16.90
D (inch)
MAX
17.10
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Marking Diagram
1218—09/09/09
26
MIN
.665
MAX
.673
ICS9LPRS365
Advance Information
THERMALLY ENHANCED, VE RY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
N
ND
NE
64
16
16
OPTION 1 DIMENSIONS (mm)
SYMBOL
MIN.
MAX.
A
0.8
1.0
A1
0
0.05
A3
0.25 Reference
b
0.18
0.3
0.50 BASIC
e
9.00 x 9.00
D x E BASIC
D2 MIN. / MAX.
7.00
7.25
E2 MIN. / MAX.
7.00
7.25
L MIN. / MAX.
0.30
0.50
OPTION 2 DIMENSIONS (mm)
SYMBOL
MIN.
MAX.
A
0.8
1.0
A1
0
0.05
A3
0.25 Reference
b
0.18
0.3
0.50 BASIC
e
9.00 x 9.00
D x E BASIC
D2 MIN. / MAX.
6.00
6.25
E2 MIN. / MAX.
6.00
6.25
L MIN. / MAX.
0.30
0.50
Marking Diagram
Ordering Information
Part/Order Number
9LPRS365BGLF
9LPRS365BGLFT
9LPRS365BKLF
9LPRS365BKLFT
Marking
See page 26
See page 27
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
1218—09/09/09
27
Package
Temperature
64-TSSOP
0 to +70° C
64-VQFN
ICS9LPRS365
Advance Information
Revision History
Rev.
0.1
0.2
Issue Date
4/5/2006
7/11/2006
Description
Initial Release
Updated Electrical Characteristics.
0.3
0.4
8/25/2006
10/25/2006
0.5
0.6
0.65
0.7
0.8
0.9
0.91
0.92
11/22/2006
11/29/2006
3/7/2007
3/9/2007
3/20/2007
4/3/2007
5/21/2007
7/16/2007
0.93
0.94
0.95
0.96
4/8/2008
6/3/2008
9/18/2008
12/12/2008
0.97
1/28/2009
0.98
0.99
4/1/2009
9/9/2009
1. Updated pin description and I2C.
Added Byte 21.
1. Updated pin description of pin #33 (TSSOP) and pin #40 (QFN)
2. Updated B1b0 in I2C.
Updated DS to reflect revision C changes
Updated Feautres/Benefits.
Updated Supply currents in Electrical Characteristics.
Updated Byte 5 bit 7 description in the I2C
Updated B[11,21] in the I2C
Removed Pull-up/Pull-Down footnotes.
Updated Case Temperature in Electrical Characteristics.
1. Updated MLF ordering Information.
2. Reformatted Dimensions Tables.
Updated Pin Description and SMBUS.
Updated Electrical Characteristics.
Added DS-Loading table.
Update Table2, SMBus Byte1 table, added 27_Select tables for TSSOP
and MLF
Update SEL27 and ITP_EN pin descriptions.
Added updated ordering information table and marking diagrams.
1218—09/09/09
Page #
12
2-5, 7-10,
22-23
23
4,9, 19
Various
1
12
20
23
1
12
26
Various
Various
16
Various
Various
26, 27
This product is protected by United States Patent NO. 7,342,420 and other patents.
28
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