9LPRS525AGILF

DATASHEET 56-pin CK505 for Intel Systems ICS9LPRS525 Recommended Application: 56-pin CK505 compatible clock, w/fully integrated Vreg and series resistors on differential outputs Output Features: • 2 - CPU differential low power push-pull pairs • 7 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 1 - SRC/SE selectable differential push-pull pair/Single-ended outputs • 5 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter SRC0 Disable CR#_D CR#_D -> SRC1 CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 0 0 0 0 0 0 0 1 Enable CR#_E Enable CR#_F Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion Default 0 0 0 0 0 0 1 Default X X X X 0 0 0 1 Byte 5 Clock Request Enable/Configuration Register Bit Pin Name 7 CR#_A_EN 6 5 4 3 2 1 0 CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 Pin Name CR#_E_EN CR#_F_EN Reserved Reserved Reserved Reserved Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F - 1 SSCD_STP_CRTL (SRC1) If set, SSCD (SRC1) stops with PCI_STOP# RW Free Running 0 SRC_STP_CRTL If set, SRCs (except SRC1) stop with PCI_STOP# RW Free Running Type R R R R R R R R 0 0 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Vendor ID ICS is 0001, binary IDT® PC MAIN CLOCK Vendor specific 1484F—08/10/12 15 ICS9LPRS525 PC MAIN CLOCK Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE SE2_OE Description Reserved Reserved Output enable for SE1 Output enable for SE2 Type R R R R RW RW RW RW Disabled Disabled Name Description Type 0 7 PCIF5 STOP EN Allows control of PCIF5 with assertion of PCI_STOP# RW 6 5 4 TME_Readback REF Strength Test Mode Select 3 Test Mode Entry 2 1 0 IO_VOUT2 IO_VOUT1 IO_VOUT0 Table of Device identifier codes, used for differentiating between CK505 package options, etc. 0 1 56-pin device Enabled Enabled Default 0 0 0 0 0 0 0 0 Byte 9 Output Control Register Bit Pin Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) R RW RW 1 Default Stops with Free running PCI_STOP# 0 assertion normal operation no overclocking Latch 1X (2Loads) 2X (3 Loads) 1 Outputs HI-Z Outputs = REF/N 0 RW Normal operation Name Description Type 7 SRC5_EN Readback Readback of SRC5 enable latch R 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable RW RW RW Test mode See Table 3: V_IO Selection (Default is 0.8V) 0 1 0 1 Byte 10 Stop Enable Register Bit Pin Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled Free Running Free Running 1 Default SRC5 Enabled Latch Stoppable Stoppable 0 0 0 0 0 1 1 1 Byte 11 iAMT Enable Register Bit 7 6 5 4 Pin Name PCI3_CFG1 PCI3_CFG0 Reserved Reserved Description See PCI3 Configuration Table 28 3 CPU2_AMT_EN 2 CPU1_AMT_EN Reserved Reserved Determines if CPU2 runs in M1 mode. Only valid if ITP_EN=1. See Note. Determines if CPU1 runs in M1 mode. See Note. 1 PCI-E_GEN2 Determines if PCI-E Gen2 compliant Type R R RW RW - - Default Latch Latch 0 1 RW Does not Run Runs 0 RW Does not Run 1 R non-Gen2 Runs PCI-E Gen2 Compliant Stoppable 0 CPU 2 Stop Enable Enables control of CPU 0 with CPU_STOP# RW NOTE: A value of '00' for Bit(3:2) in Byte 11 is reserved and not a valid configuration. IDT® PC MAIN CLOCK 0 See PCI3 Configuration Table Free Running 1 1 1484F—08/10/12 16 ICS9LPRS525 PC MAIN CLOCK Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Read Back byte count register, max bytes = 32 Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 RW RW RW RW RW RW RW RW RW 0 1 Default 1 0 1 1 1 1 0 0 Byte 13 to 28 Reserved Byte 29 Slew Rate Control Bit 7 6 5 4 3 2 1 0 Pin Name USB_Slew1 USB_Slew0 PCI_Slew1 PCI_Slew0 Reserved REF Slew Rate Reserved Reserved Description USB Slew Rate Control (MSB) USB Slew Rate Control (LSB) PCI Slew Rate Control (MSB) PCI Slew Rate Control (LSB) Changes Ref Slew Rate IDT® PC MAIN CLOCK See Slew Rate Selection Table See Slew Rate Selection Table 1.2V/ns 2.2V/ns 1484F—08/10/12 17 ICS9LPRS525 PC MAIN CLOCK Test Clarification Table HW Comments FSLC/ TEST_SEL HW PIN Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ Vlow Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control SW FSLB/ TEST TEST_MODE ENTRY BIT HW PIN B9b3 REF/N or HI-Z B9b4 2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N