9ZML1232BKLFT

2:12 Low Power Differential Z-Buffer Mux for PCIe, UPI and PFT Description 9ZML1232 Datasheet Features • 25MHz to 100MHz ZDB mode; supports PFT clock delay The 9ZML1232 is a 2-input/12-output differential mux for use in servers. It meets the demanding DB1200ZL performance specifications and utilizes Low-Power HCSL-compatible outputs to reduce power consumption and termination components. It is suitable for PCI-Express Gen1–3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI applications. management • 9 selectable SMBus addresses; multiple devices can • • • Applications • Clock Mux for Servers share same SMBus segment Separate VDDIO for outputs; allows maximum power savings PLL or bypass mode; PLL can dejitter incoming clock Hardware or software-selectable PLL BW; minimizes jitter peaking in downstream PLLs Spread spectrum compatible; tracks spreading input clock for EMI reduction SMBus interface; unused outputs can be disabled • • Differential outputs are Low/Low in power down; Output Features • 12 – Low-Power (LP) HCSL Output Pairs maximum power savings Key Specifications • • • • • • Block Diagram Cycle-to-cycle jitter < 50ps Output-to-output skew < 65ps Input-to-output delay: Fixed at 0ps Input-to-output delay variation < 50ps Phase jitter: PCIe Gen3 < 1ps rms Phase jitter: QPI/UPI 9.6GB/s < 0.2ps rms OE(11:0)# FBOUT_NC Z-PLL (SS Compatible) DIF_INB DIF_INB# DIF(11:0) DIF_INA DIF_INA# HIBW_BYPM_LOBW# SEL_A_B# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri SMBDAT SMBCLK ©2021 Renesas Electronics Corporation Logic 1 January 22, 2021 9ZML1232 Datasheet ^OE8# ^OE9# VDDIO GND DIF_8 DIF_8# DIF_9 DIF_9# GND VDD DIF_10 DIF_10# DIF_11 DIF_11# VDDIO GND ^OE10# ^OE11# Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 ^OE7# 53 ^OE6# VDDA 1 GNDA 2 52 VDDIO 51 GND 50 DIF_7# ^SEL_A_B# 3 ^vHIBW_BYPM_LOBW# 4 CKPWRGD_PD# 5 49 DIF_7 48 DIF_6# DIF_INB 6 DIF_INB# 7 47 DIF_6 46 GND GND 8 VDDR 9 9ZML1232 DIF_INA 10 45 VDD 44 DIF_5# DIF_INA# 11 43 DIF_5 42 DIF_4# vSMB_A0_tri 12 SMBDAT 13 41 DIF_4 40 VDDIO 39 GND SMBCLK 14 vSMB_A1_tri 15 GND 16 38 ^OE5# 37 ^OE4# FBOUT_NC# 17 FBOUT_NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ^OE3# ^OE2# GND VDDIO DIF_3# DIF_3 DIF_2# DIF_2 VDD GND DIF_1# DIF_1 DIF_0# DIF_0 GND VDDIO ^OE1# ^OE0# ^ prefix indicates internal 120Kohm Pull Up v prefix indicates internal 120Kohm Pull down 10mm x 10mm 72-MLF, 0.5mm pin pitch Power Management Table Inputs CKPWRGD_PD# 0 DIF_IN/ DIF_IN# X 1 Running Control Bits Outputs SMBus EN bit X 0 1 DIFx/ FBOUT_NC/ DIFx# FB_OUT_NC# Low/Low Low/Low Low/Low Running Running Running PLL Operating Mode Table Level Low Mid High 28, 45, 64 21, 33, 40, 52, 57, 69 Voltage