19-Output DB1900Z for PCIe Gen1-4 and
QPI/UPI
9ZX21901D
DATASHEET
Description
Features
The 9ZX21901D is a second generation DB1900Z differential
buffer for Intel Purley and newer platforms. The part is
backwards compatible to the 9ZX21901C while offering much
improved phase jitter performance. A fixed external feedback
maintains low drift for critical QPI/UPI applications. In bypass
mode, the 9ZX21901D can provide outputs up to 400MHz.
• Fixed feedback path; 0ps input-to-output delay
• 9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
• 8 dedicated OE# pins; hardware control of outputs
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL BW; minimizes jitter peaking in downstream
PCIe Clocking Architectures Supported
•
• Common Clocked (CC)
• Separate Reference No Spread (SRNS)
• Separate Reference Independent Spread (SRIS)
•
Typical Applications
•
•
•
• Servers, Storage, Networking
Output Features
PLL's
Hardware or software control of PLL operating mode;
change mode with software mode does not need power
cycle
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
100MHz and 133.33MHz PLL mode; legacy QPI support
72-QFN 10 x 10 mm package; small board footprint
• 19 HCSL output pairs
Key Specifications
•
•
•
•
•
•
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: < 50ps
Input-to-output delay: Fixed at 0 ps
Input-to-output delay variation: < 50ps
Phase jitter: PCIe Gen4 < 0.5ps rms
Phase jitter: UPI 9.6GB/s < 0.1ps rms
Functional Block Diagram
Low Phase
Noise Z-PLL
(SSCompatible)
DIF_IN
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
DIF[18]
Bypass path
19 outputs
CONTROL
OE(12:5)#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
DFB_OUT
DIF[0]
IREF
9ZX21901D APRIL 17, 2018
1
©2018 Integrated Device Technology, Inc.
9ZX21901D DATASHEET
DIF_12
DIF_12#
OE12#
VDD
DIF_13
DIF_13#
DIF_14
DIF_14#
GND
DIF_15
DIF_15#
DIF_16
DIF_16#
VDD
DIF_17
DIF_17#
DIF_18
DIF_18#
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDDA 1
54 OE11#
GNDA 2
53 DIF_11#
IREF 3
52 DIF_11
100M_133M# 4
51 OE10#
HIBW_BYPM_LOBW# 5
50 DIF_10#
CKPWRGD_PD# 6
49 DIF_10
GND 7
48 OE9#
9ZX21901D
connect ePad to Ground
NOTE: DFB_OUT pins must be
terminated identically to the regular DIF
outputs
VDDR 8
DIF_IN 9
DIF_IN# 10
SMB_A0_tri 11
SMBDAT 12
47 DIF_9#
46 DIF_9
45 VDD
44 GND
43 OE8#
SMBCLK 13
42 DIF_8#
SMB_A1_tri 14
41 DIF_8
NC 15
40 OE7#
NC 16
39 DIF_7#
DFB_OUT# 17
38 DIF_7
DFB_OUT 18
37 OE6#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DIF_6#
DIF_6
OE5#
DIF_5#
DIF_5
VDD
DIF_4#
DIF_4
DIF_3#
DIF_3
GND
DIF_2#
DIF_2
DIF_1#
DIF_1
VDD
DIF_0#
DIF_0
72-pin VFQFPN (10mm x10 mm, 0.5mm pad pitch)
Functionality at Power Up (PLL Mode)
DIF_IN
100M_133M#
(MHz)
1
100.00
0
133.33
PLL Operating Mode Readback Table
HiBW_BypM_LoBW#
Byte0, bit 7
Low (Low BW)
0
Mid (Bypass)
0
High (High BW)
1
PLL Operating Mode
HiBW_BypM_LoBW#
Low
Power Connections
Pin Number
DIF_x
(MHz)
DIF_IN
DIF_IN
VDD
1
8
21, 31, 45,
58, 68
Byte 0, bit 6
0
1
1
Description
GND
2
7
Analog PLL
Analog Input
26, 44, 63
DIF clocks
9ZX21901 SMBus Addressing
Pin
SMBus Address
SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0)
0
D8
0
0
M
DA
1
DE
0
M
0
C2
M
C4
M
1
M
C6
0
1
CA
M
1
CC
1
1
CE
MODE
PLL Lo BW
Mid
Bypass
High
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
Tri-level Input Thresholds
Level
Voltage
200 mV.
4
DIF_IN input.
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
6
1.4
30
4
APRIL 17, 2018
9ZX21901D DATASHEET
Electrical Characteristics – DIF HCSL/LP-HCSL Outputs
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
INDUSTRY
UNITS NOTES
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
LIMIT
V/ns
Slew rate
dV/dt
Scope averaging on
1.5
2.2
3.0
0.6 - 4
1,2,3
%
Slew rate matching, Scope averaging on
7.3
18
20
1,2,4,7
Slew rate matching
ΔdV/dt
Measurement on single ended signal using
Max Voltage
Vmax
719
772
842
1150
7,8
mV
Min Voltage
Vmin
11
50
-300
7,8
absolute value. (Scope averaging off)
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
310
367
400
250 - 550
mV
1,5,7
14
30
140
mV
1,6,7
1
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)
allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
7
At default SMBus settings.
8
If driving a receiver with input terminations, the Vmax and Vmin values will be halved.
APRIL 17, 2018
7
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
9ZX21901D DATASHEET
Electrical Characteristics – Skew and Differential Jitter Parameters
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
CLK_IN, DIF[x:0]
t SPO_PLL
CLK_IN, DIF[x:0]
t PD_BYP
CLK_IN, DIF[x:0]
t DSPO_PLL
CLK_IN, DIF[x:0]
tDSPO_BYP
DIF[x:0]
t SKEW_ALL
Output-to-Output Skew across all outputs,
common to PLL and Bypass mode, at 100MHz
PLL Jitter Peaking
PLL Jitter Peaking
jpeak-hibw
jpeak-lobw
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
PLL Bandwidth
PLL Bandwidth
Duty Cycle
pllHIBW
pllLOBW
t DC
Duty Cycle Distortion
t DCD
Jitter, Cycle to Cycle
t jcyc-cyc
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode at
100MHz
PLL mode
Input-to-Output Skew in PLL mode
at 100MHz, nominal temperature and voltage
Input-to-Output Skew in Bypass mode
at 100MHz, nominal temperature and voltage
Input-to-Output Skew Variation in PLL mode
at 100MHz, across voltage and temperature
Input-to-Output Skew Variation in Bypass
mode
at 100MHz, across voltage and temperature,
TAMB = TCOM
Additive Jitter in Bypass Mode
MIN
TYP
MAX
UNITS NOTES
-100
54
100
ps
1,2,4,5,8
1.9
2.6
3
ns
1,2,3,5,8
-50
0.0
50
ps
1,2,3,5,8
-250
0.0
250
ps
1,2,3,5,8
32
50
ps
1,2,3,8
0
0
1.4
1.2
2.5
2
dB
dB
7,8
7,8
2
0.7
45
2.8
1.1
50
4
1.4
55
MHz
MHz
%
8,9
8,9
1
-1
-0.5
0
%
1,10
17
50
ps
1,11
0.1
5
ps
1,11
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4
This parameter is deterministic for a given device.
5
Measured with scope averaging on to find mean value.
6
t is the period of the input clock.
7
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8.
Guaranteed by design and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11
Measured from differential waveform.
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
8
APRIL 17, 2018
9ZX21901D DATASHEET
Electrical Characteristics – Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
TYP
MAX
PCIe Gen 1
18
30
INDUSTRY
LIMIT
86
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.4
0.8
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
1.1
t jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
t jphPCIeG4-CC
t jphPCIeG1-CC
UNITS
Notes
ps (p-p)
1,2,3
3
ps
(rms)
1,2
1.6
3.1
ps
(rms)
1,2
0.28
0.40
1
ps
(rms)
1,2
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.28
0.40
0.5
ps
(rms)
1,2
PCIe Gen 1
0.1
0.1
ps (p-p)
1,2
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.1
0.1
ps
(rms)
1,2,4
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz or 8-5MHz, CDR = 5MHz)
0.105
0.13
ps
(rms)
1,2,4
t jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.1
0.1
ps
(rms)
1,2,4
t jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.1
0.1
ps
(rms)
1,2,4
SYMBOL
CONDITIONS
t jphPCIeG1-CC
MIN
t jphPCIeG2-CC
Phase Jitter,
PLL Mode
t jphPCIeG2-CC
Additive Phase Jitter,
Bypass mode
n/a
1
Applies to all outputs,, when driven by 9SQL4958 or equivalent
2
Based on PCIe Base Specification Rev4.0 version 0.7 draft. See http://www.pcisig.com for latest specifications.
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter.
4
APRIL 17, 2018
9
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
9ZX21901D DATASHEET
Electrical Characteristics – Filtered Phase Jitter Parameters - PCIe Separate
Reference Independent Spread (SRIS) Architectures
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
tjphPCIeG1-
MIN
TYP
MAX
INDUSTRY
LIMIT
UNITS
Notes
n/a
ps (p-p)
1,2,3
PCIe Gen 1
n/a
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
0.8
1.1
2
ps
(rms)
1,2
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.6
0.7
TBD
ps
(rms)
1,2
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
n/a
n/a
ps
(rms)
1,2
PCIe Gen 1
n/a
ps (p-p)
1,2
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
0.0
ps
(rms)
1,2,4
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.0
ps
(rms)
1,2,4
PCIe Gen 4
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
n/a
ps
(rms)
1,2,4
SRIS
tjphPCIeG2Phase Jitter, PLL
Mode
SRIS
tjphPCIeG3SRIS
tjphPCIeG4SRIS
tjphPCIeG1SRIS
tjphPCIeG2AdditivePhase Jitter,
Bypass mode
SRIS
tjphPCIeG3SRIS
tjphPCIeG4SRIS
1
0.01
n/a
0.01
Applies to all outputs, when driven by 9SQL4958 or equivalent
2
Preliminary based on PCIe Base Specification Rev3.1a. PCIe Gen4 is expected to remove the SRIS specifications. These filters are different than
Common Clock filters. See http://www.pcisig.com for latest specifications.
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total
Electrical Characteristics – Filtered Phase Jitter Parameters - QPI/UPI
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
QPI & SMI
0.15
0.3
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
Phase Jitter, PLL
QPI & SMI
tjphQPI_UPI
0.08
0.12
Mode
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
0.07
0.1
(100MHz, 9.6Gb/s, 12UI)
QPI & SMI
0.009
0.12
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
Additive Phase Jitter,
QPI & SMI
tjphQPI_UPI
0.020
0.07
Bypass mode
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
0.016
0.06
(100MHz, 9.6Gb/s, 12UI)
IND.LIMIT
0.5
0.3
0.2
n/a
UNITS
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2
1,2
1,2
1,2,3
1,2,3
1,2,3
1
Applies to all outputs, when driven by 9SQL4958 or equivalent
2
Calculated from Intel-supplied Clock Jitter Tool v 1.6.6
3
For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter.
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
10
APRIL 17, 2018
9ZX21901D DATASHEET
Electrical Characteristics – Unfiltered Phase Jitter Parameters - 12kHz to 20MHz
Over specified temperature and voltage ranges unless otherwise indicated. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Phase Jitter, PLL
t jph12k-20MHi
PLL High BW, SSC OFF, 100MHz
161
178
198
Mode
Phase Jitter, PLL
PLL Low BW, SSC OFF, 100MHz
175
193
207
t jph12k-20MLo
Mode
Additive Phase Jitter,
Bypass Mode, SSC OFF, 100MHz
104
104
110
tjph12k-20MByp
Bypass mode
IND.LIMIT
UNITS
fs
(rms)
fs
(rms)
fs
(rms)
n/a
n/a
n/a
Notes
1,2
1,2
1,2,3
1
Applies to all outputs.
2
12kHz to 20MHz brick wall filter.
For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter.
3
Power Management Table
Inputs
Control Bits/Pins
CKPWRGD_PD#
DIF_IN/
DIF_IN#
0
X
SMBus
EN bit
OE# Pin
X
0
1
Running
1
1
NOTE: 1. Due to external pull down resistors, HI-Z results
Outputs
DIF(5:12)
Other DIF
PLL
State
DFB_OUT
X
Hi-Z1
Hi-Z1
Hi-Z1
Running
X
Hi-Z1
Hi-Z1
0
Running
Running
Running
Running
Running
1
Hi-Z1
in Low/Low on the True/Complement outputs
OFF
ON
ON
ON
Clock Periods – Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
133.33
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94900
9.99900
10.00000
10.00100
7.44925
7.49925
7.50000
7.50075
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter
AbsPer
Max
10.05100
7.55075
Units Notes
ns
ns
1,2,3
1,2,4
Clock Periods – Differential Outputs with Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
133.00
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94906
9.99906
10.02406
10.02506
10.02607
7.44930
7.49930
7.51805
7.51880
7.51955
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
7.53830
1 Clock
+c2c jitter
AbsPer
Max
10.10107
7.58830
Units Notes
ns
ns
1,2,3
1,2,4
Notes:
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy
requirements (+/-100ppm). The device itself does not contribute to ppm error.
3
4
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode
APRIL 17, 2018
11
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
9ZX21901D DATASHEET
Test Loads
9ZX21901D Characterization Test Loads
10 inches
Rs
Differential Zo
2pF
Rs
Rp
2pF
Rp
HCSL Output
Buffer
Differential Output Termination Table
DIF Zo (Ω) Iref (Ω) Rs (Ω)
Rp (Ω)
100
475
33
50
85
412
27
42.2 or 43.2
Alternate Terminations
The 9ZX21901D can easily drive LVPECL, LVDS, CML, and SSTL logic. See “AN-891 Driving LVPECL, LVDS, CML, and SSTL
Logic with IDT's "Universal" Low-Power HCSL Outputs” for details.
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
12
APRIL 17, 2018
9ZX21901D DATASHEET
General SMBus Serial Interface Information
(see also 9ZX21901 SMBus Addressing on page 2)
How to Write
•
•
•
•
•
•
•
•
•
•
How to Read
Controller (host) sends a start bit
Controller (host) sends the write address XX(H)
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address XX(H)
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address YY(H)
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
WR
WRite
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
Data Byte Count = X
RT
ACK
Beginning Byte N
RD
ACK
O
O
ACK
O
Data Byte Count=X
O
ACK
O
Beginning Byte N
Byte N + X - 1
ACK
ACK
P
ReaD
stoP bit
X Byte
X Byte
O
Repeat starT
Slave Address
O
O
O
O
O
O
Byte N + X - 1
Note: XX(H) is defined by SMBus Address select pins.
APRIL 17, 2018
13
N
Not acknowledge
P
stoP bit
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
9ZX21901D DATASHEET
SMBusTable: PLL Mode, and Frequency Select Register
Byte 0
Pin
Name
Control Function
5
PLL Mode 1
PLL Operating Mode Rd back 1
Bit 7
5
PLL Mode 0
PLL Operating Mode Rd back 0
Bit 6
72/71
DIF_18_En
Output Enable
Bit 5
70/69
DIF_17_En
Output Enable
Bit 4
67/66
DIF_16_En
Output Enable
Bit 3
Reserved
Bit 2
Reserved
Bit 1
4
100M_133M#
Frequency Select Readback
Bit 0
Type
R
R
RW
RW
RW
R
133MHz
0
SMBusTable: Output Control Register
Byte 1
Pin
Name
39/38
DIF_7_En
Bit 7
35/36
DIF_6_En
Bit 6
32/33
DIF_5_En
Bit 5
29/30
DIF_4_En
Bit 4
27/28
DIF_3_En
Bit 3
24/25
DIF_2_En
Bit 2
22/23
DIF_1_En
Bit 1
19/20
DIF_0_En
Bit 0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBusTable: Output Control Register
Byte 2
Pin
Name
65/64
DIF_15_En
Bit 7
62/61
DIF_14_En
Bit 6
60/59
DIF_13_En
Bit 5
56/55
DIF_12_En
Bit 4
53/52
DIF_11_En
Bit 3
50/49
DIF_10_En
Bit 2
47/46
DIF_9_En
Bit 1
42/41
DIF_8_En
Bit 0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBusTable: Output Enable Pin Status Readback Register
Byte 3
Pin
Name
Control Function
57
OE_RB12
Real Time readback of OE#12
Bit 7
54
OE_RB11
Real Time readback of OE#11
Bit 6
51
OE_RB10
Real Time readback of OE#10
Bit 5
48
OE_RB9
Real Time readback of OE#9
Bit 4
43
OE_RB8
Real Time readback of OE#8
Bit 3
40
OE_RB7
Real Time readback of OE#7
Bit 2
37
OE_RB6
Real Time readback of OE#6
Bit 1
34
OE_RB5
Real Time readback of OE#5
Bit 0
0
1
See PLL Operating Mode
Readback Table
Hi-Z
Enable
Hi-Z
Enable
Hi-Z
Enable
100MHz
1
OE# pin
controlled
Hi-Z
Enable
0
1
Enable
Hi-Z
Type
0
R
R
R
R
OE# pin Low
R
R
R
R
OE# pin
controlled
Default
Latch
Latch
1
1
1
0
0
Latch
Default
1
1
1
1
1
1
1
1
Default
1
1
1
1
1
1
1
1
1
Default
Real time
Real time
Real time
Real time
OE# Pin High
Real time
Real time
Real time
Real time
SMBusTable: PLL SW Override Control Register
Byte 4
Pin
Name
Control Function
Type
0
1
Default
Reserved
0
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
PLL_SW_EN
Enable S/W control of PLL BW
RW
HW Latch
SMBus Control
0
Bit 3
See PLL Operating Mode
PLL Mode 1
PLL Operating Mode 1
RW
0
Bit 2
PLL Mode 0
PLL Operating Mode 1
RW
Readback Table
0
Bit 1
Reserved
0
Bit 0
Note: Setting bit 3 to '1' allows the user to override the Latch value from pin 4 via use of bits 2 and 1. Use the values from the
PLL Operating Mode Readback Table. Note that Byte 0, Bits 7:6 will keep the value originally latched on pin 4. A warm reset of
the system will have to be completed if the user changes these bits.
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
14
APRIL 17, 2018
9ZX21901D DATASHEET
SMBusTable: Vendor & Revision ID Register
Pin
Name
Byte 5
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBusTable: DEVICE ID
Pin
Name
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBusTable: Byte Count Register
Pin
Name
Byte 7
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
SMBusTable: Reserved Register
Pin
Name
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APRIL 17, 2018
Control Function
REVISION ID
VENDOR ID
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Control Function
Reserved
Reserved
Reserved
Writing to this register configures how
many bytes will be read back.
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
15
Type
R
R
R
R
R
R
R
R
0
-
-
Type
R
R
R
R
R
R
R
R
0
1
Type
1
D rev = 0011
Device ID is 219 decimal or
DB hex.
0
1
RW
Default value is 8 hex, so 9
RW
RW bytes (0 to 8) will be read back
by default.
RW
RW
Type
0
1
Default
0
0
1
1
0
0
0
1
Default
1
1
0
1
1
0
1
1
Default
0
0
0
0
1
0
0
0
Default
0
0
0
0
0
0
0
0
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
9ZX21901D DATASHEET
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package
information is the most current data available.
www.idt.com/document/psc/nlnlg72-package-outline-100-x-100-mm-body-epad-59-mm-sq-050-mm-pitch-vfqfpn-sawn
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Thermal Resistance Junction to Board
Symbol
θJA
θJA
θJA
θJC
θJB
Conditions Min. Typ. Max. Units
Still air
28.2
°C/W
1 m/s air flow
21.6
°C/W
3 m/s air flow
17.9
°C/W
14.4
°C/W
0.61
°C/W
Marking Diagram
ICS
9ZX21901DKLF
LOT
COO YYWW
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. “YYWW” is the last two digits of the year and week that the part was assembled.
4. “LF” denotes RoHS compliant package.
Ordering Information
Part / Order Number
9ZX21901DKLF
9ZX21901DKLFT
Shipping Package
Trays
Tape and Reel
Package
72-pin VFQFPN
72-pin VFQFPN
Temperature
0 to +70°C
0 to +70°C
"LF" designates PB-free configuration, RoHS compliant.
"D" designates die revision and does not correlate to data sheet revision.
19-OUTPUT DB1900Z FOR PCIE GEN1-4 AND QPI/UPI
16
APRIL 17, 2018
Revision History
Issue Date Description
1. Updated electrical tables
9/16/2016
2. Move to Final
10/5/2016 Changed IDD maximum value from 450 to 490mA
1. Features change: "Hardware or software control of PLL operating mode; change mode with software mode does not need
power cycle."
2. Change Max of Powerdown Current IDDPD to 5mA.
3. Input frequency of PLL mode:
(1). Change Min of 100MHz to 98.5HMz and Max of 100MHz to 102MHz.
(2). Change Max of 133.33MHz to 130.5MHz and Max of 133.33MHz to 135MHz.
4. DIF HCSL/LP-HCSL Outputs:
(1). Change Min of Max Voltage to 719mV and Max of Max Voltage to 842mV.
(2). Change Min of (Crossing Voltage (abs)) to 310mV and Max of (Crossing Voltage (abs)) to 400mV.
5. Change Typ of Cycle to cycle jitter of PLL mode to 17ps.
2/15/2017
6.Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures"
(1).Change Typ of additive phase jitter of bypass mode of PCIe Gen1 to 0.1.
(2). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen2 Lo Band to 0.1.
(3). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen3 to 0.1.
(4). Change Typ and max of additive phase jitter of bypass mode of PCIe Gen4 to 0.1.
7.Unfiltered Phase Jitter Parameters - 12kHz to 20MHz
(1). Change Min,TYP and Max of PLLmode High BW to 161, 178, 198ps.
(2). Change Min,TYP and Max of PLLmode Low BW to 175, 193, 207ps.
(3). Change Min,TYP and Max of Bpmode to 104, 104, 110ps.
12/1/2017 Removed “5V tolerant” reference in pins 12 and 13 descriptions.
4/17/2018 Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.idt.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
9ZX21901D APRIL 17, 2018
17
©2018 Integrated Device Technology, Inc.
72-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.90 mm Body, Epad 5.95 x 5.95 mm 0.50mm Pitch
NLG72P1, PSC-4208-01, Rev 03, Page 1
© Integrated Device Technology, Inc.
72-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.90 mm Body, Epad 5.95 x 5.95 mm 0.50mm Pitch
NLG72P1, PSC-4208-01, Rev 03, Page 2
Package Revision History
Date Created
© Integrated Device Technology, Inc.
Rev No.
Description
Sept 3, 2019
Rev 03
Update P1 Dimension from 5. 8 to 5.95 mm SQ
May 8, 2017
Rev 02
Change Package Code QFN to VFQFPN
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