9ZXL0651AKLFT

6-Output DB800ZL Derivative with Integrated 85ohm Terminations Description 9ZXL0651 Datasheet Features • 25MHz PFT clock delay management • Low-Power-HCSL outputs with Zo = 85; save power The 9ZXL0651 is a low-power 6-output differential buffer that meets all the performance requirements of the Intel DB1200Z specification. It consumes 50% less power than standard HCSL devices and has internal terminations to allow direct connection to 85 transmission lines. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications. and board space – no termination resistors required. Ideal for blade servers. • • • • • Applications Buffer for Romley, Grantley and Purley Servers, SSDs and PCIe Space-saving 40-pin VFQFPN package Fixed feedback path for 0ps input-to-output delay 6 OE# pins; hardware control of each output PLL or bypass mode; PLL can dejitter incoming clock Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs • Spread spectrum compatible; tracks spreading input Output Features clock for low EMI • 6 – LP-HCSL Output Pairs w/integrated terminations Key Specifications (Zo = 85) • • • • • Block Diagram Cycle-to-cycle jitter < 50ps Output-to-output skew < 65ps Input-to-output delay variation < 50ps PCIe Gen3 phase jitter < 1.0ps RMS QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS OE(5:0)# DFB_OUT_NC Z-PLL (SS Compatible) DIF_IN DIF_IN# DIF(5:0) HIBW_BYPM_LOBW# CKPWRGD/PD# Logic SMBDAT SMBCLK ©2021 Renesas Electronics Corporation 1 January 28, 2021 9ZXL0651 Datasheet VDD vOE4# DIF_4 DIF_4# VDD DIF_5 DIF_5# vOE5# VDD NC Pin Configuration 40 39 38 37 36 35 34 33 32 31 9ZXL0651 VDDA 1 ^vHIBW_BYPM_LOBW# 2 CKPWRGD_PD# 3 GND 4 VDDR 5 DIF_IN 6 DIF_IN# 7 SMBDAT 8 SMBCLK 9 DFB_OUT_NC# 10 30 29 28 27 26 25 24 23 22 21 EPAD is GND NC VDD vOE3# DIF_3# DIF_3 VDD DIF_2# DIF_2 vOE2# VDD VDD vOE1# DIF_1 DIF_1# VDD DIF_0# DIF_0 vOE0# VDD DFB_OUT_NC 11 12 13 14 15 16 17 18 19 20 40-VFQFPN ^ prefix indicates internal Pull-Up Resistor v pref ix indicates Internal Pull-Dow n Resistor ^v prefix indicates Internal Pull-Up/Dow n Resistor (biased to VDD/2) 5mm x 5mm 0.4mm pin pitch Power Management Table CKPWRGD_PD# 0 DIF_IN/ DIF_IN# X 1 Running SMBus EN bit X 0 1 DIF(5:0)/ DIF(5:0)# Low/Low Low/Low Running PLL STATE IF NOT IN BYPASS MODE OFF ON ON PLL Operating Mode PLL Operating Mode Readback Table HiBW_BypM_LoBW# MODE Low PLL Lo BW Mid Bypass High PLL Hi BW NOTE: PLL is OFF in Bypass Mode HiBW_BypM_LoBW# Low (Low BW) Mid (Bypass) High (High BW) Byte 0, bit 6 0 1 1 Tri-level Input Thresholds Power Connections Pin Number VDD GND 1 41 5 4 12,16,20,24,27 41 ,31,32,36,40 Byte0, bit 7 0 0 1 Level Low Mid High Description Analog PLL Analog Input 9ZXL0651 SMBus Address DIF clocks ©2021 Renesas Electronics Corporation Voltage