9ZXL0831EKKLF

4 to 12-Output Buffers for PCIe Gen1–5 and UPI 9ZXL04x1E/9ZXL06x1E/ 9ZXL08x1E/9ZXL12x1E Datasheet Description Features The 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E family of Zero-Delay/Fanout Buffers (ZDB, FOB) are 2nd-generation enhanced performance buffers for PCIe and CPU applications. The family meets all published QPI/UPI, DB2000Q and PCIe Gen1–5 jitter specifications. Devices range from 4 to 12 outputs, with each output having an OE# pin to support the PCIe CLKREQ# function for low power states. All devices meet DB2000Q, DB1200ZL and DB800ZL jitter and skew requirements. ▪ 4–12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations eliminate up to 4 resistors per output pair ▪ Dedicated OE# pins support PCIe CLKREQ# function ▪ Up to 9 selectable SMBus addresses (9ZXL12) ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference (IR) with and without spread spectrum (SRIS, SRNS) Key Specifications ▪ Fanout Buffer Mode additive phase jitter: • • • • PCIe Gen5 CC < 24s RMS DB2000Q additive jitter < 40s RMS QPI/UPI 11.4GB/s < 40fs RMS IF-UPI additive jitter < 70fs RMS ▪ ZDB Mode phase jitter: • PCIe Gen5 CC < 22fs RMS • QPI/UPI 11.4GB/s < 120fs RMS • IF-UPI additive jitter < 130fs RMS ▪ Cycle-to-cycle jitter < 50ps ▪ Output-to-output skew < 50 ps Hardware/SMBus control of ZDB and FOB modes Spread-spectrum compatible 1–400MHz FOB operation (all devices) 100MHz and 133.33MHz ZDB mode (9ZXL12, 9ZXL08) 100MHz ZDB mode (9ZXL06, 9ZXL04) -40°C to +85°C operating temperature range (all devices) -40°C to +105°C operating temperature range (9ZXL08) Package information: see Ordering Information for details Typical Applications ▪ ▪ ▪ ▪ ▪ Servers/High-performance Computing nVME Storage Networking Accelerators Industrial Control Block Diagram VDDR VDDA VDDIO (9ZXL12x1 only) VDD FBOUT_NC# FBOUT_NC PLL DIF_IN# DIFn# DIF_IN 9ZXL12x1 9ZXL08x1 only DIFn ^100M_133M# 9ZXL12x1 only vSADR1_tri 9ZXL12x1 9ZXL0451 only vSADR0_tri SMBCLK SMBDAT SMBus Engine 12, 8, 6, or 4 outputs Factory Configuration DIF0# ^vHIBW_BYPM-LOBW# ^CKPWRGD_PD# DIF0 Control Logic vOE[n:0]# Series resistors are integrated on 9ZXLxx51 devices and external on 9ZXLxx31 devices GNDA ©2020 Renesas Electronics Corporation GND 1 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCIe Clocking Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9ZXL0451E Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9ZXL06x1E Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9ZXL08x1E Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9ZXL12x1E Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9ZXL04x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9ZXL06x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9ZXL08x1 (industrial temperature range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9ZXL08x1 (extended temperature range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9ZXL12x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ©2020 Renesas Electronics Corporation 2 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Pin Assignments 9ZXL0451E Pin Assignment VDD DIF3 vOE3# VDD DIF3# VDDA NC ^HIBW_BYPM_LOBW# Figure 1. Pin Assignments for 5 × 5 mm 32-VFQFPN Package – Top View 32 31 30 29 28 27 26 25 ^CKPWRGD_PD# 1 VDDR 2 DIF_IN 3 24 vOE2# 23 DIF2# 22 DIF2 9ZXL0451E DIF_IN# 4 vSADR0_tri 5 SMBDAT 6 21 VDD 20 DIF1# 19 DIF1 connect EPAD to ground SM BCLK 7 FBOUT_NC# 8 18 vOE1# 17 NC VDD DIF0# vOE0# VDD DIF0 NC NC FBOUT_NC 9 10 11 12 13 14 15 16 5 × 5mm, 32-VFQFPN, 0.5mm pitch ^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull-down resistor ©2020 Renesas Electronics Corporation 3 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet 9ZXL06x1E Pin Assignment VDD vOE4# DIF4 DIF4# VDD DIF5 DIF5# vOE5# VDD NC Figure 2. Pin Assignments for 5 × 5 mm 40-VFQFPN Package – Top View 40 39 38 37 36 35 34 33 32 31 VDDA 1 30 NC ^HIBW_BYPM_LOBW# 2 29 VDD ^CKPWRGD_PD# 3 28 vOE3# 9ZXL0631E 9ZXL0651E GNDR 4 VDDR 5 DIF_IN 6 27 DIF3# 26 DIF3 25 VDD pin 41 is EPAD, connect to GND DIF_IN# 7 24 DIF2# SMBDAT 8 23 DIF2 SMBCLK 9 22 vOE2# FBOUT_NC# 10 21 VDD VDD vOE1# DIF1# DIF1 VDD DIF0# DIF0 vOE0# VDD FBOUT_NC 11 12 13 14 15 16 17 18 19 20 5 × 5mm, 40-VFQFPN, 0.4mm pad pitch Pins with ^ prefix have internal 120kOhm pull-up Pins with v prefix have internal 120kOhm pull-down ©2020 Renesas Electronics Corporation 4 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet 9ZXL08x1E Pin Assignment vOE6# VDD DIF7 DIF7# vOE7# VDD NC VDDA NC NC ^100M_133M# ^HIBW_BYPM_LOBW# Figure 3. Pin Assignments for 6 × 6 mm 48-VFQFPN Package – Top View 48 47 46 45 44 43 42 41 40 39 38 37 ^CKPWRGD_PD# 1 36 DIF6# GNDR 2 35 DIF6 VDDR 3 34 VDD DIF_IN 4 33 DIF5# 9ZXL0831E 9ZXL0851E DIF_IN# 5 SMBDAT 6 32 DIF5 31 vOE5# EPAD is pin 49 Connect to GND SMBCLK 7 FBOUT_NC# 8 30 vOE4# 29 DIF4# FBOUT_NC 9 28 DIF4 VDD 10 27 VDD vOE0# 11 26 DIF3# NC 12 25 DIF3 vOE3# vOE2# DIF2# DIF2 NC VDD vOE1# DIF1# DIF1 VDD DIF0# DIF0 13 14 15 16 17 18 19 20 21 22 23 24 6 × 6mm, 48-VFQFPN, 0.4mm pad pitch Pins with ^ prefix have internal 120kOhm pull-up Pins with v prefix have internal 120kOhm pull-down ©2020 Renesas Electronics Corporation 5 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet 9ZXL12x1E Pin Assignment VDDIO DIF8 DIF8# vOE8# vOE9# DIF9 DIF9# VDDIO VDD GND DIF10 DIF10# vOE10# vOE11# DIF11 DIF11# Figure 4. Pin Assignments for 9 × 9 mm 64-VFQFPN Package – Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA 1 48 GND GNDA 2 47 DIF7# NC 3 46 DIF7 ^100M_133M# 4 45 vOE7# ^HIBW_BYPM_LOBW# 5 44 vOE6# ^CKPWRGD_PD# 6 43 DIF6# GNDR 7 42 DIF6 9ZXL1231E 9ZXL1251E VDDR 8 DIF_IN 9 41 GND 40 VDD connect EPAD to ground DIF_IN# 10 39 DIF5# vSADR0_tri 11 38 DIF5 SMBDAT 12 37 vOE5# SMBCLK 13 36 vOE4# vSADR1_tri 14 35 DIF4# FBOUT_NC# 15 34 DIF4 FBOUT_NC 16 33 GND VDDIO DIF3 DIF3# vOE3# vOE2# DIF2# DIF2 VDDIO VDD GND DIF1# DIF1 vOE1# vOE0# DIF0# DIF0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 × 9mm 64-VFQFPN, 0.5mm pad pitch Pins with ^ prefix have internal 120kOhm pull-up Pins with v prefix have internal 120kOhm pull-down ©2020 Renesas Electronics Corporation 6 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Pin Descriptions Table 1. Pin Descriptions Name Type 9ZXL12x1 9ZXL08x1 Pin No. Pin No. Description 9ZXL06x1 Pin No. 9ZXL04x1 Pin No. 3.3V Input to select operating frequency. This pin has an ^100M_133M# Latched In internal pull-up resistor. See Frequency Selection (PLL Mode) for definition. 4 47 — — Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 6 1 3 1 Tri-level input to select High BW, Bypass or Low BW Mode. ^HIBW_BYPM Latched In This pin has an internal pull-up resistor. See PLL Operating _LOBW# Mode table for details. 5 48 2 32 DIF_IN Input HCSL true input. 9 4 6 3 DIF_IN# Input HCSL complementary input. 10 5 7 4 DIF0 Output Differential true clock output. 17 13 14 13 DIF0# Output Differential complementary clock output. 18 14 15 14 DIF1 Output Differential true clock output. 21 16 17 19 DIF1# Output Differential complementary clock output. 22 17 18 20 DIF10 Output Differential true clock output. 59 — — — DIF10# Output Differential complementary clock output. 60 — — — DIF11 Output Differential true clock output. 63 — — — DIF11# Output Differential complementary clock output. 64 — — — DIF2 Output Differential true clock output. 26 21 23 22 DIF2# Output Differential complementary clock output. 27 22 24 23 DIF3 Output Differential true clock output. 30 25 26 27 DIF3# Output Differential complementary clock output. 31 26 27 28 DIF4 Output Differential true clock output. 34 28 33 n/a DIF4# Output Differential complementary clock output. 35 29 34 n/a DIF5 Output Differential true clock output. 38 32 36 n/a DIF5# Output Differential complementary clock output. 39 33 37 n/a DIF6 Output Differential true clock output. 42 35 — — DIF6# Output Differential complementary clock output. 43 36 — — DIF7 Output Differential true clock output. 46 39 — — DIF7# Output Differential complementary clock output. 47 40 — — DIF8 Output Differential true clock output. 50 — — — DIF8# Output Differential complementary clock output. 51 — — — DIF9 Output Differential true clock output. 54 — — — DIF9# Output Differential complementary clock output. 55 — — — ^CKPWRGD_ PD# Input ©2020 Renesas Electronics Corporation 7 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 1. Pin Descriptions (Cont.) Name EPAD Type GND 9ZXL12x1 9ZXL08x1 Pin No. Pin No. Description 9ZXL06x1 Pin No. 9ZXL04x1 Pin No. Connect epad to ground. 65 49 41 33 FBOUT_NC Output True half of differential feedback output. This pin should NOT be connected to anything outside the chip. It exists to provide delay path matching to get 0 propagation delay. 16 9 11 9 FBOUT_NC# Output Complementary half of differential feedback output. This pin should NOT be connected to anything outside the chip. It exists to provide delay path matching to get 0 propagation delay. 15 8 10 8 GND GND Ground pin. 23 49 41 33 GND GND Ground pin. 33 49 41 n/a GND GND Ground pin. 41 49 — — GND GND Ground pin. 48 49 — — GND GND Ground pin. 58 — — — GNDA GND Ground pin for the PLL core. 2 49 41 33 GNDR GND Analog ground pin for the differential input (receiver). 7 2 4 33 No connection. 3 12, 20, 43, 45, 46 30, 40 10, 11, 17, 30 NC — SMBCLK Input Clock pin of SMBUS circuitry. 13 7 9 7 SMBDAT I/O Data pin of SMBUS circuitry. 12 6 8 6 VDD Power Power supply, nominally 3.3V. 24 10, 15, 19, 27, 34, 38, 42 VDD Power Power supply, nominally 3.3V. 40 — — — VDD Power Power supply, nominally 3.3V. 57 — — — VDDA Power Power supply for PLL core. 1 44 1 31 VDDIO Power Power supply for differential outputs. 25 — — — VDDIO Power Power supply for differential outputs. 32 — — — VDDIO Power Power supply for differential outputs. 49 — — — VDDIO Power Power supply for differential outputs. 56 — — — VDDR Power Power supply for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. Nominally 3.3V. 8 3 5 2 vOE0# Input Active low input for enabling output 0. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 19 11 13 15 vOE1# Input Active low input for enabling output 1. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 20 18 19 18 vOE10# Input Active low input for enabling output 10. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 61 — — — ©2020 Renesas Electronics Corporation 8 12, 16, 20, 12, 16, 21, 25, 29, 21, 25, 29 31, 35, 39 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 1. Pin Descriptions (Cont.) Name vOE11# vOE2# vOE3# vOE4# vOE5# vOE6# vOE7# vOE8# vOE9# vSADR0_tri vSADR1_tri 9ZXL12x1 9ZXL08x1 Pin No. Pin No. 9ZXL06x1 Pin No. 9ZXL04x1 Pin No. — — — 28 23 22 24 Input Active low input for enabling output 3. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 29 24 28 26 Input Active low input for enabling output 4. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 36 30 32 — Input Active low input for enabling output 5. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 37 31 38 — Input Active low input for enabling output 6. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 44 37 — — Input Active low input for enabling output 7. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 45 41 — — Input Active low input for enabling output 8. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 52 n/a — — Input Active low input for enabling output 9. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 53 — — — Input SMBus address bit. This is a tri-level input that works in conjunction with other SADR pins, if present, to decode SMBus Addresses. It has an internal pull down resistor. See the SMBus Addresses table. 11 — — 5 Input SMBus address bit. This is a tri-level input that works in conjunction with other SADR pins, if present, to decode SMBus Addresses. It has an internal pull down resistor. See the SMBus Addresses table. 14 — — — Type Description Input Active low input for enabling output 11. This pin has an internal pull-down. 1 = disable output, 0 = enable output. 62 Input Active low input for enabling output 2. This pin has an internal pull-down. 1 = disable output, 0 = enable output. ©2020 Renesas Electronics Corporation 9 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Symbol Supply Voltage VDDX Input Low Voltage VIL Input High Voltage VIH Except for SMBus interface Input High Voltage, SMBus VIHSMB SMBus clock and data pins. Storage Temperature Ts Junction Temperature Tj Input ESD Protection ESD prot 1 2 3 Conditions Minimum Maximum Units Notes 3.9 V 1,2 V 1 VDD + 0.5 V 1,3 3.9 V 1 150 °C 1 125 °C 1 V 1 GND - 0.5 -65 Human Body Model. 2500 Guaranteed by design and characterization, not 100% tested in production. Operation under these conditions is neither implied nor guaranteed. Not to exceed 3.9V. Thermal Characteristics Table 3. Thermal Characteristics Parameter 9ZXL04x1 Thermal Resistance 9ZXL06x1 Thermal Resistance 9ZXL08x1 Thermal Resistance Symbol Conditions Package Typical Values Units Notes θJC Junction to case. 32 °C/W 1 θJb Junction to base. 2 °C/W 1 θJA0 Junction to air, still air. 44 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 37 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 32.5 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 30.9 °C/W 1 θJC Junction to case. 32 °C/W 1 θJb Junction to base. 2 °C/W 1 θJA0 Junction to air, still air. 44 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 37 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 33 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 31 °C/W 1 θJC Junction to case. 19 °C/W 1 θJb Junction to base. 0 °C/W 1 θJA0 Junction to air, still air. 30 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 23 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 20 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 19 °C/W 1 ©2020 Renesas Electronics Corporation NLG32 NDG40 NDG48 10 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 3. Thermal Characteristics (Cont.) Parameter Symbol 9ZXL12x1 Thermal Resistance 1 EPAD Conditions Package Typical Values Units Notes θJC Junction to case. 14 °C/W 1 θJb Junction to base. 1 °C/W 1 θJA0 Junction to air, still air. 28 °C/W 1 θJA1 Junction to air, 1 m/s air flow. 21 °C/W 1 θJA3 Junction to air, 3 m/s air flow. 19 °C/W 1 θJA5 Junction to air, 5 m/s air flow. 18 °C/W 1 NLG64 soldered to board. Electrical Characteristics TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions. Table 4. SMBus Parameters Parameter Symbol SMBus Input Low Voltage VILSMB SMBus Input High Voltage VIHSMB SMBus Output Low Voltage VOLSMB At IPULLUP. SMBus Sink Current IPULLUP At VOL. Nominal Bus Voltage VDDSMB SCLK/SDATA Rise Time tRSMB SCLK/SDATA Fall Time SMBus Operating Frequency 1 2 3 4 5 Conditions Minimum Typical 2.1 Maximum Units 0.8 V VDDSMB V 0.4 V 4 Notes mA 2.7 3.6 V (Max. VIL - 0.15V) to (Min. V IH + 0.15V). 1000 ns 1 tFSMB (Min. VIH + 0.15V) to (Max. VIL - 0.15V). 300 ns 1 fSMB SMBus operating frequency. 500 kHz 5 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. Time from deassertion until outputs are > 200mV. DIF_IN input. The differential input clock must be running for the SMBus to be active. Table 5. DIF_IN Clock Input Parameters Parameter Symbol Input Crossover Voltage–DIF_IN VCROSS Crossover voltage. 150 Input Swing–DIF_IN VSWING Differential value. 300 Input Slew Rate–DIF_IN dv/dt Measured differentially. 0.4 Input Leakage Current IIN VIN = VDD , VIN = GND. Input Duty Cycle dtin Input Jitter–Cycle to Cycle JDIFIn 1 2 Conditions Minimum Typical Maximum Units Notes 900 mV 1 mV 1 8 V/ns 1,2 -5 5 μA Measurement from differential waveform. 45 55 % 1 Differential measurement. 0 125 ps 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through ±75mV window centered around differential zero. ©2020 Renesas Electronics Corporation 11 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 6. Input/Supply/Common Parameters – Normal Operating Conditions Parameter Symbol Conditions Minimum Typical Supply Voltage VDDX Output Supply Voltage VDDIO Ambient Operating Temperature TAMB Input High Voltage VIH Single-ended inputs, except SMBus, tri-level inputs. Supply voltage for core and analog. 3.135 3.3 3.465 V Supply voltage for DIF outputs, if present. 0.95 1.05 3.465 V 5 Extended Industrial range (TEXIND). -40 25 105 °C 7 Industrial range (TIND). -40 25 85 °C VDD + 0.3 V Input Low Voltage VIL Single-ended inputs, except SMBus, tri-level inputs. GND - 0.3 0.8 V Input High Voltage VIHtri Tri-level inputs. 2.2 VDD + 0.3 V Input Mid Voltage VIMtri Tri-level inputs. 1.2 1.8 V Input Low Voltage VILtri Tri-level inputs. GND - 0.3 0.8 V 2 VDD/2 Maximum Units Notes IIN Single-ended inputs, VIN = GND, VIN = VDD. -5 5 μA IINP Single-ended inputs VIN = 0 V; inputs with internal pull-up resistors. VIN = VDD; inputs with internal pull-down resistors. -50 50 μA Fibyp VDD = 3.3 V, Bypass Mode. 1 400 MHz Fipll VDD = 3.3 V, 100MHz PLL Mode. 98.5 100.00 102.5 MHz Fipll VDD = 3.3 V, 133.33MHz PLL Mode. 132 133.33 135 MHz ppm Error Contribution ppm ppm error contributed to input clock. Pin Inductance Lpin Input Current Input Frequency CIN Capacitance Logic inputs, except DIF_IN. CINDIF_IN DIF_IN differential clock inputs. COUT Output pin capacitance. CLK Stabilization tSTAB From VDD power-up and after input clock stabilization or de-assertion of PD# to 1st clock. Input SS Modulation Frequency PCIe fMODINPCIe OE# Latency 1 2 3 4 5 6 7 0 6 ppm 7 nH 1 1.5 5 pF 1 1.5 2.7 pF 1,4 6 pF 1 1.8 ms 1,2 33 kHz 1 Allowable frequency for PCIe applications (Triangular modulation). 30 tLATOE# DIF start after OE# assertion. DIF stop after OE# deassertion. 4 Tdrive_PD# tDRVPD DIF output enable after. PD# de-assertion. Fall Time tF Rise Time tR 5 10 clocks 1,2,3 49 300 μs 1,3 Fall time of control inputs. 5 ns 2 Rise time of control inputs. 5 ns 2 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. Time from deassertion until outputs are > 200mV. DIF_IN input. 9ZXL12x1 only. 9ZXL12x1 and 9ZXL08x1 only. Not all devices are available in this temperature range. See ordering information for details. ©2020 Renesas Electronics Corporation 12 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 7. LP-HCSL Outputs Parameter Symbol Conditions Minimum Typical Maximum Slew Rate dV/dt Scope averaging on. Slew Rate Matching ΔdV/dt Single-ended measurement. Maximum Voltage VMAX Minimum Voltage VMIN Measurement on single ended signal using absolute value. (Scope averaging off). 2 Crossing Voltage (abs) Vcross_abs Scope averaging off. Crossing Voltage (var) 1 Guaranteed 2 5 6 7 8 2.9 4 1–4 V/ns 1,2,3 7.1 20 20 % 1,4,7 700 792 850 660 – 1150 mV 7,8 -150 -35 150 -300 300 372 462 250 – 550 mV 1,5,7 15 50 140 mV 1,6,7 Scope averaging off. 7,8 by design and characterization, not 100% tested in production.  Measured from differential waveform. 3 Slew 4 Δ-Vcross Specification Units Notes Limit rate is measured through the Vswing voltage range centered around differential 0V. This results in a ±150mV window around differential 0V. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75 mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. At default SMBus settings. Includes previously separate values of +300mV overshoot and -300mV of undershoot. Table 8. Current Consumption – 9ZXL04x1 Parameter Symbol Operating Supply Current IDDA Power Down Current 1 Conditions Minimum Typical Maximum Units Notes VDDA, ZDB Mode at 100MHz. 37 44 mA 1 VDDA, Fanout Buffer Mode at 100MHz. 4 5 mA 1 All other VDD pins, any mode at 100MHz. 33 40 mA IDDAPD VDDA pin, CKPWRGD_PD# = 0. 3 5 mA IDDPD All other VDD pins, CKPWRGD_PD# = 0. 1 2 mA IDD 1 Includes VDDR. Table 9. Current Consumption – 9ZXL06x1 Parameter Symbol Operating Supply Current IDDA Power Down Current 1 Conditions Minimum Typical Maximum Units Notes VDDA, PLL Mode at 100MHz. 37 45 mA 1 VDDA, Fanout Buffer Mode at 100MHz. 4 5 mA 1 All other VDD pins at 100MHz. 41 50 mA IDDAPD VDDA, CKPWRGD_PD# = 0. 3 4 mA IDDPD All other VDD pins, CKPWRGD_PD# = 0. 1 2 mA IDD 1 Includes VDDR. ©2020 Renesas Electronics Corporation 13 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 10. Current Consumption – 9ZXL08x1 Parameter Symbol Operating Supply Current IDDA Power Down Current 1 Conditions Minimum Typical Maximum Units Notes VDDA, PLL Mode at 100MHz. 37 45 mA 1 VDDA, Fanout Buffer Mode at 100MHz. 4 5 mA 1 All other VDD pins at 100MHz. 55 68 mA IDDAPD VDDA, CKPWRGD_PD# = 0. 3 4 mA IDDPD All other VDD pins, CKPWRGD_PD# = 0. 1 2 mA IDD 1 Includes VDDR. Table 11. Current Consumption – 9ZXL12x1 Parameter Operating Supply Current Symbol 1 Minimum Typical Maximum Units Notes VDDA, PLL Mode at 100MHz. 38 46 mA 1 VDDA, Fanout Buffer Mode at 100MHz. 4 5 mA 1 All other VDD pins. 25 34 mA VDDIO for LP-HCSL outputs, if applicable. 83 107 mA IDDAPD VDDA, CKPWRGD_PD# = 0. 3 4 mA IDDPD All other VDD pins, CKPWRGD_PD# = 0. 1 2 mA IDDA IDD IDDIO Power Down Current Conditions 1 Includes VDDR. Table 12. PCIe Phase Jitter TAMB = over the specified operating range. Supply voltages per normal operation conditions. See Test Loads for loading conditions. Parameter PCIe Phase Jitter, Low Bandwidth ZDB Mode (Common Clocked Architecture) PCIe Phase Jitter, Low Bandwidth ZDB Mode (SRIS Architecture) Symbol Conditions Units Notes tjphPCIeG1-CC PCIe Gen1 (2.5 GT/s) 2.6 6.8 86 ps (p-p) 1,2 PCIe Gen2 Hi Band (5.0 GT/s) 0.09 0.16 3 ps (RMS) 1,2 PCIe Gen2 Lo Band (5.0 GT/s) 0.08 0.12 3.1 ps (RMS) 1,2 tjphPCIeG3-CC PCIe Gen3 (8.0 GT/s) 0.05 0.07 1 ps (RMS) 1,2 tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) 0.05 0.07 0.5 ps (RMS) 1,2,3,4 tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) 0.018 0.022 0.15 ps (RMS) 1,2,3,5 tjphPCIeG1-SRIS PCIe Gen1 (2.5 GT/s) 8.71 8.73 ps (RMS) 1,2,6 tjphPCIeG2-SRIS PCIe Gen2 (5.0 GT/s) 0.81 0.83 ps (RMS) 1,2,6 tjphPCIeG3-SRIS PCIe Gen3 (8.0 GT/s) 0.329 0.335 ps (RMS) 1,2,6 tjphPCIeG4-SRIS PCIe Gen4 (16.0 GT/s) 0.222 0.235 ps (RMS) 1,2,6 tjphPCIeG5-SRIS PCIe Gen5 (32.0 GT/s) 0.084 0.091 ps (RMS) 1,2,6 tjphPCIeG2-CC ©2020 Renesas Electronics Corporation Minimum 14 Typical Maximum Limit N/A August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 12. PCIe Phase Jitter (Cont.) TAMB = over the specified operating range. Supply voltages per normal operation conditions. See Test Loads for loading conditions. Parameter PCIe Phase Jitter, High Bandwidth ZDB Mode (Common Clocked Architecture) PCIe Phase Jitter, High Bandwidth ZDB Mode (SRIS Architecture) 1 2 3 4 5 6 Symbol Conditions Units Notes tjphPCIeG1-CC PCIe Gen1 (2.5 GT/s) 5.4 6.9 86 ps (p-p) 1,2 PCIe Gen2 Hi Band (5.0 GT/s) 0.19 0.25 3 ps (RMS) 1,2 PCIe Gen2 Lo Band (5.0 GT/s) 0.09 0.13 3.1 ps (RMS) 1,2 tjphPCIeG3-CC PCIe Gen3 (8.0 GT/s) 0.10 0.13 1 ps (RMS) 1,2 tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) 0.10 0.13 0.5 ps (RMS) 1,2,3,4 tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) 0.032 0.042 0.15 ps (RMS) 1,2,3,5 tjphPCIeG1-SRIS PCIe Gen1 (2.5 GT/s) 8.61 8.63 ps (RMS) 1,2,6 tjphPCIeG2-SRIS PCIe Gen2 (5.0 GT/s) 0.88 0.96 ps (RMS) 1,2,6 tjphPCIeG3-SRIS PCIe Gen3 (8.0 GT/s) 0.354 0.375 ps (RMS) 1,2,6 tjphPCIeG4-SRIS PCIe Gen4 (16.0 GT/s) 0.271 0.305 ps (RMS) 1,2,6 tjphPCIeG5-SRIS PCIe Gen5 (32.0 GT/s) 0.097 0.109 ps (RMS) 1,2,6 tjphPCIeG2-CC Minimum Typical Maximum Limit N/A The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table. Equipment noise is removed from all results. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. The PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, however, it does not provide specification limits, hence the N/A in the “Limit” column. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by √2. An additional consideration is the value for which to divide by √2. The conservative approach is to divide the ref clock jitter limit, and the case can be made for dividing the channel simulation values by √2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A “rule-of-thumb” SRIS limit would be either 0.5ps RMS/√2 = 0.35ps RMS if the clock chip is far from the clock input, or 0.7ps RMS/√2 = 0.5ps RMS if the clock chip is near the clock input. ©2020 Renesas Electronics Corporation 15 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 13. Skew and Differential Jitter Parameters Parameter Symbol Conditions Minimum Typical Maximum Units CLK_IN, DIF[x:0] tSPO_PLL Input-to-output skew in PLL Mode at 100MHz, nominal temperature and voltage. CLK_IN, DIF[x:0] tPD_BYP Input-to-output skew in Bypass Mode at 100MHz, nominal temperature and voltage. CLK_IN, DIF[x:0] tDSPO_PLL Notes -100 -21.3 100 ps 1,2,4,5,7 2 2.6 3 ns 1,2,3,5,7 Input-to-output skew variation in PLL Mode at 100MHz, across voltage and temperature. -50 0.0 50 ps 1,2,3,5,7 Input-to-output skew variation in Bypass Mode at 100MHz, across voltage and temperature, TAMB = 0°C to +70°C. -250 250 ps 1,2,3,5,7 Input-to-Output Skew variation in Bypass mode at 100MHz, across voltage and temperature, TAMB = -40°C to +85°C. -350 350 ps 1,2,3,5,7 CLK_IN, DIF[x:0] tDSPO_BYP CLK_IN, DIF[x:0] tDTE CLK_IN, DIF[x:0] tDSSTE DIF[x:0] tSKEW_ALL Output-to-output skew across all outputs, common to PLL and Bypass Mode, at 100MHz. PLL Jitter Peaking jpeak-hibw LOBW#_BYPASS_HIBW = 1. 0 PLL Jitter Peaking jpeak-lobw LOBW#_BYPASS_HIBW = 0. PLL Bandwidth pllHIBW PLL Bandwidth pll LOBW Duty Cycle Random differential tracking error between two 9ZX devices in Hi BW Mode. 3 5 Random differential spread spectrum tracking error between two 9ZX devices in Hi BW Mode. 23 50 ps 1,2,3,5,7 50 ps 1,2,3,7 1.3 2.5 dB 6.7 0 1.3 2 dB 6.7 LOBW#_BYPASS_HIBW = 1. 2 2.6 4 MHz 7,8 LOBW#_BYPASS_HIBW = 0. 0.7 1.0 1.4 MHz 7,8 tDC Measured differentially, PLL Mode. 45 50.3 55 % 1 Duty Cycle Distortion tDCD Measured differentially, Bypass Mode at 100MHz. -1 0 1 % 1,9 Jitter, Cycle to Cycle tjcyc-cyc PLL Mode. 14 50 ps 1,10 Additive jitter in Bypass Mode. 0.1 5 ps 1,10 1 2 3 4 5 6 7 8 9 ps 1,2,3,5,7 (rms) Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. This parameter is deterministic for a given device. Measured with scope averaging on to find mean value. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. Guaranteed by design and characterization, not 100% tested in production. Measured at 3db down or half power point. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 10 Measured from differential waveform. ©2020 Renesas Electronics Corporation 16 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 14. Additive PCIe Phase Jitter for Fanout Buffer Mode TAMB = over the specified operating range. Supply voltages per normal operation conditions. See Test Loads for loading conditions. Parameter Additive PCIe Phase Jitter, Fanout Buffer Mode7 (Common Clocked Architecture) Additive PCIe Phase Jitter, Fanout Buffer Mode7 (SRIS Architecture) 1 2 3 4 5 6 7 Symbol Conditions Units Notes tjphPCIeG1-CC PCIe Gen1 (2.5 GT/s) 1.3 1.9 86 ps (p-p) 1,2 PCIe Gen2 Hi Band (5.0 GT/s) 0.089 0.126 3 ps (RMS) 1,2 PCIe Gen2 Lo Band (5.0 GT/s) 0.023 0.034 3.1 ps (RMS) 1,2 tjphPCIeG3-CC PCIe Gen3 (8.0 GT/s) 0.044 0.062 1 ps (RMS) 1,2 tjphPCIeG4-CC PCIe Gen4 (16.0 GT/s) 0.044 0.062 0.5 ps (RMS) 1,2,3,4 tjphPCIeG5-CC PCIe Gen5 (32.0 GT/s) 0.017 0.024 0.15 ps (RMS) 1,2,3,5 tjphPCIeG1-SRIS PCIe Gen1 (2.5 GT/s) 0.127 0.181 ps (RMS) 1,2,6 tjphPCIeG2-SRIS PCIe Gen2 (5.0 GT/s) 0.112 0.159 ps (RMS) 1,2,6 tjphPCIeG3-SRIS PCIe Gen3 (8.0 GT/s) 0.029 0.042 ps (RMS) 1,2,6 tjphPCIeG4-SRIS PCIe Gen4 (16.0 GT/s) 0.031 0.043 ps (RMS) 1,2,6 tjphPCIeG5-SRIS PCIe Gen5 (32.0 GT/s) 0.027 0.038 ps (RMS) 1,2,6 tjphPCIeG2-CC Minimum Typical Maximum Limit N/A The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 5.0, Revision 1.0. See the Test Loads section of the data sheet for the exact measurement setup. The total Ref Clk jitter limits for each data rate are listed for convenience. The worst case results for each data rate are summarized in this table. If oscilloscope data is used, equipment noise is removed from all results. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA) extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at 300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both been done and produce different results, the RTO result must be used. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of any non-SSC content. Note that 0.7ps RMS is to be used in channel simulations to account for additional noise in a real system. Note that 0.25ps RMS is to be used in channel simulations to account for additional noise in a real system. The PCI Express Base Specification 5.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values, however, it does not provide specification limits, hence the N/A in the “Limit” column. In general, a clock operating in an SRIS system must be twice as good as a clock operating in a Common Clock system. For RMS values, twice as good is equivalent to dividing the CC value by √2. An additional consideration is the value for which to divide by √2. The conservative approach is to divide the ref clock jitter limit, and the case can be made for dividing the channel simulation values by √2, if the ref clock is close to the Tx clock input. An example for Gen4 is as follows. A “rule-of-thumb” SRIS limit would be either 0.5ps RMS/√2 = 0.35ps RMS if the clock chip is far from the clock input, or 0.7ps RMS/√2 = 0.5ps RMS if the clock chip is near the clock input. Additive jitter for RMS values is calculated by solving for “b” where b = √(c2 - a2) and where “a” is rms input jitter and “c” is rms output jitter. ©2020 Renesas Electronics Corporation 17 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 15. Filtered Phase Jitter Parameters – QPI/UPI, IF-UPI and DB2000Q Parameter Phase Jitter, ZDB Mode Conditions Minimum Typical Maximum Specification Limit Units Notes QPI and UPI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.16 0.37 0.5 ps (rms) 1,2 QPI and UPI (100MHz, 8.0Gb/s, 12UI) 0.10 0.15 0.3 ps (rms) 1,2 QPI and UPI (100MHz, ≤11.4Gb/s, 12UI) 0.08 0.12 0.2 ps (rms) 1,2 QPI and UPI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) 0.03 0.05 ps (rms) 1,2,3 QPI and UPI (100MHz, 8.0Gb/s, 12UI) 0.03 0.05 ps (rms) 1,2,3 QPI and UPI (100MHz, ≤11.4Gb/s, 12UI) 0.02 0.04 ps (rms) 1,2,3 IF-UPI, Lo-BW ZDB Mode 0.10 0.13 1 ps (rms) 1,4,5 IF-UPI, Hi-BW ZDB Mode 0.17 0.20 1 ps (rms) 1,4,5 IF-UPI, Fanout Mode 0.06 0.07 1 ps (rms) 1,4 DB2000Q, Fanout Mode 28 39 80 fs (rms) 1,4,5 Symbol tjphQPI_UPI tjphQPI_UPI Additive Phase Jitter, Fanout Mode tjphIF-UPI tjphDB2000Q 1  Applies to all differential outputs, guaranteed by design and characterization. See Test Loads for measurement setup details 2 Calculated 3 N/A from Intel-supplied Clock Jitter Tool. For RMS values, additive jitter is calculated by solving for “b” where b = √(c2 - a2) and where “a” is rms input jitter and “c” is rms output jitter. 4 Calculated from phase noise analyzer with Intel-specified brick-wall filter applied. This is an additive jitter specification regardless of buffer operating mode. 5 The IF-UPI specification is an additive specification, regardless of the buffer operating mode. The enhanced 9ZXL devices meet this specification in all operating modes. Table 16. Phase Jitter Parameters – 12kHz to 20MHz Parameter Symbol Conditions Minimum Typical Maximum Specification Limit 12k–20M Additive Phase Jitter, Fanout Buffer Mode tjph12k-20MFOB Fanout Buffer Mode, SSC OFF, 100MHz 98 N/A 1 Applies 2 12kHz 3 125 Units Notes fs (rms) 1,2,3 to all differential outputs, guaranteed by design and characterization. See Test Loads for measurement setup details to 20MHz brick wall filter. For RMS values, additive jitter is calculated by solving for “b” where b = √(c2 - a2) and where “a” is rms input jitter and “c” is rms output jitter. ©2020 Renesas Electronics Corporation 18 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Power Management Table 17. Power Management CKPWRGD_PD# DIF_IN SMBus EN bit OE[x]# Pin DIF[x] PLL State (in ZDB Mode) 0 X X X Low/Low OFF 0 0 Low/Low ON 0 1 Low/Low ON 1 0 Running ON 1 1 Low/Low ON 1 Running Table 18. Frequency Selection (PLL Mode) 100M_133M# DIF_IN MHz DIF[x] 1 100.00 DIF_IN 0 133.33 DIF_IN Note: 9ZXL12x1 and 9ZXL08x1 only. 9ZXL06x1 and 9ZXL0451 are 100MHz only. Table 19. PLL Operating Mode HiBW_BypM_LoBW# Mode PLL Low PLL Lo BW Running Mid Bypass Off High PLL Hi BW Running Note: See SMBus Byte 0, bits 7 and 6 for additional information. ©2020 Renesas Electronics Corporation 19 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Test Loads Figure 5. Test Load for AC/DC Measurements CL CKIN+ CK+ L CK+ Zo (differential) DUT Clock Source CK- CKIN- Test Points for High Impedance Probe CK- CL Table 20. Parameters for AC/DC Measurements Clock Source Device Under Test (DUT) Rs (Ω) Differential Zo (Ω) L (cm) CL (pF) SMA100B 9ZXLxx3x 27 External 85 25.4 2 SMA100B 9ZXLxx5x Internal 85 25.4 2 Figure 6. Test Load for Phase Jitter Measurements using Phase Noise Analyzer PNA Coax Cables L CK+ CKIN+ CK+ Zo (differential) DUT Clock Source CKIN- CK- Balun 0.1uF CK- 50 SMA Connectors Table 21. Parameters for Phase Jitter Measurements using Phase Noise Analyzer Clock Source Device Under Test (DUT) Rs (Ω) Differential Zo (Ω) L (cm) CL (pF) Notes SMA100B 9ZXLxx3x 27 External 85 25.4 N/A Fanout Mode 9FGV1006 9ZXLxx3x 27 External 85 25.4 N/A ZDB Mode SMA100B 9ZXLxx5x Internal 85 25.4 N/A Fanout Mode 9FGV1006 9ZXLxx5x Internal 85 25.4 N/A ZDB Mode ©2020 Renesas Electronics Corporation 20 Parameters Measured PCIe, IF-UPI, DB2000Q August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Figure 7. Test Load for Phase Jitter Measurements using Oscilloscope Oscillocope (≥ 20GS/s) L CK+ CKIN+ CK+ Zo (differential) DUT Clock Source CKIN- CK- Coax Cables 0.1uF CK- 50 SMA Connectors 50 Table 22. Parameters for Phase Jitter Measurements using Oscilloscope Clock Source Device Under Test (DUT) Rs (Ω) Differential Zo (Ω) L (cm) CL (pF) Notes SMA100B 9ZXLxx3x 27 External 85 25.4 N/A Fanout Mode 9FGV1006 9ZXLxx3x 27 External 85 25.4 N/A ZDB Mode SMA100B 9ZXLxx5x Internal 85 25.4 N/A Fanout Mode 9FGV1006 9ZXLxx5x Internal 85 25.4 N/A ZDB Mode ©2020 Renesas Electronics Corporation 21 Parameters Measured QPI/UPI August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet General SMBus Serial Interface Information How to Write How to Read ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Controller (host) sends a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) sends the byte count = X Renesas clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 Renesas clock will acknowledge each byte one at a time Controller (host) sends a stop bit Index Block Write Operation Controller (Host) Renesas (Slave/Receiver) Controller (host) will send a start bit Controller (host) sends the write address Renesas clock will acknowledge Controller (host) sends the beginning byte location = N Renesas clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address Renesas clock will acknowledge Renesas clock will send the data byte count = X Renesas clock sends Byte N+X-1 Renesas clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) ▪ Controller (host) will need to acknowledge each byte ▪ Controller (host) will send a not acknowledge bit ▪ Controller (host) will send a stop bit T starT bit Slave Address WR WRite Index Block Read Operation ACK Beginning Byte = N ACK Controller (Host) starT bit Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X Beginning Byte N X Byte O O O Renesas T ACK ACK O O O RT RD Byte N + X - 1 Repeat starT Slave Address ReaD ACK ACK P stoP bit Data Byte Count = X ACK Note: Address is latched on SADR pin. Beginning Byte N O O O X Byte ACK O O O Byte N + X - 1 N P ©2020 Renesas Electronics Corporation 22 Not acknowledge stoP bit August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 23. SMBus Addresses Pin SMBus Address SADR1_tri SADR0_tri 9ZXL12x1 9ZXL08x1 9ZXL06x1 9ZXL04x1 0 0 D8 D8 D8 D8 0 M DA N/A N/A DA 0 1 DE N/A N/A DE M 0 C2 N/A N/A N/A M M C4 N/A N/A N/A M 1 C6 N/A N/A N/A 1 0 CA N/A N/A N/A 1 M CC N/A N/A N/A 1 1 CE N/A N/A N/A Note: 9ZXL08x1 and 9ZXL06x1 do not have SMBus address select pins. Their address is D8. Table 24. Byte 0: PLL Mode, and Frequency Select Register Byte 0 Bit7 Bit6 Bit5 Bit4 Bit3 Control PLL Operating PLL Operating Function Mode Readback 1 Mode Readback 0 Type R R 0 00 = Low BW ZDB Mode 01 = Bypass (Fanout Buffer) 1 10 = Reserved Name Default Bit2 Enable software PLL Operating control of PLL BW Mode 1 Bit1 Bit0 PLL Operating Mode 0 Frequency Select Readback RW RW RW R HW Latch 00 = Low BW ZDB Mode 01 = Bypass (Fanout Buffer) 133MHz 11 = High BW ZDB Mode SMBus Control 10 = Reserved 11 = High BW ZDB Mode 100MHz PLL Rdbk[1] PLL Rdbk[0] PLL_SW_EN PLL Mode[1] PLL Mode[0] 100M_133M# Latch Latch 0 1 1 Latch Reserved Reserved 0 0 Note: Setting bit 3 to '1' allows the user to override the latch value from pin 5 via use of bits 2 and 1. A warm system reset is required if the user changes these bits. Bit 0 defaults to 1 on the 9ZXL0451 and 9ZXL06x1 devices. ©2020 Renesas Electronics Corporation 23 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 25. Byte 1: Output Control Register 1 Byte 1 Bit7 Bit6 Bit5 Bit4 Bit3 Control Function Output Enable Type RW 0 Low/Low 1 OE# Pin Control Bit2 Bit1 Bit0 9ZXL12x1 Name DIF7_en DIF6_en DIF5_en DIF4_en DIF3_en DIF2_en DIF1_en DIF0_en 9ZXL12x1 Default 1 1 1 1 1 1 1 1 9ZXL08x1 Name DIF5_en DIF4_en DIF3_en DIF2_en Reserved DIF1_en DIF0_en Reserved 9ZXL08x1 Default 1 1 1 1 0 1 1 0 9ZXL06x1 Name Reserved DIF3_en DIF2_en Reserved Reserved DIF1_en DIF0_en Reserved 9ZXL06x1 Default 0 1 1 0 0 1 1 0 9ZXL0451 Name Reserved DIF2_en DIF1_en Reserved Reserved DIF0_en Reserved Reserved 9ZXL0451 Default 0 1 1 0 0 1 0 0 Bit4 Bit3 Bit2 Bit1 Bit0 Table 26. Byte 2: Output Control Register 2 Byte 2 Bit7 Bit6 Bit5 Control Function Output _enable Type RW 0 Low/Low 1 OE# Pin Control 9ZXL12x1 Name Reserved Reserved Reserved Reserved DIF11_en DIF10_en DIF9_en DIF8_en 9ZXL12x1 Default 0 0 0 0 1 1 1 1 9ZXL08x1 Name Reserved Reserved Reserved Reserved Reserved DIF7_en Reserved DIF6_en 9ZXL08x1 Default 0 0 0 0 0 1 0 1 9ZXL06x1 Name Reserved Reserved Reserved Reserved Reserved DIF5_en DIF4_en Reserved ©2020 Renesas Electronics Corporation 24 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 26. Byte 2: Output Control Register 2 (Cont.) Byte 2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 9ZXL06x1 Default 0 0 0 0 0 1 1 0 9ZXL0451 Name Reserved Reserved Reserved Reserved Reserved Reserved DIF3_en Reserved 9ZXL0451 Default 0 0 0 0 0 0 1 0 Bit4 Bit3 Bit2 Bit1 Bit0 R R Bytes 3 and 4 are Reserved Table 27. Byte 5: Revision and Vendor ID Register Byte 5 Bit7 Bit6 Control Function Type Bit5 Revision ID R Vendor ID R 0 R R R E rev = 0010 1 R 0001 = IDT/Renesas Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Default 0 1 0 0 0 0 0 1 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R R R R DevID 3 DevID 2 DevID 1 DevID 0 Table 28. Byte 6: Device ID Register Byte 6 Bit7 Bit6 Control Function Type N/A R R R R 0 Device ID 1 Name DevID 7 DevID 6 DevID 5 DevID 4 9ZXL1231E 0hE7 9ZXL1251E 0hF7 9ZXL0831E 0hE5 9ZXL0851E 0hF5 9ZXL0631E 0hE3 9ZXL0651E 0hF3 9ZXL0451E 0hF3 ©2020 Renesas Electronics Corporation 25 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 29. Byte 7: Byte Count Register Byte 7 Bit7 Bit6 Bit5 Control Function Type 0 Bit4 Bit3 Bit2 Bit1 Bit0 Writing to this register configures how many bytes will be read back on a block read. Reserved Reserved Reserved RW RW RW RW Default value is 8. 1 Name Default RW 0 0 0 BC4 BC3 BC2 BC1 BC0 0 1 0 0 0 Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. 9ZXL04x1: www.idt.com/document/psc/32-vfqfpn-package-outline-drawing-50-x-50-x-090-mm-body-epad-315-x-315-mm-nlg32p1 9ZXL06x1: www.idt.com/document/psc/ndndg40-package-outline-50-x-50-mm-bodyepad-350mm-sq-040-mm-pitch-qfn 9ZXL08x1: www.idt.com/document/psc/48-vfqfpn-package-outline-drawing-60-x-60-x-090-mm-body-epad-42-x-42-mm-040mm-pitch-ndg48p2 9ZXL12x1: www.idt.com/document/psc/64-vfqfpn-package-outline-drawing-90-x-90-x-09-mm-body-05mm-pitch-epad-615-x-615-mm-nlg64p2 Marking Diagrams 9ZXL04x1 ▪ Lines 1 and 2: truncated part number. ▪ Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. ▪ Line 4: “COO” denotes country of origin. ▪ Line 5: “LOT” denotes the lot number. ©2020 Renesas Electronics Corporation 26 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet 9ZXL06x1 ▪ Lines 1 and 2: truncated part number ▪ Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. ▪ Line 4: “COO” denotes country of origin. ▪ Line 5: “LOT” denotes the lot number. 9ZXL08x1 (industrial temperature range) ▪ Lines 1 and 2: truncated part number ▪ Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. ▪ Line 4: “COO” denotes country of origin. ▪ Line 5: “LOT” denotes the lot number. ©2020 Renesas Electronics Corporation 27 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet 9ZXL08x1 (extended temperature range) ▪ Lines 1 and 2: truncated part number (“K” denotes -40°C to +105°C) ▪ Line 3: “YYWW” is the last two digits of the year and the work week the part was assembled. ▪ Line 4: “COO” denotes country of origin. ▪ Line 5: “LOT” denotes the lot number. 9ZXL12x1 ▪ Lines 1 and 2: truncated part number ▪ Line 3: “LOT” denotes the lot number. ▪ Line 4: “COO” denotes country of origin; “YYWW” is the last two digits of the year and the work week the part was assembled. ©2020 Renesas Electronics Corporation 28 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Ordering Information Table 30. Ordering Information Number of Output Orderable Part Number Clock Outputs Impedance 4 85Ω 33Ω 6 85Ω 9ZXL0451EKILF 9ZXL0451EKILFT 9ZXL0631EKILFT 9ZXL0651EKILF 9ZXL0831EKILFT 9ZXL0831EKKLF 9ZXL0851EKILF 85Ω -40° to +85°C 5 × 5 mm 32-VFQFPN -40° to +85°C 5 × 5 mm 40-VFQFPN Part Number Suffix and Shipping Method 9ZXL0651EKILFT 9ZXL0831EKKLFT 8 Package 9ZXL0631EKILF 9ZXL0831EKILF 33Ω Temperature 9ZXL0851EKILFT 9ZXL0851EKKLF 9ZXL0851EKKLFT None = Trays -40° to +85°C -40° to +105°C -40° to +85°C “T” = Tape and Reel, Pin 1 Orientation: EIA-481C (see Table 31 for more details) 6 × 6 mm 48-VFQFPN “/W” = Tape and Reel, Pin 1 Orientation: EIA-481D (see Table 31 for more details) “-1K/W” = 1K Tape and Reel Quantity, Pin 1 Orientation: EIA-481D -40° to +105°C 9ZXL1231EKILF 33Ω 12 9ZXL1231EKILF/W 9ZXL1231EKILF-1K/W 9ZXL1231EKILFT 85Ω -40° to +85°C 9 × 9 mm 64-VFQFPN 9ZXL1251EKILF 9ZXL1251EKILFT “E” is the device revision designator (will not correlate with the datasheet revision). “LF” denotes Pb-free configuration, RoHS compliant; “T” or “/W” is the orderable suffix for Tape and Reel packaging. ©2020 Renesas Electronics Corporation 29 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Table 31. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION T CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED Correct Pin 1 ORIENTATION /W CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 2 (EIA-481-D) USER DIRECTION OF FEED ©2020 Renesas Electronics Corporation 30 August 25, 2020 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet Revision History Revision Date Description of Change August 25, 2020 Updated PCIe Gen5 CC, DB2000Q, and QPI/UPI specifications in Key Specifications section on front page. February 13, 2020 Updated Byte 1, bit7 and bit5 for 9ZXL0451 default. January 31, 2020 Typo correction - swapped VMIN and VMAX symbol designators in LP-HCSL Outputs table. October 22, 2019 Combined 9ZXL04x1E, 9ZXL06x1E, 9ZXL08x1E, and 9ZXL12x1E datasheets into a single document. April 4, 2019 Last revision date of the 9ZXL0451E datasheet. November 30, 2018 Last revision date of the 9ZXL0631E_0651E datasheet. November 30, 2018 Last revision date of the 9ZXL0831E_0851E datasheet. November 30, 2018 Last revision date of the 9ZXL1231E_1251E datasheet. ©2020 Renesas Electronics Corporation 31 August 25, 2020 32-VFQFPN, Package Outline Drawing 5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm. NLG32P1, PSC-4171-01, Rev 02, Page 1 32-VFQFPN, Package Outline Drawing 5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm. NLG32P1, PSC-4171-01, Rev 02, Page 2 Package Revision History Description Date Created Rev No. April 12, 2018 Rev 02 New Format Feb 8, 2016 Rev 01 Added "k: Value 48-VFQFPN Package Outline Drawing 6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch NDG48P2, PSC-4212-02, Rev 03, Page 1 © Renesas Electronics Corporation 48-VFQFPN Package Outline Drawing 6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch NDG48P2, PSC-4212-02, Rev 03, Page 2 Package Revision History © Renesas Electronics Corporation Description Date Created Rev No. July 24, 2018 Rev 02 New Format Change QFN to VFQFPN, Recalculate Land Pattern Feb 25, 2020 Rev 03 Tolerance Format Change 64-VFQFPN, Package Outline Drawing 9.0 x 9.0 x 0.9 mm Body, 0.5mm Pitch, Epad 6.15 x 6.15 mm NLG64P2, PSC-4147-02, Rev 01, Page 1 64-VFQFPN, Package Outline Drawing 9.0 x 9.0 x 0.9 mm Body, 0.5mm Pitch, Epad 6.15 x 6.15 mm NLG64P2, PSC-4147-02, Rev 01, Page 2 Package Revision History Description Date Created Rev No. Feb 21, 2018 Rev 01 New Format, Change QFN to VFQFPN, Added P2 Nov 3, 2015 Rev 00 Initial Release IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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