ADC1005S060TS/C1,1

ADC1005S060 Single 10 bits ADC, up to 60 MHz Rev. 03 — 2 July 2012 Product data sheet 1. General description The ADC1005S060 is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 60 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device requires an external source to drive its reference ladder. 2. Features               10-bit resolution (binary or gray code) Sampling rate up to 60 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 5 MHz full-scale input at fclk = 60 MHz) No missing codes guaranteed In-Range (IR) CMOS output TTL and CMOS levels compatible digital inputs 2.7 V to 3.6 V CMOS digital outputs Low-level AC clock input signal allowed External reference voltage regulator Power dissipation only 312 mW (typical) Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required 3. Applications        Video data digitizing Radar Barcode scanners Digital instrumentation Transient signal analysis  modulators Medical imaging ® ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 4. Quick reference data Table 1. Quick reference data VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at VCCA = VCCD = 5 V; VCCO = 3.3 V; VRB = 1.3 V; VRT = 3.7 V; CL = 10 pF and Tamb = 25 C unless otherwise specified. Symbol Parameter VCCA Conditions Min Typ Max Unit analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 2.7 3.3 3.6 V ICCA analog supply current - 29 37 mA ICCD digital supply current - 33 40 mA ICCO output supply current - 0.5 2.0 mA INL integral non-linearity - 0.8 2.0 LSB DNL differential non-linearity - 0.35 0.9 LSB fclk(max) maximum clock frequency 60 - - MHz Ptot total power dissipation - 312 411 mW fclk = 60 MHz; ramp input fclk =60 MHz; ramp input 5. Ordering information Table 2. Ordering information Type number ADC1005S060TS Package Name Description Version SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 2 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 6. Block diagram VCCA CLK VCCD OE GRAY 3 1 11 10 15 2 CLOCK DRIVER RT 9 25 24 23 22 analog voltage input VI 8 CMOS OUTPUTS LATCHES ANALOG - TO - DIGITAL CONVERTER 21 20 19 RM 7 18 Rlad 17 16 RB TC 13 6 D9 MSB D8 D7 D6 D5 data outputs D4 D3 D2 D1 D0 LSB VCCO ADC1005S060 IN-RANGE LATCH CMOS OUTPUT 26 IR output 5, 27, 28 4 12 AGND DGND 14 n.c. OGND 014aaa519 Fig 1. Block diagram ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 3 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 7. Pinning information 7.1 Pinning CLK 1 28 n.c. TC 2 27 n.c. VCCA 3 26 IR AGND 4 25 D9 n.c. 5 24 D8 RB 6 23 D7 RM 7 VI 8 RT 9 20 D4 OE 10 19 D3 VCCD 11 18 D2 DGND 12 17 D1 VCCO 13 16 D0 ADC1005S 060TS OGND 14 22 D6 21 D5 15 GRAY 014aaa520 Fig 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description CLK 1 clock input TC 2 twos complement input (active LOW) VCCA 3 analog supply voltage (5 V) AGND 4 analog ground n.c. 5 not connected RB 6 reference voltage BOTTOM input RM 7 reference voltage MIDDLE input VI 8 analog voltage input RT 9 reference voltage TOP input OE 10 output enable input (active LOW) VCCD 11 digital supply voltage (2.7 V to 3.6 V) DGND 12 digital ground VCCO 13 supply voltage for output stages (2.7 V to 3.6 V) OGND 14 output ground GRAY 15 gray code input (active HIGH) D0 16 data output; bit 0 (Least Significant Bit (LSB)) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 4 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz Table 3. Pin description …continued Symbol Pin Description D4 20 data output; bit 4 D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (Most Significant Bit (MSB)) IR 26 in-range data output n.c. 27 not connected n.c. 28 not connected 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VCCA analog supply voltage Conditions [1] 0.3 +7.0 V VCCD digital supply voltage [1] 0.3 +7.0 V VCCO output supply voltage [1] 0.3 +7.0 V VCC supply voltage difference VCCA  VCCD 0.1 +1.0 V VCCD  VCCO; VCCA  VCCO 0.1 +4.0 V referenced to AGND 0.3 +7.0 V VI input voltage Vi(clk)(p-p) peak-to-peak clock input voltage for switching; referenced to DGND - VCCD V IO output current - 10 mA Tstg storage temperature 55 +150 C Tamb ambient temperature 40 +85 C Tj junction temperature - 150 C [1] The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that the supply voltage differences VCC are respected. 9. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Condition Value Unit Rth(j-a) thermal resistance from junction to ambient in free air 110 K/W ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 5 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 10. Characteristics Table 6. Characteristics VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at VCCA = VCCD = 5 V; VCCO = 3.3 V; VRB = 1.3 V; VRT = 3.7 V; CL = 10 pF and Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 2.7 3.3 3.6 V VCC supply voltage difference VCCA  VCCD 0.2 - +0.2 V VCCA  VCCO; VCCD  VCCO 0.2 +2.55 V ICCA analog supply current - 29 37 mA ICCD digital supply current - 33 40 mA ICCO output supply current fclk = 60 MHz; ramp input - 0.5 2.0 mA Ptot total power dissipation fclk = 60 MHz; ramp input - 312 411 mW Inputs Clock input CLK (Referenced to DGND)[1] VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - VCCD V IIL LOW-level input current Vclk = 0.8 V 1 0 +1 A IIH HIGH-level input current Vclk = 2 V - 2 10 A Ci input capacitance - 2 - pF Inputs OE TC and GRAY (Referenced to DGND); see Table 3 and 4 VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - VCCD V IIL LOW-level input current VIL = 0.8 V 1 - - A IIH HIGH-level input current VIH = 2.0 V - - 1 A - 0 - A Analog input VI (Referenced to AGND) IIL LOW-level input current VI = VRB = 1.3 V ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 6 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz Table 6. Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at VCCA = VCCD = 5 V; VCCO = 3.3 V; VRB = 1.3 V; VRT = 3.7 V; CL = 10 pF and Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IIH HIGH-level input current VI = VRT = 3.7 V - 55 - A Yi input admittance fi = 5 MHz Ri, input resistance - 45 - k Ci, input capacitance 3 5 7 pF 1.2 1.3 2.2 V [2] Reference voltages for the resistor ladder; see Table 7 VRB voltage on pin RB VRT voltage on pin RT 3.4 3.7 VCCA  0.8 V Vref(dif) differential reference voltage VRT  VRB 2.2 2.4 3.2 V Iref reference current Vref(dif) = 2.4 V - 17.6 - mA Rlad ladder resistance - 136 -  TCRlad ladder resistor temperature coefficient - 253 - m/K Voffset offset voltage Vi(a)(p-p) peak-to-peak analog input voltage Vref(dif) = 2.4 V BOTTOM [3] - 200 - mV TOP [3] - 190 - mV Vref(dif) = 2.4 V [4] 1.95 2.01 2.10 V Outputs Digital outputs D9 to D0 and IR (Referenced to OGND) VOL LOW-level output voltage IO = 1 mA 0 - 0.5 V VOH HIGH-level output voltage IO = 1 mA VCCO  0.5 - VCCO V IOZ OFF-state output current 0.5 V < VO < VCCO 20 - +20 A 60 - - MHz Switching characteristics; Clock input CLK; see Figure 4[1] fclk(max) maximum clock frequency tw(clk)H HIGH clock pulse width Tamb = 25 C 7.0 - - ns tw(clk)L LOW clock pulse width Tamb = 25 C 3.5 - - ns Analog signal processing; fclk = 60 MHz Linearity INL integral non-linearity ramp input - 0.8 2.0 LSB DNL differential non-linearity ramp input - 0.35 0.9 LSB ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 7 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz Table 6. Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at VCCA = VCCD = 5 V; VCCO = 3.3 V; VRB = 1.3 V; VRT = 3.7 V; CL = 10 pF and Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Eoffset offset error middle code - 1 - LSB EG gain error from device to device [5] - 0.5 - % bandwidth full-scale sine wave [6] Bandwidth B - 30 - MHz 75 % full-scale sine wave - 45 - MHz small signal at mid-scale; VI = 10 LSB at code 512 - 700 - MHz ts(LH) LOW to HIGH settling time full-scale square wave; see Figure 6 [7] - 5 - ns ts(HL) HIGH to LOW settling time full-scale square wave; see Figure 6 [7] - 5 - ns 2H second harmonic level fi = 5 MHz - 68 - dB 3H third harmonic level fi = 5 MHz - 67 - dB THD total harmonic distortion fi = 5 MHz - 64 - dB fi = 15 MHz - 57 - dB spurious free dynamic range fi = 5 MHz - 72 without harmonics; fi = 5 MHz - 58 - dB without harmonics; fi = 15 MHz 53 57 - dB fi = 5 MHz - 9.3 - bits fi = 10 MHz - 8.9 - bits fi = 15 MHz - 8.8 - bits fi = 20 MHz - 8.6 - bits intermodulation suppression fclk = 60 MHz - 67 - dB bit error rate fi = 5 MHz; VI = 16 LSB at code 512 - 1013 - times/samples - 0.7 2 ns Harmonics SFDR dB Signal-to-Noise ratio[8] S/N signal-to-noise ratio Effective bits[8] ENOB Two-tone effective number of bits intermodulation[9] IM Bit error rate BER Timing (fclk = 60 MHz; CL = 10 pF); see Figure 4[10] td(s) sampling delay time th(o) output hold time td(o) output delay time 4 - - ns VCCO = 2.7 V - 10 14 ns VCCO = 3.3 V - 9 13 ns ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 8 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz Table 6. Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at VCCA = VCCD = 5 V; VCCO = 3.3 V; VRB = 1.3 V; VRT = 3.7 V; CL = 10 pF and Tamb = 25 C unless otherwise specified. Symbol Parameter CL load capacitance Conditions SR slew rate VCCO = 2.7 V Min Typ Max Unit - - 10 pF 0.2 0.3 - V/ns 3-state output delay times (fclk = 60 MHz; VCCO = 3.3 V); see Figure 5 tdZH float to active HIGH delay time - 16 20 ns tdZL float to active LOW delay time - 30 34 ns tdHZ active HIGH to float delay time - 25 30 ns tdLZ active LOW to float delay time - 23 27 ns [1] The rise and fall times of the clock signal must not be less than 0.5 ns. [2] The input admittance is Y i + ----- + jC i R [3] Analog input voltages producing code 0 up to and including code 1023: 1 i a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 C. b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 C. [4] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. V RT – V RB R OB + R L + R OT a) The current flowing into the resistor ladder is I = --------------------------------------- and the full-scale input range at the converter, to cover code 0 RL to 1023 is V I = R L  I L = ---------------------------------------   V RT + V RB  = 0.8375   V RT – V RB  R OB + R L + R OT RL R OB + R L + R OT b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio --------------------------------------will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends mainly on the difference VRT  VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [5]  V 1023 – V 0  – V i  p – p  E G = -------------------------------------------------------  100 Vi  p – p  [6] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. [7] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. [8] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to signal-to-noise ratio: S/N = ENOB  6.02 + 1.76 dB. [9] Intermodulation measured relative to either tone with analog input frequencies of 4.3 MHz and 4.5 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. [10] Output data acquisition: the output data is available after the maximum delay time of td(o). IDT recommends the lowest possible output load. These parameters are guaranteed by characterization and not by production test. ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 9 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 11. Additional information relating to Table 6 RT ROT code 1023 RL RL RM IL RL Rlad RL code 0 ROB RB 014aaa521 Fig 3. Converter reference resistor ladder Table 7. Code Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.7 V; binary/gray codes) Vi(a)(p-p) (V) IR Binary outputs D9 to D0 Underflow < 1.5 0 00 0000 0000 00 0000 0000 0 1.5 1 00 0000 0000 00 0000 0000 1 - 1 00 0000 0001 00 0000 0001  -    1022 - 1 11 1111 1110 10 0000 0001 1023 3.51 1 11 1111 1111 10 0000 0000 Overflow > 3.51 0 11 1111 1111 10 0000 0000 Table 8. Output coding and input voltage (typical values; referenced to AGND; binary/twos complement codes) Code Vi(a)(p-p) (V) IR Binary outputs D9 to D0 twos complement outputs D9 to D0 Underflow < 1.5 00 0000 0000 10 0000 0000 0 0 1.5 1 00 0000 0000 10 0000 0000 1 - 1 00 0000 0001 10 0000 0001  -    1022 - 1 11 1111 1110 01 1111 1110 1023 3.51 1 11 1111 1111 01 1111 1111 Overflow > 3.51 0 11 1111 1111 01 1111 1111 ADC1005S060_3 Product data sheet Gray outputs D9 to D0 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 10 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz Table 9. TC mode selection TC OE D9 to D0 IR X 1 high impedance high impedance 0 0 active; two’s complement active 1 0 active; binary active Table 10. Gray mode selection Gray OE D9 to D0 IR X 1 high impedance high impedance 0 0 active; binary active 1 0 active; gray active sample N sample N + 1 sample N + 2 tw(clk)L tw(clk)H VIH 50 % CLK VIL sample N sample N + 1 sample N + 2 VI td(s) th(o) HIGH DATA D0 to D9 DATA N−2 DATA N−1 DATA N DATA N+1 50 % LOW td(o) 014aaa522 Fig 4. Timing diagram ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 11 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz VCCD 50 % OE tdHZ tdZH HIGH 90 % output data LOW tdLZ 50 % tdZL LOW HIGH 50 % output LOW data HIGH 10 % VCCD 3.3 kΩ ADC1005S060 S1 10 pF OE TEST S1 tdLZ VCCD tdZL VCCD tdHZ DGND tdZH DGND 014aaa523 frequency on pin OE = 100 kHz. Fig 5. Timing diagram and test conditions of 3-state output delay time ts(LH) ts(HL) code 1023 VI 50 % 50 % code 0 2 ns CLK 2 ns 50 % 50 % 0.5 ns 0.5 ns 014aaa524 Fig 6. Analog input settling time diagram ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 12 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz VCCA VCCO D9 to D0 IR OGND VI AGND 014aaa525 Fig 7. D9 to D0 and IR outputs 014aaa526 Fig 8. VI analog input VCCA VCCO RT RL RL OE TC GRAY RM RL RL RB OGND AGND 014aaa528 014aaa527 Fig 9. OE GRAY and TC inputs Fig 10. RB, RM and RT inputs VCCD 1.5 V CLK DGND 014aaa529 Fig 11. CLK input ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 13 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 12. Application information 12.1 Application diagrams 33 Ω (3) CLK TC VCCA (2) 100 nF AGND n.c. RB RM 100 nF 100 nF AGND AGND VI RT OE 100 nF VCCD AGND (2) 100 nF DGND VCCO (2) 100 nF OGND 1 28 2 27 3 26 4 25 5 24 6 23 7 8 ADC1005S 060TS 22 21 9 20 10 19 11 18 12 17 13 16 14 15 n.c. n.c. IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAY 014aaa530 The analog and digital supplies should be separated and decoupled. A user manual is available that describes the demonstration board that uses the version ADC1004S030/040/050 family with an application environment. (1) RB, RM and RT are decoupled to AGND (2) Decoupling capacitor for supplies must be placed close to the device. (3) This resistor is mandatory (33  is its minimum value) and must be near the clock source. Fig 12. Application diagram 12.2 Alternative parts The following alternative parts are also available: Table 11. Alternative parts Type number Description Single 8 bits ADC 30 MHz Single 8 bits ADC [1] 40 MHz ADC0804S050 Single 8 bits ADC [1] 50 MHz ADC1003S030 Single 10 bits ADC, with internal reference regulator [1] 30 MHz ADC1003S040 Single 10 bits ADC, with internal reference regulator [1] 40 MHz ADC1003S050 Single 10 bits ADC, with internal reference regulator [1] 50 MHz ADC0804S030 ADC0804S040 ADC1005S060_3 Product data sheet Sampling frequency [1] © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 14 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz Table 11. Alternative parts Type number Description ADC1004S030 Single 10 bits ADC [1] 30 MHz Single 10 bits ADC [1] 40 MHz Single 10 bits ADC [1] 50 MHz ADC1004S040 ADC1004S050 [1] Pin to pin compatible ADC1005S060_3 Product data sheet Sampling frequency © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 15 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 13. Package outline SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 13. Package outline SOT341-1 (SSOP28) ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 16 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1005S060_3 20120702 Product data sheet - ADC1005S060_2 ADC1005S060_2 20080813 Product data sheet - ADC1005S060_1 Modifications: ADC1005S060_1 • • • • • • Corrections made to INL and DNL conditions in Table 1. Corrections made to several entries and notes in Table 6. Correction made to table description in Table 7. Correction made to column D9 to D0 in Table 10. Correction made to Figure 8. Correction made to Figure 10. 20080616 Product data sheet - - 15. Contact information For more information or sales office addresses, please visit: http://www.idt.com ADC1005S060_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 17 of 18 ADC1005S060 Integrated Device Technology Single 10 bits ADC, up to 60 MHz 16. Contents 1 2 3 4 5 6 7 7.1 7.2 8 General description . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick reference data . . . . . . . . . . . . . . . . . . . . . Ordering information . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Pinning information . . . . . . . . . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 2 2 3 4 4 4 5 9 10 11 12 12.1 12.2 13 14 15 16 ADC1005S060_3 Product data sheet Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . 10 Application information . . . . . . . . . . . . . . . . . 14 Application diagrams . . . . . . . . . . . . . . . . . . . 14 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 18 of 18