AT25SF128A-SHBHD-T

AT25SF128A 128 Mbit Serial NOR Flash Memory with Dual and Quad I/O Support PRELIMINARY DATASHEET Features Single voltage operation with range of 2.7V to 3.6V Serial Peripheral Interface (SPI) compatible support Supports SPI modes 0 and 3 Supports dual and quad output read 133 MHz maximum operating frequency Read Operations 70 MHz normal read 120 MHz fast read 133 MHz Quad Output fast read Dual I/O data transfer rate up to 240 Mbps Quad I/O data transfer rate up to 480 Mbps Quad Output data transfer rate up to 532 Mbps Continuous read with 8/16/32/64-byte wrap Flexible, optimized erase architecture for code and data storage applications Sector erase 4 KB Block erase 32 KB, and 64 KB Full chip erase Erase suspend and resume Flexible programming Byte/Page program (1 to 256 Bytes) Program suspend and resume Fast program and erase times 0.6 ms typical page (256 byte) program time 70 ms typical 4-Kbyte block erase time 150 ms typical 32-Kbyte block erase time 250 ms typical 64-Kbyte block erase time Full chip erase: 30s typical Hardware and software Write Protection Hardware-controlled locking of protected sector via WP pin Three 256-byte OTP-capable security registers Write protect all or part of memory via software with top/bottom block selection Serial Flash Discoverable Parameter (SFDP) register Low power dissipation 13 µA standby current 2 µA deep power down current Endurance 100K program/erase cycles Data Retention: 20 years Temperature Range: Industrial (-40 oC to 85 oC) Industry standard green (Pb/Halide-free/RoHS compliant) package options 8-lead 0.208” Wide SOIC (8S4) 8-pad (5 x 6 x 0.6 mm) UDFN (8MA1) 24-ball (5 x 5 array) TFBGA (24CC) DS-AT25SF128A–-168D–-03/2019 Table of Contents 1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Package Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Chip Select (CS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.3 Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.4 Serial Input (Sl or I/O0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.5 Serial Data Output (SO or I/O1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.6 Write Protect (WP or I/O2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.7 Hold (HOLD or I/O3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.8 VCC Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.9 GND Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Block/Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5. SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5.1 Standard SPI Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2 Dual SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.3 Quad SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6. Operating Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 6.1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.1 Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 6.1.2 Power-up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 6.1.3 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 6.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 6.2 Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4.1 Status Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 6.4.2 Status and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 6.4.3 Status Register Protect Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 6.4.4 Write Protect Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6.4.5 Status Register Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 7. Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 8. Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 8.1 Configuration and Status Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.1 Write Enable (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8.1.2 Write Disable (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8.1.3 Read Status Register (05h or 35h or 15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8.1.4 Write Status Register (01h or 31h or 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 8.1.5 Write Enable for Volatile Status Register (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.2 Read Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2.1 Read Data (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.2.2 Fast Read (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 8.2.3 Dual Output Fast Read (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 AT25SF128A DS-AT25SF128A–-168D–-03/2019 1 Table of Contents 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 Quad Output Fast Read (6Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Dual I/O Fast Read (BBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Quad I/O Fast Read (EBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Quad I/O Word Fast Read (E7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Set Burst with Wrap (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 8.3 ID and Security Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3.1 Read Manufacture ID/ Device ID (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8.3.2 Dual I/O Read Manufacture ID/ Device ID (92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8.3.3 Quad I/O Read Manufacture ID/ Device ID (94h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 8.3.4 Read JEDEC ID (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8.3.5 Read Unique ID Number (4Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 8.3.6 Deep Power-Down (B9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 8.3.7 Release from Deep Power-Down/Read Device ID (ABh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 8.3.8 Read Security Registers (48h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 8.3.9 Erase Security Registers (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.3.10 Program Security Registers (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 8.3.11 Enable Reset (66h) and Reset Device (99h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8.4 Program and Erase Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4.1 Page Program (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8.4.2 Quad Page Program (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 8.4.3 Fast Page Program (F2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 8.4.4 Sector Erase (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 8.4.5 32KB Block Erase (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 8.4.6 64KB Block Erase (D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 8.4.7 Chip Erase (60/C7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.4.8 Erase / Program Suspend (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.4.9 Erase / Program Resume (7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 8.4.10 Read Serial Flash Discoverable Parameter (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 9. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 9.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3 Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.4 Latch Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5 Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.7 AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.8 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 11. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 11.1 8S4 — 8-Pin SOP 208-mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2 8MA1 — 8-Pad UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 24CC — 24-Ball TFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 AT25SF128A DS-AT25SF128A–-168D–-03/2019 2 1. Product Overview The Adesto® AT25SF128A is a 128 Mb Serial Peripheral Interface (SPI) Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25SF128A is ideal for data storage as well, eliminating the need for additional data storage devices. The SPI clock frequencies support up to 133 MHz enabling data transfers up to 532 Mbits/s for Quad Output operations. The AT25SF128A array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instructions. Pages can be erased in 4 KB, 32 KB, or 64 KB blocks, or the entire chip. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 2 µA for Deep Power Down. All devices offered in space-saving packages. The device supports JEDEC standard manufacturer and device identification with three 256-byte secure OTP registers. 2. Package Pinouts Figure 2-1 show the package pinouts for the following devices. CS 1 8 VCC SO (I/O1) 2 7 HOLD (I/O3) WP (I/O2) 3 6 SCK GND 4 5 SI (I/O0) CS 1 8 VCC SO (I/O1) 2 7 HOLD (I/O3) WP (I/O2) 3 6 SCK GND 4 5 SI (I/O0) 8-lead 8S1 SOIC Package (208-mil) 8-pad UDFN Package Top View, Balls Facing Down A2 A3 A4 A5 NC NC NC NC B1 B2 B3 B4 B5 NC SCK GND VCC NC C1 C2 C3 C4 C5 NC CS NC WP (IO2) NC D1 D2 D3 D4 D5 NC SO (IO1) SI (IO0) HOLD (IO3) NC C1 C2 C3 C4 C5 NC NC NC NC NC 24-ball TFBGA Package Figure 2-1. Adesto AT25SF128A Flash Memory Package Types AT25SF128A DS-AT25SF128A–-168D–-03/2019 3 3. Pin Descriptions During all operations, VCC must be held stable and within the specified valid range: VCC (min) to VCC (max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, see Section 9.6, DC Electrical Characteristics). These pins are described below. 3.1 Pin Summary Table 3-1. AT25SF128A Pin Names Pin Name I/O CS I SO (IO1) I/O Serial Output for single bit data Instructions. IO1 for dual or quad Instructions. WP (IO2) I/O Write Protect in single bit or dual data Instructions. IO2 in quad mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad Instructions. GND Chip select. Ground. SI (IO0) I/O SCLK I HOLD (IO3) I/O VCC 3.2 Description Serial input for single bit data Instructions. IO0 for dual or quad Instructions. Serial clock. Hold (pause) serial transfer in single bit or dual data Instructions. IO3 in Quad-I/O mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad Instructions. Core and I/O power supply. Chip Select (CS) The chip select signal indicates when a instruction for the device is in process and the other signals are relevant for the memory device. When the CS signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Status Registers embedded operation is in progress, the device remains in the Standby Power mode. Driving the CS input to logic low state enables the device, placing it in the Active Power mode. After Power Up, a falling edge on CS is required prior to the start of any instruction. 3.3 Serial Clock (SCLK) This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of SCLK. 3.4 Serial Input (Sl or I/O0) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI becomes I/O0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). AT25SF128A DS-AT25SF128A–-168D–-03/2019 4 3.5 Serial Data Output (SO or I/O1) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock signal. The SO pin becomes an I/O pin (I/O1) during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). 3.6 Write Protect (WP or I/O2) When WP is driven low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers, are also hardware protected against data modification while WP remains low. The WP function is not available when the Quad mode is enabled (QE bit in Status Register 2 = 1). The WP function is replaced by I/O2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK). WP has an internal pull-up resistance; when unconnected; WP is at VIH and may be left unconnected in the host system if not used for Quad mode. 3.7 Hold (HOLD or I/O3) The HOLD function is only available when QE = O. If QE = 1, The HOLD function is disabled and the pin acts as dedicated data I/O pin. The HOLD signal goes low to stop any serial communications with the device, but doesn't stop the operation of write status register, programming, or erasing in progress. The Hold condition starts on the falling edge of the HOLD signal, provided that it coincides with SCK being in the logic low state. If the falling edge does not coincide with the SCK signal being at the logic low state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the HOLD signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in progress. Figure 3-1. HOLD Pin Function 3.8 VCC Power Supply VCC is the supply voltage. It is the single voltage used for all device functions including read, program, and erase. 3.9 GND Ground GND is the ground reference for the VCC supply voltage. AT25SF128A DS-AT25SF128A–-168D–-03/2019 5 4. Block/Sector Addresses Table 4-1. Block/Sector Addresses of AT25SF128A Memory Density Block (64k byte) Block (32k byte) Half block 0 Sector No. Sector Size (KB) Address Range Sector 0 4 000000h - 000FFFh : : : Sector 7 4 007000h - 007FFFh Sector 8 4 008000h - 008FFFh Block 0 Half block 1 Half block 2 : : Sector 15 4 00F000h - 00FFFFh Sector 16 4 010000h - 010FFFh : : : Sector 23 4 017000h - 017FFFh Sector 24 4 018000h - 018FFFh : : : Sector 31 4 01F000h - 01FFFFh : : : Sector 4064 4 FE0000h - FE0FFFh : : : Sector 4071 4 FE7000h - FE7FFFh Sector 4072 4 FE8000h - FE8FFFh : : : Sector 4079 4 FEF000h - FEFFFFh Sector 4080 4 FF0000h - FF0FFFh : : : Sector 4087 4 FF7000h - FF7FFFh Sector 4088 4 FF8000h - FF8FFFh : : : Sector 4095 4 FFF000h - FFFFFFh Block 1 Half block 3 128Mbit : : Half block 508 Block 254 Half block 509 Half block 510 Block 255 Half block 511 Notes: 1. Block = Uniform Block, and the size is 64K bytes. 2. Half block = Half Uniform Block, and the size is 32k bytes. 3. Sector = Uniform Sector, and the size is 4K bytes. AT25SF128A DS-AT25SF128A–-168D–-03/2019 6 5. SPI Operation 5.1 Standard SPI Instructions The AT25SF128A features a 4-pin serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS), Serial Data Input (SI) and Serial Data Output (SO). SPI bus modes 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. 5.2 Dual SPI Instructions The AT25SF128A supports Dual SPI operation when using the Dual Output Fast Read (3BH), Dual I/O Fast Read (BBH) and Read Manufacture ID/Device ID Dual I/O (92H) instructions. These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: I/O0 and I/O1 respectively. 5.3 Quad SPI Instructions The AT25SF128A supports Quad SPI operation when using the Quad Output Fast Read (6BH), Quad I/O Fast Read (EBH), Quad I/O Word Fast Read (E7h), Read Manufacture ID/Device ID Quad I/O (94H) and Quad Page Program (32H) instructions. These instructions allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional I/O pins: I/O0 and I/O1, and /WP and HOLD pins become I/O2 and I/O3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register to be set. 6. Operating Features 6.1 Supply Voltage 6.1.1 Operating Supply Voltage Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified VCC (min) / VCC (max) range must be applied. In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with capacitors (usually 10 nF to 100 nF in parallel) placed close to the VCC/GND package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 6.1.2 Power-up Conditions When the power supply is turned on, VCC rises continuously from GND to VCC. During this time, the Chip Select (CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the CS line to VCC via a pull-up resistor. In addition, the CS input is both edge sensitive and level sensitive. After power-up, the device does not become selected until a falling edge is first detected on CS. This ensures that CS must have been High, prior to going Low to start the first operation. 6.1.3 Device Reset In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined by the DC operating ranges). When VCC has passed the POR threshold, the device is reset. AT25SF128A DS-AT25SF128A–-168D–-03/2019 7 6.1.4 Power-down At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (CS) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress). 6.2 Active Power and Standby Power Modes When Chip Select (CS) is low, the device is selected and in the Active Power mode and consuming current (ICC). When Chip Select (CS) is high, the device is deselected. If a Write cycle is not currently in progress, the device enters the Standby Power mode, and the current consumption drops to ICC1. 6.3 Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCLK) are don't care. To enter the Hold condition, the device must be selected, with Chip Select (CS) low. Normally, the device remains selected for the duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (SCLK) already being Low (as shown in Figure 6-1). The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 6-1 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (SCLK) being Low. Figure 6-1. Hold Condition Activation AT25SF128A DS-AT25SF128A–-168D–-03/2019 8 6.4 Status Register 6.4.1 Status Register Table The following diagram shows the layout of the Status Register bits. S23 S22 S21 S20 S19 S18 S17 S16 Reserved DRV1 DRV0 Reserved Reserved Reserved Reserved Reserved S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP Figure 6-2. Status Register Bit Layout 6.4.2 Status and Control Bits 6.4.2.1 WIP bit The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. 6.4.2.2 WEL bit The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 6.4.2.3 BP4, BP3, BP2, BP1, BP0 bits The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register instruction. • When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory becomes protected against Page Program, Sector Erase and Block Erase instructions. • The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. • The Chip Erase (CE) instruction is executed if the Block Protect (BP2, BP1, BP0) bits are 0 and CMP = 0 or the Block Protect (BP2, BP1, BP0) bits are 1 and CMP = 1. 6.4.2.4 SRP1, SRP0 bits The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. AT25SF128A DS-AT25SF128A–-168D–-03/2019 9 6.4.2.5 QE bit The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP pin and HOLD pin are enable. When the QE pin is set to 1, the Quad I/O2 and I/O3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP or HOLD pins directly to the power supply or ground). 6.4.2.6 LB3/LB2/LB1 bit The LB bits are non-volatile One Time Program (OTP) bits in Status Register (S13 - S11) that provide the write protect control and status to the Security Registers. The default state of LBx is 0, the security registers are unlocked. The LBx bits can be set to 1 individually using the Write Register instruction. The LBx bits are One Time Programmable. Once they are set to 1, the Security Registers become read-only permanently. 6.4.2.7 CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the SEC and BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP = 0. 6.4.2.8 SUS1/SUS2 bit The SUS1 and SUS2 bits are read only bits in the status register2 (S15 and S10) that are set to 1 after executing an Erase/Program Suspend (75h) instruction (The Erase Suspend sets SUS1 to 1, and the Program Suspend sets SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. 6.4.2.9 DRV1/DRV0 The DRV1 and DRV0 bits are used to determine the output driver strength for the Read instruction. Table 6-1. DRV1 / DRV0 Bit Encoding DRV1, DRV0 6.4.3 Driver Strength 00 100%(default) 01 75% 10 50% 11 25% Status Register Protect Table The Status Register Protect (SRP1 and SRP0) bit are non-volatile Read/Write bits in the Status Register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. Table 6-2. Status Register protect table SRP1 SRP0 WP Status Register Description 0 0 X Software Protected The Status Register can be written to after a Write Enable instruction, WEL = 1 (Factory Default). 0 1 0 Hardware Protected WP = 0, the Status Register locked and cannot be written. AT25SF128A DS-AT25SF128A–-168D–-03/2019 10 Table 6-2. Status Register protect table SRP1 SRP0 WP Status Register Description 0 1 1 Hardware Unprotected WP = 1, the Status Register is unlocked and can be written to after a Write Enable instruction, WEL = 1. 1 0 X Power Supply Lock-Down(1) Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. 1 1 X One Time Program(2) Status Register is permanently protected and cannot be written to. Notes: 6.4.4 1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. The One time Program feature is available upon special order. Please contact Adesto for details. Write Protect Features 1. Software Protection: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory array that can be read but not change. 2. Hardware Protection: WP going low to protected the writable bits of Status Register. 3. Deep Power-Down: In Deep Power-Down mode, all instructions are ignored except the Release from Deep Power-Down Mode instruction. 4. Write Enable: The Write Enable instruction is set the Write Enable Latch (WEL) bit. The WEL bit is reset under any of the following conditions: • Power -up • Write Disable • Write Status Register • Page Program • Sector Erase/Block Erase/Chip Erase • Software Reset AT25SF128A DS-AT25SF128A–-168D–-03/2019 11 6.4.5 Status Register Memory Protection 6.4.5.1 Protect Table Table 6-3. AT25SF128A Status Register Memory Protection (CMP = 0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 252 to 255 FC0000h - FFFFFFh 256 kB Upper 1/64 0 0 0 1 0 248 to 255 F80000h - FFFFFFh 512 kB Upper 1/32 0 0 0 1 1 240 to 255 F00000h - FFFFFFh 1 MB Upper 1/16 0 0 1 0 0 224 to 255 E00000h - FFFFFFh 2 MB Upper 1/8 0 0 1 0 1 192 to 255 C00000h - FFFFFFh 4 MB Upper 1/4 0 0 1 1 0 128 to 255 800000h - FFFFFFh 8 MB Upper 1/2 0 1 0 0 1 0 to 3 000000h - 03FFFFh 256 kB Upper 1/64 0 1 0 1 0 0 to 7 000000h - 07FFFFh 512 kB Upper 1/32 0 1 0 1 1 0 to 15 000000h - 0FFFFFh 1 MB Upper 1/16 0 1 1 0 0 0 to 31 000000h - 1FFFFFh 2 MB Upper 1/8 0 1 1 0 1 0 to 63 000000h - 3FFFFFh 4 MB Upper 1/4 0 1 1 1 0 0 to 127 000000h - 7FFFFFh 8 MB Upper 1/2 X X 1 1 1 0 to 255 000000h - FFFFFFh 16 MB ALL 1 0 0 0 1 255 FFF000h - FFFFFFh 4 kB Top Block 1 0 0 1 0 255 FFE000h - FFFFFFh 8 kB Top Block 1 0 0 1 1 255 FFC000h - FFFFFFh 16 kB Top Block 1 0 1 0 X 255 FF8000h - FFFFFFh 32 kB Top Block 1 0 1 1 0 255 FF8000h - FFFFFFh 32 kB Top Block 1 1 0 0 1 0 000000h - 000FFFh 4 kB Bottom Block 1 1 0 1 0 0 000000h - 001FFFh 8 kB Bottom Block 1 1 0 1 1 0 000000h - 003FFFh 16 kB Bottom Block 1 1 1 0 X 0 000000h - 007FFFh 32 kB Bottom Block 1 1 1 1 0 0 000000h - 007FFFh 32 kB Bottom Block AT25SF128A DS-AT25SF128A–-168D–-03/2019 12 Table 6-4. AT25SF128A Status Register Memory Protection (CMP = 1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 0 to 255 000000h - FFFFFFh ALL ALL 0 0 0 0 1 0 to 251 000000h - FBFFFFh 16128 kB Lower 63/64 0 0 0 1 0 0 to 247 000000h - F7FFFFh 15872 kB Lower 31/32 0 0 0 1 1 0 to 239 000000h - EFFFFFh 15 KB Lower 15/16 0 0 1 0 0 0 to 223 000000h - DFFFFFh 14 MB Lower 7/8 0 0 1 0 1 0 to 191 000000h - BFFFFFh 12 MB Lower 3/4 0 0 1 1 0 0 to 127 000000h - 7FFFFFh 8 MB Lower 1/2 0 1 0 0 1 4 to 255 040000h - FFFFFFh 16,128 kB Upper 63/64 0 1 0 1 0 8 to 255 080000h - FFFFFFh 15,872 kB Upper 31/32 0 1 0 1 1 16 to 255 100000h - FFFFFFh 15 kB Upper 15/16 0 1 1 0 0 32 to 255 200000h - FFFFFFh 14 MB Upper 7/8 0 1 1 0 1 64 to 255 400000h - FFFFFFh 12 MB Upper 3/4 0 1 1 1 0 128 to 255 800000h - FFFFFFh 8 MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 to 255 000000h - FFEFFFh 16380 kB L-4095/4096 1 0 0 1 0 0 to 255 000000h - FFDFFFh 16376 kB L-2047/2048 1 0 0 1 1 0 to 255 000000h - FFBFFFh 16368 kB L-1023/1024 1 0 1 0 X 0 to 255 000000h - FF7FFFh 16352 kB L-511/512 1 0 1 1 0 0 to 255 000000h - FF7FFFh 16352 kB L-511/512 1 1 0 0 1 0 to 255 001000h - FFFFFFh 16380 kB U-4095/4096 1 1 0 1 0 0 to 255 002000h - FFFFFFh 16376 kB U-2047/2048 1 1 0 1 1 0 to 255 004000h - FFFFFFh 16368 kB U-1023/1024 1 1 1 0 X 0 to 255 008000h - FFFFFFh 16352 kB U-511/512 1 1 1 1 0 0 to 255 008000h - FFFFFFh 16352 kB U-511/512 AT25SF128A DS-AT25SF128A–-168D–-03/2019 13 7. Device Identification Three legacy Instructions are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table. Table 7-1. AT25SF128A ID Definition table Operating Code M7-M0 ID15-ID8 ID7-ID0 9Fh 1Fh 89h 01h 90h/92h/94h 1Fh 17h ABh 8. 17h Instruction Descriptions All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 8-1, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, data bytes, both, or none. The CS pin must be driven high after the last bit of the instruction sequence has been shifted in. For the Read, Fast Read, Read Status Register, Release from Deep Power Down, and Read Device ID instructions, the shifted-in instruction sequence is followed by a data out sequence. The CS pin can be driven high after any bit of the data-out sequence is being shifted out. For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is CS must driven high when the number of clock pulses after CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table 8-1. Instruction Set Instruction Name Byte 1 Write Enable 06h Write Disable 04h Read Status Register-1 05h (S7 - S0) continuous Read Status Register-2 35h (S15 - S8) continuous Read Status Register-3 15h (S23 - S16) continuous Write Enable for Volatile Status Register 50h Write Status Register-1 01h Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 N-Bytes (S7 - S0) AT25SF128A DS-AT25SF128A–-168D–-03/2019 14 Table 8-1. Instruction Set (continued) Instruction Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 N-Bytes Write Status Register-2 31h (S15 - S8) Write Status Register-3 11h (S23 - S16) Read Data 03h A23 - A16 A15 - A8 A7 - A0 (D7 - D0) Next byte continuous Fast Read 0Bh A23 - A16 A15 - A8 A7 - A0 dummy (D7 - D0) continuous Dual Output Fast Read 3Bh A23 - A16 A15 - A8 A7 - A0 dummy (D7 D0)(1) continuous Dual I/O Fast Read BBh A23 - A8(2) A7 - A0 M7 - M0(2) (D7 - D0)(1) Next byte Next byte continuous Quad Output Fast Read 6Bh A23 - A16 A15 - A8 A7 - A0 dummy (D7 D0)(3) continuous Quad I/O Fast Read EBh A23 - A0 M7 - M0(4) dummy(5) (D7 - D0)(3) Next byte Next byte continuous Quad I/O Word Fast Read(7) E7h A23 - A0 M7 - M0 (4) dummy(6) (D7 - D0)(3) Next byte Next byte continuous Page Program 02h A23 - A16 A15 - A8 A7 - A0 (D7 - D0) Next byte continuous Quad Page Program 32h A23 - A16 A15 - A8 A7 - A0 (D7 D0)(3) Next byte continuous Fast Page Program F2h A23 - A16 A15 - A8 A7 - A0 (D7 - D0) Next byte continuous Sector Erase 20h A23 - A16 A15 - A8 A7 - A0 Block Erase(32K) 52h A23 - A16 A15 - A8 A7 - A0 Block Erase (64K) D8h A23 - A16 A15 - A8 A7 - A0 Chip Erase C7/60h Enable Reset 66h Reset 99h Set Burst with Wrap 77h Program/Erase Suspend 75h Program/Erase Resume 7Ah Deep PowerDown B9h dummy(6) W7 - W0 AT25SF128A DS-AT25SF128A–-168D–-03/2019 15 Table 8-1. Instruction Set (continued) Instruction Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Release From Deep PowerDown, And Read Device ID ABh dummy dummy dummy (ID7 - ID0) Release From Deep PowerDown ABh Manufacturer/ Device ID 90h dummy dummy 00H (MID7 MID0) Manufacturer/ Device ID by Dual I/O 92h A23 - A8 A7 - A0, (MID7 - MID0), (DID7 -DID0) dummy 94h JEDEC ID 9Fh MID7 - MID0 ID15 - ID8 ID7-ID0 Read Serial Flash Discoverable Parameter 5Ah A23 - A16 A15 - A8 A7-A0 Erase Security Registers(8) 44h A23 - A16 A15 - A8 A7-A0 Program Security Registers(8) 42h A23 - A16 A15 - A8 Read Security Registers(8) 48h A23 - A16 A15 - A8 dummy N-Bytes continuous (ID7 ID0) continuous continuous dummy(10) Manufacturer/ Device ID by Quad I/O A23 - A0, Byte 6 (MID7 - MID0) continuous (DID7 - DID0) continuous Dummy D7 - D0 continuous A7-A0 (D7 - D0) (D7 - D0) continuous A7-A0 dummy (D7 - D0) continuous Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3,M1 3. Quad Output Data IO0 = (D4, D0,Q..) IO1 = (D5, D1,Q..) IO2 = (D6, D2,Q..) IO3 = (D7, D3,Q..) 4. Quad Input Address AT25SF128A DS-AT25SF128A–-168D–-03/2019 16 IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,Q) IO1 = (x, x, x, x, D5, D1,Q) IO2 = (x, x, x, x, D6, D2,Q) IO3 = (x, x, x, x, D7, D3,Q) 6. Fast Word Read Quad I/O Data IO0 = (x, x, D4, D0,Q) IO1 = (x, x , D5, D1,Q) IO2 = (x, x, D6, D2,Q) IO3 = (x, x, D7, D3,Q) 7. Fast Word Read Quad I/O Data:the lowest address bit must be 0. 8. Security Registers Address: Security Register 1: A23 - A16 = 00h, A15 - A8 = 00010000b, A7 - A0 = Byte Address; Security Register 2: A23 - A16 = 00h, A15 - A8 = 00100000b, A7 - A0 = Byte Address; Security Register 3: A23 - A16 = 00h, A15 - A8 = 00110000b, A7 - A0 = Byte Address; 9. Dummy bits and Wraps Bits IO0 = (x, x, x, x, x, x, w4, x) IO1 = (x, x, x, x, x, x, w5, x) IO2 = (x, x, x, x, x, x, w6, x) IO3 = (x, x, x, x, x, x, x, x) 10. Address, continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2, x, x, x, x, MID6, MID2, DID6, DID2) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3, x, x, x, x, MID7, MID3, DID7, DID3) Security Register 0 can be used to store the Flash Discoverable Parameters, The feature is upon special order, please contact Adesto for details. AT25SF128A DS-AT25SF128A–-168D–-03/2019 17 8.1 Configuration and Status Instructions 8.1.1 Write Enable (06h) The Write Enable instruction is for setting the Write Enable Latch (WEL) bit. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, and Erase/Program Security Registers instruction. The Write Enable instruction sequence: CS goes low sending the Write Enable instruction CS goes high. CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 0 0 0 0 1 1 0 MSB HIGH-IMPEDANCE SO Figure 8-1. Write Enable Sequence Diagram 8.1.2 Write Disable (04h) The Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable instruction sequence: CS goes low -> sending the Write Disable instruction -> CS goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers, and Reset instructions. CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 0 0 0 0 1 0 0 MSB SO HIGH-IMPEDANCE Figure 8-2. Write Disable Sequence Diagram 8.1.3 Read Status Register (05h or 35h or 15h) The Read Status Register (RDSR) instruction is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously. For instruction code 05h, the SO outputs Status Register bits S7 - S0. For instruction code 35h, the SO outputs Status Register bits S15 - S8. For instruction code 15h, the SO outputs Status Register bits S23 - 16. AT25SF128A DS-AT25SF128A–-168D–-03/2019 18 Figure 8-3 shows a Read Status Register operation for Status Register 1 (05h). The Read Status Register 2 and 3 operations would be the same, but with a different opcode in the first eight clocks. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SCK OPCODE SI 0 0 0 0 0 1 0 1 MSB STATUS REGISTER DATA SO STATUS REGISTER DATA STATUS REGISTER DATA HIGH-IMPEDANCE D D D D D D D D D MSB D D D D D D D MSB D D D D D D D D MSB Figure 8-3. Read Status Register Sequence Diagram 8.1.4 Write Status Register (01h or 31h or 11h) The Write Status Register instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register instruction has no effect on S23, S20, S19, S18, S17, S16, S15, S1 and S0 of the Status Register. CS must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register instruction is not executed. As soon as CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in Progress (WIP) bit. This bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the WEL bit is reset. The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware Protected Mode is entered. Figure 8-3 shows a Write Status Register operation for Status Register 1 (01h). The Write Status Register 2 and 3 operations would be the same, but with a different opcode in the first eight clocks. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK OPCODE SI 0 0 0 0 0 0 MSB SO STATUS REGISTER IN 0 1 D X X X X D X X MSB HIGH-IMPEDANCE Figure 8-4. Write Status Register Sequence Diagram AT25SF128A DS-AT25SF128A–-168D–-03/2019 19 8.1.5 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register instruction does not set the Write Enable Latch bit, it is only valid for the Write Status Registers instruction to change the volatile Status Register bit values. /CS 0 Mode 3 Mode 0 SCLK 1 2 3 4 5 6 7 Mode 3 Mode 0 Instruction 50H S1 (IO0) High_Z S0 (IO1) Figure 8-5. Write Enable for Volatile Status Register 8.2 Read Instructions 8.2.1 Read Data (03h) The Read Data instruction is followed by a 3-byte address (A23 - A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC2, during the falling edge of SCLK. The address automatically increments to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single command as long as the clock continues. The command is completed by driving CS high. The whole memory can be read with a single Read Data Bytes (READ) instruction. Any Read Data instruction attempting to execute while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE SI 0 0 0 0 0 ADDRESS BITS A23-A0 0 MSB 1 1 A A A A A A A A A MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D MSB D D D D D D D MSB Figure 8-6. Read Data Bytes Sequence Diagram AT25SF128A DS-AT25SF128A–-168D–-03/2019 20 8.2.2 Fast Read (0Bh) The Read Data at Higher Speed (Fast Read) instruction is for quickly reading data out. It is followed by a 3-byte address (A23 - A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency of fc4 during the falling edge of SCLK. The first byte addressed can be at any location. The address automatically increments to the next higher address after each byte of data is shifted out. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SCK OPCODE SI 0 0 0 0 1 ADDRESS BITS A23-A0 0 1 A 1 A A A A A A DON'T CARE A MSB MSB A X X X X X X X X MSB DATA BYTE 1 SO HIGH-IMPEDANCE D D D D D D D MSB D D D MSB Figure 8-7. Fast Read Sequence Diagram 8.2.3 Dual Output Fast Read (3Bh) The Dual Output Fast Read instruction is followed by 3-byte address (A23 - A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address automatically increments to the next higher address after each byte of data is shifted out. CS SCK 0 1 2 3 4 5 6 7 8 SO & & & & & & MSB 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DON'T &$5( $''5(66%,76$$ 23&2'( 6,6,2 9 10 11 12 & & A A A A A A MSB OUTPUT DAT$% Send 24 Dummy bits -> Send 8 Wrap bits -> CS goes high. If W6-4 is set by a Set Burst with Wrap instruction, all the following Fast Read Quad I/O and Word Read Quad I/O instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the Wrap Around function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. Table 8-2. Set Burst with Wrap W4 = 0 W6, W5 W4 = 1 (Default) Wrap Around Wrap Length Wrap Around Wrap Length 0 0 Yes 8-byte No N/A 0 1 Yes 16-byte No N/A 1 0 Yes 32-byte No N/A 1 1 Yes 64-byte No N/A /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI (IO0) SO (IO1) Instruction High_Z 77H x x x x x x W4 x High_Z x x x x x x W5 x High_Z x x x x x x x High_Z W6 x x x x x x x x High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z Byte1 Byte2 Byte3 Byte4 Figure 8-16. Set Burst with Wrap Sequence Diagram AT25SF128A DS-AT25SF128A–-168D–-03/2019 26 8.3 ID and Security Instructions 8.3.1 Read Manufacture ID/ Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The instruction is initiated by driving the CS pin low and shifting the instruction code 90h followed by a 24-bit address (A23-A0) of 000000h. If the 24-bit address is initially set to 000001h, the Device ID will be read first. /CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Instruction SI 90H High_Z SO 23 24-Bit Address 22 21 3 2 1 0 /CS 32 33 34 7 6 35 36 37 38 39 40 41 42 0 6 5 43 44 45 46 47 1 0 SCLK SI SO Manufacturer ID 5 4 3 2 1 7 Device ID 4 3 2 Figure 8-17. Read Manufacture ID/ Device ID Sequence Diagram 8.3.2 Dual I/O Read Manufacture ID/ Device ID (92h) The Dual I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by Dual I/O. The instruction is initiated by driving the CS pin low and shifting the instruction code 92h followed by a 24-bit address (A23 - A0) of 000000h. If the 24-bit address is initially set to 000001h, the Device ID is read first. AT25SF128A DS-AT25SF128A–-168D–-03/2019 27 /CS 0 1 2 4 3 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Instruction SI (IO0) 92H SO (IO1) High_Z 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 Dummy /CS SCLK 23 24 25 26 27 28 29 30 39 31 32 SI (IO0) 6 4 2 0 6 4 2 0 SO (IO1) 7 5 3 1 7 5 3 1 40 6 41 42 43 44 45 46 47 0 6 7 5 3 1 MFR ID(repeat) 7 4 2 4 2 High_Z 0 High_Z MFR ID MFR and Device ID Device ID (repeat) 3 1 5 Device ID(repeat) Figure 8-18. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram 8.3.3 Quad I/O Read Manufacture ID/ Device ID (94h) The Quad I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The instruction is initiated by driving the CS pin low and shifting the instruction code 94h followed by a 24-bit address (A23 - A0) of 000000h and four dummy clocks. If the 24-bit address is initially set to 000001h, the Device ID is read out first. AT25SF128A DS-AT25SF128A–-168D–-03/2019 28 /CS 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Instruction SI (IO0) 94H SO (IO1) High_Z WP (IO2) High_Z HOLD (IO3) High_Z 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 A23-16 A15-8 A7-0 dummy dummy MFR ID Device ID /CS SCLK 23 24 25 26 27 28 29 30 31 SI (IO0) 4 0 4 0 4 0 4 0 SO (IO1) 5 1 5 1 5 1 5 1 WP (IO2) 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 HOLD (IO3) MFR ID DID ID MFR ID DID ID (repeat) (repeat) (repeat) (repeat) Figure 8-19. Quad I/O Read Manufacture ID / Device ID Sequence Diagram 8.3.4 Read JEDEC ID (9Fh) The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS to low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID instruction is terminated by driving CS to high at any time during data output. When CS is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute instructions. AT25SF128A DS-AT25SF128A–-168D–-03/2019 29 /CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 1 0 30 31 1 0 SCLK 9FH Instruction SI Manufacturer ID 7 MSB SO /CS 18 19 16 17 20 21 22 23 24 6 25 26 5 4 3 27 28 29 SCLK SI SO Memory Type ID15-ID8 5 4 3 2 1 6 7 0 MSB 7 Capacity ID7-ID0 5 4 3 2 6 MSB Figure 8-20. JEDEC ID Sequence Diagram 8.3.5 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each AT25SF128A device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS pin low and shifting the instruction code 4Bh followed by a four bytes of dummy clocks. After which, the 64-bit ID is shifted out on the falling edge of SCLK as shown in Figure 8-21. /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 Instruction SI 11 12 13 14 15 16 Dummy Byte 1 17 18 19 20 21 22 23 Dummy Byte 2 4BH SO High_Z /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 101 102 103 Mode 3 SCLK Mode 0 Dummy Byte 3 Dummy Byte 4 SI SO High_Z 63 62 MSB 2 1 0 64-bit Unique Serial Number Figure 8-21. Read Unique ID Sequence Diagram AT25SF128A DS-AT25SF128A–-168D–-03/2019 30 8.3.6 Deep Power-Down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is initiated by driving the CS pin low and shifting the instruction code B9h as shown in Figure 8-22. The CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power down instruction is not executed. After CS is driven high, the power-down state is entered within the time duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. All other Instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. /CS 0 1 2 3 4 5 6 7 tDP SCLK Instruction SI B9H Stand -by mode Power-down mode Figure 8-22. Deep Power-Down Sequence Diagram 8.3.7 Release from Deep Power-Down/Read Device ID (ABh) The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state, the instruction is issued by driving the CS pin low, shifting the instruction code ABh and driving CS high Release from Power-Down will take the time duration of tRES1 (See Section 9.8, AC Electrical Characteristics) before the device resumes normal operation and other instruction are accepted. The CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by driving the CS pin low and shifting the instruction code ABh followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 8-23. The Device ID value for the AT25SF128A is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving CS high. When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 8-23, except that after CS is driven high it must remain high for a time duration of tRES2 (See Section 9.8, AC Electrical Characteristics). After this time duration the device resumes normal operation and other instructions are accepted. If the Release from Power-Down/Device ID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction is ignored and does not effect the current cycle. AT25SF128A DS-AT25SF128A–-168D–-03/2019 31 /CS 1 0 2 3 4 5 6 tR ES1 7 SCLK Instruction SI ABH Power-down mode Stand-by mode Figure 8-23. Release Power-Down Sequence Diagram /CS 0 1 2 3 4 5 6 7 8 9 23 MSB 22 29 30 31 32 33 34 35 36 37 38 39 SCLK Instruction SI ABH SO High_Z 3 Dummy Bytes 2 tRES2 1 0 Device ID 7 MSB 6 5 4 3 2 1 0 Deep Power-down mode Stand-by mode Figure 8-24. Release Power-Down/Read Device ID Sequence Diagram 8.3.8 Read Security Registers (48h) The Read Security Registers instruction is similar to Fast Read instruction. The instruction is followed by a 3-byte address (A23 - A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address automatically increments to the next higher address after each byte of data is shifted out. Once the A7 - A0 address reaches the last byte of the register (Byte FFh), it resets to 000h, the instruction is completed by driving CS high. Table 8-3. Read Security Registers Address A23-A16 A15-A12 A11-A8 A7-A0 Security Registers 1 00h 0001 0000 Byte Address Security Registers 2 00h 0010 0000 Byte Address Security Registers 3 00h 0011 0000 Byte Address AT25SF128A DS-AT25SF128A–-168D–-03/2019 32 /CS 0 1 2 3 4 5 6 7 8 9 28 29 30 31 SCLK Instruction SI 48H SO High_Z 24-Bit Address 23 22 3 2 1 0 /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte 7 SI 6 5 4 3 2 1 0 Data Byte 1 SO 7 6 MSB 5 4 3 2 1 0 Figure 8-25. Read Security Registers Instruction Sequence Diagram 8.3.9 Erase Security Registers (44h) The AT25SF128A provides three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers instruction is similar to Sector/Block Erase instruction. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The Erase Security Registers instruction sequence: CS goes low -> sending Erase Security Registers instruction -> CS goes high. CS must be driven high after the eighth bit of the instruction code has been latched in otherwise the Erase Security Registers instruction is not executed. As soon as CS is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers are permanently locked; the Erase Security Registers instruction is ignored. Table 8-4. Erase Security Registers Address A23 - A16 A15 - A12 A11 - A8 A7 - A0 Security Registers 1 00h 0001 0000 Byte Address Security Registers 2 00h 0010 0000 Byte Address Security Registers 3 00h 0011 0000 Byte Address AT25SF128A DS-AT25SF128A–-168D–-03/2019 33 Figure 8-26. Erase Security Registers Instruction Sequence Diagram 8.3.10 Program Security Registers (42h) The Program Security Registers instruction is similar to the Page Program instruction. It allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable instruction must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers instruction. The Program Security Registers instruction is entered by driving CS low, followed by the instruction code (42h), a 3-byte address and at least one data byte on the SI pin. As soon as CS is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. If the Security Registers Lock Bit (LB3/LB2/LB1) bits are set to 1, the Security Registers are permanently locked. The Program Security Registers instruction is ignored. Program Security Registers Table 8-5. Address A23 - A16 A15 - A12 A11 - A8 A7 - A0 Security Registers 1 00h 0001 0000 Byte Address Security Registers 2 00h 0010 0000 Byte Address Security Registers 3 00h 0011 0000 Byte Address /CS 0 4 3 2 1 5 6 7 9 8 10 29 30 28 31 32 33 34 35 36 37 38 39 SCLK Instruction 24-Bit Address 23 22 MSB 42H SI 21 3 Data Byte 1 1 2 0 7 6 MSB 4 5 2 3 1 0 2079 2078 2077 2076 2075 55 2074 53 54 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 2072 /CS SCLK Data Byte 2 SI 7 MSB 6 5 4 3 2 1 0 7 6 MSB Data Byte 3 4 3 2 5 1 0 7 6 MSB Data Byte 256 3 2 5 4 1 0 Figure 8-27. Program Security Registers Instruction Sequence Diagram AT25SF128A DS-AT25SF128A–-168D–-03/2019 34 8.3.11 Enable Reset (66h) and Reset Device (99h) Because of the small package and the limitation on the number of pins, the AT25SF128A provides a software Reset instruction instead of a dedicated RESET pin. Once the software Reset instruction is accepted, any on-going internal operations are terminated and the device returns to its default power-on state and loses all of the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4). To avoid accidental reset, both Enable Reset (66h) and Reset (99h) instructions must be issued in sequence. Any other commands other than Reset (99h) after the Enable Reset (66h) command will disable the Reset Enable state. A new sequence of Enable Reset (66h) and Reset (99h) is needed to reset the device. Once the Reset command is accepted by the device, the device takes approximately 30 µs to reset. During this period, no commands are accepted. The Enable Reset (66h) and Reset (99h) instruction sequence is shown in Figure 8-28. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. Figure 8-28. Enable Reset (66h) and Reset (99h) Command Sequence 8.4 Program and Erase Instructions 8.4.1 Page Program (02h) The Page Program instruction is for programming the memory. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit before sending the Page Program instruction. The Page Program instruction is entered by driving CS Low, followed by the instruction code, 3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7 - A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7 - A0) are all zero). CS must be driven low for the entire duration of the sequence. The Page Program instruction sequence: CS goes low -> sending Page Program instruction -> 3-byte address on SI -> at least 1 byte of data on SI -> CS goes high. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program instruction is not executed. As soon as CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) AT25SF128A DS-AT25SF128A–-168D–-03/2019 35 bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed. /CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Instruction 24-Bit Address 23 22 MSB 02H SI 21 3 Data Byte 1 1 2 0 7 6 MSB 4 5 2 3 1 0 2 079 2 078 2 077 2 076 2 075 55 2 074 44 45 46 47 48 49 50 51 52 53 54 2 073 40 41 42 43 2 072 /CS SCLK SI 7 6 5 Data Byte 2 4 3 2 MSB 1 0 7 6 MSB Data Byte 3 5 4 3 2 1 0 7 6 MSB Data Byte 256 5 4 3 2 1 0 Figure 8-29. Page Program Sequence Diagram 8.4.2 Quad Page Program (32h) The Quad Page Program instruction is for programming the memory using for pins: IO0, IO1, IO2 and IO3. To use Quad Page Program the Quad Enable (QE) bit in the Status register must be set (QE = 1). A Write Enable instruction must previously have been executed to set the Write Enable Latch bit before sending the Page Program instruction. The Quad Page Program instruction is entered by driving CS low, followed by the command code (32h), three address bytes and at least one data byte on IO pins. The instruction sequence is shown in Figure 8-30. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program instruction is not executed. As soon as CS is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset.A Quad Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed. AT25SF128A DS-AT25SF128A–-168D–-03/2019 36 /CS 0 1 2 4 3 5 6 7 30 31 32 33 34 35 36 37 38 39 8 SCLK Instruction SI (IO0) 32H SO (IO1) High_Z WP (IO2) High_Z HOLD (IO3) High_Z 24-bits address 23 22 0 1 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 Byte1 Byte2 /CS SCLK 40 41 42 43 44 45 46 47 48 535 536 537 538 539 540 541 542 543 SI (IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO (IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP (IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 7 3 Byte 5 7 3 7 3 7 3 7 3 7 3 7 3 7 3 High_Z High_Z High_Z High_Z HOLD (IO3) Byte 6 Byte 253 Byte 256 Figure 8-30. Quad Page Program Sequence Diagram 8.4.3 Fast Page Program (F2h) The Fast Page Program instruction is used to program the memory. A Write Enable instruction must previously have been executed to set the WEL bit before sending the Page Program instruction. The Fast Page Program instruction is entered by driving CS Low, followed by the instruction code, 3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS must be driven low for the entire duration of the sequence. The Fast Page Program instruction sequence: CS goes low -> sending Page Program instruction -> 3-byte address on SI -> at least 1 byte data on SI -> CS goes high. The command sequence is shown in Figure 8-31. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Fast Page Program instruction is not executed. As soon as CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write-in-Progress (WIP) AT25SF128A DS-AT25SF128A–-168D–-03/2019 37 bit. The WIP bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. A Fast Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed. /CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Instruction 24-Bit Address 23 22 21 MSB F2H SI 3 Data Byte 1 1 2 0 7 6 MSB 4 5 2 3 1 0 2 079 2 078 2 077 2 076 2 075 2 074 53 54 55 2 073 40 41 42 43 44 45 46 47 48 49 50 51 52 2 072 /CS SCLK SI 7 6 5 Data Byte 2 4 3 2 1 0 MSB 7 6 MSB Data Byte 3 5 4 3 2 1 7 6 MSB 0 Data Byte 256 5 4 3 2 1 0 Figure 8-31. Fast Page Program Sequence Diagram 8.4.4 Sector Erase (20h) The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by driving CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase instruction. CS must be driven low for the entire duration of the sequence. The Sector Erase instruction sequence: CS goes low -> sending Sector Erase instruction -> 3-byte address on SI -> CS goes high. CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase instruction is not executed. As soon as CS is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write-in-Progress (WIP) bit. The WIP bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase instruction applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed. /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Instruction SI 20H 24-Bit Address 23 22 2 1 0 Figure 8-32. Sector Erase Sequence Diagram 8.4.5 32KB Block Erase (52h) The 32 KB Block Erase instruction is for erasing all data of a chosen block. A Write Enable instruction must have been previously executed to set the WEL bit. The 32 kB Block Erase instruction is entered by driving CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the 32 KB Block Erase instruction. CS must be driven low for the entire duration of the sequence. AT25SF128A DS-AT25SF128A–-168D–-03/2019 38 The 32 KB Block Erase instruction sequence: CS goes low -> sending 32 kB Block Erase instruction -> 3-byte address on SI -> CS goes high. CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32 kB Block Erase instruction is not executed. As soon as CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write-in-Progress (WIP) bit. The WIP bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32 kB Block Erase instruction applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed. /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Instruction SI 24-Bit Address 23 22 52H 2 1 0 Figure 8-33. 32KB Block Erase Sequence Diagram 8.4.6 64KB Block Erase (D8h) The 64 KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction must previously have been executed to set the WEL bit. The 64 KB Block Erase instruction is entered by driving CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the block is a valid address for the 64 KB Block Erase instruction. CS must be driven low for the entire duration of the sequence. The 64 KB Block Erase instruction sequence: CS goes low sending 64 KB Block Erase instruction 3-byte address on SI CS goes high. CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64 KB Block Erase instruction is not executed. As soon as CS is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write-inProgress (WIP) bit. The WIP bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. A 64 KB Block Erase instruction applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits is not executed. /CS 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Instruction SI D8H 24-Bit Address 23 22 2 1 0 Figure 8-34. 64KB Block Erase Sequence Diagram AT25SF128A DS-AT25SF128A–-168D–-03/2019 39 8.4.7 Chip Erase (60/C7h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device accepts the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the CS pin low and shifting the instruction code C7h or 60h. The Chip Erase instruction sequence is shown in Figure 8-35. The CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction is not executed. After CS is driven high, the self-timed Chip Erase instruction commences for a time duration of tCE. While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the WIP bit. The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other Instructions again. After the Chip Erase cycle has finished the WEL bit in the Status Register is cleared to 0. The Chip Erase instruction is executed only if all Block Protect (BP2, BP1, and BP0) bits are 0. The Chip Erase instruction is ignored if one or more sectors are protected. /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI 60/C7H High_Z SO Figure 8-35. Chip Erase Sequence Diagram 8.4.8 Erase / Program Suspend (75h) The Erase/Program Suspend instruction allows the system to interrupt a Sector or Block Erase operation, then read from or program data to any other sector. The Erase/Program Suspend instruction also allows the system to interrupt a Page Program operation and then read from any other page or erase any other sector or block. The Erase/Program Suspend instruction sequence is shown in Figure 8-36. The Write Status Registers instruction (01h) and Erase instructions (20h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Registers instruction (01h), and Program instructions (02h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program operation. / CS 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 SCLK Instruction SI 75H tSUS Instruction During Suspend Figure 8-36. Erase/Program Suspend Command Sequence AT25SF128A DS-AT25SF128A–-168D–-03/2019 40 8.4.9 Erase / Program Resume (7Ah) The Erase/Program Resume instruction 7Ah must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction 7Ah is accepted by the device only if the SUS bit in the Status Register equals to 1 and the WIP bit equals to 0. After the Resume instruction is issued the SUS bit is cleared from 1 to 0 immediately, the WIP bit is set from 0 to 1 within 200 ns and the Sector or Block completes the erase operation or the page completes the program operation. If the SUS bit equals to 0 or the WIP bit equals to 1, the Resume instruction 7Ah is ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 8-37. /CS 0 1 2 3 4 5 6 7 SCLK Instruction SI 7AH SO High_Z Figure 8-37. Erase/Program Resume Command Sequence 8.4.10 Read Serial Flash Discoverable Parameter (5Ah) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial Flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No. 216. /CS 0 1 2 3 4 5 6 7 8 9 28 29 30 31 SCLK Instruction SI 5AH SO High_Z 24-Bit Address 23 22 3 2 1 0 /CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 Data Byte 1 SO 7 6 MSB 5 4 3 2 1 0 Figure 8-38. Read Serial Flash Discoverable Parameter Command Sequence Diagram AT25SF128A DS-AT25SF128A–-168D–-03/2019 41 Table 8-6. SFDP Signature and Headers Description Comment SFDP Signature Address Byte Bits Data (binary) Data (hex) 00h 07:00 0101 0011 53h 01h 15:08 0100 0110 46h 02h 23:16 0100 0100 44h 03h 31:24 0101 0110 50h SFDP Minor Revision Start from 00h 04h 07:00 0000 0000 00h SFDP Major Revision Start from 01h 05h 15:08 0000 0001 01h Number of Parameters Headers Start from 00h 06h 23:16 0000 0001 01h Reserved FFh 07h 31:24 1111 1111 FFh JEDEC Parameter ID (LSB) JEDEC Parameter ID (LSB) = 00h 08h 07:00 0000 0000 00h Parameter Table Minor Revision Start from 00h 09h 15:08 0000 0000 00h Parameter Table Major Start from 01h 0Ah 23:16 0000 0001 01h 0Bh 31:24 0000 1001 09h 0Ch 07:00 0011 0000 30h 0Dh 15:08 0000 0000 00h 0Eh 23:16 0000 0000 00h Revision Parameter Table Length (double words) Parameter Table Pointer How many DWORDs in the parameter table Address of Adesto Parameter Table Reserved FFh 0Fh 31:24 1111 1111 FFh ID Number LSB (Manufacturer ID) Adesto Manufacturer ID 10h 07:00 0001 1111 1Fh Parameter Table Minor Revision Start from 00h 11h 15:08 0000 0000 00h Parameter Table Major Revision Start from 01h 12h 23:16 0000 0001 01h Parameter Table Length (double words) How many DWORDs in the parameter table 13h 31:24 0000 0011 03h Parameter Table Pointer (PTP) Address of Adesto Parameter Table 14h 07:00 0110 0000 60h 15h 15:08 0000 0000 00h 16h 23:16 0000 0000 00h 17h 31:24 1111 1111 FFh Reserved FFh AT25SF128A DS-AT25SF128A–-168D–-03/2019 42 Table 8-7. SFDP Parameters Table 1 Address Byte Bits Data (binary) Data (hex) 30h 01:00 01 E5h 0: 1 byte 1: 64 bytes or larger 02 1 Volatile Status Register Block Protect Bits 0: Nonvolatile status bit 1: Volatile status bit 03 0 Volatile Status Register Write Enable Opcode 0: 50h Opcode 1: 60h Opcode (If target Flash Status register is nonvolatile, then bits 3 and 4 must be set to 2’b00. 04 0 07:05 111 Description Comment Erase Granularity 01: 4KB available 11: 4KB not available Write Granularity Reserved 4KB Erase Opccde Opcode or FFh 31h 15:08 0010 0000 20h Fast Dual Read Output (1 -1 -2) 0: Not supported, 1: Supported 32h 16 1 F1h Number of Address Bytes 00: 3 Byte only 01: 3 or 4 Byte 10: 4 Byte only 11: Reserved 18:17 00 Double Transfer Rate (DTR) Clocking 0: Not supported, 1: Supported 19 0 Fast Dual I/O Read (1-2- 2) 0: Not supported, 1: Supported 20 1 Fast Quad I/O Read (1-4-4) 0: Not supported, 1: Supported 21 1 Fast Quad Output Read (1-1-4) 0: Not supported, 1: Supported 22 1 Reserved FFh 23 1 Reserved FFh 33h 31:24 1111 1111 FFh 37h:34h 31:0 0000 0111 1111 1111 1111 1111 1111 1111 07FFFFFFh 38h 04:00 00100 44h 07:05 010 15:08 1110 1011 Flash Memory Density Fast Quad I/O (1-4-4) Number of dummy clocks Number of dummy clocks Fast Quad I/O (1-4-4) Number of mode bits Number of mode bits Fast Quad I/O (1-4-4) Read Opcode Opcode or FFh 39h EBh AT25SF128A DS-AT25SF128A–-168D–-03/2019 43 Table 8-7. SFDP Parameters Table 1 (continued) Description Comment Address Byte Bits Data (binary) Data (hex) Fast Quad Output (1-1-4) Number of dummy clocks Number of dummy clocks 3Ah 20:16 01000 08h Fast Quad Output (1-1-4) Number of mode bits Number of mode bits 23:21 000 Fast Quad Output (1-1-4) Read Opcode Opcode or FFh 3Bh 31:24 0110 1011 6Bh Fast Dual Output (1-1-2) Number of dummy clocks Number of dummy clocks 3Ch 04:00 01000 08h Fast Dual Output (1-1-2) Number of mode bits Number of mode bits 07:05 000 Fast Dual Output (1-1-2) Read Opcode Opcode or FFh 3Dh 15:08 0011 1011 3Bh Fast Dual I/O (1-2-2) Number of dummy clocks Number of dummy clocks 3Eh 20:16 00010 42h Fast Dual I/O (1-2-2) Number of mode bits Number of mode bits 23:21 010 Fast Dual I/O (1-2-2) Read Opcode Opcode or FFh 3Fh 31:24 1011 1011 BBh Fast Dual (2-2-2) 0: Not supported, 1: Supported 40h 0 0 EEh Reserved FFh 03:01 111 Fast Quad (4-4-4) 0: Not supported, 1: Supported 04 0 Reserved FFh 07:05 111 Reserved FFh 41h 15:08 1111 1111 FFh Reserved FFh 42h 23:16 1111 1111 FFh Reserved FFh 43h 31:24 1111 1111 FFh Reserved FFh 44h 07:00 1111 1111 FFh Reserved FFh 45h 15:08 1111 1111 FFh Fast Dual (2-2-2) Number of dummy clocks Number of dummy clocks 46h 20:16 0 0000 00h Fast Dual (2-2-2) Number of mode bits Number of mode bits 23:21 000 Fast Dual (2-2-2) Read Opcode Opcode or FFh 47h 31:24 0000 0000 00h Reserved FFh 48h 07:00 1111 1111 FFh Reserved FFh 49h 15:08 1111 1111 FFh AT25SF128A DS-AT25SF128A–-168D–-03/2019 44 Table 8-7. SFDP Parameters Table 1 (continued) Description Comment Address Byte Bits Data (binary) Data (hex) Fast Quad QPI (4-4-4) Number of dummy clocks Number of dummy clocks 4Ah 20:16 00000 00h Fast Quad QPI (4-4-4) Number of mode bits Number of mode bits 23:21 000 Fast Quad QPI (4-4-4) Opcode or FFh 4Bh 31:24 0000 0000 00h Erase type-1 Size 4KB = 2^0Ch, 32KB = 2^0Fh, 64KB = 2^10h; (2^Nbyte) 4Ch 07:00 0000 1100 0Ch Erase type-1 Opcode Opcode or FFh 4Dh 15:08 0010 0000 20h Erase type-2 Size 4KB = 2^0Ch, 32KB = 2^0Fh, 64KB = 2^10h; (2^Nbyte) 4Eh 23:16 0000 1111 0Fh Erase type-2 Opcode Opcode or FFh 4Fh 31:24 0101 0010 52h Erase Type-3 Size 4KB = 2^0Ch, 32KB = 2^0Fh, 64KB = 2^10h; (2^Nbyte) 50h 07:00 0001 0000 10h Erase Type-3 Opcode Opcode or FFh 51h 15:08 1101 1000 D8h Erase Type-4 Size 4KB = 2^0Ch, 32KB = 2^0Fh, 64KB = 2^10h; (2^Nbyte) 52h 23:16 0000 0000 00h Erase Type-4 Opcode Opcode or FFh 53h 31:24 1111 1111 FFh Vcc Maximum Voltage 2000h: 2.0V 2700h: 2.7V 3600h: 3.6V 60h 7:0 0000 0000 00h 61h 15:8 0011 0110 36h 1650h: 1.65V 2250h: 2.25V 2350h: 2.35V 2700h: 2.70V 62h 7:0 0000 0000 00h 63h 15:8 0010 0112 27h Read Opcode Vcc Minimum Voltage AT25SF128A DS-AT25SF128A–-168D–-03/2019 45 Table 8-7. SFDP Parameters Table 1 (continued) Address Byte Bits Data (binary) Data (hex) 65h:64h 0 0 F99Eh 0: Not supported 1: Supported 1 1 Deep Power Down Mode 0: Not supported 1: Supported 2 1 Software Reset 0: Not supported 1: Supported 3 1 Software Reset Opcode Issue Reset Enable (66h) before Reset (99h) 11:4 99h Program Suspend/Resume 0: Not supported 1: Supported 12 1 Erase Suspend/Resume 0: Not supported 1: Supported 13 1 14 1 15 1 66h 23:16 0111 0111 77h Description Comment Hardware RESET Pin 0: Not supported 1: Supported Hardware HOLD Pin Reserved Wrap-around Read Mode 0: Not supported 1: Supported Wrap-around Read Mode Opcode Wrap-around Read Data Length 08h: Supports 8b wrap-around 16h: Supports 8b and 16b 32h: Supports 8b, 16, and 32b 64h: Supports 8b, 16b, 32b, and 64b 67h 31:24 0110 0100 64h Individual Block Lock 0: Not supported 1: Supported 69h:68h 0 0 C000h Individual Block Lock (Volatile/Non-volatile) 0: Not supported 1: Supported 1 0 9:2 0000 0000 Individual Block Lock Opcode Individual Block Lock (Volatile protect bit, default protect status) 0: Not supported 1: Supported 10 0 Secured OTP 0: Not supported 1: Supported 11 0 Read Lock 0: Not supported 1: Supported 12 0 Permanent Lock 0: Not supported 1: Supported 13 0 15:14 11 31:16 1111 1111 1111 1111 Reserved Reserved 6Bh:6Ah FFFFh AT25SF128A DS-AT25SF128A–-168D–-03/2019 46 9. Electrical Characteristics 9.1 Absolute Maximum Ratings Table 9-1. Absolute Maximum Ratings Parameter Symbol Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT Storage Temperature TSTG Electrostatic Discharge Voltage VESD Conditions Range Units -0.5 to 4 V Relative to Ground -0.5 to 4 V