AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Features
Datasheet
DS-AT25XE161D-158
Voltage Range: 1.65 V - 3.6 V
4 Mbit (2M x 2) Flash Memory
Flexible 256-byte page erase architecture
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports SPI single mode operation (1-1-1)
Supports dual output operation (1-1-2)
Supports quad output operation (1-1-4)
Supports quad XiP operation (1-4-4 and 0-4-4)
133 MHz maximum operating frequency
Clock-to-output of 8 ns
Flexible, optimized erase architecture for code + data storage applications
Uniform 256-Byte page erase
Uniform 4-KByte block erase
Uniform 32-KByte block erase
Uniform 64-KByte block erase
Full chip erase
Flexible non-volatile block protection
1 x 128-byte factory-programmed unique identifier
3 x 128-byte, One Time Programmable (OTP) security registers
Flexible programming
Byte/Page program (1 to 256 Bytes)
Single command page buffer direct Read-Modify-Write (page write with inclusive erase)
Flexible 256-byte SRAM page buffer operation
Sequential program mode capability
Erase program suspend resume
Software controlled Reset and Terminate commands
Hardware reset option (via /HOLD pin)
JEDEC hardware reset
Low battery detect circuit
Active interrupt device status capability
Non-volatile status register configuration option
JEDEC standard manufacturer and device ID read methodology
Serial Flash Discoverable Parameters (SFDP) version 1.6
Low power dissipation:
30 µA standby current (typical)
8.2 µA Deep Power-Down (DPD) current (typical)
7 nA Ultra Deep Power Down (UDPD) current (typical)
8.6 mA active read current (1-1-1 — 108 MHz)
9.2 mA program current
10.2 mA erase current
User configurable and auto I/O pin drive levels
Endurance
100,000 program/erase cycles
Data Retention
20 years
-40 oC to +85 oC operation
Industry standard green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-lead SOIC (208-mil)
8-pad Ultra-thin DFN (2 x 3 x 0.6 mm)
8-ball WLCSP (3 x 2 x 3 ball matrix)
Die/Wafer — Contact Dialog Semiconductor for more information
Revision H
10
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Contents
Features .................................................................................................................................................................................... 1
Contents.................................................................................................................................................................................... 2
Figures ...................................................................................................................................................................................... 8
Tables ........................................................................................................................................................................................ 9
1 Product Overview ............................................................................................................................................................... 10
2 Block Diagram .................................................................................................................................................................... 11
3 Package Pinouts ................................................................................................................................................................ 12
4 Device Operation ................................................................................................................................................................ 15
4.1 Data Transfer Modes ............................................................................................................................................... 15
4.2 Standard SPI Operation ........................................................................................................................................... 15
4.2.1 Command Only, No Address or Data (1-0-0) ............................................................................................. 16
4.2.2 Command and Address Only, No Data (1-1-0) .......................................................................................... 16
4.2.3 Command and Data Only, No Address (1-0-1) .......................................................................................... 17
4.2.4 Command, Address, and Data (1-1-1) ....................................................................................................... 18
4.3 Dual Output Operation (1-1-2) ................................................................................................................................. 19
4.4 Quad Output Operation (1-1-4) ................................................................................................................................ 20
4.5 Quad I/O Operation (1-4-4) ...................................................................................................................................... 22
4.6 XiP Mode Operation................................................................................................................................................. 23
4.6.1 Initial Transfer and XiP Mode Detection (M[5:4]) ....................................................................................... 23
4.6.2 Subsequent Transfers ................................................................................................................................ 24
4.6.3 Set Burst with Wrap ................................................................................................................................... 25
4.7 Memory Architecture ................................................................................................................................................ 25
4.8 Memory Protection ................................................................................................................................................... 28
4.8.1 Standard Memory Protection ..................................................................................................................... 28
4.8.2 Individual Block Lock and Unlock............................................................................................................... 31
4.8.3 Global Block Lock and Unlock ................................................................................................................... 31
4.8.4 Reading the State of the Lock Bits ............................................................................................................. 31
4.9 Power-Down Considerations ................................................................................................................................... 32
4.9.1 Entering Power-Down Mode ...................................................................................................................... 32
4.9.2 Exiting Power-Down Mode ......................................................................................................................... 32
4.9.3 Reset During Program and Erase Commands........................................................................................... 33
4.10 Erase/Program Suspend Considerations and Nested Operations......................................................................... 34
4.10.1 Nested Operations ................................................................................................................................... 34
4.10.2 Program and Erase Errors ....................................................................................................................... 36
4.10.3 Suspending and Terminating a Program or Erase Operation .................................................................. 37
4.10.4 Terminating a Non-Volatile Register Operation in Progress .................................................................... 39
4.11 OTP Security Register Lock................................................................................................................................... 39
4.12 Standard JEDEC Hardware Reset......................................................................................................................... 40
4.13 Chip Select Restrictions ......................................................................................................................................... 40
4.14 Active Status Interrupt............................................................................................................................................ 41
4.15 Low Battery Detect................................................................................................................................................. 41
4.16 Read-Modify-Write ................................................................................................................................................. 42
4.17 HOLD / RESET Function ....................................................................................................................................... 42
5 Status Registers ................................................................................................................................................................. 43
5.1 Register Structure and Updates............................................................................................................................... 43
5.2 Register Accesses ................................................................................................................................................... 43
5.2.1 Direct and Indirect Addressing ................................................................................................................... 44
5.2.2 Volatile and Non-Volatile Register Accesses ............................................................................................. 44
5.3 Status Register 1 ..................................................................................................................................................... 44
5.4 Status Register 2 ..................................................................................................................................................... 46
5.5 Status Register 3 ..................................................................................................................................................... 48
5.6 Status Register 4 ..................................................................................................................................................... 49
5.7 Status Register 5 .................................................................................................................................................... 50
5.8 Status Register 6 ..................................................................................................................................................... 51
Datasheet
DS-AT25XE161D-158
Revision H
10
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
6 Commands and Addressing .............................................................................................................................................. 52
6.1 Read Array (03h, 0Bh) ............................................................................................................................................. 56
6.1.1 Transfer Format ......................................................................................................................................... 56
6.1.2 Transfer Sequence..................................................................................................................................... 56
6.2 Dual Output Read Array (3Bh) ................................................................................................................................. 56
6.2.1 Transfer Format ......................................................................................................................................... 56
6.2.2 Transfer Sequence..................................................................................................................................... 56
6.3 Quad Output Read Array (6Bh) ............................................................................................................................... 57
6.3.1 Transfer Format ......................................................................................................................................... 57
6.3.2 Transfer Sequence..................................................................................................................................... 57
6.4 XiP Mode Read (EBh), XiP Mode Read with Double-word Aligned Address (E7h)................................................. 58
6.4.1 Transfer Format ......................................................................................................................................... 58
6.4.2 Mode Bits ................................................................................................................................................... 58
6.4.3 Transfer Sequence — Initial Transfer ........................................................................................................ 58
6.4.4 Transfer Sequence — Subsequent Transfers............................................................................................ 59
6.4.5 Programmable Number of Dummy Clocks................................................................................................. 59
6.5 Page Erase (81h/DBh) ............................................................................................................................................. 61
6.5.1 Command Prerequisites............................................................................................................................. 61
6.5.2 Transfer Format ......................................................................................................................................... 61
6.5.3 Transfer Sequence..................................................................................................................................... 61
6.5.4 Active Status Interrupt ................................................................................................................................ 62
6.5.5 Command Status ....................................................................................................................................... 62
6.5.6 Programming Restrictions .......................................................................................................................... 62
6.5.7 Error Reporting........................................................................................................................................... 62
6.6 Block Erase (20h, 52h, D8h) .................................................................................................................................... 62
6.6.1 Command Prerequisites............................................................................................................................. 62
6.6.2 Transfer Format ......................................................................................................................................... 63
6.6.3 Transfer Sequence..................................................................................................................................... 63
6.6.4 Erase Operation ......................................................................................................................................... 63
6.6.5 Command Status ....................................................................................................................................... 63
6.6.6 Active Status Interrupt ................................................................................................................................ 63
6.6.7 Programming Restrictions .......................................................................................................................... 63
6.6.8 Error Reporting........................................................................................................................................... 63
6.7 Chip Erase (60h, C7h) ............................................................................................................................................. 64
6.7.1 Command Prerequisites............................................................................................................................. 64
6.7.2 Transfer Format ......................................................................................................................................... 64
6.7.3 Transfer Sequence..................................................................................................................................... 64
6.7.4 Device Status ............................................................................................................................................. 64
6.7.5 Active Status Interrupt ................................................................................................................................ 64
6.7.6 Programming Restrictions .......................................................................................................................... 64
6.7.7 Error Reporting........................................................................................................................................... 65
6.8 Byte/Page Program (02h) ........................................................................................................................................ 65
6.8.1 Command Prerequisites............................................................................................................................. 65
6.8.2 Transfer Format ......................................................................................................................................... 65
6.8.3 Transfer Sequence..................................................................................................................................... 65
6.8.4 Device Status ............................................................................................................................................. 65
6.8.5 Active Status Interrupt ................................................................................................................................ 65
6.8.6 Programming Restrictions .......................................................................................................................... 66
6.8.7 Error Reporting........................................................................................................................................... 66
6.9 Sequential Program Mode (ADh/AFh) ..................................................................................................................... 66
6.9.1 Command Prerequisites............................................................................................................................. 66
6.9.2 Transfer Format ......................................................................................................................................... 67
6.9.3 Transfer Sequence — Initial Transfer ........................................................................................................ 67
6.9.4 Transfer Sequence — Subsequent Transfers............................................................................................ 67
6.9.5 Program Status .......................................................................................................................................... 67
6.9.6 Commands Allowed and Not Allowed in Sequential Program Mode.......................................................... 67
6.9.7 Programming Restrictions .......................................................................................................................... 69
Datasheet
DS-AT25XE161D-158
Revision H
11
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
6.9.8 Error Reporting...........................................................................................................................................
6.10 Dual Output Byte/Page Program (A2h)..................................................................................................................
6.10.1 Command Prerequisites...........................................................................................................................
6.10.2 Transfer Format .......................................................................................................................................
6.10.3 Transfer Sequence...................................................................................................................................
6.10.4 Program Status ........................................................................................................................................
6.10.5 Active Status Interrupt ..............................................................................................................................
6.10.6 Programming Restrictions ........................................................................................................................
6.10.7 Error Reporting.........................................................................................................................................
6.11 Quad Output Page Program (32h) .........................................................................................................................
6.11.1 Command Prerequisites...........................................................................................................................
6.11.2 Transfer Format .......................................................................................................................................
6.11.3 Transfer Sequence...................................................................................................................................
6.11.4 Programming Restrictions ........................................................................................................................
6.11.5 Error Reporting.........................................................................................................................................
6.12 Program/Erase Suspend (75h/B0h) .......................................................................................................................
6.12.1 Transfer Format .......................................................................................................................................
6.12.2 Transfer Sequence...................................................................................................................................
6.12.3 Command Behavior During a Program/Erase Operation .........................................................................
6.12.4 Device Status ...........................................................................................................................................
6.12.5 Programming Restrictions ........................................................................................................................
6.13 Program/Erase Resume (7Ah/D0h) .......................................................................................................................
6.13.1 Command Prerequisites...........................................................................................................................
6.13.2 Transfer Format .......................................................................................................................................
6.13.3 Transfer Sequence...................................................................................................................................
6.13.4 Command Behavior .................................................................................................................................
6.13.5 Programming Restrictions ........................................................................................................................
6.14 Set Burst Wrap (77h) .............................................................................................................................................
6.14.1 Transfer Format .......................................................................................................................................
6.14.2 Transfer Sequence...................................................................................................................................
6.14.3 Wrap Bits..................................................................................................................................................
6.14.4 Programming Restrictions ........................................................................................................................
6.15 Buffer Read (D4h) ..................................................................................................................................................
6.15.1 Transfer Format .......................................................................................................................................
6.15.2 Transfer Sequence...................................................................................................................................
6.16 Buffer Write (84h)...................................................................................................................................................
6.16.1 Command Prerequisites...........................................................................................................................
6.16.2 Transfer Format .......................................................................................................................................
6.16.3 Transfer Sequence...................................................................................................................................
6.16.4 Writing Buffer Entries ...............................................................................................................................
6.16.5 Writing the Buffer Entries to Flash Memory .............................................................................................
6.16.6 Programming Restrictions ........................................................................................................................
6.17 Buffer to Main Memory Page Program without Erase (88h) ..................................................................................
6.17.1 Command Prerequisites...........................................................................................................................
6.17.2 Transfer Format .......................................................................................................................................
6.17.3 Transfer Sequence...................................................................................................................................
6.17.4 Device Status ...........................................................................................................................................
6.17.5 Protected Memory ....................................................................................................................................
6.17.6 Programming Restrictions ........................................................................................................................
6.17.7 Error Reporting.........................................................................................................................................
6.18 Write Enable (06h) .................................................................................................................................................
6.18.1 Transfer Format .......................................................................................................................................
6.18.2 Transfer Sequence...................................................................................................................................
6.18.3 Programming Restrictions ........................................................................................................................
Datasheet
DS-AT25XE161D-158
Revision H
12
69
69
70
70
70
70
70
71
71
71
71
71
72
72
72
72
73
73
73
74
75
75
75
76
76
76
76
76
77
77
78
78
78
78
78
79
79
79
79
79
79
79
80
80
80
80
80
80
80
81
81
81
81
81
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
6.19 Write Disable (04h) ................................................................................................................................................
6.19.1 Transfer Format .......................................................................................................................................
6.19.2 Transfer Sequence...................................................................................................................................
6.19.3 Programming Restrictions ........................................................................................................................
6.20 Volatile Status Register Write Enable (50h)...........................................................................................................
6.20.1 Transfer Format .......................................................................................................................................
6.20.2 Transfer Sequence...................................................................................................................................
6.20.3 Programming Restrictions ........................................................................................................................
6.21 Individual Block Lock (36h) ....................................................................................................................................
6.21.1 Command Prerequisites...........................................................................................................................
6.21.2 Transfer Format .......................................................................................................................................
6.21.3 Transfer Sequence...................................................................................................................................
6.21.4 Programming Restrictions ........................................................................................................................
6.22 Individual Block Unlock (39h).................................................................................................................................
6.22.1 Command Prerequisites...........................................................................................................................
6.22.2 Transfer Format .......................................................................................................................................
6.22.3 Transfer Sequence...................................................................................................................................
6.22.4 Programming Restrictions ........................................................................................................................
6.23 Read Block Lock (3Ch/3Dh) ..................................................................................................................................
6.23.1 Command Prerequisites...........................................................................................................................
6.23.2 Transfer Format .......................................................................................................................................
6.23.3 Transfer Sequence...................................................................................................................................
6.23.4 Programming Restrictions ........................................................................................................................
6.24 Global Block Lock (7Eh) ........................................................................................................................................
6.24.1 Command Prerequisites...........................................................................................................................
6.24.2 Transfer Format .......................................................................................................................................
6.24.3 Transfer Sequence...................................................................................................................................
6.24.4 Programming Restrictions ........................................................................................................................
6.25 Global Block Unlock (98h) .....................................................................................................................................
6.25.1 Command Prerequisites...........................................................................................................................
6.25.2 Transfer Format .......................................................................................................................................
6.25.3 Transfer Sequence...................................................................................................................................
6.25.4 Programming Restrictions ........................................................................................................................
6.26 Program Security Register (9Bh) ...........................................................................................................................
6.26.1 Command Prerequisites...........................................................................................................................
6.26.2 OTP Security Register Layout..................................................................................................................
6.26.3 Transfer Format .......................................................................................................................................
6.26.4 Transfer Sequence...................................................................................................................................
6.26.5 Addressing the OTP Security Registers...................................................................................................
6.26.6 Programming Status ................................................................................................................................
6.26.7 Locking OTP Registers 1 - 3 ....................................................................................................................
6.26.8 Verifying the Locked Status of a Security Register ..................................................................................
6.26.9 Programming Restrictions ........................................................................................................................
6.27 Read OTP Security Register (4Bh) ........................................................................................................................
6.27.1 Transfer Format .......................................................................................................................................
6.27.2 Transfer Sequence — Single Register.....................................................................................................
6.27.3 Transfer Sequence — All Registers .........................................................................................................
6.28 Read Status Registers 1 - 3 (05h, 35h, 15h) .........................................................................................................
6.28.1 Transfer Format .......................................................................................................................................
6.28.2 Transfer Sequence...................................................................................................................................
6.29 Read Status Registers (65h)..................................................................................................................................
6.29.1 Transfer Format .......................................................................................................................................
6.29.2 Transfer Sequence...................................................................................................................................
6.29.3 Reading a Single Status Register ............................................................................................................
6.29.4 Continuous Read of All Status Registers .................................................................................................
6.29.5 Transfer Diagram .....................................................................................................................................
6.29.6 Programming Restrictions ........................................................................................................................
Datasheet
DS-AT25XE161D-158
Revision H
13
82
82
82
82
83
83
83
83
83
83
83
83
84
84
84
84
84
84
85
85
85
85
85
86
86
86
86
86
87
87
87
87
87
88
88
88
88
88
89
89
89
90
90
91
91
91
91
91
91
92
92
92
92
93
93
93
93
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
6.30 Write Status Registers 1 - 3 — Direct (01h, 31h, 11h)........................................................................................... 94
6.30.1 Command Prerequisites........................................................................................................................... 94
6.30.2 Transfer Format ....................................................................................................................................... 94
6.30.3 Transfer Sequence................................................................................................................................... 94
6.30.4 Programming Restrictions ........................................................................................................................ 94
6.31 Write Status Registers — Indirect (71h)................................................................................................................. 95
6.31.1 Command Prerequisites........................................................................................................................... 95
6.31.2 Transfer Format ....................................................................................................................................... 95
6.31.3 Transfer Sequence................................................................................................................................... 95
6.31.4 Writing to a Status Register ..................................................................................................................... 95
6.31.5 Transfer Diagram ..................................................................................................................................... 96
6.31.6 Programming Restrictions ........................................................................................................................ 96
6.32 Status Register Lock (6Fh) .................................................................................................................................... 97
6.32.1 Command Prerequisites........................................................................................................................... 97
6.32.2 Transfer Format ....................................................................................................................................... 97
6.32.3 Transfer Sequence................................................................................................................................... 97
6.32.4 Transfer Diagram ..................................................................................................................................... 97
6.32.5 Programming Restrictions ........................................................................................................................ 97
6.33 Deep Power-Down (B9h) ....................................................................................................................................... 98
6.33.1 Transfer Format ....................................................................................................................................... 98
6.33.2 Transfer Sequence................................................................................................................................... 98
6.33.3 Programming Restrictions ........................................................................................................................ 98
6.34 Resume from Ultra-Deep Power-Down / Deep Power-Down with Device ID (ABh) .............................................. 99
6.34.1 Command Options ................................................................................................................................... 99
6.34.2 Transfer Format — Resume from Deep Power-Down ............................................................................. 99
6.34.3 Transfer Format — Resume from Deep Power-Down and Obtain Device ID .......................................... 99
6.34.4 Transfer Sequence — Resume from Deep Power-Down ........................................................................ 99
6.34.5 Transfer Sequence — Resume from Deep Power-Down and Obtain Device ID ..................................... 99
6.34.6 Transfer Sequence — Resume from Ultra-Deep Power-Down.............................................................. 100
6.34.7 Programming Restrictions ...................................................................................................................... 100
6.35 Ultra-Deep Power-Down (79h)............................................................................................................................. 101
6.35.1 Transfer Format ..................................................................................................................................... 101
6.35.2 Transfer Sequence................................................................................................................................. 101
6.35.3 Programming Restrictions ...................................................................................................................... 101
6.36 Enable Reset (66h) and Reset Device (99h) ....................................................................................................... 102
6.36.1 Transfer Format ..................................................................................................................................... 102
6.36.2 Transfer Sequence................................................................................................................................. 102
6.36.3 Programming Restrictions ...................................................................................................................... 102
6.37 Terminate (F0h) ................................................................................................................................................... 103
6.37.1 Command Prerequisites......................................................................................................................... 103
6.37.2 Transfer Format ..................................................................................................................................... 103
6.37.3 Transfer Sequence................................................................................................................................. 103
6.37.4 Programming Restrictions ...................................................................................................................... 103
6.38 Read Manufacturer/Device ID (90h) .................................................................................................................... 104
6.38.1 Transfer Format ..................................................................................................................................... 104
6.38.2 Transfer Sequence................................................................................................................................. 104
6.39 Quad Read Manufacturer/Device ID (94h) .......................................................................................................... 105
6.39.1 Transfer Format ..................................................................................................................................... 105
6.39.2 Transfer Sequence................................................................................................................................. 105
6.40 Read JEDEC ID (9Fh) ......................................................................................................................................... 105
6.40.1 Transfer Format ..................................................................................................................................... 105
6.40.2 Transfer Sequence................................................................................................................................. 105
6.40.3 Transfer Diagram ................................................................................................................................... 106
6.41 Active Status Interrupt (25h) ................................................................................................................................ 108
6.41.1 Transfer Format ..................................................................................................................................... 108
6.41.2 Transfer Sequence................................................................................................................................. 108
6.41.3 Programming Restrictions ...................................................................................................................... 108
Datasheet
DS-AT25XE161D-158
Revision H
14
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
6.42 Single Command Read-Modify-Write — EEPROM Emulation (0Ah)................................................................... 109
6.42.1 Command Prerequisites......................................................................................................................... 109
6.42.2 Transfer Format ..................................................................................................................................... 109
6.42.3 Transfer Sequence................................................................................................................................. 109
6.42.4 Programming Restrictions ...................................................................................................................... 109
6.42.5 Error Reporting....................................................................................................................................... 109
6.43 Low Battery Detect (EFh)..................................................................................................................................... 110
6.43.1 Transfer Format ..................................................................................................................................... 110
6.43.2 Transfer Sequence................................................................................................................................. 110
6.44 Serial Flash Discoverable Parameters (5Ah) ....................................................................................................... 111
6.44.1 Transfer Format ..................................................................................................................................... 111
6.44.2 Transfer Sequence................................................................................................................................. 111
6.44.3 Programming Restrictions ...................................................................................................................... 111
6.44.4 SFDP Organization ................................................................................................................................ 111
7 Electrical Specifications .................................................................................................................................................. 112
7.1 Absolute Maximum Ratings ................................................................................................................................... 112
7.2 DC and AC Operating Range ................................................................................................................................ 112
7.3 DC Characteristics ................................................................................................................................................. 112
7.4 AC Clock Characteristics ....................................................................................................................................... 113
7.5 AC Characteristics – All Other Parameters............................................................................................................ 113
7.6 Program and Erase Characteristics ....................................................................................................................... 114
7.7 Power-On Timing ................................................................................................................................................... 115
7.8 AC Timing Diagrams .............................................................................................................................................. 116
8 Ordering Information ....................................................................................................................................................... 118
8.1 Ordering Code Detail ........................................................................................................................................... 118
9 Packaging Information ..................................................................................................................................................... 119
9.1 8S1 — JEDEC SOIC ............................................................................................................................................. 120
9.2 8S2 — 8-lead EIAJ SOIC....................................................................................................................................... 121
9.3 8MA3 – 2 x 3 UDFN ............................................................................................................................................... 122
9.4 8-WLCSP — 8-ball 3 x 2 x 3 WLCSP .................................................................................................................... 123
10 Glossary .......................................................................................................................................................................... 124
11 Revision History ............................................................................................................................................................. 125
Datasheet
DS-AT25XE161D-158
Revision H
15
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Figures
Figure 1: Block Diagram.......................................................................................................................................................... 11
Figure 2: Memory Package Types .......................................................................................................................................... 12
Figure 3: SPI Transfer — Command Only .............................................................................................................................. 16
Figure 4: SPI Transfer — Command and Address Only ......................................................................................................... 16
Figure 5: SPI Transfer — Command and Data Only — Read Operation................................................................................ 17
Figure 6: SPI Transfer — Command and Data Only — Write Operation ................................................................................ 17
Figure 7: SPI Transfer — Command, Address, and Data — Read Operation with No Dummy Bytes.................................... 18
Figure 8: SPI Transfer — Command, Address, and Data — Read Operation with Dummy Bytes ......................................... 18
Figure 9: SPI Transfer — Command, Address, and Data — Write Operation ........................................................................ 19
Figure 10: Dual Output Read — 1-pin Command, 1-Pin Address, and 2-Pin Data................................................................. 19
Figure 11: Dual Output Write — 1-pin Command, 1-Pin Address, and 2-Pin Data................................................................. 20
Figure 12: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Read Operation ........................... 20
Figure 13: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Write Operation ........................... 21
Figure 14: Quad I/O Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Read Operation ................................. 22
Figure 15: XiP Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Initial Read (M[5:4] = 2’b10) ....................... 23
Figure 16: XiP Transfer — No Command, 4-Pin Address, and 4-Pin Data — Subsequent Reads (M[5:4] = 2’b10) .............. 24
Figure 17: XiP Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Write Operation .......................................... 25
Figure 18: Flow Diagram of Nested Operations Example ....................................................................................................... 35
Figure 19: Issuing a Terminate Command Before the Suspend Command has Completed .................................................. 38
Figure 20: Allowing Enough Time for the Suspend Operation to Complete............................................................................ 38
Figure 21: OTP Security Register Program and Lock ............................................................................................................. 39
Figure 22: JEDEC Standard Hardware Reset......................................................................................................................... 40
Figure 23: AT25XE161D Register Structure ........................................................................................................................... 43
Figure 24: Status Register Read Operation Showing 8-bit Address Field .............................................................................. 93
Figure 25: Status Register Write Operation Showing 8-bit Address Field............................................................................... 96
Figure 26: Status Register Lock Operation with Two Verification Bytes ................................................................................. 97
Figure 27: Entering Deep Power-Down State ......................................................................................................................... 98
Figure 28: Resume from Deep Power-Down or Ultra-Deep Power-Down ............................................................................ 100
Figure 29: Entering Ultra-Deep Power-Down State .............................................................................................................. 101
Figure 30: Enable Reset and Reset Command Sequence (SPI Mode) ................................................................................ 102
Figure 31: Read JEDEC ID ................................................................................................................................................... 107
Figure 32: Active Status Interrupt.......................................................................................................................................... 108
Figure 33: AC Timing During Device Power Up .................................................................................................................... 115
Figure 34: AC Power-On Timing After a Brown-Out ............................................................................................................. 116
Figure 35: Serial Input Timing ............................................................................................................................................... 116
Figure 36: Serial Output Timing ............................................................................................................................................ 116
Figure 37: WP Timing for Write Status Register Command.................................................................................................. 117
Figure 38: HOLD Timing – Serial Input ................................................................................................................................. 117
Figure 39: HOLD Timing – Serial Output .............................................................................................................................. 117
Datasheet
DS-AT25XE161D-158
Revision H
10
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Tables
Table 1: Pin Descriptions .........................................................................................................................................................13
Table 2: Bus Transfer Types ....................................................................................................................................................15
Table 3: Device Block Memory Map — Block Erase Address Ranges ....................................................................................26
Table 4: AT25XE161D Device Block Memory Map — Page Erase and Page Program ..........................................................27
Table 5: AT25XE161D Device Block Protection Map — CMPRT = 0, WPS = 0......................................................................29
Table 6: AT25XE161D Device Block Protection Map — CMPRT = 1, WPS = 0......................................................................30
Table 7: Entering DPD or UDPD Mode ....................................................................................................................................32
Table 8: Exiting DPD or UDPD Mode.......................................................................................................................................32
Table 9: Resetting the Device During a Program or Erase Operation .....................................................................................34
Table 10: Encoding of Erase/Program Suspend Operations ...................................................................................................34
Table 11: Command Errors and Their Effect on the EE and PE Bits .......................................................................................36
Table 12: Indirect Addressing of Status Registers ...................................................................................................................44
Table 13: Status Register 1 Format .........................................................................................................................................45
Table 14: Status Register 2 Format .........................................................................................................................................46
Table 15: Status Register Protection During Normal Operation...............................................................................................47
Table 16: Status Register Protection During Reset..................................................................................................................47
Table 17: Status Register 3 Format .........................................................................................................................................48
Table 18: Status Register 4 Format .........................................................................................................................................49
Table 19: Status Register 5 Format .........................................................................................................................................50
Table 20: Status Register 6 Format .........................................................................................................................................51
Table 21: Command Listing .....................................................................................................................................................52
Table 22: Frequency and Number of Dummy Clocks Based on Command Type in Non-Wrap Mode (default) ......................60
Table 23: Frequency and Number of Dummy Clocks Based on Command Type in Wrap Mode (77h)...................................61
Table 24: Command Behavior During Sequential Programming Mode ...................................................................................68
Table 25: Command Behavior During Program/Erase or Program/Erase Suspend Operations..............................................73
Table 26: Encoding of Burst Wrap Bits ....................................................................................................................................78
Table 27: OTP Security Register 0 Bit Assignments................................................................................................................88
Table 28: OTP Security Register 1 Bit Assignments................................................................................................................88
Table 29: OTP Security Register 2 Bit Assignments................................................................................................................88
Table 30: OTP Security Register 3 Bit Assignments................................................................................................................88
Table 31: OTP Register Access Map .......................................................................................................................................89
Table 32: Indirect Addressing of the Status Registers .............................................................................................................92
Table 33: Indirect Status Register Read Sequence .................................................................................................................93
Table 34: Indirect Addressing of the Status Registers .............................................................................................................95
Table 35: Indirect Status Register Write Sequence .................................................................................................................96
Table 36: Options for Exiting DPD and UDPD Modes .............................................................................................................99
Table 37: Manufacturer and Device ID Details.......................................................................................................................106
Table 38: Device ID Part 4 Variants — EDI String Value.......................................................................................................106
Table 39: Power On Timing Requirements ............................................................................................................................115
Table 40: Valid Ordering Code Table.....................................................................................................................................118
Datasheet
DS-AT25XE161D-158
Revision H
10
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
1
Product Overview
The AT25XE161D is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer and
connected applications. It is optimized for low-energy applications and can be operated using modern Lithium battery technologies
over a wide input voltage range of 1.65 V - 3.6 V.
The AT25XE161D is ideally suited for systems in which program code is shadowed from Flash memory into embedded or external
RAM (code shadow) for execution, and where small amounts of data are stored and updated locally in the Flash memory.
The erase block sizes of the AT25XE161D have been optimized to meet the needs of today's code and data storage applications.
The device supports 256-byte page erase, as well as 4 kiloByte (kB), 32 kB, and 64 kB block erase operations and a full-chip
erase. By optimizing the size of the erase blocks, the memory space can be used much more efficiently.
The device also includes an active interrupt allowing the host to sleep during lengthy programming or erase operations, allowing
the memory device to wake the MCU when completed, and optimized energy consumption and class-leading 7nA ultra-deep
power-down modes. The device contains four specialized 128-byte One-Time Programmable (OTP) security registers that can
be used to store a unique device ID and locked key storage.
Specifically designed for use in a wide variety of systems, the AT25XE161D supports read, program, and erase operations. No
separate voltage is required for programming and erasing.
Throughout this document, the term Multi-I/O is used generically to refer to all of the multiple I/O modes, including dual, quad,
and XiP.
Datasheet
DS-AT25XE161D-158
Revision H
10
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
2
Block Diagram
Figure 1 shows a block diagram of the AT25XE161D device. The Interface Control Logic block connects to external device through
a set of pins. The state of these pins is distributed Interface Control Logic block to other blocks as necessary. The design also
contains a 16 Mbit serial Flash memory array, a 256-byte SRAM buffer, and an I/O Interface Unit that operates depending on the
type of data transfer mode.
Serial Flash Memory Array
CS
256-byte SRAM Buffer
SCK
SI (I/O0)
SO (I/O1)
Interface
Control Logic
WP (I/O2)
SPI
HOLD/RESET (I/O3)
Dual
Quad
Figure 1: Block Diagram
Datasheet
DS-AT25XE161D-158
Revision H
11
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
3
Package Pinouts
Figure 2 show the package pinouts for the following devices. Note that the Die Wafer Scale option is not shown.
CS
1
8
VCC
HOLD/RESET (I/O3)
SO (I/O1)
2
7
HOLD/RESET (I/O3)
6
SCK
WP (I/O2)
3
6
SCK
5
SI (I/O0)
GND
4
5
SI (I/O0)
CS
1
8
VCC
SO (I/O1)
2
7
WP (I/O2)
3
GND
4
8S1 8-lead SOIC Package (0.150”)
8MA3 8-pad Ultra-Thin DFN Package
8S2 8-lead EIAJ SOIC Package (0.208”)
2 x 3 x 0.6 mm (Top View)
(Top View)
VCC
CS
A3
GND
A1
SO
B2
HOLD
C3
SI
C1
WP
D2
SCK
E3
E1
8-ball WLCSP Package
3 x 2 x 3 ball matrix (bottom view)
Figure 2: Memory Package Types
Datasheet
DS-AT25XE161D-158
Revision H
12
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 1: Pin Descriptions
Asserted
State
Type
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is
deasserted, the device is be deselected and normally be placed in standby mode
(not Deep Power-Down mode), and the SO pin is in a high-impedance state. When
the device is deselected, data are not accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a lowto-high transition is required to end an operation. When ending an internally selftimed operation such as a program or erase cycle, the device does not enter the
standby mode until the completion of the operation.
Low
Input
SCK
SERIAL CLOCK: This pin provides a clock to the device and controls the flow of
data to and from the device. Command, address, and input data present on the
SI pin is always latched in on the rising edge of SCK, while output data on the SO
pin is always clocked out on the falling edge of SCK.
-
Input
SI (I/O0)
SERIAL INPUT: The SI pin shifts data into the device. The SI pin is used for all
data input including command and address sequences. Data on the SI pin is
always latched in on the rising edge of SCK.
With the Multi I/O Read commands, the SI pin becomes an output pin (I/O0) in
conjunction with other pins to allow either two or four bits of data on (I/O1:0 or
I/O3:0) to be clocked out on every falling edge of SCK.
Data present on the SI pin is ignored whenever the device is deselected (CS is
deasserted and the device is in the reset condition).
-
Input/
Output
SO (I/O1)
SERIAL OUTPUT: The SO pin shifts data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Multi I/O Read commands, the SO pin remains an output pin (I/O1) in
conjunction with other pins to allow either two or four bits of data on (I/O1:0 or
I/O3:0) to be clocked out on every falling edge of SCK.
The SO pin is in a high-impedance state whenever the device is deselected (CS
is deasserted and the device is in the reset condition).
-
Input/
Output
WP (I/O2)
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. When set, this bit prevents the Status Register from being written. This bit is
used in conjunction with other Status Register bits (CMPRT, BPSIZE, TB, and
BP[2:0]) to provide hardware protection of the memory array.
The WP pin is internally pulled-high and can be left floating if hardware controlled
protection is not used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible.
When the QE bit in Status Register 2 is set, enabling quad mode (Output or I/O),
the WP pin becomes bidirectional and functions as the IO2 pin used to transmit
address and/or data, depending on the transfer mode.
Low
Input/
Output
Symbol
Name and Function
Datasheet
DS-AT25XE161D-158
Revision H
13
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 1: Pin Descriptions (Continued)
Asserted
State
Type
HOLD /
RESET
(I/O3)
HOLD / RESET: The HOLD pin temporarily pauses serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions
on the SCK pin and data on the SI pin are ignored and the SO pin is placed in a
high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order
for a Hold condition to start. A Hold condition pauses serial communication only
and does not have an effect on internally self-timed operations such as a program
or erase cycle.
With the Quad Output Byte/Page Program command, the HOLD pin becomes an
input pin (I/O3) and, along with other pins, allows four bits (on I/O3-0) of data to be
clocked in on every rising edge of SCK. With the Quad-Output Read commands,
the HOLD Pin becomes an output pin (I/O3) in conjunction with other pins to allow
four bits of data on (I/O33-0) to be clocked in on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin is referenced as the HOLD pin unless specifically addressing the Quad Output mode in
which case it is referenced as I/O3.
The HOLD pin is internally pulled-high and can be left floating if the Hold function
is not used. However, it is recommended that the HOLD pin also be externally
connected to VCC whenever possible.
When the QE bit in the Status register is cleared, the IO3 pin can be configured
either as a HOLD pin or as a RESET pin depending on the state of the HOLD/
RESET bit 7 in Status Register 3. Note that when the QE bit is set, the HOLD or
RESET function is not available because this pin transfers data.
Low
Input/
Output
VCC
DEVICE POWER SUPPLY: The VCC pin supplies the source voltage to the device.
Operations at invalid VCC voltages can produce spurious results; do not attempt
this.
-
Power
GND
GROUND: The ground reference for the power supply. Connect GND to the system ground.
-
Power
Symbol
Name and Function
Datasheet
DS-AT25XE161D-158
Revision H
14
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4
Device Operation
This section describes the various data transfer modes supported by the device, as well as other system operations.
4.1 DATA TRANSFER MODES
The JEDEC specification uses a numerical system to indicate the type of transfer for a given command. The nomenclature for
this system is defined as (x-y-z) to indicate the number of active pins used for the command (x), address (y), and data (z). For an
example, a designation of 1-1-2 indicates that one pin (SI) transfers the command, one pin (SI) is for the address, and two pins
(SI and SO) are for data. The AT25XE161D supports the following transfer types.
Table 2: Bus Transfer Types
Transfer
Type
Transfer
Name
Command
Pin(s) Used for
Command
Address
Pin(s) Used for
Address
Data
Pin(s) Used for
Data
1-0-0
SPI
Yes
SI
No
--
No
--
1-1-0
SPI
Yes
SI
Yes
SI
No
--
1-0-1
SPI
Yes
SI
No
--
Yes
SI (write)
SO (read)
1-1-1
SPI
Yes
SI
Yes
SI
Yes
SI (write)
SO (read)
1-1-2
Dual Output
Yes
SI
Yes
SI
Yes
SI, SO
1-1-4
Quad Output
Yes
SI
Yes
SI
Yes
SI, SO, WP, HOLD
1-4-4
Quad I/O
Yes
SI
Yes
SI, SO, WP, HOLD
Yes
SI, SO, WP, HOLD
0-4-4
XiP
No
--
Yes
SI, SO, WP, HOLD
Yes
SI, SO, WP, HOLD
As shown in the table above, the AT25XE161D supports the following transfer formats, which are described in the following
subsections.
Standard SPI Operation
Dual Output Operation
Quad Output Operation
Quad I/O Operation
XiP Operation
4.2 STANDARD SPI OPERATION
Standard SPI transfers are divided into three elements; command, address, and data. SPI mode support the following four transfer
types, as described in Table 2.
Command only, no address or data (1-0-0)
Command and address only, no data (1-1-0)
Command and data only, no address (1-0-1)
Command, address, and data (1-1-1)
For standard SPI transfers, command and address are always transferred on the SI pin. For write operations, data is also
transferred on the SI pin. For read operations, data is transferred on the SO pin.
The AT25XE161D supports the two most common SPI modes, 0 and 3, meaning that data is always latched on the rising edge
of SCK and always output on the falling edge of SCK.
Datasheet
DS-AT25XE161D-158
Revision H
15
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.2.1 Command Only, No Address or Data (1-0-0)
The following diagram shows a command-only transfer. In this type of transfer no address or data are required. An example is
the Chip Erase (60h/C7h) command. A 1-0-0 transfer type is shown in Figure 3.
&6
6&.
&200$1'
6,
&
&
&
&
&
&
&
&
06%
+,*+,03('$1&(
62
Figure 3: SPI Transfer — Command Only
4.2.2 Command and Address Only, No Data (1-1-0)
The following diagram shows a transfer with command and address only. In this type of transfer no data is required. An example
is the Block Erase (20h) command, where the address indicates the location of the block to be erased.
The 1-1-0 transfer type is shown in Figure 4.
&6
6&.
&200$1'
6,
&
&
&
&
&
&
06%
62
$''5(66%,76$$
&
&
$
$
$
$
$
$
$
$
$
$
$
$
06%
+,*+,03('$1&(
Figure 4: SPI Transfer — Command and Address Only
Datasheet
DS-AT25XE161D-158
Revision H
16
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.2.3 Command and Data Only, No Address (1-0-1)
The following diagram shows a transfer with command and data only. In this type of transfer no address is required. An example
is the Status Register Read (05h/35h/15h) and Status Register Write (01h/31h/11h) commands, where the command itself indicates the location of the register. The 1-0-1 transfer type for a read operation is shown in Figure 5.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
COMMAND
SI
C
C
C
C
C
C
C
C
MSB
DATA OUT 1
SO
HIGH-IMPEDANCE
D
D
D
D
D
DATA OUT 1
D
D
D
MSB
D
D
D
D
D
D
MSB
D
D
D
D
MSB
Figure 5: SPI Transfer — Command and Data Only — Read Operation
The 1-0-1 transfer type for a write operation is shown in Figure 6.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
COMMAND
SI
C
C
C
C
C
C
DATA IN
C
MSB
SO
C
D
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
Figure 6: SPI Transfer — Command and Data Only — Write Operation
Datasheet
DS-AT25XE161D-158
Revision H
17
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.2.4 Command, Address, and Data (1-1-1)
The following diagram shows a command, address, and data transfer. In this type of transfer the command and address are
followed by one or more data types, depending on the command type.
Note that this type of transfer can contain one or more dummy bytes between the end of the address and the beginning of the
data output depending on the type of command. See Table 21 for more information.
The 1-1-1 transfer type for a read operation without dummy bytes is shown in Figure 7. An example is the Read Array (03h)
command.
&6
6&.
&200$1'
6,
&
&
&
&
&
&
$''5(66%,76$$
&
&
06%
$
$
$
$
$
$
$
$
$
06%
'$7$287
+,*+,03('$1&(
62
'
'
'
'
'
'
'
'
06%
'
'
06%
Figure 7: SPI Transfer — Command, Address, and Data — Read Operation with No Dummy Bytes
The 1-1-1 transfer type for a read operation with dummy bytes is shown in Figure 8. An example is the Fast Read Array (0Bh)
command. Note that eight dummy clocks are shown in the figure below for illustration purposes only. More than eight clocks may
be required, depending on the type of operation and operating frequency.
&6
6&.
&200$1'
6,
&
&
&
&
&
&
06%
$''5(66%,76$$
&
&
$
$
$
$
$
$
$
'800<
$
$
06%
;
;
;
;
;
;
;
;
06%
'$7$287
62
+,*+,03('$1&(
'
'
'
'
'
'
'
'
06%
'
'
06%
Figure 8: SPI Transfer — Command, Address, and Data — Read Operation with Dummy Bytes
The 1-1-1 transfer type for a write operation is shown in Figure 9. An example is the Byte/Page Program (02h) command.
Datasheet
DS-AT25XE161D-158
Revision H
18
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
&6
6&.
&200$1'
6,
&
&
&
&
&
$''5(66%,76$$
&
&
&
06%
$
$
$
$
$
$
$
'$7$,1
$
$
06%
'
'
'
'
'
'
'
'
06%
+,*+,03('$1&(
62
Figure 9: SPI Transfer — Command, Address, and Data — Write Operation
4.3 DUAL OUTPUT OPERATION (1-1-2)
The AT25XE161D supports the Dual Output (1-1-2) transfer type which enhances overall throughput over the standard SPI mode.
This mode transfer command and address on the SI pin like in SPI mode, but the data is transferred on to the SI and SO pins.
This means that only half the number of clocks are required to transfer the data.
A Dual Output read operation is shown in Figure 10. An example of this operation is a Dual Output Read (3Bh). Note that this
type of transfer can contain one or more dummy bytes between the end of the address and the beginning of the data output
depending on the type of command and the operating frequency. See Table 21 for more information.
A Dual Output 1-1-2 read operation is shown in Figure 10.
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
D D D D๚
D D D D๚ D D
MSB
D D D D๛ D D D D๛ D D
Figure 10: Dual Output Read — 1-pin Command, 1-Pin Address, and 2-Pin Data
Datasheet
DS-AT25XE161D-158
Revision H
19
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
A Dual Output (1-1-2) write operation is shown in Figure 11. An example of this operation is a Dual Output Byte/Page Program
(A2h).
"
!
!
" !
Figure 11: Dual Output Write — 1-pin Command, 1-Pin Address, and 2-Pin Data
4.4 QUAD OUTPUT OPERATION (1-1-4)
The AT25XE161D supports the Quad Output mode which enhances overall throughput over the standard SPI and dual operation
modes by increasing the data transfer rate. In this mode, data is transferred on four pins; SI, SO, WP, and HOLD. This means
that only 1/4th the number of clocks are required to transfer the data relative to standard SPI mode. This is known as a 1-1-4
transfer which is defined as follows:
1-pin command, 1-pin address, and 4-pin data (1-1-4)
In Quad Output mode the command (C) and address (A) are driven to the memory device on the SI (IO0) pin. During write
operations, the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to inputs and the data is driven on all four pins,
allowing four data bits to be transferred on every clock. During read operations, once the command and address are transferred
on the SI (IO0) pin, the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins switched to outputs and the data is driven on all four
pins, allowing four data bits to be transferred on every clock.
A 1-1-4 Quad Output read operation is shown in Figure 12. An example of this operation is a Quad Output Read (6Bh). Note that
this type of transfer can contain one or more dummy bytes between the end of the address and the beginning of the data output
depending on the type of command and the operating frequency. See Table 21 for more information.
CS
0
1
2
3
4
5
6
7
8
9
10 1 1 1 2
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
COMMAND
I/O0
C
C
C
C
C
C
Address Bits A23-A0
C
C
A
A
A
A
A
A
A
DATA
OUT 1
DUMMY
A
A
X
X
X
X
X
X
X
X
DATA
OUT 2
DATA
OUT 3
DATA
OUT 4
DATA
OUT 5
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
(SI)
High-Impedance
I/O1
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
(SO)
High-Impedance
I/O2
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
(WP)
High-Impedance
I/O3
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
MSB
(HOLD)
MSB
MSB
MSB
MSB
Figure 12: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Read Operation
Datasheet
DS-AT25XE161D-158
Revision H
20
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
A 1-1-4 Quad Output write operation is shown in Figure 13. An example of this operation is a Quad Output Byte/Page Program
(32h).
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41
SCK
COMMAND
I/O0
C
C
C
C
C
C
DATA
IN 1
Address Bits A23-A0
C
C
A
A
A
A
A
A
A
A
A
DATA
IN 2
DATA
IN 3
DATA
IN 4
DATA
IN 5
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
(SI)
I/O1
High-Impedance
D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
(SO)
I/O2
High-Impedance
D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
(WP)
I/O3
High-Impedance
D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
MSB
(HOLD)
MSB
MSB
MSB
MSB
Figure 13: Quad Output Transfer — 1-Pin Command, 1-Pin Address, and 4-Pin Data — Write Operation
Datasheet
DS-AT25XE161D-158
Revision H
21
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.5 QUAD I/O OPERATION (1-4-4)
The AT25XE161D supports the Quad I/O mode which enhances overall throughput over the standard SPI and dual operation
modes by increasing the data transfer rate. In this mode, address and data are transferred on four pins; SI, SO, WP, and HOLD.
This means that only 1/4th the number of clocks are required to transfer the address and data relative to standard SPI mode. This
is known as a 1-4-4 transfer which is defined as follows: 1-pin command, 4-pin address, and 4-pin data (1-4-4).
In Quad I/O mode the command (C) is driven to the memory device on the SI (IO0) pin. During write operations, the SI (IO0), SO
(IO1), WP (IO2), and HOLD (IO3) pins switched to inputs and the address and data are driven on all four pins, allowing four bits
to be transferred on every clock. During read operations, once the command is transferred on the SI (IO0) pin, address is
transferred on the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins, allowing a 24-bit address to be transferred in only six clocks.
Once the address transfer is complete, these pins are switched to outputs and the data is driven on all four pins, allowing four
data bits to be transferred on every clock. Note that mode bits M[7:0] must not be in high-Z (tri-state) mode. For optimal performance it is recommended to drive a value of 55h or FFh on these bits when not in XiP mode.
A 1-4-4 Quad I/O read operation is shown in Figure 14. An example of this operation is a Manufacturer/Device ID Read (94h).
Note that this type of transfer can contain one or more dummy bytes between the end of the address and the beginning of the
data output depending on the type of command and the operating frequency. See Table 21 for more information.
Command
High-Impedance
High-Impedance
High-Impedance
Figure 14: Quad I/O Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Read Operation
Datasheet
DS-AT25XE161D-158
Revision H
22
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.6 XIP MODE OPERATION
The XiP mode is similar to the Quad I/O mode in that both the address and data are transferred on all four pins, SI (IO0), SO
(IO1), WP (IO2), and HOLD (IO3). Using all four pins to transfer address and data allows XiP mode to reduce the overall number
of clocks required to complete the operation, thereby streamlining code execution.
The XiP mode is enabled by setting bit 2 (QE) of status register 1, and bit 3 (XiP) of status register 4. The QE bit enables Quad
I/O mode, allowing address and data to be transferred on all four pins. Setting the XiP bit enables continuous read mode, allowing
subsequent transfers to occur without driving the command each time. Continuous read mode is controlled by mode bits M[5:4]
as explained below. Therefore, the initial EBh or E7h command requires the command to be driven, but for subsequent transfers
the command is not required.
The XiP mode is only used for the following commands:
EBh: XiP mode initial read (1-4-4)
EBh: XiP mode subsequent reads (0-4-4)
E7h: XiP mode initial read with Doubleword Aligned (DWA) address (1-4-4)
E7h: XiP mode subsequent reads with DWA address (0-4-4)
As shown above, the only difference between the EBh and E7h commands is that the E7h command is performed only on a
double-word-aligned address boundary. The EBh command does not have this restriction. Note that mode bits M[7:0] must not
be in high-Z (tri-state) mode. For optimal performance it is recommended to drive a value of 55h or FFh on these bits when not
in XiP mode.
The Set Burst with Wrap (77h) command does not access the memory directly, but rather is used in conjunction with the EBh and
E7h commands to select 8-, 16-, 32-, or 64-Byte sections within a 256-byte page. The user selects the size by programming the
wrap bits as part of the 77h command. See the table in Section 6.14, Set Burst Wrap (77h) for more information.
When the EBh/E7h command is driven onto the bus, the associated data immediately following the address contains eight mode
bits, known as M[7:0]. Of these bits, M[5:4] are decoded and used by hardware to determine if the device is in XiP continuous
read mode. If the value on M[5:4] equals 2’b10, the device is placed into XiP mode to allow for continuous read operations to
occur, meaning that for subsequent operations the command field is not required. Each time a subsequent transfer is made, it
contains only the address and mode bits.
4.6.1 Initial Transfer and XiP Mode Detection (M[5:4])
The initial XiP transfer follows the 1-4-4 format, where the EBh or E7h command is transferred on the SI (IO0) pin, and address
and data are transferred on the SI (IO0), SO (IO1), WP (IO2), and HOLD (IO3) pins. Because all four pins are used, the address
requires only six clocks to transfer. The initial 1-4-4 XiP mode transfer is shown in Figure 15.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
COMMAND
I/O0
A23-A16 A15-A8
A7-A0
M7-M0
DUMMY
DATA
OUT 1
DATA
OUT 2
C A20 A16 A12 A8 A4 A0 M4 M0
D 4 D0 D4 D0
I/O1
A21 A17 A13 A9 A5 A1 M5 M1
D5 D1 D5 D1
I/O2
A22 A18 A14 A10 A6 A2 M6 M2
D6 D2 D6 D 2
A23 A19 A15 A11 A7 A3 M7 M3
D7 D3 D7 D3
(SI)
C
C
C
C
C
C
C
MSB
(SO)
(WP)
I/O3
(HOLD)
Figure 15: XiP Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Initial Read (M[5:4] = 2’b10)
Datasheet
DS-AT25XE161D-158
Revision H
23
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.6.2 Subsequent Transfers
Once XiP mode is detected, subsequent operations do not require the command to be transferred. After the data stream starts,
the user can deassert the CS pin. Once CS is deasserted, data output is suspended. Once CS is again driven low, only the address
and M[7:0] mode data are required because the device is already in XiP mode. Each time a new operation is transferred on the
bus, hardware decodes the M[7:0] bits. As long as M[5:4] have a value of 2’b10, the device is in XiP mode and it is not necessary
to transfer the command. Once M[5:4] ≠ 2’b10 (any value other than 2’b10), the operation completes and the device exits XiP
mode.
A subsequent 0-4-4 XiP mode transfer is shown in Figure 16.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
SCK
A23-A16 A15-A8
I/O 0
A7-A0
M7-M0
DUMMY
DATA
OUT 1
DATA
OUT 2
A20 A16 A12 A8 A4 A0 M4 M0
D 4 D0 D4 D0
I/O 1
A21 A17 A13 A9 A5 A1 M5 M1
D5 D1 D5 D1
I/O 2
A22 A18 A14 A10 A6 A2 M6 M2
D6 D2 D6 D 2
A23 A19 A15 A11 A7 A3 M7 M3
D7 D3 D7 D3
(SI)
(SO)
(WP)
I/O 3
(HOLD)
Figure 16: XiP Transfer — No Command, 4-Pin Address, and 4-Pin Data — Subsequent Reads (M[5:4] = 2’b10)
Datasheet
DS-AT25XE161D-158
Revision H
24
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.6.3 Set Burst with Wrap
As mentioned above, the Set Burst with Wrap (77h) command is used in conjunction with the EBh and E7h commands to select
specific sections within a 256-byte page. When this command is transferred, the data field contains 8 wrap bits. Bits 6:4 of this
field determine the wrap length, which can be between 8 and 64 bytes. See Section 6.14, Set Burst Wrap (77h) for more
information.
Note that when the device receives the EBh/E7h command with M[5:4] = 2’b10, then the device enters XiP mode. While in the
XiP (0-4-4) mode (see Subsequent Transfers subsection above) the only command that the device can execute are EBh (or E7h).
This is mandatory since the command field for subsequent transfers does not exist.
During normal operation, the user sends the 77h command before entering XiP mode. If the user wants to issue a 77h command
after XiP mode has been entered (to change the wrap length/properties), they must exit the XiP mode by sending a 0-4-4
command with M[5:4] ≠ 2’b10). This exits XiP mode. Then the user can issue the 77h command.
The 77h command is a 1-4-4 XiP mode transfer as shown in Figure 17.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
DON’T
CARE
COMMAND
I/O0
DON’T
CARE
DON”T
CARE
WRAP
BIT
X
X
X
X
X
X W4 X
I/O1
X
X
X
X
X
X W5 X
I/O2
X
X
X
X
X
X W6 X
X
X
X
X
X
X
(SI)
C
C
C
C
C
C
C
C
MSB
(SO)
(WP)
I/O3
(HOLD)
X
X
Figure 17: XiP Transfer — 1-Pin Command, 4-Pin Address, and 4-Pin Data — Write Operation
See Section 6.14, Set Burst Wrap (77h) for more information.
4.7 MEMORY ARCHITECTURE
The memory array of the AT25XE161D memory array is divided into three levels of granularity comprising of blocks and pages;
64 kB blocks
32 kB blocks
4 kB blocks
256 byte pages
The size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to
reside in their own erase regions.
details each level and the number of pages per block. The program operations to the memory array can be done at the full
page level or at the byte level (a variable number of bytes). Erase operations can be performed at the chip, block, or page level.
Table 3
Datasheet
DS-AT25XE161D-158
Revision H
25
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 3: Device Block Memory Map — Block Erase Address Ranges
64 kB Block Erase (D8h)
32 kB Block Erase (52h)
4 kB Block Erase (20h)
4 kB (B511) 1
32 kB
(block 63)
64 kB
(block 31)
32 kB
(block 62)
64 kB (block 30)
to
64 kB (block 1)
32 kB (block 61)
to
32 kB (block 2)
32 kB
(block 1)
64 kB
(block 0
32 kB
(block 0)
Block Address Range
1FF000h - 1FFFFFh
4 kB (B510)
1FE000h - 1FEFFFh
4 kB (B509)
1FD000h - 1FDFFFh
4 kB (B508)
1FC000h - 1FCFFFh
4 kB (B507)
1FB000h - 1FBFFFh
4 kB (B506)
1FA000h - 1FAFFFh
4 kB (B505)
1F9000h - 1F9FFFh
4 kB (B504)
1F8000h - 1F8FFFh
4 kB (B503)
1F7000h - 1F7FFFh
4 kB (B502)
1F6000h - 1F6FFFh
4 kB (B501)
1F5000h - 1F5FFFh
4 kB (B500)
1F4000h - 1F4FFFh
4 kB (B499)
1F3000h - 1F3FFFh
4 kB (B498)
1F2000h - 1F2FFFh
4 kB (B497)
1F1000h - 1F1FFFh
4 kB (B496)
4 kB (B495)
to
4 kB (B16)
4 kB (B15)
1F0000h - 1F0FFFh
to
010000h - 010FFFh
00F000h - 00FFFFh
4 kB (B14)
00E000h - 00EFFFh
4 kB (B13)
00D000h - 00DFFFh
4 kB (B12)
00C000h - 00CFFFh
4 kB (B11)
00B000h - 00BFFFh
4 kB (B10)
00A000h - 00AFFFh
4 kB (B9)
009000h - 009FFFh
4 kB (B8)
008000h - 008FFFh
4 kB (B7)
007000h - 007FFFh
4 kB (B6)
006000h - 006FFFh
4 kB (B5)
005000h - 005FFFh
4 kB (B4)
004000h - 004FFFh
4 kB (B3)
003000h - 003FFFh
4 kB (B2)
002000h - 002FFFh
4 kB (B1)
001000h - 001FFFh
4 kB (B0)
000000h - 000FFFh
1EF000h - 1EFFFFh
1. B = block.
Datasheet
DS-AT25XE161D-158
Revision H
26
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
shows how one 4 kB block maps to sixteen 256 byte pages. The very top and bottom 4 Kbyte blocks of the address space
are shown.
Table 4
Table 4: AT25XE161D Device Block Memory Map — Page Erase and Page Program
4 kB Blocks
4 kB (B511) 1
256 Byte Page Erase
256 Bytes
1 - 256 Byte Page Program
1FFF00h - 1FFFFFh
4 kB (B510)
256 Bytes
1FFE00h - 1FFEFFh
4 kB (B509)
256 Bytes
1FFD00h - 1FFDFFh
4 kB (B508)
256 Bytes
1FFC00h - 1FFCFFh
4 kB (B507)
256 Bytes
1FFB00h - 1FFBFFh
4 kB (B506)
256 Bytes
1FFA00h - 1FFAFFh
4 kB (B505)
256 Bytes
1FF900h - 1FF9FFh
4 kB (B504)
256 Bytes
1FF800h - 1FF8FFh
4 kB (B503)
256 Bytes
1FF700h - 1FF7FFh
4 kB (B502)
256 Bytes
1FF600h - 1FF6FFh
4 kB (B501)
256 Bytes
1FF500h - 1FF5FFh
4 kB (B500)
256 Bytes
1FF400h - 1FF4FFh
4 kB (B499)
256 Bytes
1FF300h - 1FF3FFh
4 kB (B498)
256 Bytes
1FF200h - 1FF2FFh
4 kB (B497)
256 Bytes
1FF100h - 1FF1FFh
256 Bytes
.
.
.
256 Bytes
1FF000h - 1FF0FFh
.
.
.
000F00h - 000FFFh
4 kB (B14)
256 Bytes
000E00h - 000EFFh
4 kB (B13)
256 Bytes
000D00h - 000DFFh
4 kB (B12)
256 Bytes
000C00h - 000CFFh
4 kB (B11)
256 Bytes
000B00h - 000BFFh
4 kB (B10)
256 Bytes
000A00h - 000AFFh
4 kB (B9)
256 Bytes
000900h - 0009FFh
4 kB (B8)
256 Bytes
000800h - 0008FFh
4 kB (B7)
256 Bytes
000700h - 0007FFh
4 kB (B6)
256 Bytes
000600h - 0006FFh
4 kB (B5)
256 Bytes
000500h - 0005FFh
4 kB (B4)
256 Bytes
000400h - 0004FFh
4 kB (B3)
256 Bytes
000300h - 0003FFh
4 kB (B2)
256 Bytes
000200h - 0002FFh
4 kB (B1)
256 Bytes
000100h - 0001FFh
4 kB (B0)
256 Bytes
000000h - 0000FFh
4 kB (B496)
4kB (B494)
to
4kB (B16)
4 kB (B15)
.
.
.
1. B = Block
Datasheet
DS-AT25XE161D-158
Revision H
27
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.8 MEMORY PROTECTION
The AT25XE161D device incorporates a robust memory protection scheme that allows memory locations to be protected down
to the 4 kB block level. The device provides the ability to globally lock all blocks in one operation, or to lock individual blocks on
a per-block basis.
4.8.1 Standard Memory Protection
The standard memory protection scheme is invoked by clearing bit 2 (WPS) of Status register 3. When this bit is cleared, the
AT25XE161D uses a combination of the following register fields to set the memory protection scheme:
CMPRT: When this bit is set, unprotected areas of memory become protected, and protected areas of memory become
unprotected. For example, when CMPRT = 0, a top 64 kB block can be protected while the rest of the array is not; when
CMP = 1, the same 64 kB block becomes unprotected while the rest of the array becomes read-only. See bit 6 of Section
5.4, Status Register 2 for more information.
BPSIZE: This bit works in conjunction with bits 4:2 (BP[2:0]) in Status register 1 to determine the size of the blocks to be
protected. Block sizes of 4 kB and 64 kB can be protected depending on the state of this bit. See bit 6 of Section 5.3, Status
Register 1 for more information.
TB: This bit indicates if the protection is from the bottom up of the top down of the memory. See bit 5 of Section 5.3, Status
Register 1 for more information.
BP[2:0]: This field can be programmed to protect all of the memory array, none of the memory array, or a portion of the
memory array. When that portion of the memory if protected, it is protected from the program and erase commands. See bit
4:2 of Section 5.3, Status Register 1 for more information.
The protection scheme differs based on the setting of the CMPRT bit described above. Table 5 shows the relationship between
the BPSIZE, BP[2:0], and TB bits when CMPRT = 0. The right-most column shows the protected address range. All addresses
not shown are unprotected.
Datasheet
DS-AT25XE161D-158
Revision H
28
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 5: AT25XE161D Device Block Protection Map — CMPRT = 0, WPS = 0
CMPRT
BPSIZE
TB
BP[2:0]
Protected Address Range
0
0
0
3'b000
NONE
0
0
0
3'b001
1F0000 - 1FFFFF
0
0
0
3'b010
1E0000 - 1FFFFF
0
0
0
3'b011
1C0000 - 1FFFFF
0
0
0
3'b100
180000 - 1FFFFF
0
0
0
3'b101
100000 - 1FFFFF
0
0
0
3'b110
000000 - 1FFFFF
0
0
0
3'b111
000000 - 1FFFFF
0
0
1
3'b000
NONE
0
0
1
3'b001
000000 - 00FFFF
0
0
1
3'b010
000000 - 01FFFF
0
0
1
3'b011
000000 - 03FFFF
0
0
1
3'b100
000000 - 07FFFF
0
0
1
3'b101
000000 - 0FFFFF
0
0
1
3'b110
000000 - 1FFFFF
0
0
1
3'b111
000000 - 1FFFFF
0
1
0
3'b000
NONE
0
1
0
3'b001
1FF000 - 1FFFFF
0
1
0
3'b010
1FE000 - 1FFFFF
0
1
0
3'b011
1FC000 - 1FFFFF
0
1
0
3'b100
1F8000 - 1FFFFF
0
1
0
3'b101
1F8000 - 1FFFFF
0
1
0
3'b110
000000 - 1FFFFF
0
1
0
3'b111
000000 - 1FFFFF
0
1
1
3'b000
NONE
0
1
1
3'b001
000000 - 000FFF
0
1
1
3'b010
000000 - 001FFF
0
1
1
3'b011
000000 - 003FFF
0
1
1
3'b100
000000 - 007FFF
0
1
1
3'b101
000000 - 007FFF
0
1
1
3'b110
000000 - 1FFFFF
0
1
1
3'b111
000000 - 1FFFFF
Datasheet
DS-AT25XE161D-158
Revision H
29
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 6
shows the relationship between the BPSIZE, BP[2:0], and TB bits when CMPRT = 1.
Table 6: AT25XE161D Device Block Protection Map — CMPRT = 1, WPS = 0
CMPRT
BPSIZE
TB
BP[2:0]
Protected Address Range
1
0
0
3'b000
000000 - 1FFFFF
1
0
0
3'b001
000000 - 1EFFFF
1
0
0
3'b010
000000 - 1DFFFF
1
0
0
3'b011
000000 - 1BFFFF
1
0
0
3'b100
000000 - 17FFFF
1
0
0
3'b101
000000 - 0FFFFF
1
0
0
3'b110
NONE
1
0
0
3'b111
NONE
1
0
1
3'b000
000000 - 1FFFFF
1
0
1
3'b001
010000 - 1FFFFF
1
0
1
3'b010
020000 - 1FFFFF
1
0
1
3'b011
040000 - 1FFFFF
1
0
1
3'b100
080000 - 1FFFFF
1
0
1
3'b101
100000 - 1FFFFF
1
0
1
3'b110
NONE
1
0
1
3'b111
NONE
1
1
0
3'b000
000000 - 1FFFFF
1
1
0
3'b001
000000 - 1FEFFF12
1
1
0
3'b010
000000 - 1FDFFF(1) (2)
1
1
0
3'b011
000000 - 1FBFFF(1) (2)
1
1
0
3'b100
000000 - 1F7FFF(2)
1
1
0
3'b101
000000 - 1F7FFF(2)
1
1
0
3'b110
NONE
1
1
0
3'b111
NONE
1
1
1
3'b000
000000 - 1FFFFF
1
1
1
3'b001
001000 - 1FFFFF34
1
1
1
3'b010
002000 - 1FFFFF(3) (4)
1
1
1
3'b011
004000 - 1FFFFF(3) (4)
1
1
1
3'b100
008000 - 1FFFFF(4)
1
1
1
3'b101
008000 - 1FFFFF(4)
1
1
1
3'b110
NONE
1
1
1
3'b111
NONE
1 When the 32 kB Erase command is used, the protected region is 0x00_0000 - 0x1F_7FFF.
2 When the 64 kB Erase command is used, the protected region is 0x00_0000 - 0x1E_FFFF.
3 When the 32 kB Erase command is used, the protected region is 0x00_8000 - 0x1F_FFFF.
4 When the 64 kB Erase command is used, the protected region is 0x01_0000 - 0x1F_FFFF.
Datasheet
DS-AT25XE161D-158
Revision H
30
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.8.2 Individual Block Lock and Unlock
In addition to the standard protection scheme described in the previous subsection, the AT25XE161D device also provides the
ability to lock individual memory locations. Protection of memory locations can be applied individually using the Individual Block
Lock (36h) command and the Individual Block Unlock (39h) command. Note that in the AT25XE161D device all lock bits are set
by default, making all memory locations protected. The user must execute a series of one or more Individual Block Unlock (39h)
commands to unlock the desired memory locations.
The individual memory protection scheme is invoked by setting bit 2 (WPS) of status register 3. When this bit is set, the AT25XE161D uses the Individual Block Lock (36h) command that provides the address of the 4 kB or 64 kB block to be locked. See Table
17 for more information on the WPS bit.
Table 3 above shows the address ranges for each 4 kB block corresponding to the top and bottom 64 kB blocks of the memory
map. The appropriate 24-bit address is driven on the SI pin after the 36h command. After decoding the command, hardware reads
the address and sets the appropriate lock bit for that 4 kB block.
Note that the ability to lock 4 kB blocks only applies to the top and bottom 64 kB blocks of the map. This corresponds to blocks
0 and 31. For 64 kB blocks 1 - 30, the blocks can only be locked on the 64 kB boundary (1 lock bit per 64 kB). This equates to a
total of 62 lock bits;
16 bits, one per 4 kB sub-block in the top 64 kB block
16 bits, one per 4 kB sub-block in the bottom 64 kB block
30 bits, one each for 64 kB blocks 1 - 30
See Section 6.21, Individual Block Lock (36h) and Section 6.22, Individual Block Unlock (39h) for more information.
4.8.3 Global Block Lock and Unlock
In addition to individual block protection of memory locations as described in the previous subsection, the AT25XE161D also
allows for the blocks to be locked and unlocked globally using the Global Block Lock (7Eh) and the Global Block Unlock (98h)
commands. Note that in the AT25XE161D device all lock bits are set by default, making all memory locations protected. The user
must execute a Global Unlock Block command to unlock the memory locations.
See Section 6.24, Global Block Lock (7Eh) and Section 6.25, Global Block Unlock (98h) for more information.
4.8.4 Reading the State of the Lock Bits
In addition to globally or individually locking and unlocking selected memory blocks as described above, the AT25XE161D device
allows the user to poll any block in memory to determine if it has been locked. This is done by executing either the 3Ch or 3Dh
command, along with the 24-bit address. Both of these command perform the exact same operation and can be used interchangeably.
Once this information is decoded, hardware fetches the 8-bit lock field from the requested location and outputs this information
onto the SO pin. The most significant bit (MSB) of the value is transferred first, and the least significant bit (LSB) is transferred
last. If the LSB is 1, the corresponding block is locked and no erase or program operation can be executed to that block. If the
LSB is 0, the block or section is unlocked and program/erase operations are allowed. See Section 6.23, Read Block Lock (3Ch/
3Dh) for more information.
Datasheet
DS-AT25XE161D-158
Revision H
31
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.9 POWER-DOWN CONSIDERATIONS
The AT25XE161D device supports the Deep Power-Down (B9h) and Ultra-Deep Power-Down (79h/B9h) modes. Also, bit 7 (PDM)
of Status register 4 (SR4) can be used to select either of these modes using the B9h command. The 79h command is provided
for backward compatibility.
There are three ways to enter power-down mode:
1.
Set the PDM bit in SR4 (logic 1) and execute the B9h command to place the device into Deep Power-Down (DPD) mode.
In this mode it is possible to execute the Resume from Deep Power-Down (ABh) command or Enable Reset (66h) and
Reset Device (99h) commands in order to exit DPD mode. The content of SRAM buffer is preserved in this case. The
device could also be reset by JEDEC reset, hardware reset, or power-on-reset in order to exit DPD mode. The exit from
DPD mode time is defined by the tRDPD timing parameter in Section 7.5. Also see Section 4.9.2, below. Note that in the
AT25XE161D device, simply deasserting CS as in other devices does not exit DPD mode.
2.
Clear the PDM bit in SR4 (logic 0) and execute the B9h command to place the device into Ultra-Deep Power-Down
(UDPD) mode. To exit this mode, it is necessary to execute the Resume from Ultra-Deep Power-Down (ABh) command
or a JEDEC reset, hardware reset, or power-on-reset to initiate an internal reset of the device. The contents of the SRAM
buffer are NOT preserved. The resume from UDPD mode recovery time is defined by the tRUDPD timing parameter in
Section 7.5. Also see Section 4.9.2, below. Note that in the AT25XE161D device, simply deasserting CS as in other
devices does NOT exit UDPD mode.
3.
Execute the 79h command to place the device into Ultra-Deep Power-Down (UDPD) mode. If this command is used, the
state of the PDM bit in SR4 is ignored. This mode allows for software backward compatibility. A device reset is required to
exit UPDP mode. In this mode it is necessary to execute the Resume from Ultra-Deep Power-Down (ABh) command or a
JEDEC reset, hardware reset or power-on-reset to initiate an internal reset of the device. The contents of the SRAM
buffer are NOT preserved. The exit from UDPD mode recovery time is defined by the tRUDPD timing parameter in Section
7.5. Also see Section 4.9.2, below for more information on exiting power-down mode.
4.9.1 Entering Power-Down Mode
The conditions for entering DPD or UDPD mode are shown in the Table 7. The PDM column indicates the state of the Power-Down
Mode bit in Status Register 4.
Table 7: Entering DPD or UDPD Mode
Power-Down Mode
SRAM Contents
Power-Down Exit
Recovery Time
1
Deep Power-Down
Retained
Short
0
Ultra-Deep Power-Down
Lost
Long
x
Ultra-Deep Power-Down
Lost
Long
Command
PDM bit
B9h
B9h
79h
4.9.2 Exiting Power-Down Mode
The following methods can be used to exit DPD or UDPD mode.
Table 8: Exiting DPD or UDPD Mode
Command
PDM
bit
PowerDown Mode
B9h
1
DPD
ABh2
Y
Y
Y
UDPD
ABh3
Y
Y
UDPD
ABh(3)
Y
Y
B9h
79h
0
x
Exit Com- Power On
mand
Reset
JEDEC
Reset
Hardware
66h/99h
Reset Pin1 Command
Terminate
(F0h)
Status
After Exit
Y
N
Idle
Y
N
N
Idle
Y
N
N
Idle
1 Hardware reset function must be enabled by software before entering the Power-Down mode. See bit 7 of Status Register 3.
2 Executing the ABh command in DPD mode returns the device to an idle state. The SRAM contents are retained.
3 Executing the ABh command in UDPD mode causes the device to initiate an internal reset sequence. The SRAM contents are undefined.
Datasheet
DS-AT25XE161D-158
Revision H
32
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
ABh Command
Executing the ABh command while in the Deep Power-Down (DPD) mode causes the device to exit DPD and return back to an
idle state. This command does not reset the device and no data is lost. Executing the ABh command while in the Ultra-Deep
Power-Down (UDPD) mode causes the device to perform an internal reset. In this case the SRAM contents are undefined.
Device Resets
In addition to the ABh command described above, performing a Power On Reset (POR), a JEDEC reset, or asserting the hardware
reset pin (RESET) also causes the device to exit DPD or UDPD mode. If the device is reset in any of these three ways, the SRAM
contents are undefined.
Enable Reset (66h) / Reset (99h) Command
As shown in Table 8, the 66h/99h reset command is accepted in DPD mode. In this case the SRAM contents are retained. The
device does not exit UDPD mode, regardless of whether the device entered UDPD mode using the B9h command or the 79h
command. To exit UDPD mode, the device must be reset as described in the previous subsections.
Terminate Command (F0h)
The Terminate (F0) command does not cause exit from DPD or UDPD modes. To exit DPD or UDPD mode still requires either
the ABh command, or resetting the device as described in the previous subsections.
4.9.3 Reset During Program and Erase Commands
The AT25XE161D device supports the following program and erase operations.
Program operations include:
Byte/Page Program (02h)
Sequential Program (AFh/ADh)
Dual Output Byte/Page Program (A2h)
Quad Output Byte/Page Program (32h)
Read-Modify-Write (0Ah)
Main Memory Page Program Without Erase (88h)
Program Security Register (9Bh)
Erase operations include:
Page Erase (81h/DBh)
4 kB Block Erase (20h)
32 kB Block Erase (52h)
64 kB Block Erase (D8h)
Chip Erase (60h/C7h)
These commands are affected when resetting the device as shown in Table 9. In this table, a ‘Y’ entry indicates that the device is
reset when that type of reset occurs during the corresponding command. A ‘N’ entry indicates that the operation is terminated,
but the device is not reset. For example, when the F0h command is executed during a program or erase operation, the operation
is halted, but the device is not reset.
Datasheet
DS-AT25XE161D-158
Revision H
33
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 9: Resetting the Device During a Program or Erase Operation
Command Type
Power-On Reset
JEDEC Reset
Hardware
Reset Pin
66h/99h
Command
Terminate
(F0h)
Program
Y
Y
Y
Y
N
Erase
Y
Y
Y
Y
N
4.10 ERASE/PROGRAM SUSPEND CONSIDERATIONS AND NESTED OPERATIONS
The AT25XE161D device provides three status register bits to manage program and erase suspend operations.
SUSP — Status Register 2, bit 7. The SUSP bit is set by hardware and indicates that the program or erase operation has
been suspended.
ES — Status Register 5, bit 3. The ES bit is set by hardware whenever an erase operation is suspended.
PS — Status Register 5, bit 2. The PS bit is set by hardware whenever a program operation is suspended.
These three bits work in conjunction to define the state of a suspend operation, as shown in Table 10.
In this table, the SUSP is a logical OR of the ES and PS bits. When either the ES or PS bit is set, the SUSP bit is set. When both
of the ES and PS bits are cleared, the SUSP bit is cleared.
These bits relate to the flow diagram in Figure 18 below as follows: when the erase operation is suspended, hardware sets the
ES bit. When the program operation is suspended, hardware sets the PS bit. Once the program operation is complete, hardware
clears the PS bit. Finally, when the erase operation is completed, hardware clears the ES bit.
Table 10: Encoding of Erase/Program Suspend Operations
SUSP
ES
PS
Status
0
0
0
No suspend operation in progress.
1
0
1
Program suspend operation in progress.
1
1
0
Erase suspend operation in progress.
1
1
1
Nested erase/program suspend operation in progress.
4.10.1 Nested Operations
The AT25XE161D device supports nested erase and program suspend operations. An erase operation can be suspended and a
program operation started. This operation can then also be suspended and another operation commenced, such as a read. After
the read operation is complete, the program operation can be resumed. Once the program operation is completed, the erase
operation can be resumed. Nested operations adhere to the following constraints:
Suspending an erase operation followed by a program operation is supported
Suspending a program operation followed by an erase operation is NOT supported
The erase operation must be suspended first, followed by suspension of the program operation.
Figure 18 shows an example of a flow diagram of a nested operation.
Datasheet
DS-AT25XE161D-158
Revision H
34
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
E xe c u te D 8 h
6 4 kB B lo ck E ra se
E xe cu te th e D 8 h co m m a n d to
in itia te a 6 4 kB e ra se o p e ra tio n .
E xe cu te 7 5 h
6 4 kB B lo ck E ra s e S u s p e n d
E xe cu te th e 7 5 h c o m m a n d to su s p e n d
th e 6 4 kB b lo ck e ra s e o p e ra tio n .
E xe cu te 0 2 h
B y te /P a g e P ro g ra m
E xe cu te th e 0 2 h c o m m a n d to in itia te a
b y te /p a g e p ro g ra m o p e ra tio n .
E xe cu te 7 5 h
B yte /P a g e P ro g ra m S u sp e n d
E xe cu te th e 7 5 h c o m m a n d to su s p e n d
th e b yte /p a g e p ro g ra m o p e ra tio n .
E xe cu te 0 3 h
R e a d A rra y O p e ra tio n
E xe cu te th e 0 3 h co m m a n d to in itia te a
re a d a rra y o p e ra tio n .
C h e ck to se e if th e re a d a rra y o p e ra tio n
is c o m p le te . T h e s u s p e n d e d p a g e
p ro g ra m o p e ra tio n c a n n o t b e re s u m e d
u n til th e 0 3 h co m m a n d h a s co m p le te d .
N
Is 0 3 h D o n e ?
Y
O n ce th e 0 3 h re a d a rra y c o m m a n d h a s
co m p le te d , th e su s p e n d e d p ro g ra m
o p e ra tio n ca n b e re s u m e d u sin g th e 7 A h
co m m a n d .
E x e cu te 7 A h
P ro g ra m R e s u m e O p e ra tio n
C h e ck to se e if th e b y te /p a g e p ro g ra m
o p e ra tio n is co m p le te . T h e s u s p e n d e d
6 4 kB e ra se o p e ra tio n c a n n o t b e
re su m e d u n til th e 0 2 h co m m a n d h a s
co m p le te d .
N
Is P ro g ra m
O p D one?
Y
O n ce th e 0 2 h b yte /p a g e p ro g ra m
co m m a n d h a s co m p le te d , th e
su sp e n d e d e ra se o p e ra tio n c a n b e
re s u m e d u sin g th e 7 A h co m m a n d .
E x e cu te 7 A h
E ra se R e su m e O p e ra tio n
C h e ck to se e if th e 6 4 k B e ra se
o p e ra tio n is co m p le te .
N
Is E ra s e O p
D one?
Y
N e s te d
O p e ra tio n
C o m p le te
Figure 18: Flow Diagram of Nested Operations Example
Datasheet
DS-AT25XE161D-158
Revision H
35
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.10.2 Program and Erase Errors
The AT25XE161D device provides two Status register bits to indicate program and erase errors.
EE — Status Register 4, bit 4. The EE bit is set by hardware whenever an error occurs during an erase operation.
PE — Status Register 4, bit 5. The PE bit is set by hardware whenever an error occurs during a program operation.
When a new program or erase command is accepted by the device, hardware clears the EE or PE bits, depending on the
command. The device clears the EE bit when a new Block Erase or Chip Erase command is accepted. The device clears the PE
bit when a new Byte/Page Program, Buffer to M-M P-P without Erase Sequential Programming, Program OTP Security Register,
Write Status Register or Status Register Lock command is accepted. If an error is detected during the command execution, then
the EE or PE flag is set. These flags hold their contents even if the program/erase operation is suspended. Note that the Resume
command does not change the state of the EE and PE bits. If a Terminate command is issued while the device is busy (executing
program/erase), then the PE or EE flag is set.
The PE and EE bits are volatile, meaning that any reset operation clears these bits. The ABh command exits Deep Power-Down
(DPD) or Ultra-Deep Power-Down (UDPD) mode. If the device is in DPD mode and the user issues the ABh command, then the
device exits DPD mode but does not change the state of the PE and EE bits. However, if the ABh command is executed and the
device exits from UDPD mode, then the device initiates a reset, which causes both the PE and EE bits to be cleared.
When an error occurs during a given command, the EE and PE bits are set as shown in Table 11. Note that for any of the commands
where a ‘Yes’ appears in the EE or PE columns, when a new command is issued, the EE or PE bit is cleared. Therefore, when
the bit is set initially due to an error being detected, it is incumbent on software to detect when these bits are set and take the
necessary steps to determine the exact error.
Table 11: Command Errors and Their Effect on the EE and PE Bits
Command Name
Command Code
Sets the EE Bit
Sets the PE Bit
Read Array
03h, 3Bh, 6Bh, EBh, E7h
No
No
Buffer Read
D4h
No
No
Block Erase
81h, DBh, 20h, 52h, D8h
Yes
No
Chip Erase
60h, C7h
Yes
No
Buffer Write
84h
No
No
02h, A2h, 32h
No
Yes
Buffer to M-M P-P without Erase
88h
No
Yes
Read-Modify-Write
0Ah
No
Yes
Sequential Programming
ADh, AFh
No
Yes
Program/Erase Suspend
B0h, 75h
No
No
Program/Erase Resume
Byte/Page Program
D0h, 7Ah
No
No
Write Enable
06h
No
No
Write Disable
04h
No
No
Volatile Write Enable
50h
No
No
Individual Block Lock
36h
No
No
Individual Block Unlock
39h
No
No
Global Block Lock
7Eh
No
No
Global Block Unlock
98h
No
No
3Ch, 3Dh
No
No
9Bh
No
Yes
Read Block Lock Status
Program OTP Security Register
Datasheet
DS-AT25XE161D-158
Revision H
36
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 11: Command Errors and Their Effect on the EE and PE Bits (Continued)
Command Name
Command Code
Sets the EE Bit
Sets the PE Bit
4Bh
No
No
05h, 35h, 15h
No
No
65h
No
No
01h, 31h, 11h
No
Yes
Write Status Registers (indirect)
71h
No
Yes
Status Register Lock
6Fh
No
Yes
Active Interrupt
25h
No
No
Terminate
F0h
Enable Reset
66h
No
No
Reset Device
99h
Cleared on POR
Cleared on POR
9Fh, 90h, 94h
No
No
Deep Power-Down
B9h
No
No
Resume from Deep Power-Down
ABh
No
No
Resume from Ultra-Deep
Power-Down
ABh
Cleared on POR
Cleared on POR
Ultra-Deep Power-Down
79h
No
No
Read SFDP
5Ah
No
No
Set Burst with Wrap
77h
No
No
Low Battery Detect
EFh
No
No
Read OTP Security Register
Read Status Registers (direct)
Read Status Registers (indirect)
Write Status Registers (direct)
Read Mfg ID and Device ID
Yes
Yes
(if Erase command is terminat- (if Program command is termied)
nated)
4.10.3 Suspending and Terminating a Program or Erase Operation
Program Operation
A self-timed program operation can be suspended using the Suspend (75h) command and terminated using the Terminate (F0h)
command. The device responds to either of these commands by initiating a sequence which completes some internal suboperations, brings the internal voltage supplies to their quiescent state, saves the intermediate address counters and states, and
sets either the PS (Program Suspend) bit in Status register 4 in the case of a Suspend command, or the PE (Program Error) bit
in status register 5 in case of the Terminate command.
When the user issues the Suspend command the device requires a period of time equal to tSUS before the BUSY flag goes low
and the PS flag goes high. Similarly, when the user issues the Terminate command the device requires a period of time equal to
tSWTERM before the BUSY flag goes low and the PE flag goes high.
If the user issues the Suspend command, and then issues the Terminate command before the device has completed the internal
suspend operation, the device honors the Terminate command and sets the PE flag. The PS flags is not set, and the BUSY flag
is cleared. At this point the self-timed command that was terminated cannot be resumed, and the region of the memory that was
being programmed/erased is left in an intermediate state.
Erase Operation
A self-timed erase operation can be suspended using the Suspend (75h) command and terminated using the Terminate (F0h)
command. The device responds to either of these commands by initiating a sequence which completes some internal suboperations, brings the internal voltage supplies to their quiescent state, saves the intermediate address counters and states, and
sets either the ES (Erase Suspend) bit in status register 4 in the case of a Suspend command, or the EE (Erase Error) bit in
status register 5 in case of the Terminate command.
Datasheet
DS-AT25XE161D-158
Revision H
37
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
When the user issues the Suspend command the device requires a period of time equal to tSUS before the BUSY flag goes low
and the PE flag goes high. Similarly, when the user issues the Terminate command the device requires a period of time equal to
tSWTERM before the BUSY flag goes low and the EE flag goes high.
If the user issues the Suspend command, and then issues the Terminate command before the device has completed the internal
suspend operation, the device honors the Terminate command and sets the EE flag. The ES flags is not set, and the BUSY flag
is cleared. At this point the self-timed command that was terminated cannot be resumed, and the region of the memory that was
being programmed/erased is left in an intermediate state.
This concept is shown in Figure 19.
BUSY
CSB
Command
Suspend
Stop
Terminate
EE/PE
ES/PS
Figure 19: Issuing a Terminate Command Before the Suspend Command has Completed
Terminate After Suspend
If the time between the Suspend command and the Terminate command is large enough, then the device can finish the internal
suspend operation before the Terminate command is received. In this case, the device clears the BUSY bit in Status register 1,
and the ES/PS flags in Status register 5 are set. Now when the device receives the Terminate command, it is ignored by the
hardware. This concept is shown in Figure 20.
BUSY
CSB
Command
Suspend
Stop
Terminate
EE/PE
ES/PS
Figure 20: Allowing Enough Time for the Suspend Operation to Complete
If the user wishes to perform another program operation, they must check the status of both the PS and PE flags in Status registers
4 and 5, respectively, to determine the next action.
If the PS bit is cleared and the PE bit is set, the user can issue a new Program command. Note that previous Program command
that was terminated leaves that region of memory in an intermediate state, and it is recommended to erase this region of memory
before attempting to program it.
If the ES/PS bit is set, then the user cannot issue another Program/Erase command. The user must first issue a Resume command
to re-start the suspended program/erase operation, then either allow it to run to completion or terminate it using the Terminate
command. The user can now issue a new Program/Erase command.
Datasheet
DS-AT25XE161D-158
Revision H
38
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.10.4 Terminating a Non-Volatile Register Operation in Progress
The Terminate (F0h) command, the Software Reset command (66h + 99h), the hardware reset (RESET on IO3) pin, and the
JEDEC Reset are ways to terminate any on-going internal self-timed program/erase operation (and in some cases reset the
device). However, abruptly terminating the Status Register Write, Status Register Lock, or OTP Security Register Program
command is not desirable because this can leave these non-volatile registers in an indeterminate state.
Therefore when the device is busy executing the Status Register Write, the Status Register Lock or the OTP Security Register
Program command, then the Terminate command is ignored. The software reset, hardware reset, and JEDEC reset actions are
delayed until after the internal self-timed operations are completed; once the internal operation is completed, the device is reset.
See Section 4.12 for more information on how to perform a JEDEC hardware reset.
4.11 OTP SECURITY REGISTER LOCK
The AT25XE161D device supports four 128-byte OTP security registers. One register is programmed by Dialog Semiconductor
at the factory and is always locked. The other three OTP registers can be programmed by the user and become locked whenever
any bit in the most significant byte of that register is written. In response to this write operation, hardware writes bits 5:3 (SL3:SL1)
of Status register 2 to indicate that the corresponding register has been locked. Software can read this field to determine which
registers have been locked.
Each byte of each register can be written using address bits 8:0 that are driven with the Program OTP Security register command
(9Bh). See Table 31 in Section 6.26, Program Security Register (9Bh) for an exact encoding of these address bits.
This concept is shown in Figure 21. In this figure, A[8:7] are used to select between the four OTP Security registers, and A[6:0]
are used to select one of the 128 bytes within that register. A value of 7’b1111111 on A[6:0] indicates an access to the MSB of
that register as shown below.
Software programs any bit in
the most significant byte of
OTP Security register 3.
Software programs any bit in
the most significant byte of
OTP Security register 2.
Software programs any bit in
the most significant byte of
OTP Security register 1.
A[8:0] = 111111111
A[8:0] = 101111111
A[8:0] = 011111111
Byte number
511
510:385
OTP Register 3
User-Defined
Byte number
384
383
Hardware sets
bit 4 of SR2
Hardware sets
bit 5 of SR2
No programming allowed. OTP
register 0 is programmed by
Adesto at the factory. The value
in this register can be read by
executing the 4Bh command.
Byte number
382:257
256
255
OTP Register 2
User-Defined
254:129
Byte number
128
OTP Register 1
User-Defined
127
126:1
0
OTP Register 0
Factory Programmed by Adesto
Hardware sets
bit 3 of SR2
SL3 SL2 SL1
7
5
4
3
Status Register 2
0
Figure 21: OTP Security Register Program and Lock
Datasheet
DS-AT25XE161D-158
Revision H
39
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.12 STANDARD JEDEC HARDWARE RESET
The JEDEC hardware reset sequence does not use the SCK pin. The SCK pin must be held low (mode 0) or high (mode 3)
through the entire reset sequence. This prevents any confusion with a command, as no command bits are transferred.
A reset is commanded when the data on the SI pin is 0101 on four consecutive positive edges of the CS pin with no edge on the
SCK pin throughout. This is a sequence where
1.
CS is driven active low to select the device.
2.
Clock (SCK) remains stable in either a high or low state.
3.
SI is driven low by the bus master, simultaneously with CS going active low. No SPI bus slave drives SI during CS low
before a transition of SCK.
4.
CS is driven inactive. The slave captures the state of SI on the rising edge of CS.
The above steps are repeated 4 times, each time alternating the state of SI.
After the fourth CS pulse, the slave triggers its internal reset. SI is low on the first CS, high on the second, low on the third, high
on the fourth. This provides a value of 5h, unlike random noise. Any activity on SCK during this time halts the sequence, and a
Reset is not generated.
After a JEDEC hardware reset while the device is in Ultra-Deep Power-Down (UDPD) mode, the SRAM buffer resets to an
undefined value. Hardware resets all volatile status registers, including the block protection bits, to their default values.
After a JEDEC hardware reset while the device is in any other mode than UDPD mode, the SRAM buffer keeps the values it had
prior to Reset, with the following exception: If the reset sequence is initiated during an update of the SRAM buffer, the contents
of the SRAM buffer can be corrupted. Hardware resets all volatile status registers, including the block protection bits, reset to their
default values.
All non-volatile status registers keep the value they had prior to reset, with the following exception: If the reset sequence is initiated
during a write to a non-volatile status register, the value of that register can be corrupted.
The device reverts to standard SPI mode after JEDEC hardware reset. Figure 22 shows the timing for the JEDEC hardware reset
operation.
tCH
CS
tCL
Mode 3
SCK
Mode 0
SI
SO
High-Impedance
tRST
Internal Reset
Figure 22: JEDEC Standard Hardware Reset
4.13 CHIP SELECT RESTRICTIONS
The CS pin starts and ends operations in the device. Once the CS pin is asserted and the operation begins, it can only be
deasserted on a byte boundary. If the CS pin is deasserted on a non-byte boundary, the operation is ignored.
For example, when executing the ABh command to exit power-down mode, only the command is required. No address and data
are required to perform this operation. Therefore, only eight clocks are required to transfer the command. If the CS pin is raised
Datasheet
DS-AT25XE161D-158
Revision H
40
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
after the 8th clock (most significant bit of the command is transferred), hardware performs the operation. If the CS pin is raised
after the 9th or 10th clock (not a byte boundary), the operation is ignored and no ABh command is executed.
Similarly, if the ABh command fetches the device ID. Once the CS pin is asserted, 40 clock cycles are required: 8 clocks for the
command, 24 dummy clocks, and 8 clocks to shift out the device ID. If the CS pin is raised after the 40th clock, hardware transfers
the ID information, exits power-down mode, and completes the operation. However, if the CS pin is raised on the 41st of 42nd
clock (not a byte boundary), the ID information is still returned as that occurred in clocks 32 - 40, but the device does not exit
power-down mode.
4.14 ACTIVE STATUS INTERRUPT
When a program or erase operation is in progress, there are two ways to determine when the operation has finished.
Repeatedly poll bit 0 (RDY/BSY) of Status register 1 looking for a high to low transition.
Once the program or erase operation begins, execute the Active Status Interrupt (25h) command, and watch for a high to
low transition on the SO pin.
For example, assume a Byte/Page Program (02h) operation is initiated and 256 bytes are transferred into the buffer. Once the
CS pin is deasserted, indicating the completion of the 02h command, hardware sets the RDY/BSY bit and starts moving the data
to memory. Executing the 25h command causes hardware to drive the state of the RDY/BSY bit onto the SO pin. This allows
external logic to monitor the state of the SO pin for a high to low transition.
When the Active Status Interrupt (25h) command is used, the SO pin can be connected to an external interrupt controller. The
controller recognizes the high to low transition and takes the appropriate action. This command is an alternative to the polling of
the RDY/BSY bit in Status register 1 and uses less overhead than continually executing the 05h command to read the contents
of Status register 1.
4.15 LOW BATTERY DETECT
The AT25XE081D device includes a Low Battery Detect (EFh) command that can be used to probe the battery and determine its
status. The low battery detect function is programmable. Software uses Status register (SR6) to program parameters such as
what voltage level constitutes a low battery, and how much load is applied to the battery to determine the amount of charge left.
Another field sets the amount of time the desired load is applied to the battery.
Status register 6 is used in the following manner to determine the low battery status. For the exact programmable values for these
registers fields, see Section 5.4, Status Register 2.
1.
Program the LBVL field (bits 5:3) of SR6 to set the low battery detect level. When a test is performed, the device does not
indicate a low voltage level until that level falls below the value programmed into this field. Values range from 1.8V to
3.2V in 200 mV increments.
2.
Program the LBLD field (bits 2:1) of SR6 to indicate the amount of load applied to the battery for testing purposes. The
amount of load applied ranges from 0 μA to 10 mA.
3.
Program the LBD field (bit 0) to indicate the amount of time the load selected by the LBLD field is applied to the battery.
Values of 100 μs and 1 ms are supported.
4.
Execute the Low Battery Detect (EFh) command. This operation sets bits 7:6 (LBST) of SR6 to a value of 2’b01,
indicating that a low battery detect operation is in progress.
5.
Software can poll bits 7:6 of SR6 to determine whether the test has completed. As long as the value of these bits is 2’b01
the battery test is in progress. Alternatively, the active status interrupt (25h) command can be used to determine when the
test has completed. See the previous subsection for more information on the active status interrupt command.
6.
Once the operation is complete, bits 7:6 of SR6 indicate the result of the test. If the field contains a value of 2’b10, the
voltage of the battery is greater than the threshold set by the LBVL field. A value of 2’b11 indicates the voltage of the
battery is less than the threshold set by the LBVL field.
Bits 7:6 of SR6 can be reset by hardware when certain internal conditions are met. The user can reset this field by executing a
Terminate command (F0h). See Section 6.43, Low Battery Detect (EFh) for more information.
Datasheet
DS-AT25XE161D-158
Revision H
41
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
4.16 READ-MODIFY-WRITE
The AT25XE161D device incorporates a completely self-contained Read-Modify-Write (R-M-W) operation (command 0Ah) that
can be used to reprogram any number of sequential bytes in a page in the main memory array without affecting the rest of the
bytes in the same page. This command allows the device to easily emulate an EEPROM by providing a method to modify a single
byte or more in the main memory in a single operation, without pre-erasing the memory or any external RAM buffers. The main
advantage of this command is that it allows a memory location to be erased and reprogrammed in one operation.
The device also incorporates an intelligent erase and programming algorithm that can detect when a byte location fails to erase
or program properly. If an erase or program error arises, hardware indicates this condition by setting bit 5:4 (EE and PE) in Status
register 4. See Section 5.6, Status Register 4 for more information on these bits. See Section 6.42, Single Command ReadModify-Write — EEPROM Emulation (0Ah) for more information on the 0Ah command.
4.17 HOLD / RESET FUNCTION
The AT25XE161D device provides a configurable HOLD/RESET pin. This pin can be configured to operate as either a HOLD pin,
or as a device RESET pin, by programming bit 7 (HOLD/RESET) of Status register 3. When this bit is cleared, the HOLD/RESET
pin functions as an active low HOLD pin. When this bit is set, the HOLD/RESET pin functions as a active low device RESET pin.
The HOLD/RESET function is only valid in the SPI and dual modes of operation. When bit 1 (QE) of Status register 2 is set,
indicating the device is in one of the quad modes (quad output or I/O) the HOLD/RESET functions are not available and the pin
functions as the I/O3 data pin.
When configured as a RESET pin, no commands are accepted while the pin is low and the device is in reset.
Configuring the pin for the HOLD function allows an operation to be paused, then resumed when the HOLD pin is deasserted.
Once the HOLD pin is asserted (with CS low), the HOLD function takes effect on the next falling edge of SCK. Conversely, once
the HOLD pin is deasserted, the HOLD function is removed on the next falling edge of SCK. Note that the CS pin must be low
for the entire time in which the HOLD operation is in progress.
The HOLD function can be used in situations where the clock and data signals of the AT25XE081D device are shared with other
external agents, allowing the device to share the bus with other high priority events such as interrupts or other events that need
immediate attention. Once the condition is resolved, the HOLD pin can be deasserted, allowing the operation to resume.
During the time the HOLD pin is asserted, the Serial Output (SO) pin is forced to the high impedance state. The state of the Serial
Input (SI) and Serial Clock (SCK) pins are ignored. Note that the CS pin must be low for the entire time in which the HOLD
operation is in progress.
Datasheet
DS-AT25XE161D-158
Revision H
42
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
5
Status Registers
The device contains six Status registers (SR) described in the following subsections. The Status registers can be read to determine
the device's ready/busy status, as well as the status of many other functions such as hardware locking and software protection.
5.1 REGISTER STRUCTURE AND UPDATES
In the AT25XE161D device there are two sets of Status registers. One set is implemented in hardware and is accessed as Status
registers 1 - 6. These are known as volatile registers as their data is lost during a device reset. Also, the device keeps a copy of
the Status registers in memory. These are known as non-volatile registers because they are stored in the Flash and are not
affected by a device reset. On power up, the non-volatile contents of the memory are copied to the Status registers. See Section
5.2.2 for more information on volatile and non-volatile register types.
The AT25XE161D provides two methods for updating the Status Registers. When the Write to Status Register command is
preceded by the Volatile Status Register Write Enable (50h) command, only the flip-flops holding the Status register bits are
updated; the non-volatile memory dedicated to the Status registers is not updated. When the Write to Status Register command
is preceded with a Write Enable (06h) command, then both the flip-flops holding the Status register bits and the non-volatile
memory dedicated to the Status registers are updated. This concept is shown in Figure 23.
The main difference between these two commands is the time required to execute them. Accesses to memory are much slower
by default. So for the 50h command, the write is to the volatile Status registers only which is very fast. For the 06h command, the
write is to non-volatile memory which is much slower.
50h
Status
Registers
06h
Power-Up
Memory
Figure 23: AT25XE161D Register Structure
5.2 REGISTER ACCESSES
This section describes the various ways to access the AT25XE161D Status registers. The AT25XE161D incorporates six Status
registers. Each of these registers can be written or read using both the direct and indirect addressing methods as described in
Section 5.2.1. Also, the device supports both volatile and non-volatile registers as described in Section 5.2.2.
Datasheet
DS-AT25XE161D-158
Revision H
43
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
5.2.1 Direct and Indirect Addressing
The AT25XE161D device supports both direct and indirect addressing for accessing the Status registers. The indirect addressing
method can be used for all six Status registers, and the direct addressing for the first three Status registers. This means that Status
registers 4 - 6 can only be accessed using the indirect addressing method.
These registers have been accessed using the direct addressing method, where every register has a specific command used to
access it and perform read or write operations. An example of these commands is as follows:
05h: Read Status Register 1
35h: Read Status Register 2
15h: Read Status Register 3
01h: Write Status Register 1
31h: Write Status Register 2
11h: Write Status Register 3
The above commands have been retained to provide backward compatibility with existing software. Also to the direct method,
the AT25XE161D device also provides an indirect method. In the indirect method, a single command (65h) executes a read
operation on all of the Status registers. Another command (71h) executes a write operation on all of the Status registers. Once
the command is provided, an 8-bit address field determines which register to access. The encoding of the address field is shown
in Table 12.
Table 12: Indirect Addressing of Status Registers
Command
65h
71h
Address
01h
02h
03h
04h
05h
06h
01h
02h
03h
04h
05h
06h
Action
Read Status Register 1
Read Status Register 2
Read Status Register 3
Read Status Register 4
Read Status Register 5
Read Status Register 6
Write Status Register 1
Write Status Register 2
Write Status Register 3
Write Status Register 4
Write Status Register 5
Write Status Register 6
Note that by using the indirect address method, an address width of 8 bits indicates that up to 256 registers can be accessed,
allowing for future expansion without requiring additional commands or associated hardware complexity.
5.2.2 Volatile and Non-Volatile Register Accesses
As shown in Figure 23, the AT25XE161D device supports both volatile and non-volatile register accesses. Volatile register
accesses are to the Status registers implemented in hardware. Non-volatile register accesses are to the Status registers stored
in memory. During power-up, the contents of the registers in memory are copied to the hardware Status registers.
As shown in Figure 23, the 50h command writes only to the volatile register set, whereas the 06h command writes to both the
volatile and non-volatile register sets.
5.3 STATUS REGISTER 1
Table 13
shows the bit assignments for Status register 1.
Datasheet
DS-AT25XE161D-158
Revision H
44
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 13: Status Register 1 Format
Bit #
Acronym
Name
SRP0
Status
Register
Protect 0
7
6
BPSIZE
5
TB
4:2
BP2:0
1
0
WEL
RDY/BSY
Datasheet
DS-AT25XE161D-158
Block Protect
Size
Top/Bottom
Block Protect
Write Enable
Latch Status
Ready/Busy
Status
Type
R/W
R/W
R/W
R/W
R
R
Default
Description
0
SRP0 works with the SRP1 bit in Status Register 1 and the WP
pin to control write protection. Types of protection include software protection, hardware protection, one-time programmable
(OTP) protection, and power supply lock-down protection. See
Table 15 for an encoding of these bits.
0
BPSIZE controls the size of the blocks protected by the Block
Protect Bits (BP2, BP1, BP0 in bits 4:2 of this register). Its encoding is:
0: 64 kB block size
1: 4 kB block size
The blocks can be protected from the bottom up, or from the
top down, as described in the TB bit of this register.
0
TB controls the direction of the blocks to be protected by the
Block Protect Bits (BP2, BP1, BP0 in bits 4:2 of this register).
Its encoding is:
0: Protect from bottom up
1: Protect from top down
The size of the protected blocks can also be selected, as described in the BPSIZE bit of this register.
000
The Block Protect field provides write protection control and
status. These bits are set using the Write Status register 1 (01h)
command. This field can be programmed to protect all, none,
or a portion of the memory array. When that portion of the memory is selected, it is protected from the Program and Erase commands as described in the Memory Protection table.
The default is 3’b000 for this field, indicating that none of the
memory array is protected.
0
WEL gives the current status of the internal Write Enable Latch.
When WEL is logic “0,” the device does not accept any program,
erase, memory protection, or Write Status Register commands.
WEL defaults to logic “0” after a device power-up or reset.
Its encoding is:
0: Device is not write enabled (default).
1: Device is write enabled.
If WEL is “1,”, it is not reset to a logic “0” if an operation aborts
due to an incomplete or unrecognized command being clocked
into the device before the CS pin is deasserted.
To reset the WEL bit when an operation aborts prematurely, the
entire command for a program, erase, memory protection, or
Write Status Register command must have been clocked into
the device.
When the Write Enable (06h) command is executed, the WEL
bit is set. Conversely, when the Volatile Status Register Write
Enable (50h) command is executed, the WEL bit is not set.
0
RDY/BSY determines if an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect
the completion of a program or erase cycle, new Status Register
data must be continually clocked out of the device until the state
of the RDY/BSY bit changes from a logic “1” to a logic “0”.
Its encoding is:
0: Device is ready.
1: Device is busy with an internal operation.
Revision H
45
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
5.4 STATUS REGISTER 2
The following table shows the bit assignments for Status register 2.
Table 14: Status Register 2 Format
Bit #
Acronym
7
6
SUSP
CMPRT
Name
Suspend
Status
Complement
Protect
Type
R
R/W
Default
Description
0
SUSP is set by hardware and indicates that the program or erase
operation has been suspended. This bit is set after software executes an Erase/Program Suspend (75h) command. Hardware
clears this bit when it detects any of the following conditions:
Erase/Program Resume (7Ah) command, Hardware Reset, JEDEC Hardware Reset, 66h / 99h Reset command
0
CMPRT is used with BPSIZE, TB, and BP2:BP0 bits to provide
additional memory array protection. Its encoding is:
0: Current protection mechanism is unchanged
1: Current protection mechanism is reversed
When set, unprotected areas of memory become protected, and
protected areas of memory become unprotected. For example,
when CMPRT = 0, a top 64 kB block can be protected, while the
rest of the array is not; when CMP = 1, the same 64 kB block
becomes unprotected, the rest of the array is then read-only.
SL3:SL1 gives the One-Time-Program (OTP) lock status of Security Registers 1 - 3. This field determines which of these Security Registers have been locked. Note that Security register 0 is
always locked as the value is programmed at the factory.
The default state of SL[3:1] is 0: all registers are unlocked. Each
bit corresponds to a Status register, as follows:
SL3 (bit 5): Security register 3
SL2 (bit 4): Security register 2
SL1 (bit 3): Security register 1
Each bit is set by hardware when the most significant byte of the
corresponding Security Register (the 128th byte) is programmed. For example, when the MSB of Security register 1 is
set, bit 3 (SL1) of this field is set. Conversely, when the MSB of
Security register 3 is set, bit 5 (SL3) of this field is set. Each time
a bit is set, it indicates that the corresponding 128-Byte Security
Register has become read-only permanently.
5:3
SL3:SL1
Security
Lock 3:1
R
000
2
R
Reserved
R
0
Reserved.
0
QE enables Quad SPI and XiP operation.Its encoding is:
0: QE mode is disabled
1: QE mode is enabled
When QE is logic 0, the WP and HOLD / RESET pins are enabled.
When QE is logic 1, the WP and HOLD / RESET pins function
as the IO2 and IO3 pins, respectively, and the WP and HOLD /
RESET pins functions are disabled.
This bit only pertains to the following commands:
6Bh: Quad Output Read
EBh: XiP Mode Read
E7h: Quad I/O Read with Double-word Aligned Address
32h: Quad Output Program
77h: Set Burst with Wrap
94h: Quad I/O Manufacturer/Device ID
0
SRP1 works with the SRP0 bit in Status Register 0 and the WP
pin to control write protection. Types of protection include software protection, hardware protection, one-time programmable
(OTP) protection, and reset lock-down protection. See Table 15 for
an encoding of these bits.
1
0
QE
Quad Enable
SRP1
Status
Register
Protect 1
Datasheet
DS-AT25XE161D-158
R/W
R/W
Revision H
46
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
Table 15
shows the operation of the SRP[1:0] volatile Status register bits during normal operation.
Table 15: Status Register Protection During Normal Operation
SRP1
SRP0
SRLOCK
WP
Type of Protection
When both the SRP0 and SRP1 bits are 0, the Status registers
can be written by executing a Write Status Register command
(01h, 31h, 11h, 71h) and setting the WEL bit of this register.
Note that the WP pin has no meaning during this type of operation.
When the SRP[1:0] bits are 0, 1 respectively, and the WP pin
is low, the registers are hardware protected and cannot be
written to.
When the SRP[1:0] bits are 0, 1 respectively, and the WP pin
is high, the registers are not hardware protected and can be
written to by executing a Write Status Register command (01h,
31h, 11h, 71h) and setting the WEL bit of this register.
When the SRP[1:0] bits are 1, 0 respectively, the Status registers are write protected and cannot be written until the device
is reset (caused by a power-cycle, hardware reset, or software
reset). After reset, hardware changes the state of the volatile
SRP[1:0] bits to 0,0 as shown in Table 16.
When the SRP[1:0] bits are 1,1 respectively, and the SRLOCK
bit is 0, the Status registers are write protected and cannot be
written until the device is reset (caused by a power-cycle, hardware reset or software reset). After reset, hardware changes
the state of the volatile SRP[1:0] bits to 0,1 as shown in Table 16.
When the SRP[1:0] bits are 1,1 respectively, and the SRLOCK
bit is 1, the Status registers are permanently write protected.
Software Protected
(protection is controlled by
the CMPRT, BPSIZE, TB,
BP[2:0], or WPS bits)
0
0
x
x
0
1
x
0
0
1
x
1
1
0
x
x
Reset Lockdown
1
1
0
x
Reset Lockdown
1
1
1
x
OTP
Table 16
Description
Hardware Protected
(protection is controlled
by the WP pin)
Hardware Unprotected
(protection is controlled by
the CMPRT, BPSIZE, TB,
BP[2:0], or WPS bits)
shows the behavior of the SRP1 and SPR0 bits after a reset condition.
Table 16: Status Register Protection During Reset
Non-Volatile Memory Bits
SRP1
SRP0
SRLOCK
0
0
x
0
1
x
1
0
x
1
1
0
1
1
1
Datasheet
DS-AT25XE161D-158
Type of
Protection
Software
Protected
Hardware
Protected
Reset Lockdown
Reset Lockdown
One-Time
Program
(OTP)
Volatile
Register Bits
Description
The reset operation maintains the volatile SRP1 and SRP0 at
0,0.
The reset operation maintains the volatile SRP1 and SRP0 at
0,1.
The reset operation changes the volatile SRP1 and SRP0 bits
to 0,0.
The reset operation changes the volatile SRP1 and SRP0 bits
to 0,1.
The reset operation maintains the volatile SRP1 and SRP0 at
1,1. This makes the Status registers permanently write protected.
Revision H
47
SRP1
SRP0
0
0
0
1
0
0
0
1
1
1
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
5.5 STATUS REGISTER 3
Table 17
shows the bit assignments for Status register 3.
Table 17: Status Register 3 Format
Bit #
7
1
Acronym
HOLD/
RESET
Name
HOLD or RESET
Function
Type
R/W
Default
Description
0
Dialog Semiconductor provides a variety of packages for the
AT25XE161D, as shown in Section 3. Each of these packages
provides a dedicated HOLD / RESET pin that can be configured as a RESET pin, or as a HOLD pin, depending on the
programming of this bit. Its encoding is:
0: HOLD function is enabled
1: RESET function is enabled
Note that this pin can only be configured as HOLD or RESET
when the QE bit (see bit 1 of Status register 2) is cleared (logic
0). If the QE bit is set, the pin functions as a dedicated data
pin and the HOLD / RESET functionality is disabled.
Drive level. The DRV1 and DRV0 bits are used to determine
the output driver strength during read operations. The driver
strength is automatically adjusted with VCC level. The driver
strength is encoded as following:
00: Reserved
01: 100% (increase 1.66X at low VCC)
10: 66% (increase 2X at low VCC)
11: 33% (increase 3X at low VCC)
6:5
DRV1:0
Drive Level
R/W
011
4:3
R
Reserved
R
0
Reserved
2
WPS
Write Protection
Select
R/W
0
The WPS bit selects the Write Protect scheme. Its encoding is:
0: The AT25XE161D uses a combination of CMPRT, BPSIZE,
TB, and BP[2:0] bits in Status register 1 to protect a specific
area of the memory array.
1: The AT25XE161D uses the individual block locks to protect
any individual block. The default value for all individual block
lock bits is 1 upon device power on or after reset.
When this bit is set, software uses the Block Lock (36h) and
Block Unlock (39h) commands to lock and unlock blocks of
memory.
For more information on this functionality, see Section 4.8,
Memory Protection.
1:0
R
Reserved
R
0
Reserved.
Default driver strength was used for device test and characterization.To achieve optimal performance, it is recommended to adjust driver strength setting
to match the user system load under application-specific environmental conditions.
Datasheet
DS-AT25XE161D-158
Revision H
48
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
5.6 STATUS REGISTER 4
The following table shows the bit assignments for Status register 4.
Table 18: Status Register 4 Format
Bit #
Acronym
7
PDM
Name
PowerDown Mode
Type
R/W
Default
Description
0
This bit is used in conjunction with the Deep Power-Down command (B9h) to place the device into either Deep Power-Down
mode, or Ultra-Deep Power-Down mode. Its encoding is:
0: Execution of the B9h command invokes Ultra-Deep PowerDown mode. This is the same as executing the UDPD command
79h. In this mode the SRAM buffer contents are not preserved.
1: Execution of the B9h command invokes Deep Power-Down
mode. In this mode the SRAM buffer contents are preserved.
In both modes, the ABh command is required to exit the corresponding Power-Down mode. Simply toggling the CS pin does
not result in exiting from Power-Down mode. For more information see Section 4.9, Power-Down Considerations.
6
SPM
Sequential
Program
Mode Status
R
0
The SPM bit indicates whether the device is in the Byte/Page
Program mode or the Sequential Program Mode. The default
state after power-up or device reset is the Byte/Page Program
mode.
Its encoding is:
0: Byte/Page Programming Mode (default)
1: Sequential Programming Mode entered
If software sets this bit to 1, the address is only required for the
first transfer of the sequential operation. Therefore, on the first
transfer, command, address, and data are required. If there are
subsequent operations, the address is not required. Software
must only supply the command and data (on a write).
5
PE
Program
Error
R
0
This bit is set by hardware whenever an error occurs during a
program operation.
4
EE
Erase Error
R
0
This bit is set by hardware whenever an error occurs during an
erase operation.
0
This bit determines whether a command is required each time a
read operation is executed using the E7h or EBh (Quad Read)
commands. Its encoding is:
0: XiP mode (continuous read mode) is disabled
1: XiP mode (continuous read mode) is enabled
If this bit is set and either the E7h or EBh commands are executed, the command is only required for the first access (1-4-4). In
this case, the command is transferred on the SI pin, and the
address and data are transferred on the SI (I/O0), SO (I/O1), WP
(I/O2), and HOLD (I/O3) pins. Subsequent accesses require only
address and data (0-4-4).
Note that if either this bit or the QE bit (see bit 1 of Status register
2) is 0, the device can never be placed into 0-4-4 mode, and a
command is required for each access.
001
This 3-bit field maps to the W6:W4 bits of the Set Burst Wrap
command (77h) to determine the burst wrap status and the wrap
length. See Section 6.14 for more information on the Set Burst
Wrap command.
XiP
XiP Mode
Select
BWS[2:0]
Burst Wrap
Settings
3
2:0
Datasheet
DS-AT25XE161D-158
R/W
R
Revision H
49
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
5.7 STATUS REGISTER 5
The following table shows the bit assignments for Status register 5.
Table 19: Status Register 5 Format
Bit #
Acronym
Name
Type
Default
Description
7
SRLOCK
Status Register
Lock
R
0
Hardware sets this bit when the user executes the Status
Register Lock (6Fh) command, immediately followed by
two verification bytes, 4Dh and 67h. Once this action occurs, the Status registers can be permanently locked.
6:4
DC[2:0]
Dummy Clocks
R/W
000
This field indicates the number of dummy clocks to be inserted between the address and data transactions for the
EBh and E7h commands. Note that the dummy clocks include the 2 clocks required to clock in the M[7:0] bits.
000: 2 clocks
001: 4 clocks
010: 6 clocks
011: 8 clocks
100: 10 clocks.
101 - 111: Reserved
3
ES
Erase Suspend
R
0
This bit is set by hardware whenever an erase operation is
suspended.
2
PS
Program Suspend
R
0
This bit is set by hardware whenever a program operation
is suspended.
0
The TERE bit enables or disables the Terminate command.
Its encoding is:
0: Terminate command is disabled
1: Terminate command is enabled
When the TERE bit is cleared (the default state after powerup), the Terminate command is disabled and any attempts
to reset the device using the Terminate command are ignored. When the TERE bit is set, the Terminate command
is enabled.
The TERE bit retains its state as long as power is applied
to the device. Once set, the TERE bit remains in that state
until it is modified using the Write Status Register Byte 5
command or until the device has been power cycled.
0
Setting the DWA bit indicates that the devices adheres to
double-word aligned addressing. This bit is only used when
the EBh (XiP DWA Read) command is executed and is
encoded as follows:
0: Double-word addressing is disabled
1: Double-word addressing is enabled
When this bit is set, the lower 2 bits of address are ignored
and assumed to be 00.
1
0
TERE
DWA
Datasheet
DS-AT25XE161D-158
Terminate Enable
Doubleword
Aligned
R/W
R/W
Revision H
50
2021-Aug-5
© 2021 Dialog Semiconductor
AT25XE161D
Datasheet
16-Mbit, 1.65 V - 3.6 V Range SPI Serial Flash Memory
with Multi-I/O Support
5.8 STATUS REGISTER 6
The following table shows the bit assignments for Status register 6.
Table 20: Status Register 6 Format
Bit #
7:6
5:3
2:1
0
Acronym
LBS
LBVL
LBLD
LBD
Datasheet
DS-AT25XE161D-158
Name
Low Battery Status
Low Battery Voltage Level
Low Battery Load
Load Battery Delay
Type
R
R/W
R/W
R/W
Default
Description
0
This 2-bit field indicates the state of the low battery test.
The status is reported when the Battery Status command (EFh) is executed. This field is encoded as follows:
00: No test in progress. Normal operation.
01: Battery test in progress.
10: Battery test complete. Result is >Vth
11: Battery test complete. Result is
工商网监
湘ICP备2023018690号
