AT25XE512C-XMHN-T

AT25XE512C 512-Kbit, 1.65V Minimum SPI Serial Flash Memory with Dual-Read Support Features  Single 1.65V - 3.6V Supply  Serial Peripheral Interface (SPI) Compatible   Supports SPI Modes 0 and 3 Supports Dual Output Read  104MHz Maximum Operating Frequency  Clock-to-Output (tV) of 6 ns  Flexible, Optimized Erase Architecture for Code + Data Storage Applications  Uniform 256-Byte Page erase  Uniform 4-Kbyte Block Erase  Uniform 32-Kbyte Block Erase  Full Chip Erase  Hardware Controlled Locking of Protected Sectors via WP Pin  128-byte, One-Time Programmable (OTP) Security Register   64 bytes factory programmed with a unique identifier 64 bytes user programmable  Flexible Programming  Byte/Page Program (1 to 256 Bytes)  Fast Program and Erase Times  2ms Typical Page Program (256 Bytes) Time  50ms Typical 4-Kbyte Block Erase Time  400ms Typical 32-Kbyte Block Erase Time  Automatic Checking and Reporting of Erase/Program Failures  Software Controlled Reset  JEDEC Standard Manufacturer and Device ID Read Methodology  Low Power Dissipation     200nA Ultra Deep Power Down current (Typical) 4.5µA Deep Power-Down Current (Typical) 25uA Standby current (Typical) 3.5mA Active Read Current (Typical)  Endurance: 100,000 Program/Erase Cycles  Data Retention: 20 Years  Temperature Range:-10°C to +85°C (1.65V to 3.6V), -40°C to +85° (1.7V to 3.6V)  Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options    8-lead SOIC (150-mil) 8-pad Ultra Thin DFN (2 x 3 x 0.6 mm) 8-lead TSSOP Package DS-25XE512C–060C–11/2015 1. Description The Adesto® AT25XE512C is a highly optimized ultra-low energy serial interface Flash memory device designed for use in a wide variety of high-volume low energy consumer and industrial applications. The AT25XE512C device has been optimized by design to meet the needs of today's connected applications in the Internet of Things market space. The granular Page Erase and Block Erase architecture allows the memory space to be used much more efficiently supporting data storage and over the air updates. Key program code subroutines and data storage segments need to reside by themselves in their own separate erase regions, and with a granular architecture the wasted and unused memory space that occurs with large sectored and large block erase flash memory devices can be greatly reduced. The resulting improvement to software efficiency contributes to reduced CPU / MCU overheads that translate to further reduce the system energy usage levels. The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. Specifically designed for use in many different systems, the AT25XE512C supports read, program, and erase operations with a wide supply voltage range of 1.65V to 3.6V. No separate voltage is required for programming and erasing. 2. Pin Descriptions and Pinouts Table 2-1. Symbol CS SCK Pin Descriptions Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. Asserted State Type Low Input - Input - Input/Output SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK. SI (I/O0) With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O0) in conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as the SI pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O0 Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). AT25XE512C DS-25XE512C–060C–11/2015 2 Table 2-1. Symbol Pin Descriptions (Continued) Name and Function Asserted State Type - Input/Output Low Input Low Input - Power - Power SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. SO (I/O1) With the Dual-Output Read commands, the SO Pin remains an output pin (I/O1) in conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK. To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as the SO pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O1. The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted). WP WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 12 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. HOLD The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to “Hold” on page 27 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. VCC GND Operations at invalid VCC voltages may produce spurious results and should not be attempted. GROUND: The ground reference for the power supply. GND should be connected to the system ground. AT25XE512C DS-25XE512C–060C–11/2015 3 Figure 2-1. 8-SOIC Top View CS SO WP GND 1 2 3 4 Figure 2-3. 8-UDFN (Top View) 8 7 6 5 VCC HOLD SCK SI 8 7 6 5 VCC HOLD SCK SI CS SO WP GND 1 8 2 7 3 6 4 5 VCC HOLD SCK SI Figure 2-2. 8-TSSOP Top View CS SO WP GND 3. 1 2 3 4 Block Diagram Figure 3-1. Block Diagram &21752/$1' 3527(&7,21 /2*,& &6 6,,2 62 :3 +2/' 65$0 '$7$  %8))(5 ,17(5)$&( &21752/ $1' /2*,&