BB505MES

BB505M Build in Biasing Circuit MOS FET IC UHF RF Amplifier REJ03G0365-0100Z Rev.1.00 Jun.14.2004 Features • • • • Build in Biasing Circuit; To reduce using parts cost & PC board space. Low noise; NF = 1.5 dB typ. at f = 900 MHz High gain; PG = 24 dB typ. at f = 900 MHz Withstanding to ESD; Build in ESD absorbing diode. Withstand up to 190 V at C = 200 pF, Rs = 0 conditions. • Provide mini mold packages; MPAK-4 (SOT-143mod) Outline MPAK-4 2 3 1 4 1. Source 2. Gate1 3. Gate2 4. Drain Notes: 1. Marking is “ES-”. 2. BB505M is individual type number of RENESAS BBFET. Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Drain current Channel power dissipation Channel temperature Storage temperature Symbol VDS VG1S VG2S ID Pchnote3 Tch Tstg Ratings 6 +6 –0 +6 –0 20 300 150 –55 to +150 Unit V V V mA mW °C °C Notes: 3. Value on the glass epoxy board (50 mm × 40 mm × 1 mm ). Rev.1.00, Jun.14.2004, page 1 of 8 BB505M Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss Crss PG NF Min 6 +6 +6 — — 0.5 0.5 7 28 1.4 1.0 — 19 — Typ — — — — — 0.7 0.7 11 33 1.75 1.4 0.03 24 1.5 Max — — — +100 +100 1.0 1.0 15 38 2.1 1.8 0.05 29 2.2 Unit V V V nA nA V V mA mS pF pF pF dB dB Test Conditions ID = 200 µA, VG1S = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = +10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V, ID = 100 µA VDS = 5 V, VG1S = 5 V, ID = 100 µA VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ, f = 1 MHz VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ, f = 900 MHz Bias Circuit for Operating Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG) VG2 Gate 2 Gate 1 RG VG1 Drain A ID Source Rev.1.00, Jun.14.2004, page 2 of 8 BB505M 900 MHz Power Gain, Noise Figure Test Circuit VG1 VG2 C4 C5 VD C6 R1 R2 C3 G2 R3 D L3 RFC Output (50 Ω) L4 Input (50 Ω) L1 L2 G1 S C1 C2 C1, C2 C3 C4 to C6 R1 R2 R3 : : : : : : Variable Capacitor (10 pF MAX) Disk Capacitor (1000 pF) Air Capacitor (1000 pF) 220 kΩ 47 kΩ 4.7 kΩ L1: 10 10 L2: 26 3 3 (φ1mm Copper wire) Unit : mm 8 21 L4: 29 10 7 7 10 L3: 18 RFC : φ1mm Copper wire with enamel 4 turns inside dia 6 mm Rev.1.00, Jun.14.2004, page 3 of 8 BB505M Main Characteristics Maximum Channel Power Dissipation Curve 400 Typical Output Characteristics 20 VG2S = 4 V VG1 = VDS = R G Channel Power Dissipation Pch* (mW) 12 15 200 10 100 5 0 50 100 150 Ambient Temperature Ta (°C) Drain Current vs. Gate1 Voltage 200 0 1 2 3 4 5 Drain to Source Voltage VDS (V) Forward Transfer Admittance vs. Gate1 Voltage * Value on the glass epoxy board (50mm × 40mm × 1mm) |yfs| (mS) 20 VDS = 5 V RG = 220 kΩ ID (mA) 50 Forward Transfer Admittance 15 4V VDS = 5 V VG1 = 5V 40 RG = 220 kΩ f = 1 kHz 30 18 kΩ 20 2Ω k 0 27 kΩ 0 33 Drain Current 10 3V 2V 20 5 VG2S = 1 V 10 VG2S = 1 V 0 1 2 3 4 Gate1 Voltage VG1 (V) 5 0 1 2 3 4 Gate1 Voltage VG1 (V) Input Capacitance vs. Gate2 to Source Voltage 0 kΩ 0 4V 3V 2V kΩ 300 Drain Current ID (mA) 15 0k Ω 5 Drain Current vs. Gate Resistance 20 Input Capacitance Ciss (pF) 4 VDS = 5 V VG1 = 5 V VG2S = 4 V Drain Current ID (mA) 15 3 10 2 VDS = 5 V VG1 = 5 V RG = 220 kΩ f = 1 MHz 0 2 1 3 4 Gate2 to Source Voltage VG2S (V) 5 1 0 100 200 500 Gate Resistance RG (kΩ) 1000 0 Rev.1.00, Jun.14.2004, page 4 of 8 BB505M Power Gain vs. Gate Resistance 50 VDS = 5 V VG1 = 5 V 40 VG2S = 4 V f = 900 MHz 30 4 VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz Noise Figure vs. Gate Resistance Power Gain PG (dB) NF (dB) Noise Figure 3 2 20 10 0 100 1 0 200 500 Gate Resistance RG (kΩ) Power Gain vs. Gate2 to Source Voltage VDS = 5 V VG1 = 5 V RG = 220 kΩ f = 900 MHz 1000 100 200 500 1000 Gate Resistance RG (kΩ) Noise Figure vs. Gate2 to Source Voltage 5 25 Noise Figure NF (dB) Power Gain PG (dB) 20 4 15 3 10 2 VDS = 5 V VG1 = 5 V RG = 220 kΩ f = 900 MHz 1 2 3 VG2S (V) 4 5 1 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage 0 Gate2 to Source Voltage 40 Gain Reduction GR (dB) 30 VDS = 5 V VG1 = 5 V RG = 220 kΩ f = 900MHz 20 10 0 1 2 3 4 Gate2 to Source Voltage VG2S (V) Rev.1.00, Jun.14.2004, page 5 of 8 BB505M S21 Parameter vs. Frequency 90° 2 .4 3 .2 4 5 10 0 .2 .4 .6 .8 1 1.5 2 3 45 10 -10 -.2 -3 -.4 -.6 -.8 -1.5 -2 -120° -90° -60° -1 -5 -4 180° 0° 150° 30° 120° S11 Parameter vs. Frequency .8 .6 1 1.5 Scale: 1 / div. 60° -150° -30° Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ, Zo = 50 Ω 50 to 1000 MHz (50 MHz Step) Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ, Zo = 50 Ω 50 to 1000 MHz (50 MHz Step) S12 Parameter vs. Frequency Scale: 0.02 / div. 90° 120° 60° S22 Parameter vs. Frequency .8 .6 .4 3 1 1.5 2 150° 30° .2 4 5 10 180° 0° 0 .2 .4 .6 .8 1 1.5 2 3 45 10 -10 -.2 -150° -30° -3 -.4 -120° -90° -60° -.6 -.8 -1.5 -2 -1 -5 -4 Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ, Zo = 50 Ω 50 to 1000 MHz (50 MHz Step) Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 220 kΩ, Zo = 50 Ω 50 to 1000 MHz (50 MHz Step) Rev.1.00, Jun.14.2004, page 6 of 8 BB505M S parameter (VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 200 kΩ, ZO = 50 Ω) S11 f (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 MAG 0.991 0.991 0.993 0.983 0.977 0.969 0.962 0.952 0.944 0.929 0.914 0.897 0.881 0.863 0.842 0.819 0.797 0.775 0.746 0.721 ANG -2.4 -5.9 -8.9 -11.9 -15.3 -18.5 -21.6 -25.2 -28.7 -32.2 -36.0 -40.0 -44.2 -48.3 -52.7 -57.3 -62.0 -66.8 -71.8 -76.9 MAG 3.55 3.58 3.58 3.56 3.59 3.50 3.51 3.52 3.52 3.51 3.51 3.50 3.49 3.47 3.45 3.41 3.37 3.33 3.27 3.20 S21 ANG 178.2 172.9 170.2 165.9 162.6 155.5 151.0 146.9 142.6 138.2 133.4 129.0 124.2 119.4 114.5 109.7 104.9 99.9 94.9 90.2 MAG 0.009 0.011 0.002 0.004 0.006 0.008 0.006 0.007 0.008 0.008 0.008 0.008 0.010 0.010 0.008 0.008 0.008 0.008 0.007 0.007 -64.5 18.0 61.4 77.7 87.6 87.8 94.6 80.9 87.1 78.1 74.7 84.8 72.6 67.5 78.7 82.1 85.3 95.6 97.4 122.8 S12 ANG MAG 0.976 0.995 0.990 0.986 0.986 0.990 0.984 0.982 0.977 0.973 0.968 0.963 0.957 0.950 0.943 0.939 0.931 0.924 0.916 0.909 S22 ANG -1.8 -3.1 -5.2 -6.5 -8.2 -12.9 -15.1 -17.3 -19.5 -21.8 -24.0 -26.1 -28.2 -30.4 -32.6 -34.6 -36.6 -38.7 -40.6 -42.4 Rev.1.00, Jun.14.2004, page 7 of 8 BB505M Package Dimensions As of January, 2003 Unit: mm 2.95 ± 0.2 1.9 ± 0.2 0.95 0.95 0.4 – 0.05 + 0.1 0.4 – 0.05 + 0.1 0.65 0.16 – 0.06 + 0.1 1.5 ± 0.15 + 0.2 – 0.6 0 – 0.1 0.95 0.85 1.8 ± 0.2 0.3 1.1 – 0.1 + 0.2 0.65 0.4 – 0.05 + 0.1 0.1 0.6 + 0.05 – 2.8 Package Code JEDEC JEITA Mass (reference value) MPAK-4 — Conforms 0.013 g Ordering Information Part Name BB505MES3000 Quantity Taping Shipping Container Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.1.00, Jun.14.2004, page 8 of 8 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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