DATASHEET
CA3130, CA3130A
FN817
Rev.6.00
Aug 1, 2005
15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output
CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS transistors in the input stage
results in common-mode input-voltage capability down to
0.5V below the negative-supply terminal, an important
attribute in single-supply applications.
A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.
The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (2.5V to 8V). They can be phase
compensated with a single external capacitor, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.
• The CA3130A offers superior input characteristics over
those of the CA3130.
Features
• MOSFET Input Stage Provides:
- Very High ZI = 1.5 T (1.5 x 1012) (Typ)
- Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . = 2pA (Typ) at 5V Operation
• Ideal for Single-Supply Applications
• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ground-Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long-Duration Timers/Monostables
• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)
• High-Input-Impedance Wideband Amplifiers
Ordering Information
PART NO.
(BRAND)
CA3130AE
CA3130AM
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld SOIC
PKG.
DWG. #
E8.3
M8.15
(3130A)
CA3130AM96
-55 to 125
(3130A)
CA3130AMZ
-55 to 125
(3130AZ) (Note)
CA3130AMZ96
-55 to 125
(3130AZ) (Note)
CA3130E
CA3130EZ
(Note)
CA3130M
-55 to 125
-55 to 125
-55 to 125
8 Ld SOIC
Tape and Reel
8 Ld SOIC
(Pb-free)
8 Ld SOIC
Tape and Reel (Pb-free)
8 Ld PDIP
8 Ld PDIP*
(Pb-free)
8 Ld SOIC
M8.15
-55 to 125
(3130)
CA3130MZ
-55 to 125
(3130MZ) (Note)
CA3130MZ96
(3130MZ)
-55 to 125
• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
• Peak Detectors
• Single-Supply Full-Wave Precision Rectifiers
M8.15
M8.15
• Photo-Diode Sensor Amplifiers
Pinout
CA3130, CA3130A
(PDIP, SOIC)
TOP VIEW
E8.3
E8.3
M8.15
(3130)
CA3130M96
• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)
8 Ld SOIC
M8.15
Tape and Reel
8 Ld SOIC
M8.15
(Pb-free)
8 Ld SOIC
M8.15
Tape and Reel (Pb-free)
OFFSET
NULL
INV.
INPUT
NON-INV.
INPUT
1
V-
4
8
STROBE
2
-
7
V+
3
+
6
OUTPUT
5
OFFSET
NULL
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not
intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN817 Rev.6.00
Aug 1, 2005
Page 1 of 17
CA3130, CA3130A
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short-Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2)
JA (oC/W) JC (oC/W)
PDIP Package* . . . . . . . . . . . . . . . . . .
115
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified
SYMBOL
TEST
CONDITIONS
VS = 7.5V
CA3130
CA3130A
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-
8
15
-
2
5
mV
-
10
-
-
10
-
V/oC
Input Offset Voltage
|VIO|
Input Offset Voltage
Temperature Drift
VIO/T
Input Offset Current
|IIO|
VS = 7.5V
-
0.5
30
-
0.5
20
pA
II
VS = 7.5V
-
5
50
-
5
30
pA
50
320
-
50
320
-
kV/V
94
110
-
94
110
-
dB
CMRR
70
90
-
80
90
-
dB
VICR
0
-0.5 to 12
10
0
-0.5 to 12
10
V
-
32
320
-
32
150
V/V
Input Current
Large-Signal Voltage Gain
Common-Mode
Rejection Ratio
Common-Mode Input
Voltage Range
Power-Supply
Rejection Ratio
Maximum Output Voltage
Maximum Output Current
Supply Current
FN817 Rev.6.00
Aug 1, 2005
AOL
VIO/VS
VO = 10VP-P
RL = 2k
VS = 7.5V
VOM+
RL = 2k
12
13.3
-
12
13.3
-
V
VOM-
RL = 2k
-
0.002
0.01
-
0.002
0.01
V
VOM+
RL =
14.99
15
-
14.99
15
-
V
VOM-
RL =
-
0
0.01
-
0
0.01
V
IOM+ (Source) at VO = 0V
12
22
45
12
22
45
mA
IOM- (Sink) at VO = 15V
12
20
45
12
20
45
mA
I+
VO = 7.5V,
RL =
-
10
15
-
10
15
mA
I+
VO = 0V,
RL =
-
2
3
-
2
3
mA
Page 2 of 17
CA3130, CA3130A
Electrical Specifications
Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified
PARAMETER
SYMBOL
Input Offset Voltage Adjustment Range
TEST CONDITIONS
10k Across Terminals 4 and 5 or
4 and 1
CA3130,
CA3130A
UNITS
22
mV
1.5
T
Input Resistance
RI
Input Capacitance
CI
f = 1MHz
4.3
pF
Equivalent Input Noise Voltage
eN
BW = 0.2MHz, RS = 1M
(Note 3)
23
V
Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability 47pF Required.)
fT
CC = 0
15
MHz
CC = 47pF
4
MHz
Slew Rate:
SR
Open Loop
CC = 0
30
V/s
Closed Loop
CC = 56pF
10
V/s
0.09
s
10
%
1.2
s
Transient Response:
Rise Time
tr
Overshoot
OS
Settling Time (To
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