CSPU877ANLG8

IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPU877A DESCRIPTION: FEATURES: The CSPU877A is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500μA. The CSPU877A requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPU877A, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPU877A is available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details. • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 340MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 52-Ball VFBGA and 40-pin VFQFPN packages APPLICATIONS: • Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver • Along with SSTU32864/65/66, DDR2 register, provides complete solution for DDR2 DIMMs FUNCTIONAL BLOCK DIAGRAM OE OS AVDD LD or OE POWER DOWN AND LD, OS, or OE TEST MODE PLL BYPASS LOGIC LD Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK Y5 CLK Y5 10KΩ - 100KΩ PLL Y6 Y6 FBIN Y7 FBIN Y7 Y8 Y8 Y9 NOTE: The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK. Y9 FBOUT The IDT logo is a registered trademark of Integrated Device Technology, Inc. FBOUT COMMERCIAL TEMPERATURE RANGE OCTOBER 2006 1 c 2006 Integrated Device Technology, Inc. DSC-6495/8 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION Y8 Y8 GND GND Y9 VDDQ NB GND Y9 VDDQ NB GND Y4 VDDQ GND GND Y4 Y3 Y3 J K 6 Y6 Y6 Y7 Y7 FBIN FBIN FBOUT FBOUT 5 Y5 GND GND OS VDDQ OE VDDQ 4 Y5 GND NB VDDQ NB NB 3 Y0 GND NB VDDQ NB NB 2 Y0 GND GND 1 Y1 Y1 Y2 Y2 CLK CLK A B C D E F VDDQ VDDQ VDDQ AGND AVDD H G VFBGA TOP VIEW 52 BALL VFBGA PACKAGE LAYOUT 0.65mm 6 5 TOP VIEW 4 3 2 1 A A B C D B C D E E 1 2 3 4 5 6 2 F G H F G H J J K K IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1,2) Y0 Y0 VDDQ Y5 Y5 Y6 Y6 VDDQ 38 36 35 34 33 32 31 39 37 Y1 Y1 40 PIN CONFIGURATION, CONT. VDDQ 1 30 Y7 Y2 2 29 Y7 Y2 3 28 VDDQ CLK 4 27 FBIN CLK 5 26 FBIN GND 18 19 20 Y8 VDDQ OS Y8 21 17 10 Y9 GND 16 OE Y9 VDDQ 22 15 23 9 VDDQ 8 VDDQ 14 AVDD Y4 FBOUT 13 24 Y4 7 11 FBOUT AGND 12 25 Y3 6 Y3 VDDQ Symbol Rating VDDQ, AVDD VI(3) VO(3) Supply Voltage Range Input Voltage Range Voltage range applied to any output in the high or low state Input clamp current IIK (VI