DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
General Description
DA7280 is a linear resonant actuator (LRA) and eccentric rotating mass (ERM) haptic driver offering
automatic closed-loop LRA resonant frequency tracking. The feature guarantees consistency across
LRA production tolerances, operating temperature, aging, and mechanical coupling. DA7280 offers
wideband operation that fully utilizes the capabilities of newer wideband and multi-directional LRAs.
The differential output drive architecture and continuous actuator motion sensing enable efficient,
calibration-free playback and minimize software complexity. Featuring wake-up on General Purpose
Input (GPI) sequence triggers and/or I2C activity, DA7280 automatically returns to a low quiescent
current state (typically 0.36 µA) between playbacks. At only 20 % of the idle current of the nearest
alternative solution, DA7280 significantly extends battery life in mobile systems.
To reduce system complexity, an integrated Waveform Memory allows haptic sequences to be preloaded to DA7280. Independent sequences can be triggered, with low-latency (0.75 ms), by up to
three separate input pins without host interaction. Haptic sequences can also be streamed to
DA7280 from an external source via I2C or pulse width modulated (PWM) signal.
DA7280 actively monitors the back electromotive force (BEMF) while continuously driving and
applies closed-loop Active Acceleration and Rapid Stopping for sharper clicks and a higher fidelity
user experience. This offers significant advantages over existing solutions that need to move into a
high-impedance state during drive to measure the BEMF, which adds a considerable amount of
inactive time to the sequence and lowers the effective click strength for a given LRA.
Key Features
■
■
■
■
■
■ No software requirements with embedded
LRA or ERM drive capability
Automatic LRA resonant frequency tracking
Wideband LRA support
I2C and PWM input streaming
Low latency (0.75 ms) I2C/GPI wake-up
from low power consumption IDLE state,
IQ = 0.36 µA
■ Ultra-low latency (0.15 ms) wake-up from
operation
■ Differential PWM output drive
■ Current driven system to deliver constant
actuator power
■ Configurable EMI suppression
■ Automatic short circuit protection
■ Ultra-low power consumption, IQ = 0.36 µA,
STANDBY state, IQ = 0.8 mA
with state retention in IDLE state
■ Three GPI pins for triggering of up to six
■ Supply monitoring, reporting, and automatic
independent haptic sequences
output limiting
■ On-board Waveform Memory with amplitude, ■ Open- and closed-loop modes
time, and frequency control
■ Custom wave drive support
■ Active Acceleration and Rapid Stop
■ Small solution footprint requiring only one
technology for high-fidelity haptic feedback
decoupling capacitor in both WLCSP and QFN
■ Actuator diagnostics and fault handling
VDDIO
■
■
■
■
■
■
SCL
SDA
Smartphones, wearables, and hearables
I2C
VDD
References
nIRQ
Computer peripherals
Gaming
Automotive and industrial
GPI_0 / PWM
Virtual and augmented reality controllers
GPI_1
Television remote control
GPI_2
Resonant
Frequency
Tracking,
Active
Acceleration,
Rapid Stop,
and
Waveform
Memory
Battery
Monitor
OverTemperature
Protection
BEMF Sensing and
Actuator Diagnostics
OUTP
ERC Driver
Regulation
Loop
Applications
Short Circuit
Protection
LRA/
ERM
ERC Driver
OUTN
DA7280
GND
Datasheet
CFR0011-120-00
Revision 3.0
1 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
System Diagrams
VDDIO
VBAT
VDDIO
VBAT
VDDIO
VDD
VDDIO
VDD
OUTP
OUTP
SDA
SCL
nIRQ
SDA
SCL
nIRQ
Host
LRA/
ERM
DA7280
GPI_0/PWM
GPI_1
GPI_2
DA7280
Host
GPI_0/PWM
GPI_1
GPI_2
OUTN
OUTN
GND
GND
GPI and I2C
I2C Only
VDDIO
VBAT
VDDIO
VBAT
VDDIO
VDD
VDDIO
VDD
OUTP
OUTP
SDA
SCL
nIRQ
SDA
SCL
nIRQ
Host
LRA/
ERM
LRA/
ERM
DA7280
GPI_0/PWM
GPI_1
GPI_2
DA7280
Host
GPI_0/PWM
GPI_1
GPI_2
OUTN
LRA/
ERM
OUTN
GND
GND
PWM Only
Embedded Operation
VBAT
External Boost
up to 5.5V
VDDIO
VBAT
VDDIO
VDDIO
VDD
VDDIO
VBST
VDD
OUTP
OUTP
Host
(startup
only)
Sensor
Hub
or
Button
Press
Detect
SDA
SCL
nIRQ
SDA
SCL
nIRQ
LRA/
ERM
DA7280
GPI_0/PWM
GPI_1
GPI_2
Host
DA7280
GPI_0/PWM
GPI_1
GPI_2
OUTN
GND
LRA/
ERM
OUTN
GND
Embedded Operation
No Host
External Boost
Operation
Figure 1: System Diagrams
Datasheet
CFR0011-120-00
Revision 3.0
2 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 1
System Diagrams ................................................................................................................................ 2
Figures .................................................................................................................................................. 4
Tables ................................................................................................................................................... 4
Legal ..................................................................................................................................................... 6
Product Family ..................................................................................................................................... 6
1
Terms and Definitions ................................................................................................................... 7
2
Block Diagram ............................................................................................................................... 8
3
Pinout ............................................................................................................................................. 9
4
Characteristics ............................................................................................................................ 10
4.1 Absolute Maximum Ratings ................................................................................................ 10
4.2 Recommended Operating Conditions ................................................................................. 10
4.3 Electrical Characteristics ..................................................................................................... 11
4.4 Timing Characteristics......................................................................................................... 12
4.5 Thermal Characteristics ...................................................................................................... 13
5
Functional Description ............................................................................................................... 14
5.1 Features Description ........................................................................................................... 14
5.2 Functional Modes ................................................................................................................ 19
5.3 Resonant Frequency Tracking ............................................................................................ 23
5.4 Active Acceleration and Rapid Stop .................................................................................... 23
5.5 Wideband Frequency Control ............................................................................................. 25
5.6 Device Configuration and Playback .................................................................................... 25
5.7 Advanced Operation ........................................................................................................... 34
5.8 Waveform Memory .............................................................................................................. 42
5.9 General Data Format .......................................................................................................... 48
5.10 I2C Control Interface ............................................................................................................ 51
6
Register Overview ....................................................................................................................... 54
6.1 Register Map ....................................................................................................................... 54
6.2 Register Descriptions .......................................................................................................... 56
7
Package Information ................................................................................................................... 71
7.1 WLCSP Package Outline .................................................................................................... 71
7.2 QFN Package Outline ......................................................................................................... 72
7.3 Moisture Sensitivity Level.................................................................................................... 73
7.4 WLCSP Handling ................................................................................................................ 73
7.5 Soldering Information .......................................................................................................... 73
8
Ordering Information .................................................................................................................. 74
9
Application Information .............................................................................................................. 74
10 Layout Guidelines ....................................................................................................................... 75
Datasheet
CFR0011-120-00
Revision 3.0
3 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Figures
Figure 1: System Diagrams ................................................................................................................... 2
Figure 2: DA7280 Block Diagram .......................................................................................................... 8
Figure 3: DA7280 Pinout Diagrams (Top View) for WLCSP (Left) and QFN (Right) ............................ 9
Figure 4: I2C Interface Timing .............................................................................................................. 12
Figure 5: LRA Output Acceleration Swept in Frequency with Constant Power Input Signal .............. 14
Figure 6: Narrowband and Wideband LRA Response across Frequency .......................................... 15
Figure 7: Dual Mode LRA Response across Frequency ..................................................................... 15
Figure 8: System State Diagram ......................................................................................................... 19
Figure 9: Example PWM Inputs with ACCELERATION_EN = 0 ......................................................... 21
Figure 10: LRA Single Step Drive without Acceleration and Rapid Stop ............................................ 24
Figure 11: LRA Single Step with Acceleration and Rapid Stop........................................................... 24
Figure 12: Simple Drive (Top) versus Active Acceleration and Rapid Stop Enabled (Bottom) ........... 24
Figure 13: Operation in DRO Mode ..................................................................................................... 28
Figure 14: Operation in PWM Mode .................................................................................................... 29
Figure 15: Operation in RTWM Mode ................................................................................................. 30
Figure 16: Operation in ETWM Mode .................................................................................................. 32
Figure 17: Output Voltage and Current for Different AMP_PID_EN Values ....................................... 35
Figure 18: Custom Wave Point Numbering ......................................................................................... 36
Figure 19: Half-Period Control in DRO Mode ...................................................................................... 37
Figure 20: Polarity Timing Relationship ............................................................................................... 38
Figure 21: Equivalent Electrical Model of an Actuator ........................................................................ 38
Figure 22: Automatic Output Limiting .................................................................................................. 40
Figure 23: Coin ERM Physical and Electrical Summary ..................................................................... 41
Figure 24: Waveform Memory Structure ............................................................................................. 42
Figure 25: Snippet Ramp and Step with ACCELERATION_EN = 1 ................................................... 44
Figure 26: Snippet Example ................................................................................................................ 44
Figure 27: Command Structure for a Single Frame ............................................................................ 45
Figure 28: Sequence Structure ........................................................................................................... 46
Figure 29: Waveform Memory Example .............................................................................................. 47
Figure 30: Overview of Data Formats with Acceleration Disabled ...................................................... 48
Figure 31: Overview of Data Formats with Acceleration Enabled ....................................................... 49
Figure 32: Schematic of the I2C Control Interface Bus........................................................................ 51
Figure 33: I2C START and STOP Conditions ...................................................................................... 51
Figure 34: I2C Byte Write (SDA line) ................................................................................................... 52
Figure 35: Examples of the I2C Byte Read (SDA line) ........................................................................ 52
Figure 36: Examples of I2C Page Read (SDA line) ............................................................................. 52
Figure 37: I2C Page Write (SDA line) .................................................................................................. 53
Figure 38: I2C Repeated Write (SDA line) ........................................................................................... 53
Figure 39: WLCSP Package Outline Drawing ..................................................................................... 71
Figure 40: QFN Package Outline Drawing .......................................................................................... 72
Figure 41: External Components Diagram .......................................................................................... 74
Figure 42: WLCSP Example PCB Layout ........................................................................................... 75
Figure 43: QFN Example PCB Layout ................................................................................................ 75
Tables
Table 1: DA728x Feature Comparison .................................................................................................. 6
Table 2: Pin Description ........................................................................................................................ 9
Table 3: Pin Type Definition .................................................................................................................. 9
Table 4: Absolute Maximum Ratings ................................................................................................... 10
Table 5: Recommended Operating Conditions ................................................................................... 10
Table 6: Current Consumption ............................................................................................................ 11
Table 7: Electrical Characteristics ....................................................................................................... 11
Table 8: Timing Characteristics ........................................................................................................... 12
Datasheet
CFR0011-120-00
Revision 3.0
4 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 9: I2C Interface Timing Requirements ....................................................................................... 12
Table 10: WLCSP Thermal Ratings .................................................................................................... 13
Table 11: QFN Thermal Ratings ......................................................................................................... 13
Table 12: Operating Modes ................................................................................................................. 20
Table 13: Haptics Event Flag Descriptions ......................................................................................... 33
Table 14: Default CUSTOM_WAVE_GEN_COEFFx Settings ............................................................ 36
Table 15: LOOP_FILT_CAP_TRIM Register Trim Settings ................................................................ 38
Table 16: LOOP_FILT_RES_TRIM Register Trim Settings ................................................................ 39
Table 17: PWL Byte Structure ............................................................................................................. 43
Table 18: Bit Definitions for Frame Parameters .................................................................................. 45
Table 19: Register Map ....................................................................................................................... 54
Table 20: CHIP_REV (0x0000) ........................................................................................................... 56
Table 21: IRQ_EVENT1 (0x0003) ....................................................................................................... 56
Table 22: IRQ_EVENT_WARNING_DIAG (0x0004) .......................................................................... 56
Table 23: IRQ_EVENT_SEQ_DIAG (0x0005) .................................................................................... 57
Table 24: IRQ_STATUS1 (0x0006) ..................................................................................................... 57
Table 25: IRQ_MASK1 (0x0007) ......................................................................................................... 57
Table 26: CIF_I2C1 (0x0008) .............................................................................................................. 58
Table 27: FRQ_LRA_PER_H (0x000A) .............................................................................................. 58
Table 28: FRQ_LRA_PER_L (0x000B) ............................................................................................... 59
Table 29: ACTUATOR1 (0x000C) ....................................................................................................... 59
Table 30: ACTUATOR2 (0x000D) ....................................................................................................... 59
Table 31: ACTUATOR3 (0x000E) ....................................................................................................... 59
Table 32: CALIB_V2I_H (0x000F) ....................................................................................................... 60
Table 33: CALIB_V2I_L (0x0010) ....................................................................................................... 60
Table 34: CALIB_IMP_H (0x0011) ...................................................................................................... 60
Table 35: CALIB_IMP_L (0x0012) ...................................................................................................... 61
Table 36: TOP_CFG1 (0x0013) .......................................................................................................... 61
Table 37: TOP_CFG2 (0x0014) .......................................................................................................... 61
Table 38: TOP_CFG3 (0x0015) .......................................................................................................... 62
Table 39: TOP_CFG4 (0x0016) .......................................................................................................... 62
Table 40: TOP_INT_CFG1 (0x0017) .................................................................................................. 62
Table 41: TOP_INT_CFG6_H (0x001C) ............................................................................................. 62
Table 42: TOP_INT_CFG6_L (0x001D) .............................................................................................. 63
Table 43: TOP_INT_CFG7_H (0x001E) ............................................................................................. 63
Table 44: TOP_INT_CFG7_L (0x001F) .............................................................................................. 63
Table 45: TOP_INT_CFG8 (0x0020) .................................................................................................. 63
Table 46: TOP_CTL1 (0x0022) ........................................................................................................... 63
Table 47: TOP_CTL2 (0x0023) ........................................................................................................... 64
Table 48: SEQ_CTL1 (0x0024) ........................................................................................................... 64
Table 49: SWG_C1 (0x0025) .............................................................................................................. 64
Table 50: SWG_C2 (0x0026) .............................................................................................................. 65
Table 51: SWG_C3 (0x0027) .............................................................................................................. 65
Table 52: SEQ_CTL2 (0x0028) ........................................................................................................... 65
Table 53: GPI_0_CTL (0x0029) .......................................................................................................... 65
Table 54: GPI_1_CTL (0x002A) .......................................................................................................... 66
Table 55: GPI_2_CTL (0x002B) .......................................................................................................... 66
Table 56: MEM_CTL1 (0x002C) ......................................................................................................... 66
Table 57: MEM_CTL2 (0x002D) ......................................................................................................... 66
Table 58: ADC_DATA_H1 (0x002E) ................................................................................................... 66
Table 59: ADC_DATA_L1 (0x002F) .................................................................................................... 67
Table 60: POLARITY (0x0043)............................................................................................................ 67
Table 61: LRA_AVR_H (0x0044) ........................................................................................................ 67
Table 62: LRA_AVR_L (0x0045) ......................................................................................................... 67
Table 63: FRQ_LRA_PER_ACT_H (0x0046) ..................................................................................... 67
Table 64: FRQ_LRA_PER_ACT_L (0x0047) ...................................................................................... 68
Table 65: FRQ_PHASE_H (0x0048) ................................................................................................... 68
Table 66: FRQ_PHASE_L (0x0049) ................................................................................................... 68
Table 67: FRQ_CTL (0x004C) ............................................................................................................ 68
Datasheet
CFR0011-120-00
Revision 3.0
5 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 68: TRIM3 (0x005F) .................................................................................................................. 68
Table 69: TRIM4 (0x0060)................................................................................................................... 69
Table 70: TRIM6 0x(0062)................................................................................................................... 69
Table 71: D2602_TOP_CFG5 (0x006E) ............................................................................................. 69
Table 72: IRQ_EVENT_ACTUATOR_FAULT (0x0081) ..................................................................... 69
Table 73: IRQ_STATUS2 (0x0082) ..................................................................................................... 70
Table 74: IRQ_MASK2 (0x0083) ......................................................................................................... 70
Table 75: SNP_MEM_xx (0x0084 to 0x00E7)..................................................................................... 70
Table 76: MSL Classification ............................................................................................................... 73
Table 77: Ordering Information ........................................................................................................... 74
Legal
NOTWITHSTANDING ANYTHING TO THE CONTRARY IN THIS DOCUMENT OR IN ANY OTHER
AGREEMENT, CUSTOMER ACKNOWLEDGES THAT THE PRODUCTS ARE PROVIDED
WITHOUT ANY WARRANTY OF NON-INFRINGEMENT, AND THAT IF ANY LICENSE OR RIGHT
IS REQUIRED TO BE OBTAINED FROM ANY THIRD PARTY, THIS RESPONSIBILITY SHALL
REST SOLELY WITH CUSTOMER.
Product Family
Table 1: DA728x Feature Comparison
Feature
DA7280
DA7281
DA7282
DA7283
OFF state via EN pin
No
No
Yes
Yes
OFF state current
N/A
N/A
5 nA
5 nA
IDLE state current
360 nA
360 nA
680 nA
680 nA
3
1
3
3
Yes
Yes
Yes
No
Multiple I2C addressing
No
Yes
No
N/A
Operation without a host
No
No
No
Yes
Number of GPI sequence trigger pins
I2 C
interface
Datasheet
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© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
1
Terms and Definitions
BEMF
CDM
DMA
DRO
EMI
ERC
ERM
ESD
ETWM
FET
GND
GPI
Half-period
HBM
IRQs
LRA
OTP
PCB
PID
PoR
PWL
PWM
QFN
RC
RTWM
WLCSP
Datasheet
CFR0011-120-00
Back electromotive force
Charged device model
Dual mode actuator
Direct register override
Electromagnetic interference
Edge rate control
Eccentric rotating mass
Electrostatic discharge
Edge triggered Waveform Memory
Field-effect transistor
Ground
General purpose input
One half of the LRA resonant frequency period. For example, if fLRA = 200 Hz,
one half-period is 2.5 ms.
Human body model
Interrupt requests
Linear resonant actuator
One time programmable
Printed circuit board
Proportional-Integral-Derivative
Power-on reset
Piecewise linear
Pulse width modulated
Quad flat no leads
Resistor-capacitor
Register triggered Waveform Memory
Wafer level chip scale package
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Block Diagram
VDD
VDDIO
SCL
SDA
I2C
BEMF Sensing and
Actuator Diagnostics
nIRQ
GPI_0 /
PWM
GPI_1
OverTemperature
Protection
Battery
Monitor
Oscillator and
References
Frequency
Tracking,
Active
Acceleration,
Rapid Stop,
and
Waveform
Memory
Short Circuit
Protection
DA7280
GPI_2
Regulation Loop
2
p-Side
Output
Driver with
ERC
n-Side
Output
Driver with
ERC
OUTP
LRA/
ERM
OUTN
GND
Figure 2: DA7280 Block Diagram
Datasheet
CFR0011-120-00
Revision 3.0
8 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Pinout
Pin 1
A
SCL
B
11
10
GPI_2
GPI_2
1
9
VDDIO
GPI_1
2
8
OUTN
GPI_0/
PWM
3
7
GND_2
VDDIO
C
GPI_0/PWM
OUTN
GND_2
VDD
OUTP
GND_1
4
5
6
GND_1
GPI_1
12
SDA
OUTP
nIRQ
SDA
3
SCL
2
nIRQ
1
VDD
3
D
Top view
Power
Digital
signal
Analog
signal
Power
Ground
Digital
signal
Top view
Analog
signal
Ground
Figure 3: DA7280 Pinout Diagrams (Top View) for WLCSP (Left) and QFN (Right)
Table 2: Pin Description
Pin No.
WLCSP
Pin No.
QFN
Pin Name
Type
(Table 3)
Description
A1
12
nIRQ
DO
Interrupt request line to host, open-drain, active low, connect
to VDDIO via external pull-up resistor
A2
11
SCL
DI
I2C clock input
A3
10
SDA
DIO
I2C data input/output, open-drain, connect to VDDIO via
external pull-up resistor
B1
2
GPI_1
DI
GPI sequence trigger 1
B2
1
GPI_2
DI
GPI sequence trigger 2
B3
9
VDDIO
PWR
Supply for digital I/O interfaces
C1
3
GPI_0/PWM
DI
GPI sequence trigger 0, or PWM input
C2
8
OUTN
AO
Haptic driver negative output
C3
7
GND_2
GND
Ground
D1
4
VDD
PWR
Haptics power supply; decouple to GND_1
D2
5
OUTP
AO
Haptic driver positive output
D3
6
GND_1
GND
Ground
Table 3: Pin Type Definition
Pin Type
Description
Pin Type
Description
DI
Digital input
AO
Analog output
DO
Digital output
PWR
Power
DIO
Digital input/output
GND
Ground
Datasheet
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30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
4
Characteristics
4.1
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, so functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Table 4: Absolute Maximum Ratings
Parameter
Description
VDD
Conditions
Min
Max
Unit
Haptics power supply
-0.3
6
V
VDDIO
Haptics IO supply
-0.3
6
V
VOUTN
Haptic driver negative output
-0.3
6
V
VOUTP
Haptic driver positive output
-0.3
6
V
Referenced to GND
VnIRQ
Interrupt request line to host
-0.3
6
V
VSCL
I2C clock input
-0.3
6
V
VSDA
I2 C
data input/output
-0.3
6
V
VGPI
General purpose inputs
-0.3
6
V
TA
Operating ambient
temperature
-40
85
°C
TJ
Operating junction
temperature
-40
125
°C
TSTG
Storage temperature
-65
150
°C
ESDHBM
ESD protection
Human Body Model (HBM)
All non-exposed pins
4
kV
ESDCDM
ESD protection
Charged Device Model
(CDM)
1
kV
4.2
Recommended Operating Conditions
Unless otherwise noted, the parameters listed in Table 5 are valid for TA = 25 ºC, VDD = 3.8 V, and
VDDIO = 1.8 V.
Table 5: Recommended Operating Conditions
Parameter
Description
VDD
Min
Typ
Max
Unit
Haptics power supply
(battery or regulated rail)
2.8
3.8
5.5
V
VDDIO
Haptics IO supply (Note 1)
1.35
1.8
5.5
V
ZLD
Load impedance
50
Ω
CLD
Capacitance to ground on
OUTP and OUTN
1
nF
fLRA
LRA resonant frequency
Frequency tracking enabled
50
300
Hz
fLRA_OL
LRA resonant frequency,
open-loop
Frequency tracking disabled
25
1000
Hz
Note 1
Conditions
4
During device operation VDDIO must be ≤ VDD if GPI_0, GPI_1, and GPI_2 are not grounded.
Datasheet
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30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
4.3
Electrical Characteristics
Unless otherwise noted, the parameters listed in Table 6 and Table 7 are valid for TA = 25 ºC,
VDD = 3.8 V, and VDDIO = 1.8 V.
Table 6: Current Consumption
Parameter
Description
Conditions
IQ_IDLE
System VDD current in
IDLE state
IQ_VDDIO
Min
Typ
Max
Unit
System waiting for
playback request
0.36
1
μA
VDDIO pin current
No I/O or nIRQ activity
0.13
0.5
μA
IQ_STANDBY
System VDD current in
STANDBY state
System waiting for
playback request
0.8
1
mA
IQ_NO_LD
System VDD current with
no load
High-impedance load >
10 MΩ, H-bridge switching
1.35
1.5
mA
Table 7: Electrical Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
ISHRT
Short circuit protection
threshold
Short to GND or VDD
400
500
600
mA
IOUT_MAX
Maximum drive current
250
500
(Note 1)
mA
fTRCK_LRA
LRA frequency tracking
range
Automatic tracking limits
300
(Note 2)
Hz
fTRCK_ACC_LRA
LRA frequency tracking
accuracy
Frequency tracking
accuracy during playback
fWIDEBAND
Wideband frequency
range
User defined drive
frequency
25
fOUT_PWM
PWM output frequency
Differential OUTP and
OUTN switching
frequency
183
ERC
Programming range of
output switching pins
edge rate control
OUTP and OUTN slope
25
fIN_PWM
PWM data input
frequency
RDS_ON
H-bridge drain to
source resistance when
on
High side plus low side
FETs
2
Ω
ZFLT_UZ
Actuator underimpedance threshold
Not applicable for coin
ERM
4
Ω
ZFTL_OZ
Over-impedance
threshold
Not applicable for coin
ERM
50
Ω
ZOUT_OFF
Output impedance
when H-bridge not
switching
Pull-down enabled
15
kΩ
VDD_POR_FALL
VDD Power-on-Reset
falling threshold
50
0.5
Note 1
For operation up to 500 mA (instead of 250 mA), see Section 5.7.12.
Note 2
For operation outside this range, see Section 5.7.1.
Datasheet
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1000
Hz
187.5
192
kHz
100
100
mV/ns
250
kHz
10
2.4
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
4.4
Timing Characteristics
Unless otherwise noted, the parameters listed in Table 8 are valid for TA = 25 ºC, VDD = 3.8 V, and
VDDIO = 1.8 V.
Table 8: Timing Characteristics
Parameter
Description
Conditions
Min
tON
Cold boot to IDLE state time
VDD present and PoR released
I 2C
tOUT_IDLE
Time to output from IDLE
state
From GPI or
drive
tOUT_STANDBY
Time to output from
STANDBY state
From GPI or I2C trigger to output
drive
START
tFALL
trigger to output
ACK
Typ
Max
Unit
1.2
1.5
ms
0.75
ms
0.15
ms
STOP
tRISE
70%
SDA
30%
tSETUP_START
tFALL
tSETUP_DATA tHOLD_DATA
tHI_SCL
tDATA
tDATA_ACK
tSETUP_STOP
70%
SCL
30%
tHOLD_START
1/fSCL
tLO_SCL
Figure 4: I2C Interface Timing
Table 9: I2C Interface Timing Requirements
Parameter
Description
Conditions
tBUF
Bus free time from STOP to START condition
Min
Max
0.5
Unit
µs
Standard, Fast, and Fast-Plus Modes
CBUS
Bus line capacitive load
fSCL
SCL clock frequency
tSETUP_START
Start condition setup time
0.26
µs
tHOLD_START
Start condition hold time
0.26
µs
tLO_SCL
SCL low time
0.5
µs
tHI_SCL
SCL high time
0.26
µs
tRISE
SCL and SDA rise time
120
ns
tFALL
SCL and SDA fall time
120
ns
tSETUP_DATA
Data setup time
50
ns
tHOLD_DATA
Data hold-time
0
ns
tSETUP_STOP
Stop condition setup time
0.26
µs
tDATA
Data valid time
0.45
µs
tDATA_ACK
Data valid acknowledge time
0.45
µs
tSPIKE
Spike suppression (SCL, SDA)
50
ns
Note 1
0
Fast/Fast+ mode
520
pF
1000
(Note 1)
kHz
fSCL maximum is 400 kHz at VDDIO ≤ 1.65 V and 1000 kHz at VDDIO > 1.65 V.
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LRA/ERM Haptic Driver with Multiple Input Triggers,
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4.5
Thermal Characteristics
Table 10: WLCSP Thermal Ratings
Parameter
Description (Note 1)
RƟJA
Junction-to-ambient thermal resistance
90.3
°C/W
RƟJC_TOP
Junction-to-case (top) thermal resistance
43.6
°C/W
RƟJB
Junction-to-board thermal resistance
49.0
°C/W
JT
Junction-to-top characterization parameter
6.4
°C/W
JB
Junction-to-board characterization parameter
45.8
°C/W
Note 1
Min
Typ
Max
Unit
Multilayer JEDEC standard, still air, ambient temperature 25 °C, simulated value.
Table 11: QFN Thermal Ratings
Parameter
Description (Note 1)
RƟJA
Junction-to-ambient thermal resistance
88.2
°C/W
RƟJC_TOP
Junction-to-case (top) thermal resistance
54.6
°C/W
RƟJB
Junction-to-board thermal resistance
39.3
°C/W
JT
Junction-to-top characterization parameter
3.4
°C/W
JB
Junction-to-board characterization parameter
50.0
°C/W
RƟJC_BOTTOM
Junction-to-case (bottom) thermal resistance
4.4
°C/W
Note 1
Min
Typ
Max
Unit
Multilayer JEDEC standard, still air, ambient temperature 25 °C, simulated value.
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
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5
Functional Description
DA7280 is a haptic driver capable of driving both LRA and ERM actuators. The power-optimized
architecture and advanced closed-loop digital algorithms achieve a very high-fidelity haptic drive. It
features frequency control within an onboard Waveform Memory and three distinct GPI inputs, for
triggering up to six distinct sequences. This helps with emulating button pressing in many
applications including gaming, mobile, and wearable devices.
The device controls the level of drive across the load and senses the movement of the actuator. The
driven waveform is generated by a current regulated loop using a high-frequency PWM modulation.
The differential output drive features a switching regulator architecture with H-bridge differential drive
across the load at a frequency of 187.5 kHz. The drive level is based on the sequence from the data
source selected by I2C interface, input PWM signal, or Waveform Memory.
DA7280 is capable of closed-loop actuator monitoring while driving to enable calibration-free
playback, frequency tracking (LRA only), Active Acceleration, Rapid Stop, and actuator diagnostics.
Continuous resonant frequency tracking can be enabled while driving an LRA to track the mechanical
resonance of the actuator through closed-loop control. This maximizes electrical to mechanical
energy conversion efficiency for narrowband actuators and is especially useful in applications such
as operating system notifications and alarms.
Resonant frequency tracking can be disabled to operate DA7280 in open-loop wideband frequency
operation while driving LRAs with a wider bandwidth frequency response.
Active Acceleration and Rapid Stop features enable automated driving of both ERM and LRA loads
(when frequency tracking is enabled). This reduces the time to reach the target acceleration level
and the time for the actuator to come to a complete stop.
5.1
Features Description
Driving LRA and ERM Actuators
DA7280 can drive both ERMs and LRAs depending on the register configuration, see Section 5.6.2.
Automatic LRA Resonant Frequency Tracking
LRA resonant frequency shifts over time due to changing operating conditions, such as temperature
or position, and manufacturing spread. LRAs are high-Q systems; if driven at a fixed frequency, the
consequences are loss of electrical to mechanical energy conversion efficiency, weaker than nominal
actuator acceleration output, and significant part-to-part variation in the end-product haptic feel.
Figure 5 illustrates that if the drive frequency is fixed, for example at 200 Hz, frequency variation in
the resonant peak of only 10 Hz can result in a loss of 50 % of the output acceleration.
Typical Resonant Peak Variation
(part-to-part, across temperature, drive signal level, and manufacturing lots)
Acceleration Output [g]
1
Resonant Peak
with Max Accel.
0.5
150
190
200
210
250
Frequency [Hz]
Figure 5: LRA Output Acceleration Swept in Frequency with Constant Power Input Signal
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
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For a consistent user experience, DA7280 automatically locks onto and tracks the resonant
frequency of the LRA through active BEMF sensing and closed-loop digital control. This ensures
optimal output acceleration on every individual LRA throughout its lifetime and consistent part-to-part
haptic feedback in the end product, see Section 5.3.
Wideband LRA Support
Wideband LRAs respond across a frequency range typically several times wider than narrowband
ones, as demonstrated in Figure 6, and can be used in combination with DA7280 to a create richer
haptic feedback experience by utilizing the increased vibrational frequency range, see Section 5.5.
Acceleration Output [g]
1
Standard
Narrowband LRA
0.5
Wideband LRA
200
Frequency [Hz]
Figure 6: Narrowband and Wideband LRA Response across Frequency
Dual mode actuators (DMA) consist of two modes of vibration in different axes around different
resonance points, depending on actuator construction. The two resonant points, wide response
frequency, and different direction of vibration allow immersive gaming experience with multiple
unique feedback effects. Figure 8 shows a typical DMA response, vibration in the y-axis occurs if the
DMA is driven at 100 Hz and vibration in the x-axis occurs if the DMA is driven at 200 Hz.
X-axis Vibration
Acceleration Output [g]
Dual Mode LRA
Y-axis Vibration
Y-axis Resonance
X-axis Resonance
1
0.5
Useful Operating Range
100
200
Frequency [Hz]
Figure 7: Dual Mode LRA Response across Frequency
The ability of DA7280 to control the frequency (25 Hz to 1000 Hz) and amplitude of the drive over
time as well as the type of output wave allows the use of wideband sequences fully utilizing the
capabilities of wideband and dual mode actuators for creating a richer user experience, see
Section 5.7.5. Example use cases in DMAs are excitation of both resonant peaks simultaneously for
maximum perceptible vibration or distinct single-frequency event-signaling clicks at different resonant
frequencies and physical directions. Both DMAs and wideband LRAs can also be used to augment
user audio experience by playing audio-derived haptic sequences over their useful frequency
operating range.
DA7280 supports all of the above use cases and drives wideband LRAs via I 2C or wideband
Waveform Memory sequences triggered by I2C or GPIs. The output drive can be configured as either
square wave, sine wave, or custom wave to create different end effects, see Section 5.7.6.
Usually, LRA resonant frequency tracking is disabled during wideband operation. However, it can be
enabled to either locate the resonant peak of wideband actuators, or to operate at a selected DMA
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resonance point and achieve the maximum possible actuator acceleration for a set input power, see
Section 5.3 and Section 5.7.1.
I2C and PWM Input Streaming
Haptic playback data can be streamed externally either via I2C direct register override or from a PWM
data source, see Section 5.2.2. The external input data PWM frequency is independent of the output
PWM signal frequency driven to the actuator. The input PWM signal is low-pass filtered to create a
varying DC level that is the envelope for the drive across the actuator.
Low Latency I2C/GPI Wake-Up from IDLE State
The device supports low latency (0.75 ms) wake-up from IDLE state, which is the lowest power state
(typically 0.36 µA from VDD). Wake-up is triggered by either GPI or I2C activity. I2C is fully functional in
all modes including IDLE state and DA7280 retains register settings in all modes, see Section 5.2.1.
Three GPI Sequence Triggers for up to Six Independent Haptic Responses
DA7280 supports up to three GPI inputs which can be used to trigger low-latency playback of up to
six distinct sequences from IDLE state, see Section 5.2.7. Triggering is activated on events caused
by rising or falling edges, or both. The sequence playback is configurable and a GPI can be
associated with either one or two sequences. In the second case, odd events trigger one sequence,
while even events another.
On-Board Waveform Memory with Amplitude, Time, and Frequency Control
DA7280 contains 100 bytes of highly optimized on-board Waveform Memory for user programmable
haptic sequences, see Section 5.8. The Dialog Semiconductor specific format allows control of not
only amplitude and time, but also frequency during the playback of a haptic sequence. This is
specifically intended for use with wideband and dual mode actuators to create a richer user
experience.
Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback
By measuring and responding to the BEMF of the actuator, DA7280 supports Active Acceleration
which improves actuator response both when increasing and decreasing drive amplitude by
overdriving or underdriving relative to the desired drive level. Similarly, Rapid Stop minimizes the
time needed for the actuator to come to a complete stop by driving against the direction of actuator
movement. These two features enable a high-fidelity haptic response of the actuator and improve on
its inherent physical performance and mechanical time constant, see Section 5.4.
Continuous Actuator Diagnostics and Fault Handling
DA7280 monitors the actuator impedance at the start of each haptic sequence. The value of the
impedance can be read back from a dedicated register, see Section 5.7.3. In addition, impedance,
BEMF, and resonant frequency faults are flagged with automatic shutdown and notification via the
nIRQ pin, see Section 5.6.6.
No Software Requirements with Embedded Operation
The device can function in a stand-alone embedded operation where no host action is needed to
clear generated faults and the device will attempt to drive on each request. This also allows operation
in GPI trigger mode without the need for a host device or host communication, see Section 5.7.7.
Note that initial download of sequences to the device is still required. Once loaded, the Waveform
Memory is retained in all states as long as the supply does not drop below the PoR threshold.
Differential Output Drive
DA7280 includes a full H-bridge differential output PWM drive that has the advantage of maximizing
the power delivered to the LRA from a given supply and allows braking of DC motors by reversing
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DA7280
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voltage polarity. This doubles the voltage swing across the actuator and significantly increases
system efficiency relative to a single transistor/LDO solution in legacy ERM or LRA applications.
Current Driven System
The device outputs regulated current, rather than voltage, which allows BEMF tracking without the
need to stop driving to sense the BEMF. This maximizes power delivery to the actuator per unit time
when compared to voltage driven solutions, resulting in shorter and sharper haptic clicks. In addition,
constant current drive provides constant force into an actuator independently of the BEMF amplitude.
Configurable EMI Suppression
Switching node edge rate control (ERC) on the OUTP and OUTN pins reduces electromagnetic
interference (EMI) and electrical interference via capacitive coupling in the end application, see
Section 5.7.11. This eliminates any need for resistor-capacitor (RC) or ferrite bead filtering of the
outputs, which offers a lower-cost bill of materials when using DA7280. Programmability of the ERC
also gives DA7280 a distinct advantage over competing solutions as it helps fine-tune a system
without any PCB modifications.
Automatic Short Circuit Protection
Automatic low-latency short circuit protection detects shorts on the OUTP and OUTN pins to supply,
ground, or between OUTP and OUTN, and protects DA7280 by forcing the H-bridge into a highimpedance state, see Section 5.6.6.
Ultra-Low Power Consumption with State Retention
In IDLE state, DA7280 has an ultra-low current consumption from the power supply at typically
0.36 µA with a time to output of 0.75 ms. DA7280 returns automatically to IDLE after completing
playback, keeps its internal state, and is available for I2C communications, see Section 5.2.1.
Ultra-Low Latency in STANDBY State
In STANDBY state, the time to output is 0.15 ms with current consumption of typically 0.8 mA, see
Section 5.2.1.
Supply Monitoring, Reporting, and Automatic Output Limiting
DA7280 monitors the power supply voltage level and adjusts the drive voltage accordingly, so that
the output does not clip to the supply voltage. This feature guarantees controlled output allowing
continued resonant frequency tracking and Active Acceleration/Rapid Stop functionality even when
the device is operating under low power supply conditions or heavy battery load. Supply voltage can
be read back by the host from a dedicated register, see Section 5.7.13.
Open- and Closed-Loop Modes
DA7280 can be configured in either open- or closed-loop mode. In open-loop mode any actuator
BEMF monitoring is disabled and the device works as a simple current based drive without any autoadjustment on the drive period or amplitude. This is useful in wideband LRA playback. In closed-loop
mode, the user can optionally turn on the frequency tracking, Active Acceleration, Rapid Stop, and
amplitude control features, see Section 5.7.5 and Section 5.7.6.
Open-Loop Sine/Custom Wave Drive Support
In open-loop operation DA7280 can be configured to drive the actuator with a non-square wave
signal. This improves the electrical efficiency, reduces audibility in some actuators, and allows
simultaneous drive of multiple resonant points in DMAs. The exact shape of the output waveform can
be configured via dedicated registers with the default set to a sine wave, see Section 5.7.6.
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
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Small Solution Footprint
Available in an ultra-small 1.35 mm x 1.75 mm, 0.4 mm pitch, 0.545 mm height, 3 x 4 WLCSP, or a
3.0 mm x 3.0 mm, 0.65 mm pitch, 0.78 mm height, 12 lead QFN package, DA7280 minimizes the
required PCB size and overall solution cost. In the typical application case, only a single 100 nF
decoupling capacitor is required. See Section 9 and Section 10.
Additional Features
DA7280 also features:
● A temperature and supply stable (±1.5 %) internal oscillator which guarantees consistent haptic
playback in the frequency domain over a wide range of operating conditions.
●
●
●
●
●
Automatic over-temperature warning and shutdown capability.
Low pad leakage current (typ. < 50 nA, for all pads combined).
Low idle current from VDDIO (typ. 130 nA at 1.8 V).
I2C operation down to VDDIO = 1.35 V
Output PWM frequency, at 187.5 kHz, is 167.5 kHz away from the audio band and at a non-audio
sample rate multiple. This prevents audible fold back via supply disturbance common in nearaudio-band switching haptic drivers.
● Easy to use Dialog SmartCanvas™ GUI with a user tab for fast device setup without the need to
directly interact with registers and an intuitive graphical environment for Waveform Memory
editing and visualization.
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.2
5.2.1
Functional Modes
System States
DA7280 features IDLE and STANDBY states ensuring lowest power consumption and lowest startup latency in different operating conditions. In addition, when any fault is detected, the device returns
directly to the IDLE state. Figure 8 shows the device states and the transitions into and out of each
state.
When a power supply is applied, DA7280 loads the register default settings. Once BOOT is
complete, DA7280 remains in the IDLE state and awaits further I2C communication.
DA7280 enters the DRIVE state when playback of a haptic sequence begins. There are several
different operating modes for playback, see Section 5.2.2.
On completion of playback, DA7280 leaves DRIVE state and returns either to IDLE state (for low
power consumption) or STANDBY state (for low latency-to-drive). This is configured using
STANDBY_EN.
If a fault condition occurs, DA7280 returns to the IDLE state, see Section 5.6.6 .
OFF
VDD ≥ 2.7 V
BOOT
Boot
complete
Set STANDBY_EN = 0
DA7280 returns to
the IDLE state in a
fault condition
IDLE
(IQ = 0.36 µA)
Start driving
approx. 0.75 ms
after drive request
STANDBY
(IQ = 0.8 mA)
Start driving
after approx.
0.15 ms delay
DRIVE
The conditions for start/
stop driving vary
depending on
OPERATION_MODE
Stop
driving
1
STANDBY_EN
0
Figure 8: System State Diagram
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.2.2
Operating Modes
DA7280 offers multiple operating modes for use in different applications and to minimize power
consumption, see Table 12.
Table 12: Operating Modes
Operating Mode
Description
Inactive
System waits in IDLE or STANDBY state based on
STANDBY_EN setting
0
Direct register override (DRO)
Playback streaming via I2C; input written to
OVERRIDE_VAL
1
Pulse width modulated (PWM)
Playback streaming from PWM data input source on
pin GPI_0/PWM
2
Register triggered waveform
memory (RTWM)
Playback from Waveform Memory triggered only by
I2C write to SEQ_START
3
Edge triggered waveform
memory (ETWM)
Playback from Waveform Memory triggered by
rising/falling edge on any of three GPIs or via I2C write
to SEQ_START
4
5.2.3
OPERATION_MODE
Inactive Mode
DA7280 can be configured to automatically return to IDLE state (for lower IQ) or STANDBY state (for
minimized latency) after completion of playback, see Section 5.2.1. In both states the register
contents are retained. DA7280 remains in Inactive mode until it receives a playback request via
either the GPI pins or I2C (providing any faults in the fault registers have been cleared, see
Section 5.6.6).
In the event of a fault the system will automatically return to the IDLE state, see Section 5.6.6.
5.2.4
Direct Register Override Mode
In DRO mode haptic sequences are streamed to DA7280 via I2C input. The drive level of the output
is set via OVERRIDE_VAL. For optimal start-up timing, update OVERRIDE_VAL before setting
OPERATION_MODE = 1. OVERRIDE_VAL is treated as a two's complement proportional value
where:
If ACCELERATION_EN = 1, the output drive level is equal to the value in OVERRIDE_VAL multiplied
by the voltage stored in ACTUATOR_NOMMAX. OVERRIDE_VAL is interpreted as a proportion
between 0 % (0x00) and 100 % (0x7F). The range from 0xFF to 0x80 is not used, see Figure 30. If
enabled, the automatic Active Acceleration and Rapid Stop features will take the output up to the
voltage in ACTUATOR_ABSMAX and/or reverse the drive level to be negative during level
transitions, but in steady state the value will always scale to the voltage in ACTUATOR_NOMMAX.
If ACCELERATION_EN = 0, the output drive level is equal to the value in OVERRIDE_VAL multiplied
by the voltage stored in ACTUATOR_ABSMAX. In this case OVERRIDE_VAL is interpreted as a
proportion between -100% (0x80) and 100% (0x7F), see Figure 31. When DA7280 is set up to drive
an ERM, the negative value represents a change in drive voltage polarity, while for an LRA it
represents a phase shift of 180° in the drive signal. Negative drive can be used to speed up output
acceleration level changes without the use of the Active Acceleration and Rapid Stop. Note that in
the ACCELERATION_EN = 0 case Rapid Stop can still be enabled if an automatic stop to zero
actuator acceleration is required.
Note: The output amplitude updates at twice the LRA frequency (when the differential voltage across
the LRA crosses zero), therefore input changes more frequent than this are not required as sampling
occurs only around a zero cross. Since the I2C is asynchronous to the output drive, updates to
OVERRIDE_VAL will have a one LRA half-period of uncertainty before propagating to the output.
Synchronization of OVERRIDE_VAL updates to the half period is possible via software by looking at
the POLARITY register and updating the output drive level, see Section 5.7.8.
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LRA/ERM Haptic Driver with Multiple Input Triggers,
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When driving a wideband LRA in DRO mode, resonant frequency tracking can be turned off. This
enables wideband operation and two-dimensional effects using DMAs, see Sections 5.7.5 and 5.7.6.
During playback, if a value written to OVERRIDE_VAL results in the output driving strength being
maintained at 0 %, DA7280 will disable its output stage to save power. Drive is re-enabled
automatically, with one LRA half-period delay, when a non-zero OVERRIDE_VAL value I2C input is
received.
5.2.5
Pulse Width Modulation Mode
PWM mode is used to stream haptic sequences to DA7280 via the GPI_0/PWM input pin where the
output drive level is determined by the duty cycle of the PWM signal. For optimal start-up timing, the
PWM input signal needs to be provided before setting OPERATION_MODE = 2. The PWM duty
cycle can be interpreted in two ways as follows:
If ACCELERATION_EN = 1, the output drive level is equal to the input signal duty cycle multiplied by
the voltage stored in ACTUATOR_NOMMAX. In this case the duty cycle is interpreted as a
proportion between 0 % and 100 %, see Figure 30. The automatic Active Acceleration and Rapid
Stop (if enabled) features will take the output up to the voltage in ACTUATOR_ABSMAX and/or
reverse the drive level to be negative during level transitions, but in steady state the final value will
always scale to the voltage in ACTUATOR_NOMMAX.
If ACCELERATION_EN = 0, the output drive level is equal to the input signal duty cycle multiplied by
the voltage stored in ACTUATOR_ABSMAX. In this case the duty cycle is interpreted as a proportion
between -100 % and 100 % where 50 % duty cycle is 0 %, see Figure 31. When DA7280 is set up to
drive an ERM, the negative value represents a change in drive voltage polarity, while for an LRA it
represents a phase shift of 180° in the drive signal. Negative drive can be used to speed up output
acceleration level changes without the use of the Active Acceleration and Rapid Stop. Note that in
the ACCELERATION_EN = 0 case Rapid Stop can still be enabled if an automatic stop to zero
actuator acceleration is required.
Note: The output PWM frequency is always independent of the PWM input frequency regardless of
whether frequency tracking is enabled or disabled. To maximize accuracy and minimize power
consumption and noise, it is best to keep the input PWM frequency as low as possible.
The PWM demodulator is rising edge sensitive. The minimum duty cycle that can be used to create
the drive level can be configured in FULL_BRAKE_THR; any duty cycle below that value will produce
a 0 % drive level.
During playback streaming in PWM mode, if a 0 % drive level is maintained by applying a 0 % (or
50 % if Active Acceleration is disabled) duty cycle PWM input, the DA7280 output stage is disabled
to save power. Drive is re-enabled automatically, with one LRA half-period delay, when the duty
cycle forces the drive level to be greater than 0 %.
ACCELERATION_EN = 0,
90% Duty Cycle
ACCELERATION_EN = 0,
60% Duty Cycle
PWM
Signal
ACCELERATION_EN = 0,
50% Duty Cycle
DA7280
Output
ACCELERATION_EN = 0,
40% Duty Cycle
ACCELERATION_EN = 0,
10% Duty Cycle
Figure 9: Example PWM Inputs with ACCELERATION_EN = 0
Note the 180° phase difference between driving > 50 % and < 50 %.
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5.2.6
Register Triggered Waveform Memory Mode
If sequence consistency or I2C bus availability is a concern, register triggered waveform memory
mode (RTWM) mode can be used to play back previously defined sequences from the Waveform
Memory, see Section 5.8, via I2C register trigger only. Enter this mode by setting
OPERATION_MODE = 3.
I2C Triggering and Sequence Looping
5.2.6.1
Sequence selection is done via PS_SEQ_ID with the additional option to loop the sequence up to
16 times using PS_SEQ_LOOP. To trigger a sequence, set SEQ_START = 1. Once a sequence
completes, the event is reported by dropping the nIRQ pin low and signaling via SEQ_DONE_M.
To repeat a sequence immediately following completion of playback, set SEQ_CONTINUE = 1.
5.2.7
Edge Triggered Waveform Memory Mode
If there is no host available, or for minimal host interaction, edge triggered waveform memory mode
(ETWM) mode can be used to play back a previously defined sequences from the Waveform
Memory, see Section 5.8, via external GPI edge trigger or also via I2C trigger, as in RTWM mode.
The ETWM is also useful if deterministic timing is required without reliance on the I2C bus.
Each of the GPI_0, GPI_1 and GPI_2 pins can be independently configured and will react according
to the setting in GPIx_POLARITY as follows:
● Rising edge trigger, GPIx_POLARITY = 0: only a rising GPI edge creates an event that triggers a
pre-programmed sequence.
● Falling edge trigger, GPIx_POLARITY = 1: only a falling GPI edge creates an event that triggers
a pre-programmed sequence.
● Rising and falling edge trigger, GPIx_POLARITY = 2: both edges create events that trigger a preprogrammed sequence.
Any event received during playback from any GPI after the initial GPI trigger event will result in a
sequence stop.
● There are two ways of reacting to a GPI event based on GPIx_MODE:
● Single sequence, GPIx_MODE = 0: no matter how many times a particular GPI is triggered, it will
play the sequence located at GPIx_SEQUENCE_ID.
● Multi-sequence, GPIx_MODE = 1: odd GPI events trigger the sequence at
GPIx_SEQUENCE_ID, while even GPI events trigger the sequence located at the value of
GPIx_SEQUENCE_ID + 1 bit.
In ETWM mode, a maximum of six different sequences can be configured (two per GPI, when multisequence mode is enabled). The desired haptic sequence for each GPI must be set by programming
GPIx_SEQUENCE_ID.
Once a sequence has finished playing, a signal is sent via the nIRQ pin and DA7280 automatically
returns to IDLE state, assuming STANDBY_EN = 0, to await the next trigger event.
Sequence looping operates in the same way as RTWM mode, see Section 5.2.6.1.
Datasheet
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.3
Resonant Frequency Tracking
LRAs are high-Q systems that have to be driven exactly at resonance to achieve maximum possible
output acceleration. DA7280 supports continuous resonant frequency tracking via BEMF sensing
during playback to achieve optimum LRA acceleration output across manufacturing spread,
operating temperature range, external damping, and actuator aging.
When the FREQ_TRACK_EN is high, a digital resonant frequency tracking loop locks onto the LRA
resonant frequency in real time by adjusting the drive period. This ensures that the actuator is always
driven at the optimum frequency for the highest efficiency electrical to mechanical energy conversion.
The loop range of 50 Hz to 300 Hz covers existing narrowband LRAs; typical resonant frequency lock
accuracy is 0.5 Hz.
To increase absolute accuracy of the lock during playback, D7280 supports automatic scaling of the
frequency tracking controller gain. The feature is enabled via FREQ_TRACKING_AUTO_ADJ and
becomes active after the device has achieved initial lock, see Section 5.7.1.
The resonant frequency tracking algorithm is designed to converge to the correct value from up to
25 % offset between the initial nominal datasheet value and the actual resonant frequency. This
range is conservative in order to prevent unwanted behavior. A fault will trigger if the actuator
resonant frequency is outside the 50 Hz to 300 Hz range. To block these two features, set
FREQ_TRACKING_FORCE_ON = 1, see Section 5.7.1.
5.4
Active Acceleration and Rapid Stop
Mechanical systems such as LRAs and ERMs accelerate and decelerate exponentially and the time
between transitions (for example from stopping of the drive signal to the actuator coming to a
complete rest) can be perceptibly slow for the user. DA7280 features Active Acceleration and Rapid
Stop to overcome this latency, which enables stronger clicks and a higher fidelity playback in both
LRAs and ERMs. This capability offers a distinct advantage over legacy systems, which do not sense
BEMF, because it allows the use of cheaper, slower response time actuators while keeping haptic
effects crisp.
Active Acceleration employs relative drive architecture based on BEMF sensing, which enables
temporary overdrive on all level changes reducing the time required to achieve a target drive level.
The DA7280 Active Acceleration algorithm does not require dedicated calibration procedures and
enables accurate overdrive and underdrive throughout the lifetime of an actuator. The feature
removes the need for a separate calibration sequence to determine the correct overdrive duration,
see Figure 10 and Figure 11.
Enabling Active Acceleration typically reduces the time to achieve the target drive level by a factor of
two on sequence level changes. The Rapid Stop feature typically reduces the time to achieve a zero
drive level by a factor of three when enabled. Figure 10 shows a drive sequence without the features
enabled and Figure 11 illustrates the reduced time to target when Active Acceleration and Rapid
Stop are enabled.
Note: The Active Acceleration and Rapid Stop features require frequency tracking to be enabled.
Figure 12 demonstrates the system with an actual LRA for an equivalent duration sequence without
and with the Active Acceleration and Rapid Stop features. The nominal actuator acceleration is
achieved faster and the stopping time is reduced by a factor of approximately eight.
Active Acceleration and Rapid Stop are enabled using ACCELERATION_EN and RAPID_STOP_EN.
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
DRIVE LEVELENVELOPE
LRA Acceleration
Time to reach nominal level drive
Time to stop
Figure 10: LRA Single Step Drive without Acceleration and Rapid Stop
DRIVE LEVEL ENVELOPE
LRA ACCELERATION
Shorter time to reach nominal drive level
Shorter time to stop
Figure 11: LRA Single Step with Acceleration and Rapid Stop
Accelerometer Output,
Sensor next to LRA
OUTP/N pins filtered
by a 3kHz RC filter
Accelerometer Output,
Sensor next to LRA
OUTP/N pins filtered
by a 3kHz RC filter
Length of
Desired Effect
Figure 12: Simple Drive (Top) versus Active Acceleration and Rapid Stop Enabled (Bottom)
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.5
Wideband Frequency Control
DA7280 can be configured for wideband LRA support in DRO, RTWM, and ETWM modes. This
allows an actuator to be driven outside of resonance to create a richer user experience. In this mode
frequency tracking, Active Acceleration, and Rapid Stop features should be disabled. The accessible
frequency range becomes 25 Hz to 1000 Hz. After configuring the device, see Section 5.6, the
following applies:
In DRO mode, streaming is as described in Section 5.2.4. To change output frequency, a new value
is uploaded to LRA_PER_H and LRA_PER_L.
In RTWM or ETWM modes, the frequency information is encoded into the frames of a sequence, see
Section 5.8.3. For information on sequence playback, see Section 5.6. If a repeatable frequency is
required at the start of a sequence, the first frame of a sequence must contain frequency information.
5.6
Device Configuration and Playback
Minimal one-time setup is required to drive any given actuator. This consists of setting the chosen
actuator type with its key parameters and selecting the drive mode. The Dialog SmartCanvas GUI
automatically calculates the values required and sets the registers based on the entered actuator
datasheet parameters. If the Dialog SmartCanvas GUI is not used, follow the steps outlined in this
section.
5.6.1
Boot
DA7280 comes out of reset when a power supply is provided to the device and boots for 1.5 ms. This
is followed by entry to the Inactive mode where the device is kept in its lowest power state.
5.6.2
Actuator Setup
The following setup procedure needs to be observed to program DA7280 to work with a specific
actuator:
1. Choose the correct actuator type using ACTUATOR_TYPE, 0 = LRA and 1 = ERM.
2. Choose the correct nominal maximum voltage across the actuator by checking the actuator
datasheet for the maximum allowed RMS voltage and writing the value to
ACTUATOR_NOMMAX. The allowable range is between 0 V and 6 V in 23.4 mV steps. The
ACTUATOR_NOMMAX setting can be calculated using the following formula:
𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝑁𝑂𝑀𝑀𝐴𝑋[7: 0] =
𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑛𝑜𝑚𝑚𝑎𝑥
23.4 × 10−3
(1)
3. Choose the correct absolute maximum peak voltage across the actuator by checking the actuator
datasheet and writing the value to ACTUATOR_ABSMAX. The allowable range is between 0 V
and 6 V in 23.4 mV steps. The ACTUATOR_ABSMAX value can be calculated using the
following formula:
𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝐴𝐵𝑆𝑀𝐴𝑋[7: 0] =
𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑎𝑏𝑠𝑚𝑎𝑥
23.4 × 10−3
(2)
4. Program the IMAX value (in units of mA) for the actuator using the following formula:
𝐼𝑀𝐴𝑋[4: 0] =
𝐼max _𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑚𝐴 − 28.6
7.2
(3)
– where Imax_actuator_mA is the actuator max rated current in mA, as listed in its datasheet.
Note that in general this should slightly exceed the ACTUATOR_ABSMAX voltage
divided by the actuator impedance.
5. Program the impedance of the actuator by checking the actuator datasheet and calculating the
values for V2I_FACTOR_H and V2I_FACTOR_L using the following formulae:
Datasheet
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
𝑍 × (𝐼𝑀𝐴𝑋[4: 0] + 4)
1.6104
(4)
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0]
256
(5)
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] =
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0] =
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0] = 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 256 × 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0]
(6)
– Where V2I_FACTOR[15:0] is the 16-bit concatenation of V2I_FACTOR_H[7:0] and
V2I_FACTOR_L[7:0], Z is the impedance of the actuator in Ω (as read from its datasheet),
and IMAX[4:0] is the 5-bit value of IMAX.
6. Program the LRA resonant frequency in terms of period by updating LRA_PER_H and
LRA_PER_L based on the following formula:
𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] =
𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0] =
1
𝐿𝑅𝐴𝑓𝑟𝑒𝑞 × 1333.32 × 10−9
(7)
𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0]
128
(8)
𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0] = 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0]
(9)
– Where LRAfreq represents the LRA resonant frequency in Hz, as listed in the actuator
datasheet.
Note: For ERM this value will signify the frequency of BEMF sensing; if more frequent updates are
required, the value can be increased up to 300 Hz.
For driving coin ERMs, see Section 5.7.18.
5.6.3
Automatic Output Control
DA7280 has several automatic control loops and mechanisms to ensure excellent playback fidelity
and easy actuator setup:
● Automatic frequency tracking - this feature allows resonant frequency tracking during playback
and is enabled via FREQ_TRACK_EN. Frequency tracking must be enabled to use the Active
Acceleration and Rapid Stop features. For fine-tuning the frequency tracking loop, see Section
5.7.1.
● Active Acceleration - this feature improves playback fidelity by overdriving and underdriving the
actuator to allow faster transitions between acceleration levels. This improves on the inherent
actuator mechanical time constant. To enable Active acceleration set ACCELERATION_EN = 1.
Note that the input data is interpreted as either unsigned (ACCELERATION_EN = 0) or signed
(ACCELERATION_EN = 1). For more detail on data formatting, see Section 0.
● Rapid Stop - this is a mechanism to allow the fastest possible stop to zero acceleration output for
the actuator. DA7280 achieves this by driving in full reverse the actuator by applying a 180°
phase shift in the case of an LRA or inverting the voltage across the actuator in the case of an
ERM actuator. For fine-tuning the Rapid Stop feature, see Section 5.7.2.
Datasheet
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.6.4
Waveform Memory Setup
The Waveform Memory is initially empty. The user can create any set of haptic sequences by
following the Waveform Memory format described in Section 5.8. For ease of use, the Dialog
SmartCanvas GUI also provides a graphical tool to create sequences. The sequences can then be
uploaded to the DA7280 Waveform Memory by going through the following steps:
1. Ensure that DA7280 is in Inactive mode (no playback ongoing and at least 1.5 ms have passed
since cold boot).
2. Ensure the Waveform Memory is unlocked, set WAV_MEM_LOCK = 1.
3. Read back the location of SNP_MEM_0 by checking WAV_MEM_BASE_ADDR.
4. Write the new contents of the Waveform Memory by starting from SNP_MEM_0.
5. If desired, re-lock the Waveform Memory, set WAV_MEM_LOCK = 0.
Once the DA7280 Waveform Memory is configured, it is retained until a power-on reset event. The
host can update the Waveform Memory as many times as needed during the lifetime of the device.
5.6.5
Mode Configuration
Set OPERATION_MODE according to the operating mode to be used. The device configuration flow
is different for each operating mode. Sections 5.6.5.1 to 5.6.5.5 explain how to set up and operate
the device in each of the operating modes.
5.6.5.1
Inactive Mode
In Inactive mode, DA7280 waits in a low-power state in between playback events. For more details
on power and latency trade-offs see Sections 5.2.1 and 5.2.3.
1. Set OPERATION_MODE = 0 for DA7280 to go to Inactive mode.
2. Configure STANDBY_EN to return to IDLE or STANDBY state after playback has finished.
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.6.5.2
Direct Register Override (DRO) Mode
Figure 13 shows how to operate the device in DRO mode.
1. Starting from either the IDLE or STANDBY state, write the initial drive amplitude of the haptic
sequence to OVERRIDE_VAL.
2. When ready to begin playback, set OPERATION_MODE = 1. The output will begin switching
after approximately 0.75 ms.
3. While in the DRIVE state, write to OVERRIDE_VAL to drive a new amplitude and create the
desired envelope of the haptic sequence. If OVERRIDE_VAL = 0 during the DRIVE state,
DA7280 will disable its output stage, but remain in a low latency-to-drive state and wait for further
updates to OVERRIDE_VAL.
4. To stop driving set OPERATION_MODE = 0. DA7280 returns to either the IDLE or STANDBY
state, depending on the value of STANDBY_EN.
Note: The allowable range of values written to OVERRIDE_VAL depends on whether
ACCELERATION_EN is set to 1 or 0. If ACCELERATION_EN = 1 then the usable range for
OVERRIDE_VAL is 0x00 to 0x7F. If ACCELERATION_EN = 0 then the usable range for
OVERRIDE_VAL is 0x00 to 0xFF in two’s complement. For further explanation, see Figure 30 and
Figure 31.
IDLE/STANDBY
Write to register
OVERRIDE_VAL
The allowable range
differs depending on
the state of
ACCELERATION_EN
Write
OPERATION_
MODE = 1
DA7280
stops
driving
I2C writes to start driving
Output starts
switching
Write
OPERATION_
MODE = 0
DRIVE
Drive
amplitude
changes
I2C write to stop driving
Change
OVERRIDE_VAL
Figure 13: Operation in DRO Mode
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.6.5.3
PWM Mode
Figure 14 shows how to operate the device in PWM mode.
1. Starting from either the IDLE or STANDBY state, apply a PWM signal to the GPI_0/PWM pin.
2. When ready to begin playback, set OPERATION_MODE = 2. The output will begin switching
after approximately 0.75 ms with a drive amplitude proportional to the duty cycle of the incoming
PWM signal.
3. While in the DRIVE state, update the duty cycle of the PWM signal to drive a new amplitude level
and create the desired envelope of the haptic sequence. If the duty cycle of the PWM signal falls
below the threshold set by FULL_BRAKE_THR, it is interpreted as a zero output drive level.
4. In order to stop driving, set OPERATION_MODE = 0. DA7280 will return to either the IDLE or
STANDBY state depending on the value of STANDBY_EN.
Note: The duty cycle of the PWM signal is interpreted differently depending on the value of
ACCELERATION_EN. If ACCELERATION_EN = 1, then zero drive corresponds to 50 % duty cycle ±
FULL_BRAKE_THR. If ACCELERATION_EN = 0, then zero drive corresponds to 0 % duty cycle +
FULL_BRAKE_THR. For further explanation, see Figure 30 and Figure 31.
IDLE/STANDBY
Apply PWM signal
to GPI_0/PWM pin
Write
OPERATION_
MODE = 2
DA7280
stops
driving
I2C writes to start driving
Output starts
switching
Write
OPERATION_
MODE = 0
DRIVE
Drive
amplitude
changes
I2C write to stop driving
Change the duty
cycle of the PWM
signal
Figure 14: Operation in PWM Mode
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.6.5.4
Register Triggered Waveform Memory (RTWM) Mode
The following registers should be set up prior to operation in RTWM mode:
● Set FREQ_WAVEFORM_TIMEBASE according to the minimum or maximum sequence timebase
required.
● Set SNP_MEM_x (where x = 0 to 99), see Section 5.8.
● If custom waveform sequences are required, see Section 5.7.5.
● Set WAV_MEM_LOCK = 0 to prohibit access to the waveform memory if required.
Figure 15 shows how to operate the device in RTWM mode.
1. While in the IDLE or STANDBY state, configure PS_SEQ_ID and PS_SEQ_LOOP to select the
desired sequence from Waveform Memory.
2. For first-time playback, set OPERATION_MODE = 3. On subsequent sequence playbacks, this
step can be skipped (if OPERATION_MODE = 3). The haptic sequence will not begin playing
until a start event is created by setting SEQ_START = 1.
3. While in the DRIVE state, set SEQ_CONTINUE = 1 to repeat the sequence.
4. When the haptic sequence is completed, DA7280 will signal this by setting nIRQ = 0 and setting
SEQ_DONE_M = 1. DA7280 will then return to IDLE or STANDBY state, depending on the value
of STANDBY_EN.
5. Clear the nIRQ and SEQ_DONE_M signals, set SEQ_DONE_M =1.
At any time during operation in RTWM mode, set OPERATION_MODE or SEQ_START = 0 to return
to the IDLE or STANDBY state.
IDLE/STANDBY
No
Are PS_SEQ_ID and
PS_SEQ_LOOP already
configured?
Configure the
PS_SEQ_LOOP
register
Yes
DA7280
ready to
play next
sequence
Select a sequence
via PS_SEQ_ID
Can be skipped
for subsequent
sequence
playbacks
Write
OPERATION_MODE = 3
No
OPERATION_MODE = 3?
Create a start
event by writing to
SEQ_START
Write SEQ_DONE_M = 1
to clear register and nIRQ
Yes
Output starts
switching
Sequence playback is
complete and output
stops switching
SEQ_CONTINUE
can be set if
required during
playback
Sequence
playback
Sequence is
continued
nIRQ = 0 and
SEQ_DONE_M = 1
Yes
No
SEQ_CONTINUE = 1?
Figure 15: Operation in RTWM Mode
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.6.5.5
Edge Triggered Waveform Memory (ETWM) Mode
The following registers should be set up prior to operation in ETWM mode:
● Set SNP_MEM_x (where x = 0 to 99), see Section 5.8.
● Set FREQ_WAVEFORM_TIMEBASE according to the minimum or maximum sequence timebase
required.
● If custom waveform sequences are required, see Section 5.7.5.
● Set WAV_MEM_LOCK = 0 to prohibit access to the waveform memory if required.
Figure 16 shows how to operate the device in ETWM mode.
1. Before first-time playback, set GPIx_SEQUENCE_ID, GPI_x_MODE, and GPIx_POLARITY, see
Section 5.2.7. These bits determine which sequence each of the GPI pins points to, whether they
trigger single or multiple sequences, and whether they react to rising, falling, or both edges.
2. Set PS_SEQ_ID and PS_SEQ_LOOP to select the sequence to play from Waveform Memory
when a start event is created via writing to I2C (SEQ_START). Note: If this has already been
done, then this step can be skipped.
3. Set OPERATION_MODE = 4. On subsequent sequence playbacks, this step can be skipped (if
OPERATION_MODE = 4). Haptic sequences will not begin playing until a start event is detected
either by an edge on one of the GPI pins, or by setting SEQ_START = 1 via I2C.
4. While in the DRIVE state, set SEQ_CONTINUE = 1 to repeat the sequence.
5. When the haptic sequence is completed, DA7280 will signal this by setting nIRQ = 0 and setting
SEQ_DONE = 1. DA7280 will then return to IDLE or STANDBY state, depending on the value of
the STANDBY_EN.
6. Clear the nIRQ and SEQ_DONE_M signals by setting SEQ_DONE_M = 0 via I2C.
At any time during operation in ETWM mode, set OPERATION_MODE or SEQ_START = 0 to return
to IDLE or STANDBY state.
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Integrated Waveform Memory and Wideband Support
IDLE/STANDBY
Are
GPIx_SEQUENCE_ID,
GPIx_MODE, and
GPIx_POLARITY already
configured?
No
Configure
GPIx_SEQUENCE_ID
Configure GPIx_MODE
Yes
Configure
GPIx_POLARITY
Are
PS_SEQ_ID and
PS_SEQ_LOOP already
configured?
No
Yes
DA7280
ready to
play next
sequence
Select a sequence
via PS_SEQ_ID
Configure the
PS_SEQ_LOOP
register
Can be skipped
for subsequent
sequence
playbacks
Write
OPERATION_MODE = 4
Write
SEQ_DONE_M = 1
to clear register and
nIRQ
No
OPERATION_MODE = 4?
Yes
Trigger via GPIx
or I2C
Output starts
switching
Sequence playback is
complete and output
stops switching
Sequence
playback
SEQ_CONTINUE
can be set if
required during
playback
Yes
Sequence is
continued
nIRQ = 0 and
SEQ_DONE_M = 1
No
SEQ_CONTINUE = 1?
Figure 16: Operation in ETWM Mode
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.6.6
Events and Diagnostics
DA7280 supports a comprehensive system for device, supply, and actuator diagnostics based on
faults, warnings, and notifications. Faults return DA7280 to IDLE state and hold the system in IDLE
until cleared, while warnings and notifications are used for host information only. If events are
generated, the host is notified by the open-drain nIRQ pin pulling low.
A single IRQ_EVENT1 byte containing all faults is presented to the host for simplified signaling.
Warnings are reported via IRQ_EVENT_WARNING_DIAG and input data faults via
IRQ_EVENT_SEQ_DIAG. Table 13 provides a summary of the full array of faults:
Table 13: Haptics Event Flag Descriptions
Event Name
Description
Required Action
E_OC_FAULT
Short circuit / over-current fault
Write 1 to clear
E_ACTUATOR_FAU
LT
An issue detected with the actuator impedance,
BEMF amplitude, or resonant frequency
Write 1 to clear
E_SEQ_FAULT
Sequence ID, Waveform Memory, or PWM fault
has occurred
Read IRQ_EVENT_SEQ_DIAG
for diagnostic information
E_OVERTEMP_CRI
T
Over-temperature event
Write 1 to clear
E_UVLO
Under-voltage fault
Write 1 to clear
E_SEQ_DONE
Memory sequence playback is complete
Write 1 to clear
E_SEQ_CONTINUE
Playback of a new sequence has started by the
host setting SEQ_CONTINUE
Write 1 to clear
E_WARNING
A system warning is in effect
Read warnings in
IRQ_EVENT_WARNING_DIAG
E_ADC_SAT
The input to the voltage sense ADC has saturated
Check if V2I_FACTOR_H/L is set
correctly for the driven actuator
E_LIM_DRIVE
Playback is limited due to battery lower than
sequence target
Reduce drive level if needed
E_LIM_DRIVE_ACC
Acceleration is limited due battery lower than
overdrive level
Reduce drive level if needed
E_MEM_TYPE
Input memory data type does not match
acceleration configuration
Check data format
E_SEQ_ID_FAULT
Requested sequence ID does not exist
Reload PS_SEQ_ID and
Waveform Memory
E_MEM_FAULT
Waveform Memory corruption (empty bytes, nonexistent snippet ID, wrong frame parameter)
Reload Waveform Memory
E_PWM_FAULT
PWM timeout
Restart PWM interface and write 1
to E_SEQ_FAULT to clear
Faults
Notifications
Warnings
Input Data Faults
All events are write 1 to clear and can be masked using IRQ_MASK1 and IRQ_MASK2. Some of the
sources generating E_ACTUATOR_FAULT can be disabled, for frequency tracking see Section 5.7.1
and for BEMF voltage amplitude see Section 5.7.14. For self-clearing of faults once in IDLE state,
see Section 5.7.7.
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.7
Advanced Operation
DA7280 features several advanced modes of operation to fine-tune actuator haptic performance.
5.7.1
Frequency Tracking
The closed-loop frequency tracking on DA7280 is implemented via a proportional-integral (PI)
controller. The proportional coefficient is stored in FRQ_PID_Kp_H/L and the integral coefficient in
FRQ_PID_Ki_H/L. The default values of the coefficients are optimized to cover a wide range of
actuators with typical settling times of approximately 40 ms from a 20 % frequency offset. If further
optimization is required to target a specific actuator the coefficients can be updated. The LRA tuning
tool in the DA7280 SmartCanvas GUI provides an intuitive and graphical way to easily adjust the Kp
and Ki coefficients.
To increase absolute accuracy of the lock during playback, DA7280 supports automatic scaling of the
frequency tracking controller proportional coefficient. This feature is enabled via
FREQ_TRACKING_AUTO_ADJ and becomes active after the device has achieved initial frequency
lock. The FRQ_LOCKED_LIM value is used to determine the threshold for the initial lock and can be
scaled up or down depending on system requirements. If optimizing FRQ_PID_K coefficients with
the FREQ_TRACK_AUTO_ADJ enabled in normal operation, ensure that the closed loop is stable
for a step response when FREQ_TRACK_AUTO_ADJ is set at either 0 or 1.
The resonant frequency tracking algorithm converges to the correct value from up to 25 % offset
between the initial nominal datasheet value and the actual resonant frequency. This range is
conservative to prevent unwanted behavior. A fault triggers if the actuator resonant frequency is
outside the 50 Hz to 300 Hz range. To block these checks, set FREQ_TRACKING_FORCE_ON = 1.
FRQ_TRACK_BEMF_LIM disables the frequency tracking if the BEMF signal becomes too low. It
should always be set lower than the value in RAPID_STOP_LIM.
The instantaneous value of the resonant frequency period is updated every half-period and written to
LRA_PER_ACTUAL_H/L. The values can be converted to period using the following formula:
𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) = 1333.32 × 10−9 × (128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐿)
(10)
If more accurate information is required (for example if a frequency tracking enabled sequence is
played to determine the resonant frequency before entering wideband operation), the average
resonant frequency information over the last four half-periods is written to
LRA_PER_AVERAGE_H/L. The values can be converted to period using the following formula:
𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) = 1333.32 × 10−9 × (128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐿) (11)
5.7.2
Rapid Stop
The Rapid Stop algorithm relies on actuator BEMF sensing to detect actuator motion during a stopto-zero LRA acceleration. The algorithm provides a stopping signal to the LRA until the actuator
crosses the point of no acceleration. Since drive updates happen only at the zero cross point, this
introduces latency that may cause the actuator to overshoot the stop position. Due to this, the Rapid
Stop will also trigger at a pre-determined threshold set by RAPID_STOP_LIM. The default setup
covers most actuators, but if Rapid Stop is too short (actuator not fully stopped), the register value
should be decreased; and if Rapid Stop overshoots (actuator stopped and then reversed), the
register value should be increased.
Note: The Rapid Stop algorithm can be triggered only for sequences longer than three half-periods.
5.7.3
Initial Impedance Update
DA7280 performs an impedance measurement at the very first half-period of drive at the start of
playback. This allows a one-shot update of V2I_FACTOR_H/L to take into account specific actuator
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
variation for increased voltage accuracy of the drive. The result is reported to IMPEDANCE_H/L,
which can be read by the host and converted to impedance using the following formula:
𝐴𝑐𝑡𝑢𝑎𝑡𝑜𝑟 𝐼𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒(𝑅𝑠𝑒𝑟𝑖𝑒𝑠 ) = (𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐻 × 4 + 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐿) × 0.0625Ω
(12)
To disable this feature, set V2I_FACTOR_FREEZE and CALIB_IMPEDANCE_DIS = 1.
5.7.4
Amplitude PID
AMP_PID_EN = 0
VOUT
BEMF Voltage
Output Voltage
Envelope [V]
Output Voltage
Envelope [V]
Some cylinder based ERMs generate excessively large-amplitude BEMF voltages. DA7280 can
compensate for this by reducing the drive current level, set AMP_PID_EN = 1. The result is an
improved haptic response. Figure 17 describes how the actuator voltage and current differs when
AMP_PID_EN enabled or disabled.
IOUT
VOUT
Time [s]
Output Current
Envelope [A]
Output Current
Envelope [A]
Time [s]
AMP_PID_EN = 1
Time [s]
IOUT drops automatically to compensate
BEMF and keep VOUT constant
IOUT
Time [s]
Figure 17: Output Voltage and Current for Different AMP_PID_EN Values
Note: This is not usually required for LRAs as the amplitude of the BEMF is typically very low.
5.7.5
Wideband Operation
DA7280 natively supports wideband LRAs and allows continuous frequency updates to the output
signal while driving. Amplitude and frequency data use parallel data paths, for configuration see
Section 5.6.5. This section describes how to use the frequency component only.
For wideband operation, frequency tracking must be disabled, by setting FREQ_TRACK_EN = 0,
because drive at frequencies different from the actuator resonant frequency is required. Rapid Stop
and Active Acceleration also rely on frequency tracking so must be deactivated by setting
ACCELERATION_EN = 0 and RAPID_STOP_EN = 0. There are two ways to operate DA7280 during
wideband operation:
● In the limited frequency range of 25 Hz to 300 Hz:
○ No further settings are required in RTWM and ETWM modes if the frequency information is
already stored in the Waveform Memory frame data as described in Section 5.8.3. If the
Waveform Memory does not contain frequency information, then each sequence can be
played at a different frequency by setting LRA_PER_H and LRA_PER_L to the desired value
via the formulae in Section 5.6.2 before triggering playback using the method described in
Sections 5.6.5.4 and 5.6.5.5.
○ In the DRO and PWM modes, the frequency information can be updated via the LRA_PER_H
and LRA_PER_L using the formulae in Section 5.6.2 either before triggering playback of
each sequence, see Sections 5.6.5.2 and 5.6.5.3, or during the playback itself. As with
amplitude, the one half-period uncertainty on the output frequency update also applies.
● In the full range of 25 Hz to 1024 Hz, the same procedures apply for all modes, but the following
registers need to be set:
○
○
○
○
BEMF_SENSE_EN = 0
DELAY_H = 0
DELAY_SHIFT_L = 0
DELAY_FREEZE = 1
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LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
5.7.6
Custom Waveform Operation
With frequency tracking, Active Acceleration, and Rapid Stop disabled, and with the additional setup
for wideband operation described in Section 5.7.5, DA7280 can be configured to drive a custom
waveform to an LRA actuator. It is important to note that here the custom waveform denotes the
actual output during a single LRA resonant period and not the overall amplitude envelope during
drive events, which is controlled as previously described in Section 5.6.5. Amplitude and frequency
data can be streamed as usual in DRO, PWM, RTWM, or ETWM modes.
The waveform output during a single resonant period comprises of 16 distinct points, see Figure 18,
where points 0 to 4 are mirrored and repeated to create, by default, a sine wave (for example, point 3
and point 5, and point 2 and point 6 have the same amplitude).
Extrapolation
point
Value to
output
Repeated
Points
0
(0 %)
1
(37.9 %)
2
(70.3 %)
3
(92.2 %)
4
(100 %)
5
(92.2 %)
6
(70.3 %)
7
(37.9 %)
8
(0 %)
9
10
(-37.9 %) (-70.3 %)
11
(-92.2 %)
12
(-100 %)
13
(-92.2 %)
14
15
(-70.3 %)
(-37.9 %)
0
(0 %)
Figure 18: Custom Wave Point Numbering
Point 0 is corresponds to an amplitude of 0 % of the value of IMAX, point 4 corresponds to an
amplitude of 100 %, and points 1, 2, and 3 are scaled to the IMAX value by the unsigned
CUSTOM_WAVE_GEN_COEFF1, CUSTOM_WAVE_GEN_COEFF2, and
CUSTOM_WAVE_GEN_COEFF3 coefficient values. The default coefficients are set to correspond to
a sine wave but can be updated to recreate any required waveform that is built of four symmetrical
sections, see Figure 18.
Table 14 contains a summary of the default coefficients and their settings.
Table 14: Default CUSTOM_WAVE_GEN_COEFFx Settings
Point
% of IMAX[4:0]
Corresponding Bits
0
0
-
1
37.9
CUSTOM_WAVE_GEN_COEFF1
2
70.3
CUSTOM_WAVE_GEN_COEFF2
3
92.2
CUSTOM_WAVE_GEN_COEFF3
4
100
-
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LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Configure the following bits to enable custom waveform operation:
●
●
●
●
●
●
●
●
●
BEMF_SENSE_EN = 0
WAVEGEN_MODE = 1
V2I_FACTOR_FREEZE = 1
DELAY_H = 0
DELAY_SHIFT_L = 0
DELAY_FREEZE = 1
ACCELERATION_EN = 0
RAPID_STOP_EN = 0
AMP_PID_EN = 0
After the above setup is executed, amplitude data can be streamed in any mode, see Section 5.6.5,
and output frequency can be updated, see Section 5.7.6.
5.7.7
Embedded Operation
Should DA7280 be required to operate in a setup where no host is present or due to software
limitations unable to communicate with the device during its required operation, DA7280 can operate
in embedded operation by setting EMBEDDED_MODE = 1. In this case DA7280 is configured to
clear all system faults as it enters inactive mode when playback is finished or if a fault has been
detected, see Section 5.6.6.
For example, if a short circuit occurs, the system will react in its usual way: stop driving, disable the
current loop, and go to Inactive mode. Once in Inactive mode, the generated interrupt is
automatically cleared and DA7280 will attempt to drive again on the next playback request without
the host having to come in and clear faults.
5.7.8
Polarity Change Reporting for Half-Period Control in DRO Mode
For advanced sequence playback in DRO mode, the host may require DA7280 to update the output
drive amplitude every half period. Since the I2C clock is asynchronous to the DA7280 internal clock
and the exact timing of the half-period will change dynamically based on the frequency tracking loop,
this is not a trivial operation.
To overcome this limitation, the register POLARITY provides feedback. POLARITY toggles at the
start of every half-period (so at a rate of 400 Hz for a 200 Hz resonant frequency actuator). This
allows software synchronization of the updates to the OVERRIDE_VAL, see Figure 19.
Wait 25 µs
Read POLARITY
register
Did POLARITY
toggle?
No
Yes
Update
OVERRIDE_VAL
Figure 19: Half-Period Control in DRO Mode
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LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Output Voltage
Envelope [V]
The timing of the sequence can be described as follows in Figure 20 where Amplitude X denotes
consecutive different output drive values:
OUTP
Amplitude
0
Amplitude
1
Amplitude
2
Amplitude
3
OUTN
Time [s]
POLARITY
0
I2C Update
OVERRIDE_VAL
1
1
0
0
2
1
3
1
2
4
3
4
Figure 20: Polarity Timing Relationship
5.7.9
Loop Filter Configuration
Haptic actuators (both ERM and LRA) can be modelled as a series combination of a resistor (Series
R) and inductor (Series L) followed by a BEMF voltage source, see Figure 21.
RSERIES
O
LSERIES
BEMF
Figure 21: Equivalent Electrical Model of an Actuator
The usual variation of RSERIES is from 8 Ω to 50 Ω and LSERIES is from 20 µH to either 2 mH or 3 mH.
The current regulation loop in the output drive must be kept stable by applying the correct setting in
the loop's filter. While the defaults cover the vast majority of available LRAs and ERMs further tuning
is possible by adjusting LOOP_FILT_CAP_TRIM, LOOP_FILT_RES_TRIM, and
LOOP_FILT_LOW_BW.
For LOOP_FILT_CAP_TRIM apply the settings in Table 15.
Table 15: LOOP_FILT_CAP_TRIM Register Trim Settings
Actuator Series Resistance (Ω)
Register
< 18
18 to 28
28 to 41
> 41
LOOP_FILT_CAP_TRIM
3
2
1
0
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For LOOP_FILT_RES_TRIM apply the settings in Table 16.
Table 16: LOOP_FILT_RES_TRIM Register Trim Settings
Lseries (µH)
Rseries
(Ω)
25 or
lower
50
75
100
125
150
175
200
225
250 or
higher
4
2
2
3
3
3
3
3
3
3
3
6
1
2
2
3
3
3
3
3
3
3
8
1
2
2
2
3
3
3
3
3
3
10
0
1
2
2
2
3
3
3
3
3
12
0
1
2
2
2
2
3
3
3
3
14
0
1
1
2
2
2
2
3
3
3
16
0
1
1
2
2
2
2
2
3
3
18
0
0
1
1
2
2
2
2
2
3
20
0
1
1
2
2
2
3
3
3
3
22
0
1
1
2
2
2
2
3
3
3
24
0
1
1
2
2
2
2
3
3
3
26
0
1
1
2
2
2
2
2
3
3
28
0
1
2
2
2
3
3
3
3
3
30
0
1
2
2
2
3
3
3
3
3
32
0
1
2
2
2
2
3
3
3
3
34
0
1
1
2
2
2
3
3
3
3
36 to 40
0
1
1
2
2
2
2
3
3
3
42
0
1
2
2
3
3
3
3
3
3
44
0
1
2
2
3
3
3
3
3
3
46 to 50
0
1
2
2
2
3
3
3
3
3
Set LOOP_FILT_LOW_BW high if the actuator inductance exceeds 1 mH.
5.7.10
UVLO Threshold
The DA7280 UVLO has a default fall threshold of 2.8 V. This is adjustable in 100 mV steps via
REF_UVLO_THRES. The full range is 2.7 V to 3.0 V.
5.7.11
Edge Rate Control
DA7280 contains an advanced switching node ERC to minimize EMI and board disturbances. The
slope of the ERC can be adjusted by changing the values of the HBRIDGE_ERC_LS_TRIM (for lowside FET ERC) and HBRIDGE_ERC_HS_TRIM (for high-side FET ERC). Default value is 100 mVn/s
and the adjustable range is 25 mV/ns to 100 mV/ns in 25 mV/ns steps.
5.7.12
Double Output Current Range
The nominal current rating for the DA7280 current regulation output is 250 mA. This range covers
existing LRAs, however some LRA manufacturers allow significant actuator overdrive over short
periods of time. DA7280 supports this by enabling LOOP_IDAC_DOUBLE_RANGE, which doubles
the maximum output current. When this is enabled, the following setup changes apply:
● IMAX now corresponds to twice the value computed by the formula in Section 5.6.2.
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● When setting the impedance in V2I_FACTOR_H and V2I_FACTOR_L via the formula in Section
5.6.2, use Zformula = 2*Zreal.
● When reading back from IMPEDANCE_H and IMPEDANCE_L, use an LSB of 0.03125 Ω.
5.7.13
Supply Monitoring, Reporting, and Automatic Output Limiting
DA7280 monitors the level of the supply during playback and reports it via ADC_VDD_H and
ADC_VDD_L. The two should be concatenated and read using the following formula:
𝑉𝐷𝐷 𝑆𝑢𝑝𝑝𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 = (𝐴𝐷𝐶_𝑉𝐷𝐷_𝐻 × 128 + 𝐴𝐷𝐶_𝑉𝐷𝐷_𝐿) × 0.1831 𝑚𝑉
(13)
DA7280 uses this information to prevent the device from clipping to supply by limiting the drive to a
value determined by the VDD_MARGIN register in 187.5 mV steps where 0x0 corresponds to no
margin, see Figure 22.
VDD
VDD_MARGIN
VDD - VDD_MARGIN
Voltage [V]
ABSMAX
Output drive clipping to
VDD – VDD_MARGIN, not ABSMAX
Time [s]
Figure 22: Automatic Output Limiting
The functionality is needed as DA7280 regulates current and if supply clipping occurs, the regulation
stops and the BEMF information is lost. Furthermore, the VDD_MARGIN register allows limiting of
the power across the actuator for low supply values to prevent the battery from discharging too fast.
5.7.14
BEMF Fault Limit
To detect malfunctioning actuators that have stopped moving due to a mechanical fault, DA7280 can
be configured to trigger an actuator fault if the BEMF voltage level falls below a threshold for long
drive durations. The threshold for detection is set in BEMF_FAULT_LIM; a zero value of the register
disables the fault checking.
5.7.15
Increasing Impedance Detection Accuracy
To increase the accuracy of the impedance reading in IMPEDANCE_H and IMPEDANCE_L, the
register V2I_FACTOR_OFFSET_EN could be set to 0. This removes an algorithmic offset utilized by
the acceleration algorithm. Should V2I_FACTOR_OFFSET_EN be equal to 0, ACCELERATION_EN
is recommended to be set to 0.
5.7.16
Frequency Pause during Rapid Stop
To address low mechanical time constant LRAs (start/stop times less than 20 ms) and improve the
braking behavior, DA7280 has the option to pause frequency tracking during the execution of the
Rapid Stop algorithm by setting FRQ_PAUSE_ON_POLARITY_CHANGE to 1.
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5.7.17
Frequency Pause during Rapid Stop
If DA7280 is used with LRAs that have significant BEMF voltage amplitude that can transiently
exceed the IR drop across an actuator when reversing the phase of the drive signal, it is
recommended to set DELAY_BYPASS to 0.
5.7.18
Coin ERM Operation
The term coin ERM is used to describe an eccentric rotating mass actuator that is flat and has coinlike external appearance. The eccentric rotating mass is circular and contains two coil windings that
are used for commutation, see Figure 23.
Plan View
VOUT Constant Current
Driven System
Electrical Commutation
Elevation View
Case
Case
B
A
INP
1
C
2
INN
Voltage [V]
Commutator PCB Electrical Diagram
VOUT
Rotor Top
View w/o Case
B’
A’
C’
Coil 1 or Coil 2
Stator
2
1
Rotor
B
A
Coils
1
C
2
Rotor
Rotor Bottom
B
A
Time [s]
Coil 1 and 2
in parallel
Coil 1 in series with Coil 2
Commutation Event 1: Single Inductor
B’
A’
C’
C
C’
Commutator PCB
A’
B’
Commutation Event 2: Double Inductor
Shaft
Stator
Stator
B
A
Brushes
1
A’
C
Commutation Event 3: Parallel Inductors
B’
B
A
2
1
C’
C
2
B’
A’
C’
Magnet
Figure 23: Coin ERM Physical and Electrical Summary
Due to the commutation of the motor, the impedance varies between one coil, two coils in series, and
for very short periods two coils in parallel. Due to this behavior, DA7280 cannot extract the BEMF
and actuator motion is not detectable for coin ERM actuators. Therefore, Active Acceleration and
Rapid Stop features are not available. Manual overdrive or underdrive of the coin ERM to speed up
the transition between two levels of acceleration is possible and recommended for better user
experience. Note that due to the varying impedance and the constant current drive of DA7280, the
output voltage will vary, with no effect on the performance of the DA7280, see Figure 23.
Recommended setup specific for a coin ERM, in addition to generic ERM setup described in
Section 5.6.2:
●
●
●
●
●
●
●
●
ACCELERATION_EN = 0
RAPID_STOP_EN = 0
AMP_PID_EN = 0
V2I_FACTOR_FREEZE = 1
CALIB_IMPEDANCE_DIS = 1
BEMF_FAULT_LIM = 0
Set the V2I factor using the single winding impedance, see Section 5.6.2
Set IMAX using the maximum start-up current, see Section 5.6.2
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5.8
Waveform Memory
The Waveform Memory stores haptic drive sequences. A single haptic effect is called a sequence
and each sequence is formed by one or more frames that address one or more snippets stored in
memory. The overall Waveform Memory structure is described in detail in Section 5.8.1;
Sections 5.8.2 to Section 5.8.4 provide definitions for snippets, frames, and sequences.
NOTE
It is recommended that the Dialog SmartCanvas GUI is used to construct sequences and upload them to the
Waveform Memory. The easy to use GUI provides intuitive visualization of the sequences in the Waveform
Memory and requires only basic knowledge of the overall memory format.
5.8.1
Waveform Memory Structure
The waveform memory structure has a 100-byte capacity for storing snippets, frames, and
sequences. Sequences reference the snippets using frames to allow complex haptic sequences to
be created in a memory efficient manner. The overall structure of the Waveform Memory can be
seen in Figure 24. For Waveform Memory programming, see Section 5.6.4.
WAVEFORM MEMORY
100 Bytes
Byte 0
num_of_sequences[7:0]
Byte 1
snippet_1_endpointer
Byte 2
snippet_n_endpointer
sequence_0_endpointer
HEADER SECTION
num_of_snippets[7:0]
sequence_n_endpointer
snippet_1
snippet_1_endpointer
PWL_point_n
snippet_n
sequence_0
frame_0
frame_n
DATA SECTION
(SNIPPETS/SEQUENCES)
PWL_point_ 0
Byte n
sequence_n
Figure 24: Waveform Memory Structure
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5.8.1.1
Header Section
The three sections constituting the header for the Waveform Memory are:
● Byte 0: Defines the number of snippets stored.
● Byte 1: Defines the number of sequences stored.
● Byte 2 and onwards: The snippet(s) and sequence(s) end address pointer(s) are stored. Each
pointer address occupies one byte. Up to 15 snippets can be addressed in addition to snippet 0,
which is the silence snippet, see Note 1. Up to 16 sequences can be addressed. A snippet or
sequence pointer points to the location in the waveform memory where the last byte of the
respective snippet or sequence resides.
5.8.1.2
Data Section
The upper memory section contains the PWL data describing the snippets, see Table 17. The lower
part of the memory contains the pre-stored sequences.
Snippet IDs are determined by the order in which they are listed, starting from SNP_ID = 1.
Sequence IDs are determined by the order in which they are listed, starting from 0.
5.8.2
Snippet Definition
Snippets are formed by storing a series of one or more piecewise linear (PWL) amplitude and time
pairs. Snippets represent the basic building blocks used in the Waveform Memory.
Table 17: PWL Byte Structure
Bit
7
6
Description
RMP
TIME[6:4]
5
4
3
2
1
0
AMP[3:0]
A byte is allocated for each amplitude and time pair in the Waveform Memory, see Table 17. A
snippet consists of one or more bytes containing RMP, TIME and AMP data.
● RMP defines whether a ramp (RMP = 1) or a step (RMP = 0) is required between consecutive
time and amplitude pairs.
● TIME contains the unitless time information (number of timebases) with the minimum being
1 timebase. Consequently, TIME = 0 signifies time base of 1, TIME = 1 signifies time base of 2,
and so on, with the longest duration at 8 timebases for TIME = 7.
● AMP contains the amplitude information of the snippet. If ACCELERATION_EN = 1, AMP is
unsigned and scales between 0 and 15, where 0 represents silence and 15 represents 100 %
drive. If ACCELERATION_EN = 0, AMP is in two's compliment and scales between 7 and -7
where 7 represents 100 % full scale and -7 represents -100 % (full scale 180° reversed polarity).
To maintain symmetry, -8 is interpreted as -7.
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LRA/ERM Haptic Driver with Multiple Input Triggers,
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For example, assuming ACCELERATION_EN = 1, the snippet shown in Figure 25 creates a
waveform that ramps from zero to an amplitude of 1111 over a period of 2 timebases, then step from
1111 to 1000, and remains there for 4 timebases. The length (in milliseconds) of a timebase is
specified using the TIMEBASE frame bits, see Section 5.8.3.
Description
RMP
TIME[6:4]
AMP[3:0]
Ramp
1
0
0
1
1
1
1
1
Step
0
0
1
1
1
0
0
0
Amplitude
P1
1111
P2
1000
1
2
3
4
5
6
Timebase
7
Figure 25: Snippet Ramp and Step with ACCELERATION_EN = 1
If a constant drive level of longer than 8 timebases is required, set RMP = 0 for subsequent PWL
points.
A generic example of a snippet is shown in Figure 26. Pn represents the PWL pair located at
amplitude An and with time step Tn, where n represents the PWL pair number. Note that a snippet
played at the start of a non-looped sequence will start from a default point P0 set at zero amplitude;
however, if the snippet is not at the start of a sequence or is read during the looping of a sequence,
the starting point will be the last played PWL point.
RMP = 1 for all PWL points
P4
P2
Amplitude
[%]
P3
Pn
P1
A4
A5
P2
An
A3
A2
A1
P4
Amplitude
[%]
P5
P0
P3
Pn
T0 = 0
P1
T1
T2
T3
T4
T5
Tn
Time
An
RMP = 0 for all PWL points
P4
P2
Amplitude
[%]
A5
A1
A3
A2
A4
P5
P0
P3
Pn
P1
T2
T3
T4
T5
Tn
Time
P5
A4
T1
An
A5
A1
A3
A2
T0 = 0
P0
T0 = 0
T1
T2
T3
T4
T5
Tn
Time
Figure 26: Snippet Example
Note 1
A built-in snippet containing a single silent PWL point (amplitude = 0) is available by setting
SNP_ID = 0. The duration is set to 2 timebases. Because of the existence of this snippet, customer
defined snippets start at SNP_ID = 1. The snippet is inherent to the decoding and is not actually stored
in the waveform memory. The number of snippets (byte 0) does not include snippet 0 and there is no
end pointer for snippet 0 stored in the waveform memory.
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5.8.3
Frame Definition
A frame consists of a collection of parameters used to define the playback of a snippet with differing
gain, time base, carrier frequency, and number of repetitions. A frame consists of up to three bytes,
its structure is shown in Figure 27. The frame parameters can be easily set up using the Dialog
SmartCanvas GUI.
● Byte 1 is mandatory. For byte 1, always set COMMAND_TYPE = 0. If set incorrectly, the device
will generate an interrupt of the type E_MEM_FAULT.
● Byte 2 is optional. When used, set COMMAND_TYPE = 1 in Byte 2.
● Byte 3 is optional, for use in wideband sequences only, and contains the frame frequency's eight
LSBs.
If COMMAND_TYPE of frame Byte 2 is set to 1 and FREQ_CMD = 1, then the Byte 3 contains drive
frequency data to enable wideband LRA support.
All frame parameters except COMMAND_TYPE, SNP_ID_L, GAIN, and TIMEBASE are optional. For
a full description, see Table 18.
Bit 7
Byte 1 =>
COMMAND_TYPE
=0
Byte 2 =>
COMMAND_TYPE
=1
Bit 6
Bit 5
GAIN [1:0]
Bit 4
Bit 3
Bit 2
TIMEBASE[1:0]
SNP_ID_LOOP[3:0]
Byte 3 =>
Bit 1
Bit 0
SNP_ID_L[2:0]
FREQ_CMD
FREQ[8]
SNP_ID_H
FREQ[7:0]
Figure 27: Command Structure for a Single Frame
Table 18: Bit Definitions for Frame Parameters
Byte
Number
1 and/or 2
Register Bit
Definitions
COMMAND_TYPE
Description
COMMAND_TYPE labels the byte and tells the system how to interpret the
following seven LSBs.
COMMAND_TYPE = 0 in Byte 1
COMMAND_TYPE = 1 signifies Byte 2 is present following Byte 1
Gain applied to the snippet identified by SNP_ID_L/H:
1
GAIN[1:0]
00 = 0 dB
01 = -6 dB
10 = -12 dB
11 = -18 dB
The timebase length of the snippet pointed to by the snippet ID. This
register is interpreted differently depending on
FREQ_WAVEFORM_TIMEBASE:
If FREQ_WAVEFORM_TIMEBASE = 0 (default):
00 = 5.44 ms
1
TIMEBASE[1:0]
01 = 21.76 ms
10 = 43.52 ms
11 = 87.04 ms
If FREQ_WAVEFORM_TIMEBASE = 1:
00 = 1.36 ms
01 = 5.44 ms
10 = 21.76 ms
11 = 43.52 ms
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Byte
Number
Register Bit
Definitions
Description
1
SNP_ID_L[2:0]
SNP_ID_L is mandatory and contains the LSBs of the snippet ID (SNP_ID).
Up to eight snippets can be addressed.
2
SNP_ID_LOOP[3:0]
SNP_ID_LOOP is the loop multiplier of the snippet identified by
SNP_ID_L/H and shows how many times a snippet is looped. If not
present, the loop multiplier is 1. The number of loop iterations is equal to
SNP_ID_LOOP + 1 (that is, 0 = 1 iteration, 15 = 16 iterations). When the
loop multiplier is > 1, playback begins from P1 instead of P0, see Figure
26, after the first playback loop is complete.
2
FREQ_CMD
If FREQ_CMD = 1, the frame is a 3-byte command with frequency
information. The frequency information is stored in FREQ[7:0].
2
FREQ[8]
Drive frequency MSB. The total frequency range is represented by the 9-bit
concatenation of FREQ[8] and FREQ[7:0] (possible values: 0 to 511),
which corresponds to the range 1 Hz to 1024 Hz. The LSB step size is 2 Hz
and values below 25 Hz are interpreted as 25 Hz. The result is also
converted from frequency to period and stored in the
FRQ_LRA_PER_ACT_x registers for read-back.
2
SNP_ID_H
SNP_ID_H is the MSB of the snippet ID (SNP_ID). This can be used to
increase the range of addressable snippets from 8 to 16. This bit is optional
and if not present SNP_ID_H = 0.
FREQ[7:0]
Drive frequency LSBs. The total frequency range is represented by the 9bit concatenation of FREQ[8] and FREQ[7:0] (possible values: 0 to 511),
which corresponds to the range 1 Hz to 1024 Hz. The LSB step size is 2 Hz
and values below 25 Hz are interpreted as 25 Hz. The result is also
converted from frequency to period and stored in the
FRQ_LRA_PER_ACT_x registers for read-back.
3
Note: The frequency command should be used only when FREQ_TRACK_EN = 0, otherwise the
frequency tracking loop will update the frequency away from the set one.
Note: The If FREQ_TRACK_EN = 0 and a frequency update containing frame is played, the new
frequency will be maintained for all subsequent frames or sequences until a new frame with a new
frequency command is played. Assume that Sequence 0 contains no frames with frequency
commands, Sequence 1 has a frame with command setting the frequency at 150 Hz, and Sequence
2 has one at 200 Hz. If Sequence 0 is played after Sequence 1, it will be played at 150 Hz. If
Sequence 0 is played after Sequence 2, it will be played at 200 Hz.
5.8.4
Sequence Definition
A sequence is built up of one or more frames, see Figure 28, and written to memory using the format
described in Section 5.8.1.
Sequence
Frame0
Frame1
Frame2
FrameN
Each frame points to an individual snippet with certain playback parameters
Figure 28: Sequence Structure
Note: Only sequences can be played. It is not possible to point directly to a snippet (although a
sequence can be created which contains only one snippet).
Note: If a sequence ends on a non-zero value, zero is assumed to follow and the device will end the
haptic playback at the end of the sequence.
Note: The starting amplitude at the beginning of a frame or snippet is dependent on the ending
amplitude of the previous frame or snippet. The starting amplitude at the start of a sequence is zero,
see Figure 26.
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5.8.4.1
Pre-Stored Waveform Memory Example
Figure 29 shows an example of a typical Waveform Memory operation with all features enabled.
Waveform Memory
Number of Snippets
Number of Sequences
Snippet 1 Addr Pointer
Snippet 2 Addr Pointer
...
Snippet 5 Addr Pointer
...
Sequence 0 Addr Pointer
...
Sequence 3 Addr Pointer
...
Example Snippet_1
p2
p1
PWL : P1 = Ramp to 80%, time 4
PWL : P2 = Step to 80%, time 2
PWL : P3 = Ramp to 0%, time 4 p0
p3
Example Snippet_2
PWL : P1 = Ramp to 50%, time 4
PWL : P2 = Step to 50%, time 1
PWL : P3 = Step to 100%, time 3
PWL : P4 = Step to 0%, time 2
p3
p1
p2
p4
p0
...
p1
Example Snippet_5
p3
PWL : P1 = Ramp to 60%, time 3
PWL : P2 = Step to 0%, time 1
PWL : P3 = Ramp to 40%, time 2
p2
p0
...
p1
Example Snippet_7
PWL : P1 = Step to 50%, time 1
PWL : P2 = Step to 00%, time 1
p2
p0
...
Snippet_M
Amplitude
Narrowband Example , Sequence 0
Example Sequence_0
SEQ_0_FR_0 snippet 7
0dB
Timebase
20ms
2 loops
SEQ_0_FR_1 snippet 1
-6dB
Timebase
20ms
0 loops
snippet 1
0dB
Timebase
40ms
0 loops
SEQ_0_FR_2
Snip 7,
loop 1
@20ms
loop 2
Snip 1
@ -6dB,
20ms
Snip 1
@ 0dB, 40ms
...
Snippet 1
Three loops of Snippet 7 is played
played with 20ms
at 20ms
timebase and 0dB gain timebase
and -6dB
gain
Snippet 1 is
played at 40ms
timebase and
0dB gain.
Time
Example Sequence_3
snippet 5
Timebase
5ms
Wideband
SEQ_3_FR_1 snippet 2
0dB
SEQ_3_FR_2 snippet 0
SEQ_3_FR_3
snippet 7
Freq :90Hz
Timebase
20ms
Wideband
0 loops
Freq :162.5Hz
Timebase 20ms
0dB
Wideband Example , Sequence 3
1 loops
Amplitude
-6dB
SEQ_3_FR_0
Timebase
5ms
loop 1
@90Hz
Snip 2 @162.5Hz
Snip 0 Snip 7, @5ms,
162.5Hz
LRA drive
frequency set @
90Hz.
Two loops of
Snippet 5, 5ms
timebase, -6dB
gain.
LRA drive
frequency set @
162.5Hz.
Snippet 2 is
played once at
20ms timebase,
0dB gain
40ms LRA drive
frequency set
of
silence @ 162.5Hz.
Snippet 7
played with
5ms timebase
and 0dB gain
Snip 5
@90Hz
Time
0 loops
0 loops
...
Sequence_N
Figure 29: Waveform Memory Example
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5.9
General Data Format
This section describes the data format used by the three different data input sources (DRO, PWM,
and Waveform Memory). Four bits are used for storing the envelope value of snippets in Waveform
Memory. Interpretation of the data is different depending on ACCELERATION_EN. For an overview
of the data interpretation with and without Active Acceleration enabled, see Figure 30 and Figure 31.
Data format for ERM and LRA
ACCELERATION_EN = 0
Waveform/Data source
MEM
DRO
4 bits
2's c.
8 bits
2's c.
0x7
0x7F
0x6
0x7E
0x5
0x7D
.
.
.
.
.
.
0x2
0x02
0x1
0x01
0x0
0x00
0xF
0xFF
0xE
0xFE
0xD
0xFD
.
.
.
.
.
.
0x9
0x81
0x8
0x80
Driving Strength
[%]
PWM
[Mark / space]
100 %
100%
mark – space ratio
Drive positive direction
FULL_BRAKE_THRS[3:0]
0
full brake
(only for PWM)
50%
Drive negative direction
-100 %
0%
Figure 30: Overview of Data Formats with Acceleration Disabled
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Data format for ERM and LRA
ACCELERATION_EN = 1
Waveform/Data source
MEM
DRO
4 bits
uns.
8 bits
2's c.
0xF
0x7F
0xE
0x7E
0xD
0x7D
.
.
.
.
.
.
0x2
0x02
0x1
0x01
0x0
0x00
N/A
0xFF
N/A
0xFE
N/A
0xFD
.
.
.
.
.
.
N/A
0x81
N/A
0x80
Driving Strength in ENV GEN
[%]
PWM
[Mark / space]
100 %
mark – space ratio
100%
Drive positive direction
FULL_BRAKE_THRS[3:0]
full brake
(only for PWM)
0
NO NEGATIVE DRIVE
0%
Drive negative direction
-100 %
Figure 31: Overview of Data Formats with Acceleration Enabled
5.9.1
DRO Mode
DRO data is supplied from I2C and is interpreted as 8-bit two’s complement signed number.
● For ACCELERATION_EN = 0:
○ The most negative value corresponds to -100 % driving strength.
○ The most positive value corresponds to +100 % driving strength.
○ A zero value corresponds to no drive.
○ The full range is between 127 (100 %) and -127 (-100 %), with -128 interpreted as -127 to
keep the ranges symmetrical.
● For ACCELERATION_EN = 1:
○ Negative values are omitted and substituted with zero.
○ The most positive value corresponds to +100 % driving strength.
○ Zero value corresponds to no drive.
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5.9.2
PWM Mode
PWM provides mark / space ratio between 0 % and 100 %. The interpretation of duty cycle depends
on the state of ACCELERATION_EN.
● For ACCELERATION_EN = 0:
○ A 0 % duty cycle corresponds to -100 % driving strength.
○ A 50 % duty cycle corresponds to no drive.
○ A 100 % duty cycle corresponds to +100 % driving strength.
○ FULL_BRAKE_THR defines a lower threshold for driving strength, below this threshold, drive
is interpreted as zero.
● For ACCELERATION_EN = 1:
○ A 0 % duty cycle corresponds to no drive.
○ A 50 % duty cycle corresponds to +50 % driving strength.
○ A 100 % duty cycle corresponds to +100 % driving strength.
○ Negative drive is not possible.
○ FULL_BRAKE_THR defines a lower threshold for driving strength, below this threshold, drive
is interpreted as zero.
The encoded value of PWM data is converted to 8-bit two’s complement data using the DRO format
and is written to OVERRIDE_VAL so it can be read back.
5.9.3
RTWM and ETWM Modes
● For ACCELERATION_EN = 0:
○ The 4 bits of the amplitude value are interpreted as a two’s complement signed value.
○ The most negative value corresponds to -100 % driving strength.
○ The most positive value corresponds to +100 % driving strength.
○ A zero value corresponds to no drive.
○ The full range is between 7 (100%) and -7 (-100%), with -8 interpreted as -7 to keep the
ranges symmetrical.
● ACCELERATION_EN = 1
○ The 4 bits of the amplitude value are interpreted as an unsigned value.
○ The most positive value corresponds to +100 % driving strength.
○ Negative drive is not possible.
○ A zero value corresponds to no drive.
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5.10 I2C Control Interface
DA7280 is software controlled from the host by registers accessed via an I2C compatible serial
control interface. Data is shifted into or out of the DA7280 under the control of the host processor,
which also provides the serial clock.
The DA7280 7-bit I2C slave address is 0x4A (1001010 binary), which is equivalent to 0x94 (8-bit) for
writing and 0x95 (8-bit) for reading.
The I2C clock is supplied by the SCL line and the bidirectional I2C data is carried by the SDA line.
The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be
pulled HIGH by external pull-up resistors (1 kΩ to 20 kΩ range). The attached devices only drive the
bus lines LOW by connecting them to ground. This means that two devices cannot conflict if they
drive the bus simultaneously.
DA7280 supports Standard-mode, Fast-mode, and Fast-mode Plus, with the highest frequency of the
bus at 1 MHz in Fast-mode Plus. The exact frequency can be determined by the application and
does not have any relation to the DA7280 internal clock signals. DA7280 will follow the host clock
speed within the described limitations and does not initiate any clock arbitration or slow-down.
Communication on the I2C bus always takes place between two devices, one acting as the master
and the other as the slave. The DA7280 will only operate as a slave.
VDDIO
Host
Processor
SCL
SDA
VDDIO
SCL
SDA DA7280
SCL
SDA Peripheral
Device
Figure 32: Schematic of the I2C Control Interface Bus
All data is transmitted across the I2C bus in groups of eight bits. To send a bit the SDA line is driven
to the intended state while the SCL is LOW (a LOW on SCL indicates a zero bit). Once the SDA has
settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the
receiver’s shift register.
A two-byte serial protocol is used containing one byte for address and one byte for data. Data and
address transfer is transmitted MSB first for both read and write operations. All transmission begins
with the START condition from the master while the bus is in the Idle mode (the bus is free). It is
initiated by a HIGH to LOW transition on the SDA line while the SCL is in the HIGH state (a STOP
condition is indicated by a LOW to HIGH transition on the SDA line while the SCL line is in the HIGH
state).
SCL
SDA
Figure 33: I2C START and STOP Conditions
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The I2C bus is monitored by DA7280 for a valid slave address whenever the interface is enabled. It
responds with an Acknowledge immediately when it receives its own slave address. The
Acknowledge is done by pulling the SDA line LOW during the following clock cycle (white blocks
marked with A in Figure 34 to Figure 38).
The protocol for a register write from master to slave consists of a START condition, a slave address
with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP
condition (DA7280 responds to all bytes with Acknowledge), see Figure 34.
S
SLAVE addr
7-bits
W
A
REG addr
1-bit
A
DATA
8-bits
Master to Slave
P
A
8-bits
Slave to Master
S = START condition
P = STOP condition
A = Acknowledge (low)
W = Write (low)
Figure 34: I2C Byte Write (SDA line)
When the host reads data from a register it first has to write access DA7280 with the target register
address and then read access DA7280 with a repeated START, or alternatively a second START
condition. After receiving the data the host sends a Not Acknowledge (NAK) and terminates the
transmission with a STOP condition:
S SLAVEaddr W A
7-bits
1-bit
S SLAVEaddr W A
7-bits
REG addr
A Sr SLAVEaddr R
8-bits
7-bits
REG addr
1-bit
A
P
1-bit
7-bits
*
DATA
A
P
8-bits
S SLAVEaddr R
8-bits
Master to Slave
A
A
1-bit
DATA
*
P
A
8-bits
Slave to Master
S = START condition
Sr = Repeated START condition
P = STOP condition
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 35: Examples of the I2C Byte Read (SDA line)
Consecutive (Page) Read-Out mode, I2C_WR_MODE (register CIF_I2C1) = 0, is initiated from the
master by sending an Acknowledge instead of Not Acknowledge (NAK) after receipt of the data word.
The I2C control block then increments the address pointer to the next I2C address and sends the data
to the master. This enables an unlimited read of data bytes until the master sends an NAK directly
after the receipt of data, followed by a subsequent STOP condition. If a non-existent I2C address is
read out, the DA7280 will return code zero.
S SLAVEaddr W A
7-bits
1 bit
S SLAVEaddr W A
7-bits
REG addr
A Sr SLAVEaddr R A
8-bits
REG addr
7-bits
Master to Slave
S = START condition
Sr = Repeat START condition
P = STOP condition
8-bits
S SLAVEaddr R A
A P
7-bits
8-bits
1-bit
1-bit
DATA
1-bit
A
DATA
A
8-bits
DATA
*
DATA
A
P
8-bits
A
8-bits
DATA
*
A
P
8-bits
Slave to Master
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 36: Examples of I2C Page Read (SDA line)
In Page mode the slave address after Sr (Repeated START condition) must be the same as the
previous slave address.
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Consecutive (Page) Write mode, I2C_WR_MODE = 0, is supported if the master sends several data
bytes following a slave register address. The I2C control block then increments the address pointer to
the next I2C address, stores the received data and sends an Acknowledge until the master sends the
STOP condition.
S SLAVEaddr W A
7-bits
1 bit
REGadr
A
8-bits
Master to Slave
DATA
8-bits
A
DATA
1-bit
A
8-bits
DATA
A
8-bits
……….
A
P
Repeated writes
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 37: I2C Page Write (SDA line)
An alternative Repeated-Write mode that uses non-consecutive slave register addresses is available
using the CIF_I2C1 register. In this Repeat Mode, I2C_WR_MODE = 1, the slave can be configured
to support a host’s repeated write operations into several non-consecutive registers. Data is stored at
the previously received register address. If a new START or STOP condition occurs within a
message, the bus returns to Idle mode. This is illustrated in Figure 38.
S SLAVEaddr W A
7-bits
1 bit
REG addr
8-bits
Master to Slave
A
DATA
8-bits
A
REG addr
1-bit
8-bits
A
DATA
8-bits
A
……….
A
P
Repeated writes
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 38: I2C Repeated Write (SDA line)
In Page mode, I2C_WR_MODE = 0, both Page mode reads and writes using auto-incremented
addresses, and Repeat mode reads and writes using non auto-incremented addresses, are
supported. In Repeat mode, I2C_WR_MODE = 1, however, only Repeat mode reads and writes are
supported.
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© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
6
6.1
Register Overview
Register Map
All register bits classed as Reserved are Read-Only and can be ignored.
Table 19: Register Map
Addr
Register
7
6
0x00
CHIP_REV
CHIP_REV_MINOR
5
4
3
2
1
0
Reset
0x00
CHIP_REV_MAJOR
0xBA
0x03
IRQ_EVENT1
E_OC_F
AULT
E_ACTU
ATOR_F
AULT
0x04
IRQ_EVENT_
WARNING_D
IAG
E_LIM_D
RIVE
E_LIM_D
RIVE_AC
C
Reserved
E_MEM_T
YPE
E_OVERT
EMP_WAR
N
Reserved
Reserved
Reserve
d
0x00
0x05
IRQ_EVENT_
SEQ_DIAG
E_SEQ_I
D_FAUL
T
E_MEM_
FAULT
E_PWM_
FAULT
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x00
0x06
IRQ_STATU
S1
STA_OC
STA_AC
TUATOR
STA_WA
RNING
STA_SEQ
_FAULT
STA_OVE
RTEMP_C
RIT
STA_SE
Q_DONE
STA_UVL
O_VBAT_
OK
STA_SE
Q_CON
TINUE
0x00
0x07
IRQ_MASK1
OC_M
ACTUAT
OR_M
WARNIN
G_M
SEQ_FAU
LT_M
OVERTEM
P_CRIT_M
SEQ_DO
NE_M
E_UVLO_
M
SEQ_C
ONTINU
E_M
0x00
0x08
CIF_I2C1
I2C_WR_
MODE
I2C_TO_
ENABLE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x40
0x0A
FRQ_LRA_P
ER_H
LRA_PER_H
0x21
0x0B
FRQ_LRA_P
ER_L
Reserved
0x4F
0x0C
ACTUATOR1
ACTUATOR_NOMMAX
0x0D
ACTUATOR2
ACTUATOR_ABSMAX
0x0E
ACTUATOR3
Reserved
0x0F
CALIB_V2I_H
V2I_FACTOR_H
0x01
0x10
CALIB_V2I_L
V2I_FACTOR_L
0x0D
0x11
CALIB_IMP_
H
IMPEDANCE_H
0x00
0x12
CALIB_IMP_
L
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IMPEDANCE_L
0x00
0x13
TOP_CFG1
EMBEDD
ED_MOD
E
Reserved
ACTUAT
OR_TYP
E
BEMF_SE
NSE_EN
FREQ_TR
ACK_EN
ACCELE
RATION_
EN
RAPID_S
TOP_EN
0x1E
0x14
TOP_CFG2
Reserved
Reserved
Reserved
MEM_DAT
A_SIGNED
FULL_BRAKE_THR
0x01
0x15
TOP_CFG3
Reserved
Reserved
Reserved
Reserved
VDD_MARGIN
0x03
0x16
TOP_CFG4
V2I_FAC
TOR_FR
EEZE
CALIB_I
MPEDAN
CE_DIS
Reserved
Reserved
Reserved
0x17
TOP_INT_CF
G1
FRQ_LOCKED_LIM
0x1C
TOP_INT_CF
G6_H
FRQ_PID_Kp_H
0x0E
0x1D
TOP_INT_CF
G6_L
FRQ_PID_Kp_L
0x20
0x1E
TOP_INT_CF
G7_H
FRQ_PID_Ki_H
0x03
Datasheet
CFR0011-120-00
E_WARN
ING
E_SEQ_F
AULT
E_OVERT
EMP_CRIT
E_SEQ_
DONE
E_UVLO
E_SEQ_
CONTIN
UE
LRA_PER_L
Reserved
0x5A
0x78
Reserved
IMAX
Revision 3.0
54 of 76
0x17
Reserved
AMP_PI
D_EN
Reserve
d
0x40
BEMF_FAULT_LIM
0x81
Reserved
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Addr
Register
7
0x1F
TOP_INT_CF
G7_L
6
FRQ_PID_Ki_L
0x20
TOP_INT_CF
G8
Reserved
0
RAPID_STOP_LIM
0x22
TOP_CTL1
Reserved
Reserved
0x23
TOP_CTL2
OVERRIDE_VAL
0x24
SEQ_CTL1
Reserved
0x25
SWG_C1
CUSTOM_WAVE_GEN_COEFF1
0x61
0x26
SWG_C2
CUSTOM_WAVE_GEN_COEFF2
0xB4
0x27
SWG_C3
CUSTOM_WAVE_GEN_COEFF3
0x28
SEQ_CTL2
PS_SEQ_LOOP
Reserved
5
4
3
2
1
0
Reset
0x20
SEQ_STA
RT
Reserved
FRQ_TRACK_BEMF_LIM
0x43
STANDBY
_EN
0x00
OPERATION_MODE
0x00
Reserved
Reserved
Reserved
FREQ_W
AVEFOR
M_TIME
BASE
WAVEGE
N_MODE
SEQ_C
ONTINU
E
0x08
0xEC
PS_SEQ_ID
0x00
0x29
GPI_0_CTL
Reserved
GPI0_SEQUENCE_ID
GPI0_M
ODE
0x2A
GPI_1_CTL
Reserved
GPI1_SEQUENCE_ID
GPI1_M
ODE
GPI1_POLARITY
0x08
0x2B
GPI_2_CTL
Reserved
GPI2_SEQUENCE_ID
GPI2_M
ODE
GPI2_POLARITY
0x10
0x2C
MEM_CTL1
WAV_MEM_BASE_ADDR
0x2D
MEM_CTL2
WAV_ME
M_LOCK
0x2E
ADC_DATA_
H1
ADC_VDD_H
0xFF
0x2F
ADC_DATA_
L1
Reserved
ADC_VDD_L
0x7F
0x43
POLARITY
Reserved
Reserved
0x44
LRA_AVR_H
LRA_PER_AVERAGE_H
0x00
0x45
LRA_AVR_L
Reserved
0x00
0x46
FRQ_LRA_P
ER_ACT_H
LRA_PER_ACTUAL_H
0x21
0x47
FRQ_LRA_P
ER_ACT_L
Reserved
0x4F
0x48
FRQ_PHASE
_H
DELAY_H
0x49
FRQ_PHASE
_L
DELAY_
FREEZE
0x4C
FRQ_CTL
Reserved
GPI0_POLARITY
0x00
0x84
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
POLARI
TY
LRA_PER_AVERAGE_L
LRA_PER_ACTUAL_L
Reserved
0x80
0x00
0x25
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LOOP_FI
LT_LOW
_BW
REF_UVLO_THRES
DELAY_SHIFT_L
0x05
Reserved
FREQ_T
RACKIN
G_AUTO
_ADJ
FREQ_T
RACKIN
G_FOR
CE_ON
0x02
Reserved
Reserved
Reserve
d
0x0E
0x5F
TRIM3
Reserved
LOOP_ID
AC_DOU
BLE_RA
NGE
0x60
TRIM4
Reserved
Reserved
Reserved
Reserved
LOOP_FILT_CAP_TRIM
LOOP_FILT_RES_TRI
M
0x9C
0x62
TRIM6
Reserved
Reserved
Reserved
Reserved
HBRIDGE_ERC_LS_TRI
M
HBRIDGE_ERC_HS_
TRIM
0x5F
FRQ_PA
USE_ON
_POLARI
TY_CHA
NGE
0x01
0x6E
TOP_CFG5
Datasheet
CFR0011-120-00
Reserved
Reserved
Reserved
Reserved
Revision 3.0
55 of 76
Reserved
DELAY_
BYPASS
V2I_FAC
TOR_OF
FSET_E
N
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Addr
Register
7
6
5
4
3
2
1
0
Reset
0x81
IRQ_EVENT_
ACTUATOR_
FAULT
Reserved
E_TEST_
ADC_SA
T_FAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x00
0x82
IRQ_STATU
S2
STA_
ADC_SA
T
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x00
0x83
IRQ_MASK2
ADC_SA
T_M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserve
d
0x00
0x84
to
0xE7
SNP_MEM_x
SNP_MEM_x where x = 0 to 99
6.2
0x00
Register Descriptions
Table 20: CHIP_REV (0x0000)
Bit
Mode
Symbol
Description
Reset
[7:4]
RO
CHIP_REV_MINOR
Device revision code (minor)
0xB
[3:0]
RO
CHIP_REV_MAJOR
Device revision code (major)
0xA
Table 21: IRQ_EVENT1 (0x0003)
Bit
Mode
Symbol
Description
Reset
[7]
RW
E_OC_FAULT
Over-current / short-circuit fault on the OUTP or OUTN pin
(write 1 to clear)
0x0
[6]
RW
E_ACTUATOR_FAULT
Actuator fault, see Section 5.6.6
(write 1 to clear)
0x0
[5]
RW
E_WARNING
System warnings
Read IRQ_EVENT_WARNING_DIAG for warning diagnostic
(write 1 to clear)
0x0
0x0
[4]
RW
E_SEQ_FAULT
Sequence faults: SEQ_ID_FAULT, memory fault or PWM
fault
Read IRQ_EVENT_SEQ_DIAG for diagnostic information
(write 1 to clear)
[3]
RW
E_OVERTEMP_CRIT
Critical chip temperature event, chip temperature has
exceeded the critical limit of 125 °C
(write 1 to clear)
0x0
[2]
RW
E_SEQ_DONE
IRQ indicating that sequence playback from waveform
memory is complete
(write 1 to clear)
0x0
[1]
RW
E_UVLO
Under-voltage fault, supply below the UVLO threshold
Clear to attempt restart
(write 1 to clear)
0x0
[0]
RW
E_SEQ_CONTINUE
IRQ indicating that playback of a new sequence has
occurred because SEQ_CONTINUE is set to 1
0x0
(write 1 to clear)
Table 22: IRQ_EVENT_WARNING_DIAG (0x0004)
Bit
Mode
Symbol
Description
Reset
[7]
RW
E_LIM_DRIVE
IRQ indicating that playback is limited because the power
supply level is lower than the sequence target
(write 1 to E_WARNING to clear)
0x0
Datasheet
CFR0011-120-00
Revision 3.0
56 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Bit
Mode
Symbol
Description
Reset
[6]
RW
E_LIM_DRIVE_ACC
IRQ indicating that acceleration is limited because the power
supply level is lower than required for the acceleration target
(write 1 to E_WARNING to clear)
0x0
Indicates that the memory data type configured in register
MEM_DATA_SIGNED does not match the acceleration
configuration (ACCELERATION_EN).
[4]
RW
E_MEM_TYPE
0x0
MEM_DATA_SIGNED = 1 for ACCELERATION_EN = 0
MEM_DATA_SIGNED = 0 for ACCELERATION_EN = 1
(write 1 to E_WARNING to clear)
[3]
RW
E_OVERTEMP_WARN
Over-temperature warning, chip temperature has exceeded
the warning limit of 105 °C
(write 1 to E_WARNING to clear)
0x0
Table 23: IRQ_EVENT_SEQ_DIAG (0x0005)
Bit
Mode
Symbol
Description
Reset
[7]
RW
E_SEQ_ID_FAULT
IRQ indicating that requested sequence ID configured in
PS_SEQ_ID is not valid
(write 1 to E_SEQ_FAULTto clear)
0x0
[6]
RW
E_MEM_FAULT
Indicates that the Waveform Memory is corrupted (empty,
invalid snippet ID, invalid frame structure)
(write 1 to E_SEQ_FAULTto clear)
0x0
[5]
RW
E_PWM_FAULT
IRQ indicating that the PWM input signal has timed out
(write 1 to E_SEQ_FAULTto clear)
0x0
Table 24: IRQ_STATUS1 (0x0006)
Bit
Mode
Symbol
Description
Reset
[7]
RO
STA_OC
Over-current / short circuit fault status
0x0
[6]
RO
STA_ACTUATOR
Actuator fault status
0x0
[5]
RO
STA_WARNING
System warnings status
0x0
[4]
RO
STA_PAT_FAULT
Sequence faults status
0x0
[3]
RO
STA_OVERTEMP_CRIT
Over-temperature status
0x0
[2]
RO
STA_PAT_DONE
Memory based sequence status
0x0
[1]
RO
STA_UVLO_VBAT_OK
UVLO output status: 0 during normal operation; 1 if there is
a UVLO event
0x0
[0]
RO
STA_SEQ_CONTINUE
Continuous sequence status
0x0
Table 25: IRQ_MASK1 (0x0007)
Bit
Mode
Symbol
Description
Reset
[7]
RW
OC_M
Over-current / short circuit fault mask
0x0
[6]
RW
ACTUATOR_M
Actuator fault mask
0x0
[5]
RW
WARNING_M
System warnings mask
0x0
[4]
RW
SEQ_FAULT_M
Sequence faults mask
0x0
[3]
RW
OVERTEMP_CRIT_M
Over-temperature fault mask
0x0
[2]
RW
SEQ_DONE_M
Memory based sequence interrupt mask
0x0
[1]
RW
E_UVLO_M
Soft shutdown fault mask
0x0
Datasheet
CFR0011-120-00
Revision 3.0
57 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Bit
Mode
Symbol
Description
Reset
[0]
RW
SEQ_CONTINUE_M
Continuous sequence interrupt mask
0x0
Description
Reset
Table 26: CIF_I2C1 (0x0008)
Bit
Mode
Symbol
I2 C
[7]
[6]
RW
RW
I2C_WR_MODE
I2C_TO_ENABLE
write mode
0x0 = Auto-increment (addr, data, data, data,…)
0x1 = Repeat (addr, data, addr, data,...)
0x0
I2C timeout enable. If there are no negative edges on SCL
for approx. 35 ms, the slave resets.
0x0 = Disabled
0x1
0x1 = Enabled
Table 27: FRQ_LRA_PER_H (0x000A)
Bit
Mode
Symbol
Description
Reset
Used for specifying the LRA drive frequency. MS-bits of the
initial LRA resonant frequency period.
𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] =
[7:0]
RW
LRA_PER_H
1
𝐿𝑅𝐴𝑓𝑟𝑒𝑞 × 1333.32 × 10−9
𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0]
𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0]
=
128
0x21
𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0]
= 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0]
− 128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0]
Where LRAfreq represents the LRA resonant frequency (in
Hz) as listed in the actuator datasheet. See Section 5.6.2.
Default corresponds to 174 Hz.
Datasheet
CFR0011-120-00
Revision 3.0
58 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 28: FRQ_LRA_PER_L (0x000B)
Bit
Mode
Symbol
Description
Reset
Used for specifying the LRA drive frequency. LS-bits of the
initial LRA resonant frequency period.
𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] =
[6:0]
RW
1
𝐿𝑅𝐴𝑓𝑟𝑒𝑞 × 1333.32 × 10−9
𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0]
𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0]
=
128
LRA_PER_L
0x4F
𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0]
= 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0]
− 128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0]
Where LRAfreq represents the LRA resonant frequency in
Hz as listed in the actuator datasheet. See Section 5.6.2.
Default corresponds to 174 Hz.
Table 29: ACTUATOR1 (0x000C)
Bit
[7:0]
Mode
RW
Symbol
Description
Reset
ACTUATOR_NO
MMAX
Nominal actuator voltage rating, unsigned, see Section 5.6.2
Sets full-scale of unsigned haptic waveform when acceleration
enabled (ACCELERATION_EN = 1)
𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑛𝑜𝑚𝑚𝑎𝑥
𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝑁𝑂𝑀𝑀𝐴𝑋 =
23.4 × 10−3
Default: 0x5A = 2.106 V
0x5A
Table 30: ACTUATOR2 (0x000D)
Bit
[7:0]
Mode
RW
Symbol
Description
Reset
ACTUATOR_ABS
MAX
Absolute actuator maximum voltage rating, see Section 5.6.2.
Overdrive is limited to this value when acceleration enabled
(ACCELERATION_EN = 1)
Sets full-scale of unsigned haptic waveform when acceleration
disabled
𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑎𝑏𝑠𝑚𝑎𝑥
𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝐴𝐵𝑆𝑀𝐴𝑋 =
23.4 × 10−3
Default: 0x78 = 2.808 V
0x78
Table 31: ACTUATOR3 (0x000E)
Bit
Mode
Symbol
Description
Reset
Actuator max current rating
𝐼𝑀𝐴𝑋 =
[4:0]
RW
IMAX
𝐼max _𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑚𝐴 − 28.6
7.2
0x17
where Imax_actuator_mA is the actuator max rated current in mA, as
listed in its datasheet, see Section 5.6.2.
Default: 0x17 = 194 mA
Datasheet
CFR0011-120-00
Revision 3.0
59 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 32: CALIB_V2I_H (0x000F)
Bit
Mode
Symbol
Description
Reset
MS-bits for translating actuator impedance to output voltage drive
level
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] =
𝑍 × (𝐼𝑀𝐴𝑋[4: 0] + 4)
1.6104
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0]
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0]
=
256
[7:0]
RW
V2I_FACTOR_H
0x01
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0]
= 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0]
− 256 × 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0]
Where V2I_FACTOR[15:0] is the 16-bit concatenation of
V2I_FACTOR_H[7:0] and V2I_FACTOR_L[7:0], Z is the
impedance of the actuator in Ω (as read from its datasheet), and
IMAX[4:0] is the 5-bit value of IMAX, see Section 5.6.2.
Table 33: CALIB_V2I_L (0x0010)
Bit
Mode
Symbol
Description
Reset
LS-bits for translating actuator impedance to output voltage drive
level
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] =
𝑍 × (𝐼𝑀𝐴𝑋[4: 0] + 4)
1.6104
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0]
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0]
=
256
[7:0]
RW
V2I_FACTOR_L
0x0D
𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0]
= 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0]
− 256 × 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0]
Where V2I_FACTOR[15:0] is the 16-bit concatenation of
V2I_FACTOR_H[7:0] and V2I_FACTOR_L[7:0], Z is the
impedance of the actuator in Ω (as read from its datasheet), and
IMAX[4:0] is the 5-bit value of IMAX, see Section 5.6.2.
Table 34: CALIB_IMP_H (0x0011)
Bit
Mode
Symbol
Description
Reset
MS-bits of calculated impedance (default 22 Ω), see
Section 5.7.3.
[7:0]
RO
Datasheet
CFR0011-120-00
IMPEDANCE_H
𝐼𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 (Ω) = 4 × 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐻
+ 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐿
Revision 3.0
60 of 76
0x00
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 35: CALIB_IMP_L (0x0012)
Bit
Mode
Symbol
Description
Reset
LS-bits of calculated impedance (default 22 Ω), see Section 5.7.3.
[1:0]
RO
IMPEDANCE_L
𝐼𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 (Ω) = 4 × 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐻
+ 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐿
0x0
Table 36: TOP_CFG1 (0x0013)
Bit
Mode
Symbol
[7]
RW
EMBEDDED_M
ODE
[5]
RW
ACTUATOR_TY
PE
[4]
RW
BEMF_SENSE_
EN
Description
Reset
Embedded operation enable (self-clearing IRQs), see
Section 5.7.7.
0x0
0x0 = Faults cleared by host
0x1 = DA7280 clears faults automatically
Specifies actuator type: LRA or ERM, see Section 5.6.2.
0x0 = LRA
0x0
0x1 = ERM
Enable internal loop computations; should be disabled only in
custom waveform and wideband operation, see Sections 5.7.5
and 5.7.6.
0x1
0x0 = Custom Waveform Operation
0x1 = Standard Operation
[3]
RW
FREQ_TRACK_
EN
Enable resonant frequency tracking; ignored in ERM mode, see
Section 5.3.
0x0 = frequency tracking disabled
0x1
0x1 = frequency tracking enabled
[2]
RW
ACCELERATION
_EN
[1]
RW
RAPID_STOP_E
N
[0]
RW
AMP_PID_EN
Enable Active Acceleration, see Section 5.4.
0x0 = Active Acceleration disabled
0x1 = Active Acceleration enabled
0x1
Enable Rapid Stop, see Section 5.4.
0x0 = Rapid Stop disabled
0x1 = Rapid Stop enabled
Enable Amplitude PID, see Section 5.4.
0x0 = Amplitude PID disabled
0x1
0x0
0x1 = Amplitude PID enabled
Table 37: TOP_CFG2 (0x0014)
Bit
[4]
Mode
Symbol
Description
Reset
RW
MEM_DATA_SIG
NED
Memory data format; set according to the value of
ACCELERATION_EN:
0x0 = unsigned (for ACCELERATION_EN = 1)
0x0
0x1 = signed (for ACCELERATION_EN = 0)
Datasheet
CFR0011-120-00
Revision 3.0
61 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Bit
Mode
Symbol
Description
Reset
Full-brake threshold for PWM mode with step size 6.66%, see
Section 5.2.5.
[3:0]
RW
FULL_BRAKE_T
HR
0x0 = brake threshold disabled
0x1 = 6.66 % of ACTUATOR_NOMMAX
0x1
0x2 = 13.33 % of ACTUATOR_NOMMAX
...
…~6.66% steps…
0x15 = 100 % of ACTUATOR_NOMMAX
Table 38: TOP_CFG3 (0x0015)
Bit
Mode
Symbol
Description
Reset
VDD margin setting. Target voltage needs to be below
VDD - VDD_MARGIN, otherwise voltage is clamped to
VDD - VDD_MARGIN and a LIM_DRIVE IRQ is generated. See
Section 5.7.13 for further details.
0x0 = 0 mV
[3:0]
RW
VDD_MARGIN
0x3
0x1 = 187.5 mV
0x2 = 375 mV
0x3 = 562.5 mV
...
…187.5 mV steps…
0xF = 2.8125 V
Table 39: TOP_CFG4 (0x0016)
Bit
Mode
Symbol
[7]
RW
V2I_FACTOR_FR
EEZE
[6]
RW
CALIB_IMPEDAN
CE_DIS
Description
Reset
Stop automatic updates to V2I_FACTOR_x, see Section 5.7.3.
0x0 = updates enabled
0x0
0x1 = updates disabled
Stop automatic updates to V2I_FACTOR_x during playback, see
Section 5.7.3.
0x0 = updates enabled
0x1
0x1 = updates disabled
Table 40: TOP_INT_CFG1 (0x0017)
Bit
Mode
Symbol
Description
Reset
[7:2]
RW
FRQ_LOCKED_L
IM
Limit for generating frequency locked signal that enabled scaling
of the frequency tracking PID gain, see Section 5.7.1. If error is
below the FRQ_LOCKED_LIM*4 frequency is locked
0x20
[1:0]
RW
BEMF_FAULT_LI
M
Limit for BEMF fault generation. If voltage is below the threshold
BEMF, a fault is generated, see Section 5.7.14.
0x0 = BEMF fault disabled
0x1 = 4.9 mV
0x2 = 27.9 mV
0x1
0x3 = 49.9 mV
Table 41: TOP_INT_CFG6_H (0x001C)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
FRQ_PID_Kp_H
MS-bits of the frequency tracking loop PID Kp proportional
coefficient, see Section 5.7.1 for details
0x0E
Datasheet
CFR0011-120-00
Revision 3.0
62 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 42: TOP_INT_CFG6_L (0x001D)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
FRQ_PID_Kp_L
LS-bits of the frequency tracking loop PID Kp proportional
coefficient, see Section 5.7.1 for details
0x20
Table 43: TOP_INT_CFG7_H (0x001E)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
FRQ_PID_Ki_H
MS-bits of the frequency tracking loop PID Ki integral coefficient,
see Section 5.7.1 for details
0x03
Table 44: TOP_INT_CFG7_L (0x001F)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
FRQ_PID_Ki_L
LS-bits of the frequency tracking loop PID Ki integral coefficient,
see Section 5.7.1 for details
0x20
Table 45: TOP_INT_CFG8 (0x0020)
Bit
Mode
Symbol
Description
Reset
[6:4]
RW
RAPID_STOP_
LIM
Selects the Rapid Stop threshold at which DA7280 stops driving
while braking, see Section 5.7.2
0x4
[3:0]
RW
FRQ_TRACK_
BEMF_LIM
Selects the frequency tracking threshold at which DA7280 pauses
frequency tracking, see Section 5.7.1
0x3
Table 46: TOP_CTL1 (0x0022)
Bit
Mode
Symbol
Description
Reset
[4]
RW
SEQ_START
Start/stop control of Waveform Memory sequence playback
0x0 = Stop playback and return to IDLE state
0x0
0x1 = Start playback
[3]
RW
STANDBY_E
N
Sets the state DA7280 returns to after completion of playback, see
Section 5.2.1.
0x0 = Return to IDLE state after playback
0x0
0x1 = Return to STANDBY state after playback
Haptic operation mode, see Section 5.2.
0x0 = Inactive mode
[2:0]
RW
OPERATION
_MODE
0x1 = Direct register override (DRO) mode
0x2 = Playback from PWM data source (PWM) mode
0x0
0x3 = Register triggered waveform memory (RTWM) mode
0x4 = Edge triggered waveform memory (ETWM) mode
Datasheet
CFR0011-120-00
Revision 3.0
63 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 47: TOP_CTL2 (0x0023)
Bit
Mode
Symbol
Description
Reset
Used to set the output drive level in DRO mode. Scales the
contents of ACTUATOR_ABSMAX and/or
ACTUATOR_NOMMAX, depending on whether Active
Acceleration is enabled. See Section 5.2.4.
[7:0]
RW
OVERRIDE_
VAL
OVERRIDE_VAL
Value
Scaling factor
when
ACCELERATION_
EN = 0
Scaling factor
when
ACCELERATION_
EN = 1
0x7F
1
1
0x7E
0.992
0.992
...
…step of 0.008…
…step of 0.008…
0x01
0.0079
0.0079
0x00
0
0
0xFF
-0.0079
0
...
…step of 0.008…
…step of 0.008…
0x81
-1
0
0x80
-1
0
0x0
Table 48: SEQ_CTL1 (0x0024)
Bit
[2]
Mode
Symbol
RW
FREQ_WAVE
FORM_TIME
BASE
Description
Reset
Frequency waveform timebase setting for waveform memory
frames. See Section 5.8.3.
0x0
5.44, 21.76, 43.52, 87.04 ms
0x1
0x0
1.36, 5.44, 21.76, 43.52 ms
Enable bit for custom waveform operation, see Section 5.7.5.
[1]
RW
WAVEGEN_
MODE
● If WAVEGEN_MODE = 0, then set BEMF_SENSE_EN = 1
● If WAVEGEN_MODE = 1,then set BEMF_SENSE_EN = 0
0x0
0x0 = Normal wave mode (step/ramp sequences)
0x1 = Custom wave mode (sinewave sequences)
[0]
RW
SEQ_CONTI
NUE
Control for back-to-back Waveform Memory sequence playback
during RTWM and ETWM modes. If SEQ_CONTINUE = 1, new
sequence playback starts at end of current sequence. Register is
self-cleared when the next sequence is started, see Section 5.6.5.
0x0
Description
Reset
Table 49: SWG_C1 (0x0025)
Bit
[7:0]
Mode
RW
Symbol
CUSTOM_W
AVE_GEN_C
OEFF1
Coefficient1 for custom wave generation, represents a proportion
of the set IMAX, see Section 5.7.5. Default corresponds to a sine
wave.
0x00 = 0 %
0x01 = 0.4 %
…
…steps of approx. 0.4 %
0x61
0x61 = 37.9 %
...
…steps of approx. 0.4 %
0xFF = 100 %
Datasheet
CFR0011-120-00
Revision 3.0
64 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 50: SWG_C2 (0x0026)
Bit
[7:0]
Mode
RW
Symbol
CUSTOM_W
AVE_GEN_C
OEFF2
Description
Reset
Coefficient2 for custom wave generation, represents a proportion
of the set IMAX, see Section 5.7.5. Default corresponds to a sine
wave.
0x00 = 0 %
0x01 = 0.4 %
…
…steps of approx. 0.4 %
0xB4
0xB4 = 70.3 %
...
…steps of approx. 0.4 %
0xFF = 100 %
Table 51: SWG_C3 (0x0027)
Bit
[7:0]
Mode
RW
Symbol
CUSTOM_W
AVE_GEN_C
OEFF3
Description
Reset
Coefficient1 for custom wave generation, represents a proportion
of the set IMAX, see Section 5.7.5. Default corresponds to a sine
wave.
0x00 = 0 %
0x01 = 0.4 %
…
…steps of approx. 0.4 %
0xEC
0xEC = 92.2 %
...
…steps of approx. 0.4 %
0xFF = 100 %
Table 52: SEQ_CTL2 (0x0028)
Bit
[7:4]
Mode
RW
Symbol
PS_SEQ_LOOP
Description
Reset
Number of times the pre-stored sequence (pointed to by
PS_SEQ_ID) is repeated, see Section 5.6.5.
0x0 = No repetition (sequence played once)
0x0
0x1 = 1 repetition (sequence played twice)
…
…step of 1…
0xF = 15 repetitions (sequence played 16 times)
[3:0]
RW
PS_SEQ_ID
ID of pre-stored and read-back of GPI triggered sequence,
see Section 5.6.5.4.
0x0
Table 53: GPI_0_CTL (0x0029)
Bit
Mode
Symbol
Description
Reset
[6:3]
RW
GPI0_SEQUENCE_ID
GPI_0 sequence ID, see Section 5.2.7.
0x0
[2]
RW
GPI0_MODE
GPI_0 mode of operation, see Section 5.2.7.
[1:0]
RW
Datasheet
CFR0011-120-00
GPI0_POLARITY
0x0 = Single sequence
0x1 = Multi-sequence
Selection which GPI edge triggers an event:
0x0 = Rising edge
0x1 = Falling edge
0x2 = Both edges
Revision 3.0
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0x0
0x0
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 54: GPI_1_CTL (0x002A)
Bit
Mode
Symbol
Description
Reset
[6:3]
RW
GPI1_SEQUENCE_ID
GPI_1 sequence ID, see Section 5.2.7.
0x1
[2]
RW
GPI1_MODE
GPI_1 mode of operation, see Section 5.2.7.
0x0 = Single sequence
0x0
0x1 = Multi-sequence
Selection which GPI edge triggers an event:
[1:0]
RW
0x0 = Rising edge
0x1 = Falling edge
GPI1_POLARITY
0x0
0x2 = Both edges
Table 55: GPI_2_CTL (0x002B)
Bit
Mode
Symbol
Description
Reset
[6:3]
RW
GPI2_SEQUENCE_ID
GPI_2 mode of operation, see Section 5.2.7.
0x2
GPI_2 mode of operation, see Section 5.2.7.
[2]
[1:0]
RW
RW
GPI2_MODE
0x0 = Single sequence
0x1 = Multi-sequence
0x0
Selection which GPI edge triggers an event:
0x0 = Rising edge
GPI2_POLARITY
0x0
0x1 = Falling edge
0x2 = Both edges
Table 56: MEM_CTL1 (0x002C)
Bit
Mode
Symbol
Description
Reset
[7:0]
RO
WAV_MEM_BAS
E_ADDR
Snippet memory start address, see Section 5.8.
0x84
Description
Reset
Table 57: MEM_CTL2 (0x002D)
Bit
[7]
Mode
RW
Symbol
WAV_MEM_LOCK
Lock bit for preventing access to Waveform Memory, see
Section 0.
0x0 = Locked
0x1
0x1 = Unlocked
Table 58: ADC_DATA_H1 (0x002E)
Bit
[7:0]
Mode
RO
Datasheet
CFR0011-120-00
Symbol
Description
Reset
ADC_VDD_H
Unsigned VDD measurement, see Section 5.7.13
𝑉𝐷𝐷 𝑆𝑢𝑝𝑝𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
= (𝐴𝐷𝐶_𝑉𝐷𝐷_𝐻 × 128 + 𝐴𝐷𝐶_𝑉𝐷𝐷_𝐿)
× 0.1831𝑚𝑉
0xFF
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 59: ADC_DATA_L1 (0x002F)
Bit
[6:0]
Mode
RO
Symbol
Description
Reset
ADC_VDD_L
Unsigned VDD measurement, see Section 5.7.13
𝑉𝐷𝐷 𝑆𝑢𝑝𝑝𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
= (𝐴𝐷𝐶_𝑉𝐷𝐷_𝐻 × 128 + 𝐴𝐷𝐶_𝑉𝐷𝐷_𝐿)
× 0.1831𝑚𝑉
0x7F
Table 60: POLARITY (0x0043)
Bit
Mode
Symbol
Description
Reset
[0]
RO
POLARITY
Current polarity read-back, see Section 5.7.8
0x0
Table 61: LRA_AVR_H (0x0044)
Bit
Mode
Symbol
Description
Reset
MS-bits of the average LRA resonant period based on the last
four half-periods, see Section 5.7.1. The following formula
describes the output:
[7:0]
RO
LRA_PER_AVE
RAGE_H
𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠)
= 1333.32 × 10−9 × (128
× 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐻
+ 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐿)
0x0
Table 62: LRA_AVR_L (0x0045)
Bit
Mode
Symbol
Description
Reset
LS-bits of the average LRA resonant period based on the last
four half-periods, see Section 5.7.1. The following formula
describes the output:
[6:0]
RO
LRA_PER_AVERA
GE_L
𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠)
= 1333.32 × 10−9 × (128
× 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐻
+ 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐿)
0x0
Table 63: FRQ_LRA_PER_ACT_H (0x0046)
Bit
Mode
Symbol
Description
Reset
MS-bits of the actual LRA resonant period based on halfperiod, see Section 5.5.The following formula describes the
output:
[7:0]
RO
Datasheet
CFR0011-120-00
LRA_PER_ACTUA
L_H
𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠)
= 1333.32 × 10−9 × (128
× 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐻
+ 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐿)
Revision 3.0
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0x21
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 64: FRQ_LRA_PER_ACT_L (0x0047)
Bit
Mode
Symbol
Description
Reset
LSBs of the actual LRA resonant period based on half-period,
see Section 5.5.The following formula describes the output:
[6:0]
RO
𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠)
= 1333.32 × 10−9 × (128
× 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐻
+ 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐿)
LRA_PER_ACTUAL
_L
0x4F
Table 65: FRQ_PHASE_H (0x0048)
Bit
[7:0]
Mode
RW
Symbol
DELAY_H
Description
Reset
Used during custom waveform operation, see Section 5.7.5.
Only use the following settings, all other settings are reserved:
0x0 = Setting for wideband mode
0x25
0x25 = Setting for closed-loop frequency tracking mode
Table 66: FRQ_PHASE_L (0x0049)
Bit
[7]
Mode
RW
Symbol
Description
Reset
DELAY_FREEZE
Used during custom waveform operation. Set to 1 only in
wideband mode with frequency tracking disabled, see
Section 5.7.5
0x0
0x0 = Setting for closed-loop frequency tracking mode
0x1 = Setting for wideband mode
[2:0]
RW
DELAY_SHIFT_L
Used during custom waveform operation, see Section 5.7.5.
Only use the following settings, all other settings are reserved:
0x0 = Setting for wideband mode
0x5
0x5 = Setting for closed-loop frequency tracking mode
Table 67: FRQ_CTL (0x004C)
Bit
[1]
Mode
Symbol
Description
Reset
RW
FREQ_TRACKING_
AUTO_ADJ
Enables the auto-scaling of the frequency tracking
proportional coefficient, see Section 5.7.1.
0x0 = No auto-scaling
0x1
0x1 = Auto-scaling
[0]
RW
FREQ_TRACKING_
FORCE_ON
Force the tracking on when the error exceeds 25 % of initial
guess, see Section 5.7.1.
0x0 = Off
0x0
0x1 = On
Table 68: TRIM3 (0x005F)
Bit
Mode
Symbol
Description
Reset
[6]
RW
LOOP_IDAC_DOU
BLE_RANGE
Loop IDAC double range control, see Section 5.7.12
0x0
[5]
RW
LOOP_FILT_LOW_
BW
Loop filter low bandwidth, see Section 5.7.9
0x0
Datasheet
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Revision 3.0
68 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Bit
[4:3]
Mode
RW
Symbol
REF_UVLO_THRE
S
Description
Reset
UVLO threshold, see Section 5.7.10
00 = 2.7 V
01 = 2.8 V
10 = 2.9 V
0x1
11 = 3.0 V
Table 69: TRIM4 (0x0060)
Bit
Mode
Symbol
Description
Reset
[3:2]
RW
LOOP_FILT_CAP_
TRIM
Loop capacitor trim, see Section 5.7.9
0x3
[1:0]
RW
LOOP_FILT_RES_
TRIM
Loop resistance trim, see Section 5.7.9
0x0
Description
Reset
Table 70: TRIM6 0x(0062)
Bit
[3:2]
Mode
RW
Symbol
HBRIDGE_ERC_L
S_TRIM
Low side edge rate control setting, see Section 5.7.11.
00 = 25 mV/ns
01 = 50 mV/ns
10 = 75 mV/ns
0x3
11 = 100 mV/ns
High side edge rate control setting, see Section 5.7.11
[1:0]
RW
HBRIDGE_ERC_H
S_TRIM
00 = 25 mV/ns
01 = 50 mV/ns
0x3
10 = 75 mV/ns
11 = 100 mV/ns
Table 71: D2602_TOP_CFG5 (0x006E)
Bit
Mode
Symbol
Description
Reset
[2]
RW
DELAY_BYPASS
Delay comparator bypass enable
0x0
RW
FRQ_PAUSE_ON_
POLARITY_CHANG
E
Pause the frequency update when the drive polarity changes
(during rapid stop, negative accelaration, negative DRO
value)
0x0 = Pause disabled
[1]
0x0
0x1 = Pause enabled
[0]
RW
V2I_FACTOR_OFF
SET_EN
Apply a 50 mV offset to the V2I factor calculation
0x0 = No offset applied
0x1
0x1 = 50 mV offset applied
Table 72: IRQ_EVENT_ACTUATOR_FAULT (0x0081)
Bit
Mode
Symbol
Description
Reset
[2]
RO
ADC_SAT_FAULT
ADC produced saturated result, which is not expected to
happen (write 1 to E_ACTUATOR to clear)
0x0
Datasheet
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Revision 3.0
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DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Table 73: IRQ_STATUS2 (0x0082)
Bit
Mode
Symbol
Description
Reset
[7]
RO
STA_ADC_SAT
Status of ADC saturation fault: ADC_SAT_FAULT
0x0
Table 74: IRQ_MASK2 (0x0083)
Bit
Mode
Symbol
Description
Reset
[7]
RW
ADC_SAT_M
Masking for ADC saturation fault: ADC_SAT_FAULT
0x0
Register SNP_MEM_xx
Table 75 shows the first, intermediary, and last snippet memory registers.
● The snippet register addresses increment by 1 for each snippet.
● The Bit ([7:0]), Mode (RW), and Reset (0x0) are identical for each snippet register.
● For further details on the Waveform Memory, see Section 5.8.
Table 75: SNP_MEM_xx (0x0084 to 0x00E7)
Bit
Mode
Symbol
Description
Reset
[7:0]
RW
SNP_MEM_00
Snippet memory byte 0
0x0
[7:0]
RW
SNP_MEM_xx
Snippet memory byte x
0x0
[7:0]
RW
SNP_MEM_99
Snippet memory byte 99
0x0
Datasheet
CFR0011-120-00
Revision 3.0
70 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
7
7.1
Package Information
WLCSP Package Outline
Figure 39: WLCSP Package Outline Drawing
Datasheet
CFR0011-120-00
Revision 3.0
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30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
7.2
QFN Package Outline
Figure 40: QFN Package Outline Drawing
Datasheet
CFR0011-120-00
Revision 3.0
72 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
7.3
Moisture Sensitivity Level
The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor
lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be
exposed to an environment with a specified maximum temperature and a maximum relative humidity
before the solder reflow process. The MSL classification is defined in Table 76.
For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be
downloaded from http://www.jedec.org.
The WLCSP package is qualified for MSL 1.
The QFN package is qualified for MSL 3.
Table 76: MSL Classification
MSL Level
Floor Lifetime
Conditions
MSL 4
72 hours
30 °C / 60 % RH
MSL 3
168 hours
30 °C / 60 % RH
MSL 2A
4 weeks
30 °C / 60 % RH
MSL 2
1 year
30 °C / 60 % RH
MSL 1
Unlimited
30 °C / 85 % RH
7.4
WLCSP Handling
Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it
is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be
used, but metal tweezers are not acceptable, since contact may easily damage the silicon chip.
Removal of a WLCSP package will cause damage to the solder balls. Therefore, a removed sample
cannot be reused.
WLCSP packages are sensitive to visible and infrared light. Precautions should be taken to properly
shield the chip in the final product.
7.5
Soldering Information
Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can
be downloaded from http://www.jedec.org.
Datasheet
CFR0011-120-00
Revision 3.0
73 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
8
Ordering Information
The ordering number consists of the part number followed by a suffix indicating the packing method.
For details and availability, please consult Dialog Semiconductor’s customer support portal or your
local sales representative.
Table 77: Ordering Information
Part Number
Package
Size (mm)
Shipment Form
Pack Quantity
DA7280-00V42
WLCSP
1.35 x 1.75
Tape and reel
4500
DA7280-00V4C
WLCSP
1.35 x 1.75
Tape and reel
250
DA7280-00FV2
QFN
3.0 x 3.0
Tape and reel
6000
DA7280-00FVC
QFN
3.0 x 3.0
Tape and reel
250
9
Application Information
The Dialog SmartCanvas GUI enables easy access to the device and can be used to accelerate
product development time. For further information, contact your Dialog Semiconductor
representative.
VDD
VDD
C1
100 nF
GND_1
VDDIO
VDDIO
OUTP
GND_2
DA7280
LRA/
ERM
GPI_0/PWM
GPI_1
OUTN
GPI_2
VDDIO
VDDIO
R1
2k2 Ω
R2
2k2 Ω
R3
5k6 Ω
SDA
nIRQ
SCL
Figure 41: External Components Diagram
Note: Drive the GPI pins from the same voltage level as the VDDIO pin.
Note: Ground any unused GPI pins.
Note: The C1 capacitor should be placed as close as possible to, and between, VDD and GND_1. It
removes high-frequency noise only; ensure additional decoupling (typ. 10 µF) is included elsewhere
in the system.
Datasheet
CFR0011-120-00
Revision 3.0
74 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
10 Layout Guidelines
For optimal layout, place the 100 nF capacitor as close to VDD and GND_1 pins as possible. It is
also advisable to use solid a ground plane under the device.
The QFN can be routed out on a single layer. It is recommended to connect GND_1 and GND_2 to a
local ground plane on the top layer with a low-impedance via connection to the main ground plane,
see Figure 43.
VIA TO
VDD
LAYER
nIRQ
SCL
SDA
GPI_1
GPI_2
VDDIO
GPI_0/
PWM
OUTN
GND_2
VDD
OUTP
GND_1
VIA
VIA
VIA
VIA TO
VDDIO
LAYER
VIA TO GND LAYER
SOLID GND
CONNECTION
ON TOP LAYER
100 nF Capacitor
0201 (0603)
Figure 42: WLCSP Example PCB Layout
nIRQ
SCL
SDA
GPI_2
VDDIO
GPI_1
OUTN
GPI_0/PWM
GND_2
VDD
OUTP
GND_1
VIA
VIA TO
VDDIO
LAYER
VIA
VIAS TO
GND LAYER
SOLID GND
CONNECTION
ON TOP LAYER
VIA
100 nF Capacitor
0603 (1608)
Figure 43: QFN Example PCB Layout
Datasheet
CFR0011-120-00
Revision 3.0
75 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
DA7280
LRA/ERM Haptic Driver with Multiple Input Triggers,
Integrated Waveform Memory and Wideband Support
Status Definitions
Revision
Datasheet Status
Product Status
Definition
1.
Target
Development
This datasheet contains the design specifications for product development.
Specifications may be changed in any manner without notice.
2.
Preliminary
Qualification
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
3.
Final
Production
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification changes
are communicated via Customer Product Notifications. Datasheet changes
are communicated via www.dialog-semiconductor.com.
4.
Obsolete
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
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Datasheet
CFR0011-120-00
Revision 3.0
76 of 76
30-Jul-2019
© 2019 Dialog Semiconductor
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