DAC1627D1G25HN-C18

DAC1627D1G25 Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating Rev. 4.00 — 12 December 2012 Product data sheet 1. General description The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter (DAC). It incorporates selectable ×2, ×4 and ×8 interpolation filters optimized for multi-carrier and broadband wireless transmitters at sample rates of up to 1.25 Gsps. The DAC1627D1G25 is supplied by two power supplies and integrates a differential scalable output current up to 34 mA. The DAC1627D1G25 meets multi-carrier Global System for Mobile communications (GSM) specifications. For example, with an NCO frequency of 153.6 MHz and a DAC clock frequency of 1.2288 Gsps the full-scale dynamic range is: • SFDRRBW = 90 dBc (bandwidth = 180 MHz) • IMD3 = 85 dBc The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25. The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR interface accepts a multiplex input data stream such as interleaved or folded. An internal LVDS input auto-calibration ensures the robustness and stability of the interface. Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. A 40-bit Numerically Controlled Oscillator (NCO) sets the mixer frequency. High resolution internal gain, phase and offset control provide outstanding image and Local Oscillator (LO) signal rejection at the system analog modulator output. An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at the DAC output. Multiple Device Synchronization (MDS) allows synchronization of the outputs of multiple DAC devices. MDS guarantees a maximum skew of one output clock period between several devices. The DAC1627D1G25 includes a low noise capacitor-free integrated Phase-Locked Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate. The DAC1627D1G25 is available in an HVQFN72 package (10 mm × 10 mm). ® DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 2. Features and benefits
Dual-channel 16-bit resolution










Synchronization of multiple DAC devices 1.25 Gsps maximum update rate
3-wire or 4-wire mode SPI interface Selectable ×2, ×4 and ×8 interpolation
Differential scalable output current from filters 8.1 mA to 34 mA Low noise capacitor-free integrated
External analog offset control Phase-Locked Loop (PLL) (10-bit auxiliary DACs) Embedded Numerically Controlled
High resolution internal digital gain and Oscillator (NCO) with 40-bit offset control to support high programmable frequency performance IQ-modulator image rejection Embedded complex (I/Q) modulator
Internal phase correction Two power supplies
Inverse (sin x) / x function LVDS DDR compatible input interface
Power-down mode and Sleep mode; with on-chip 100 Ω terminations 5-bit NCO low-power mode LVDS DDR input clock up to 400 MHz
On-chip 1.25 V reference LVDS or LVPECL compatible DAC clock
Industrial temperature range −40 °C to +85 °C Interleaved or folded I and Q data input
72 pins small form factor HVQFN mode package 3. Applications





Wireless infrastructure: MC_GSM, LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communications: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Digital radio links Instrumentation Automated Test Equipment (ATE) 4. Ordering information Table 1. Ordering information Type number DAC1627D1G25 Package Name Description Version HVQFN72 plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 × 10 × 0.85 mm SOT813-3 DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 2 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SDO SDIO SCS_N SCLK DAC NCO 40-bit frequency setting 16-bit phase adjustment SPI DCMSU cos IO0 LDCLKP CDI FIR 2 x2 FIR 3 x2 FIR 1 FIR 2 - FIR 3 + LDCLKN x2 x2 x2 IOUTAP + MDS COARSE 16 AUXAN + X sin X DAC A REF. BANDGAP AND BIASING OFFSET CONTROL X sin X + IOUTAN CLIPPING + GAPOUT VIRES IOUTBP CLIPPING DAC B IOUTBN 10-BIT ANALOG GAIN CONTROL CLKP CLOCK GENERATOR/PLL CLKN COMPLEX MODULATOR MDSP MDSN 10-BIT OFFSET CONTROL MULTI-DAC SYNCHRONIZATION Fig 1. DAC1627D1G25 block diagram AUXBP AUXBN 3 of 81 © IDT 2012. All rights reserved. DAC1627D1G25 RESET_N AUX. DAC Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 LD(15)N to LD(0)N x2 16 LVDS DDR/ DIF AUXAP 10-BIT ANALOG GAIN CONTROL ALIGNP ALIGNN AUX. DAC sin INTERRUPT INTERNAL MONITORING FIR 1 LD(15)P to LD(0)P 10-BIT OFFSET CONTROL PHASE COMPENSATION DIGITAL GAIN/OFFSET IO1 Integrated Device Technology DAC1627D1G25 Product data sheet 5. Block diagram DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 6. Pinning information 55 VDDA(1V8)_D 56 IOUTBN 57 IOUTBP 58 VDDA(1V8)_D 59 VDDA(3V3) 60 AUXBP 61 AUXBN 62 VDDA(1V8)_P1 63 VIRES 64 GAPOUT 65 VDDA(1V8)_P2 66 AUXAN 67 AUXAP 69 VDDA(1V8)_D 68 VDDA(3V3) 70 IOUTAP terminal 1 index area 71 IOUTAN 72 VDDA(1V8)_D 6.1 Pinning CLKP 1 54 RESET_N CLKN 2 53 SCS_N MDSP 3 52 SCLK MDSN 4 51 SDIO TM 5 50 SDO ALIGNP 6 49 IO0 ALIGNN 7 48 IO1 LD[15]P 8 47 LD[0]N LD[15]N 9 46 LD[0]P DAC LD[14]P 10 45 LD[1]N VDDD 36 LD[5]N 35 LD[5]P 34 LD[6]N 33 LD[6]P 32 LD[7]N 31 LD[7]P 30 n.c. 29 LCKN 28 37 LD[4]P LCKP 27 38 LD[4]N LD[11]N 18 VDDD 26 39 LD[3]P LD[11]P 17 LD[8]P 24 40 LD[3]N LD[12]N 16 LD[8]N 25 41 LD[2]P LD[12]P 15 LD[9]N 23 LD[13]N 14 LD[9]P 22 43 VDDD 42 LD[2]N LD[10]N 21 LD[13]P 13 VDDD 19 44 LD[1]P VDDD 12 LD[10]P 20 LD[14]N 11 Transparent top view Fig 2. DAC1627D1G25 pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Type[1] Description CLKP 1 I DAC clock positive input CLKN 2 I DAC clock negative input MDSP 3 IO multi-device synchronization positive signal MDSN 4 IO multi-device synchronization negative signal TM 5 I Test mode selection (connect to GND) ALIGNP 6 I positive input for data alignment ALIGNN 7 I negative input for data alignment LD[15]P 8 I LVDS positive input bit 15[2] LD[15]N 9 I LVDS negative input bit 15[2] DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 4 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 2. Pin description …continued Symbol Pin Type[1] Description LD[14]P 10 I LVDS positive input bit 14[2] LD[14]N 11 I LVDS negative input bit 14[2] VDDD 12 P digital power supply LD[13]P 13 I LVDS positive input bit 13[2] LD[13]N 14 I LVDS negative input bit 13[2] LD[12]P 15 I LVDS positive input bit 12[2] LD[12]N 16 I LVDS negative input bit 12[2] LD[11]P 17 I LVDS positive input bit 11[2] LD[11]N 18 I LVDS negative input bit 11[2] VDDD 19 P digital power supply LD[10]P 20 I LVDS positive input bit 10[2] LD[10]N 21 I LVDS negative input bit 10[2] LD[9]P 22 I LVDS positive input bit 9[2] LD[9]N 23 I LVDS negative input bit 9[2] LD[8]P 24 I LVDS positive input bit 8[2] LD[8]N 25 I LVDS negative input bit 8[2] VDDD 26 P digital power supply LCKP 27 I LVDS positive data clock input LCKN 28 I LVDS negative data clock input n.c. 29 - not connected LD[7]P 30 I LVDS positive input bit 7[2] LD[7]N 31 I LVDS negative input bit 7[2] LD[6]P 32 I LVDS positive input bit 6[2] LD[6]N 33 I LVDS negative input bit 6[2] LD[5]P 34 I LVDS positive input bit 5[2] LD[5]N 35 I LVDS negative input bit 5[2] VDDD 36 P digital power supply LD[4]P 37 I LVDS positive input bit 4[2] LD[4]N 38 I LVDS negative input bit 4[2] LD[3]P 39 I LVDS positive input bit 3[2] LD[3]N 40 I LVDS negative input bit 3[2] LD[2]P 41 I LVDS positive input bit 2[2] LD[2]N 42 I LVDS negative input bit 2[2] VDDD 43 P digital power supply LD[1]P 44 I LVDS positive input bit 1[2] LD[1]N 45 I LVDS negative input bit 1[2] LD[0]P 46 I LVDS positive input bit 0[2] LD[0]N 47 I LVDS negative input bit 0[2] IO1 48 IO IO port bit 1 IO0 49 IO IO port bit 0 SDO 50 O SPI data output DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 5 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 2. Pin description …continued Symbol Pin Type[1] Description SDIO 51 IO SPI data input/output SCLK 52 I SPI clock SCS_N 53 I SPI chip select (active LOW) RESET_N 54 I general reset (active LOW) VDDA(1V8)_D 55 P 1.8 V analog power supply (DAC core) IOUTBN 56 O complementary DAC B output current IOUTBP 57 O DAC B output current VDDA(1V8)_D 58 P 1.8 V analog power supply (DAC core) VDDA(3V3) 59 P 3.3 V analog power supply AUXBP 60 O auxiliary DAC B output current AUXBN 61 O complementary auxiliary DAC B output current VDDA(1V8)_P1 62 P 1.8 V analog power supply (PLL) VIRES 63 IO DAC biasing resistor GAPOUT 64 IO band gap input/output voltage VDDA(1V8)_P2 65 P 1.8 V analog power supply (PLL) AUXAN 66 O complementary auxiliary DAC A output current AUXAP 67 O auxiliary DAC A output current VDDA(3V3) 68 P 3.3 V analog power supply VDDA1V8_D 69 P 1.8 V analog power supply (DAC core) IOUTAP 70 O DAC A output current IOUTAN 71 O complementary DAC A output current VDDA(1V8)_D 72 P 1.8 V analog power supply (DAC core) GND H G ground (exposed die pad) [1] P: power supply; G: ground; I: input; O: output. [2] The LVDS input data bus order can be reversed and each element can be swapped between P and N using dedicated registers (see Table 60). 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDDA(3V3) analog supply voltage (3.3 V) VDDD digital supply voltage [1] VDDA(1V8) analog supply voltage (1.8 V) Max Unit −0.5 +4.6 V −0.5 +2.5 V −0.5 +2.5 V VI input voltage input pins referenced to GND −0.5 +2.5 V VO output voltage pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to GND −0.5 +4.6 V DAC1627D1G25 Product data sheet Min © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 6 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 3. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Tstg Min Max Unit storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature −40 +125 °C [1] Conditions Connect the analog 1.8 V power supply to pins VDDA1V8_D, VDDA1V8_P1, and VDDA1V8_P2. 8. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Typ Unit Rth(j-a) thermal resistance from junction to ambient [1] 16.2 K/W Rth(j-c) thermal resistance from junction to case [1] 6.7 K/W [1] Conditions Value for six-layer board in still air with a minimum of 49 thermal vias. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 7 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 9. Characteristics Table 5. Characteristics VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 42; output level = 1 V (p-p). Test[1] Min Typ Max Unit analog supply voltage (3.3 V) C 3.15 3.3 3.45 V VDDD digital supply voltage C 1.7 1.8 1.9 V VDDA(1V8) analog supply voltage (1.8 V) C 1.7 1.8 1.9 V IDDA(3V3) analog supply Auxiliary DAC on current (3.3 V) C 51 55 59 mA IDDD digital supply current fs = 983.04 Msps; ×4 interpolation; no NCO; MDS off C 475 525 585 mA fs = 620 Msps; ×2 interpolation; NCO on; no MDS C 400 450 500 mA 207 218 230 mA 207 218 230 mA fs = 1228.8 Msps; C ×4 interpolation; 5-bit NCO; MDS off - 1730 - mW fs = 983.04 Msps; C ×4 interpolation; 5-bit NCO; MDS off - 1580 - mW fs = 983.04 Msps; ×4 interpolation; NCO off; MDS off - 1500 - mW - 1370 - mW C - 63 - mW C 150 - 1000 mV Symbol Parameter VDDA(3V3) IDDA(1V8) Ptot Conditions analog supply fs = 983.04 Msps; 1 V (p-p) C current fs = 620 Msps; 1 V (p-p) C (1.8 V) total power dissipation C fs = 620 Msps; ×2 interpolation; 5-bit NCO; MDS off power-down using SPI register [2] [2] Clock inputs (pins CLKP, CLKN) Vi(clk)dif differential clock input voltage peak-to-peak Ri input resistance D - 200 - kΩ Ci input capacitance D - 1 - pF DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 8 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 5. Characteristics …continued VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 42; output level = 1 V (p-p). Symbol Parameter Test[1] Conditions Min Typ Max Unit Digital inputs (pins LD[15]P to LD[0]P, LD[15]N to LD[0]N, LCKP and LCKN, ALIGNP and ALIGNN) Vi input voltage Vidth input differential threshold voltage Ri input resistance Ci input capacitance |Vgpd| < 50 mV[3] C 825 - 1575 mV mV[3] C −100 - +100 mV D - 100 - Ω |Vgpd| < 50 D - 0.8 - pF D - 0.9 - pF C - 500 - mV D - 0.6 - pF D - 100 - Ω |Vgpd| < 50 mV[3] C 825 - 1575 mV mV[3] C −100 - +100 mV pins LCKP and LCKN Digital inputs/outputs (pins MDSN, MDSP) Vo(dif)(p-p) peak-to-peak differential output voltage Ci input capacitance Ri input resistance Vi input voltage Vidth input differential threshold voltage between GND and pin MDSN or MDSP |Vgpd| < 50 Digital inputs/outputs (pins IO0, IO1, SDO, SDIO, SCLK, SCS_N, RESET_N) VIL LOW-level input voltage C GND - 0.3VDDD V VIH HIGH-level input voltage C 0.7VDDD - VDDD V VOL LOW-level output voltage pins IO0, IO1, SDO, and SDIO C GND - 0.1VDDD V VOH HIGH-level output voltage pins IO0, IO1, SDO, and SDIO C 0.9VDDD - VDDD V IIL LOW-level input current maximum VIL I −10 - +10 µA IIH HIGH-level input current minimum VIH I −10 - +10 µA Ci input capacitance D - 2.2 - pF DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 9 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 5. Characteristics …continued VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 42; output level = 1 V (p-p). Symbol Parameter Test[1] Conditions Min Typ Max Unit D - 2.5 - mA D 8.1 - 34 mA default value D - 20 - mA compliance range D 2.3 - VDDA(3V3) V Analog outputs (pins IOUTAP, IOUTAN, IOUTBP, IOUTBN) Ibias bias current DC current IO(fs) full-scale controlled by the analog output current GAIN registers (see Table 33) VO output voltage VO(cm) common-mod 1 V (p-p) DAC output e output configuration voltage 2 V (p-p) DAC output configuration D - 3 - V D - 2.8 - V Ro output resistance D - 250 - kΩ Co output capacitance D - 5 - pF I - 1.21 - V D - 40 - µA between pins OUTAN and OUTBN and pins OUTAP and OUTBP Reference voltage output (pin GAPOUT) VO(ref) reference output voltage Tamb = +25 °C IO(ref) reference 1.25 V external voltage output current Analog auxiliary outputs (pins AUXAP, AUXAN, AUXBP and AUXBN) IO(fs) VO(aux) full-scale auxiliary DAC A; output current differential outputs I - 3.1 - mA auxiliary DAC B; differential outputs I - 3.1 - mA compliance range D 0 - 2.3 V auxiliary output voltage LVDS input timing fdata data rate fs(max) specification must be C respected (fs = fdata × interpolation factor) - - 400 MHz tsk(clk-D) skew time from clock to data input fDATA = 184.32 Mhz C 800 - 830 ps fDATA = 245.76 MHz C 500 - 675 ps fDATA = 307.2 MHz C 300 - 520 ps fDATA = 368.64 MHz C 150 - 500 ps DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 10 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 5. Characteristics …continued VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 42; output level = 1 V (p-p). Symbol Parameter Conditions tsu set-up time manual tuning mode (see Figure 29); depends on LDCLK_DEL[3:0] 0000 thold hold time Test[1] Min Typ Max Unit C −300 - - ps 0001 C −365 - - ps 0010 C −440 - - ps 0011 C −520 - - ps 0100 C −590 - - ps 0101 C −675 - - ps 0110 C −750 - - ps 0111 C −830 - - ps 1000 C −845 - - ps 1001 C −845 - - ps 1010 C −1000 - - ps 1011 C −1100 - - ps 1100 C −1220 - - ps 1101 C −1290 - - ps 1110 C −1360 - - ps 1111 C −1450 - - ps 0000 C 790 - - ps 0001 C 870 - - ps manual tuning mode (see Figure 28); depends on LDCLK_DEL[3:0]: 0010 C 950 - - ps 0011 C 1055 - - ps 0100 C 1140 - - ps 0101 C 1230 - - ps 0110 C 1360 - - ps 0111 C 1460 - - ps 1000 C 1900 - - ps 1001 C 2075 - - ps 1010 C 2250 - - ps 1011 C 2400 - - ps 1100 C 2560 - - ps 1101 C 2740 - - ps 1110 C 2900 - - ps 1111 C 3000 - - ps DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 11 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 5. Characteristics …continued VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 42; output level = 1 V (p-p). Symbol Parameter Conditions Test[1] Min Typ Max Unit DAC output timing fs(max) maximum sampling rate C 1250 - - Msps ts settling time D - 20 - ns D 50 - 1000 Msps register value = 8000000000h D - −500 - MHz register value = FFFFFFFFFFh D - −0.9095 - mHz register value = 0000000000h D - 0 - Hz register value = 0000000001h D - +0.9095 - mHz register value = 7FFFFFFFFFh D - +499.99909 - MHz D - 0.9095 - mHz register value = F8000000000h D - −500 - MHz register value = F8000000000h D - −31.25 - MHz register value = 00000000000h D - 0 - Hz register value = 08000000000h D - +31.25 - MHz register value = 7FFFFFFFFFh D - +468.75 - MHz D - 31.25 - MHz I - 85.5 - dBc I - 85.5 - dBc to ± 0.5 LSB Internal PLL timing fs sampling rate 40-bit NCO frequency range; fs = 1000 Msps fNCO fstep NCO frequency two’s complement coding step frequency Low-power NCO frequency range; fs = 1000 MHz fNCO fstep NCO frequency two’s complement coding step frequency Dynamic performance SFDR spurious-free dynamic range fdata = 184.32 MHz; fs = 737.28 Msps; BW = fs / 2 fo = 20 MHz at −1 dBFS; fdata = 245.76 MHz; fs = 983.04 Msps; BW = fs / 2 fo = 20 MHz at −1 dBFS DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 12 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 5. Characteristics …continued VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 42; output level = 1 V (p-p). Test[1] Min Typ Max Unit BW = 100 MHz I - 90 - dBc BW = 180 MHz I - 91 - dBc BW = 100 MHz I - 88 - dBc BW = 180 MHz I - 91 - dBc fdata = 245.76 MHz; C fs = 983.04 Msps; fo1 = 20 MHz; fo2 = 21 MHz; ×4 interpolation; output level = −1 dBFS - > 95 - dBc fdata = 245.76 MHz; fs = 983.04 Msps; fo1 = 152 MHz; fo2 = 155.1 MHz; ×4 interpolation; output level = −1 dBFS I - 85 - dBc 1 carrier; BW = 5 MHz C - 81.5 - dBc 2 carriers; BW = 10 MHz C - 76.5 - dBc 4 carriers; BW = 20 MHz C - 73 - dBc C - 73.5 - dBc Symbol Parameter Conditions SFDRRBW restricted bandwidth spurious-free dynamic range fdata = 245.76 MHz; fs = 983.04 Msps; fo = 147 MHz fdata = 307.2 MHz; fs = 1228.8 Msps; fo = 158.6 MHz IMD3 ACPR third-order intermodulati on distortion adjacent channel power ratio with WCDMA pattern; fs = 1228.8 Msps; ×4 interpolation; fNCO = 153.6 MHz with WCDMA pattern; fs = 983.04 Msps; ×4 interpolation; fNCO = 40 MHz 4 carriers; BW = 20 MHz DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 13 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 5. Characteristics …continued VDDA(1V8) = 1.8 V; VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition defined in Figure 42; output level = 1 V (p-p). Symbol Parameter Conditions αisol(ch-ch) isolation between channels NSD Test[1] Min Typ Max Unit fs = 1228.8 Msps; C ×4 interpolation; fout = 10 MHz; NCO = off; level = 0.1 dBFS; both DAC channels enabled - 110 - dBc C fs = 1228.8 Msps; ×4 interpolation; fout = 83 MHz; NCO = off; level = 0.1 dBFS; both DAC channels enabled - 95 - dBc fs = 1228.8 Msps; C ×4 interpolation; fout = 210 MHz; NCO = on; level = 0.1 dBFS; one DAC channel enabled; one DAC channel disabled - 81 - dBc D - −166 - dBm/Hz D - −164 - dBm/Hz noise spectral fs = 983.04 Msps; ×4 interpolation; density fo = 20 MHz at −1 dBFS fs = 983.04 Msps; ×4 interpolation; fo = 153.6 MHz at −1 dBFS [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. [2] Connect VDDA(1V8)_D, VDDA(1V8)_P1 and VDDA(1V8)_P2 to the same 1.8 V analog power supply. Use dedicated filters for the three power pins. [3] |Vgpd| represents the ground potential difference voltage. This voltage is the result of current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground voltages. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 14 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 10. Typical characteristics Typical measurement done at Tamb = +25 °C in typical power supply condition, IO(fs) = 20 mA, external PLL, no auxiliary DAC, no inverse (sinus x) / x, and no output correction. The output load condition defined in Figure 42. All graphs are based on average measurements using several devices. 90 90 H2 (dBc) H2 (dBc) 80 80 70 70 (1) (2) (3) 60 (1) (2) (3) 60 50 50 40 40 0 100 200 300 0 100 200 fout (MHz) (1) 0 dBFS (1) 0 dBFS (2) −7 dBFS (2) −7 dBFS (3) −10 dBFS Fig 3. (3) −10 dBFS Second harmonic distortion versus output frequency over input scale at fs = 983.04 MHz Fig 4. Second harmonic distortion versus output frequency over input scale at fs = 1228.8 MHz 95 95 H3 (dBc) H3 (dBc) 85 85 75 75 (1) (2) (3) 65 (1) (2) (3) 65 55 55 45 45 0 50 100 150 200 250 0 300 350 fout (MHz) (1) 0 dBFS 50 (2) −7 dBFS (3) −10 dBFS (3) −10 dBFS Third harmonic distortion versus output frequency over input scale at fs = 983.04 MHz Fig 6. 150 200 250 300 350 fout (MHz) Third harmonic distortion versus output frequency over input scale at fs = 1228.8 MHz DAC1627D1G25 Product data sheet 100 (1) 0 dBFS (2) −7 dBFS Fig 5. 300 fout (MHz) © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 15 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 95 95 SFDRrbw (dBc) SFDRrbw (dBc) 85 85 (1) (2) (3) 75 (1) (2) (3) 75 65 65 55 55 45 45 0 50 100 150 200 250 fout (MHz) (1) 0 dBFS 0 50 (2) −7 dBFS (3) −10 dBFS (3) −10 dBFS SFDR restricted bandwidth (200 MHz) versus output frequency over input scale at fs = 983.04 MHz 95 200 250 fout (MHz) Fig 8. SFDR restricted bandwidth (200 MHz) versus output frequency over input scale at fs = 1228.8 MHz 95 IMD3 (dBc) IMD3 (dBc) 85 85 (1) (2) (3) 75 75 65 65 55 55 45 0 50 100 150 200 250 300 350 fNCO (MHz) (1) (2) (3) 45 0 50 (1) -7 dBFS (1) -7 dBFS (2) -10 dBFS (2) -10 dBFS (3) -12 dBFS (3) -12 dBFS Fig 9. 150 (1) 0 dBFS (2) −7 dBFS Fig 7. 100 IMD3 versus output frequency over input scale at fs = 983.04 MHz 150 200 250 300 350 fNCO (MHz) Fig 10. IMD3 versus output frequency over input scale at fs = 1228.8 MHz DAC1627D1G25 Product data sheet 100 © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 16 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 85 85 ACLR (dBc) ACLR (dBc) (1) (2) (3) 75 75 (1) (2) (3) 65 65 55 55 0 100 200 300 0 100 fNCO (MHz) 200 300 fNCO (MHz) (1) fs = 1228.8 Msps (1) fs = 1228.8 Msps (2) fs = 983 Msps (2) fs = 983 Msps (3) fs = 737 Msps (3) fs = 737 Msps Fig 11. One carrier ACLR as a function of output frequency (fout) over sampling frequency (fs) Fig 12. Two carriers ACLR as a function of output frequency (fout) over sampling frequency (fs) 85 ACLR (dBc) 75 (1) (2) (3) 65 55 0 100 200 300 fNCO (MHz) (1) fs = 1228.8 Msps (2) fs = 983 Msps (3) fs = 737 Msps Fig 13. Four carriers ACLR as a function of output frequency (fout) over sampling frequency (fs) DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 17 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 100 highest digital spur (dBc) 90 100 highest digital spur (dBc) 90 (1) (2) (3) 80 (1) (2) (3) 80 70 70 60 60 0 40 80 120 160 200 240 280 fout (MHz) 0 40 (1) 1 dBFS (1) 1 dBFS (2) 7 dBFS (2) 7 dBFS (3) 10 dBFS (3) 10 dBFS Fig 14. Highest digital spur [ n / 8 × fs ± fout (n = 1 to 4)] at 1228.8 MHz as a function of fout over input scale 80 120 160 200 240 280 fout (MHz) Fig 15. Highest digital spur [ n / 8 × fs ± fout (n = 1 to 4)] at 983.04 MHz as a function of fout over input scale 11. Application information 11.1 General description The DAC1627D1G25 is a dual 16-bit DAC operating up to 1250 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer subDAC and a 10-bit binary weighted subDAC. A maximum input LVDS DDR data rate of up to 400 MHz and a maximum output sampling rate of 1250 Msps ensure more flexibility for wide bandwidth and multi-carrier systems. The internal 40-bit NCO of the DAC1627D1G25 simplifies the frequency selection of the system. The DAC1627D1G25 provides ×2, ×4 or ×8 interpolation filters that are useful for removing the undesired images. Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (IO(fs)) of up to 34 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. High resolution internal gain, phase and offset control provide outstanding image and Local Oscillator (LO) signal rejection at the system analog modulator output. Multiple device synchronization enables synchronization of the outputs of multiple DAC devices. MDS guarantees a maximum skew of one output clock period between several devices. All functions can be set using an SPI interface. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 18 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.2 Serial Peripheral Interface (SPI) 11.2.1 Protocol description The DAC1627D1G25 serial interface is a synchronous serial communication port ensures easy interface with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read mode. This interface can be configured as a 3-wire type (pin SDIO as bidirectional pin) or 4-wire type (pins SDIO and SDO as unidirectional pins, input and output port, respectively). In both configurations, SCLK acts as the serial clock and SCS_N as the serial chip select. Figure 16 shows the SPI protocol. An SCS_N signal follows each read/write operation. A LOW assertion to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte (see Table 7) enables the read/write operation. RESET_N (optional) SCS_N SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 SDO (optional) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Fig 16. SPI protocol R/W indicates the mode access (see Table 6) Table 6. Read or Write mode access description R/W Description 0 Write mode operation 1 Read mode operation Table 7 shows the number of bytes to be transferred. N1 and N0 indicate the number of bytes transferred after the instruction byte. Table 7. Number of bytes to be transferred N1 N0 Number of bytes transferred 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes A[4:0] indicates which register is being addressed. If a multiple transfer occurs, this address concerns the first register. Other registers follow directly in a decreasing order (see Table 21, Table 35 and Table 53). DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 19 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating The DAC1627D1G25 incorporates more than the 32 SPI registers allowed by the address value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each containing 32 registers. The 32nd register of each page indicates which page is currently addressed (00h, 01h or 0Ah). 11.2.2 SPI timing description The SPI interface can operate at a frequency up to 25 MHz. The SPI timings are shown in Figure 17. tw(RESET_N) RESET_N 50 % th(SCS_N) tsu(SCS_N) SCS_N 50 % tw(SCLK) SCLK SDIO 50 % 50 % th(SDIO) tsu(SDIO) Fig 17. SPI timing diagram The SPI timing characteristics are given in Table 8. Table 8. SPI timing characteristics Symbol Parameter Min Typ Max Unit fSCLK SCLK frequency - - 25 MHz tw(SCLK) SCLK pulse width 30 - - ns tsu(SCS_N) SCS_N set-up time 20 - - ns th(SCS_N) SCS_N hold time 20 - - ns tsu(SDIO) SDIO set-up time 10 - - ns th(SDIO) SDIO hold time 5 - - ns tw(RESET_N) RESET_N pulse width 30 - - ns 11.3 Power-on sequence There are three steps for the power-on sequence (see Figure 18): 1. The board is power-on. At the turn-on time, all DAC1627D1G25 supplies have reached their specification ranges. 2. At least 1 µs after the turn-on time pin RESET_N must be released. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 20 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 3. When the DAC clock and LVDS clock are stable, the SPI configuration is sent to the DAC1627D1G25. Writing 0 in bits RST_DCLK and RST_LCLK of the register MAIN_CNTRL (see Table 54) starts the automatic calibration. 30 µs after this calibration, the DAC1627D1G25 is operational. WRITE DAC CONFIGURATION START CLOCK CALIBRATION SPI bus RESET_N power supplies trst ton power in specification range time tspi_start Fig 18. Power-on sequence 11.4 LVDS Data Input Format (DIF) block The Data Input Formatting (DIF) block captures and resynchronizes data on the LVDS bus with its own LCLKP/LCLKN clock. Each LVDS input buffer has an internal resistance of 100 Ω, so an external resistor is not required. The DIF block includes two subblocks: • LVDS receiver: Provides high flexibility for the LVDS interface, especially for the Printed-Circuit Board (PCB) layout and the control of the input port polarity and the input port mapping. • Data format block: Enables the adaptation, which ensures the support of several data encoding modes. LD[15]P 16 PA[15..0] 16 I[15..0] to DAC A LD[15]N LD[0]P LD[0]N 16 PB[15..0] LVDS RECEIVER DATA FORMAT 16 Q[15..0] to DAC B LCLKP LCLKN LCLK Fig 19. LVDS Data Input Format (DIF) block diagram 11.4.1 Input port polarity The polarity of each individual LVDS input (LD[15]P to LD[0]P and LD[15]N to LD[0]N) can be changed, ensuring a much easier PCB layout design. The input polarity is controlled with bits LD_POL[15:0] (see Table 59). DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 21 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.4.2 Input port mapping Inverting the order of the LSB and the MSB of the LVDS bus using bit WORD_SWAP in register LD_CNTRL (see Table 60) also simplifies the design of the PCB (see Table 9). Table 9. Input LVDS bus swapping Internal LVDS bus External LVDS bus (WORD_SWAP = 0) External LVDS bus (WORD_SWAP = 1) LDI[15]P,N LD[15]P,N LD[0]P,N LDI[14]P,N LD[14]P,N LD[1]P,N LDI[13]P,N LD[13]P,N LD[2]P,N LDI[12]P,N LD[12]P,N LD[3]P,N LDI[11]P,N LD[11]P,N LD[4]P,N LDI[10]P,N LD[10]P,N LD[5]P,N LDI[9]P,N LD[9]P,N LD[6]P,N LDI[8]P,N LD[8]P,N LD[7]P,N LDI[7]P,N LD[7]P,N LD[8]P,N LDI[6]P,N LD[6]P,N LD[9]P,N LDI[5]P,N LD[5]P,N LD[10]P,N LDI[4]P,N LD[4]P,N LD[11]P,N LDI[3]P,N LD[3]P,N LD[12]P,N LDI[2]P,N LD[2]P,N LD[13]P,N LDI[1]P,N LD[1]P,N LD[14]P,N LDI[0]P,N LD[0]P,N LD[15]P,N 11.4.3 Input port swapping The LVDS DDR receiver block internally maps the incoming LVDS data bus into two buses with a single data rate (Figure 20). A0 B0 A1 B1 A2 B2 A3 B3 A2 A3 B2 B3 to DAC A PA[15..0] A0 A1 LD[15..0]P/N LVDS RECEIVER PB[15..0] LCLKP/N B0 B1 to DAC B LCLK Fig 20. LVDS DDR receiver mapping LDAB SWAP = 0 These two buses can be swapped internally using bit LDAB_SWAP of register LD_CNTRL (see Table 60 and Figure 21). DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 22 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating B0 B1 PA[15..0] A0 B0 A1 B1 A2 B2 A3 B3 B2 B3 A2 A3 to DAC A LD[15..0]P/N LVDS RECEIVER A0 A1 PB[15..0] LCLKP/N to DAC B LCLK Fig 21. LVDS DDR receiver mapping LDAB SWAP = 1 11.4.4 Input port formatting The LVDS DDR input bus multiplexes two 16-bit streams. The LVDS receiver block demultiplexes these two streams. The two streams can carry two data formats: • Folded • Interleaved The data format block is in charge of the data format adaptation (see Figure 22). A0 A1 A2 A3 I0 PA[15..0] A0 B0 A1 B1 A2 B2 A3 B3 I1 I2 I3 Q2 Q3 to DAC A LD[15..0]P/N LVDS RECEIVER B0 B1 B2 B3 DATA FORMAT Q0 PB[15..0] LCLKP/N Q1 to DAC B LCLK Fig 22. LVDS DDR data formats The DAC1627D1G25 can correctly decode the input stream using bit IQ_FORMAT of register LD_CNTRL (see Table 60), because it can determine which format is used on the LVDS DDR bus. Table 10 shows the format mapping between the LVDS input data and the data sent to the two DAC channels depending on the data format selected. Table 10. Folded and interleaved format mapping Data format Data bit mapping interleaved format (IQ_FORMAT = 1) In[15..0] = An[15..0]; Qn[15..0] = Bn[15..0] folded format (IQ_FORMAT = 0) In[15..8] = An[15..8]; In[7..0] = Bn[15..8] Qn[15..8] = An[7..0]; Qn[7..0] = Bn[7..0] DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 23 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.4.5 Data parity/data enable The ALIGN pins can be used in several ways: • As datastream start flag for Multiple Devices Synchronization (see Section 11.13). • As LVDS data enable which can be used to insert a DC level into the datastream. The SEL_EN bits in register LD_CNTRL (see Table 60) enable the programming of this mode. The DC level for both channels is selected using registers I_DC_LVL and Q_DC_LVL (see Table 62) • As parity bit for the LD[15:0] to detect disruptions at the LVDS-input port bit PARITYC in register LD_CNTRL (see Table 60) enabling the control of this mode. A Parity error can generate an interrupt (INTR) reported on either IO0 or IO1 pin 11.5 Interrupt controller The DAC1627D1G25 incorporates an interrupt controller that makes notifying a host-controller in case of an internal event. The INTR-signal can be made available on one of the IO pins. The polarity on the IO pins is programmable. The internal event that must be tracked and generates an interrupt can be selected using the INTR_EN register (see Table 45). Two types of interrupt sources are considered: • The ready-indicators (MAQ_RDY_B, MAQ_RDY_A, AUTO_CAL_RDY, and AUTO_DL_RDY; register INTR_FLAGS; see Table Table 47) notify the host-interface that the corresponding process (invoked by the host interface) has been finalized • The error flags indicate that a failure has been detected. For example, on the LVDS-interface it is possible to check for parity errors and/or to monitor if the internal timing of the LVDS clock delay has changed since the calibration. Errors like these can result in critical timings within the Clock Domain Interface (CDI) which transfers the data from the LCLK to the DCLK domain The selected event that has invoked the interrupt can be determined using the INTR_FLAGS register (see Table 47). The flags and the INTR signal are reinitialized by setting the INTR_CLEAR control bit in register INTR_CTRL (see Table 45). 11.6 General-purpose IO pins The DAC1627D1G25 provides two general-purpose pins, IO0 and IO1. These pins can be used to observe the interrupt signal (INTR) or other internal signals (internal clocks, LVDS data, etc.). These pins can also be used as generic outputs to control external devices. The internal signals that must be observed on these pins are selected using registers IO_MUX0, IO_MUX1, and IO_MUX2 (see Table 63 and Table 64). 11.7 Input clock The DAC1627D1G25 operates with two clocks, one for the LVDS DDR interface and one for the DAC core. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 24 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.7.1 LVDS DDR clock The LVDS DDR clock can be interfaced as shown in Figure 23 because the clock buffer contains a 100 Ω internal resistor. DAC LCLKP Z = 100 Ω LVDS 100 Ω LVDS LCLKN Fig 23. LVDS DDR clock configuration 11.7.2 DAC core clock The DAC core clock can achieve a frequency of up to 1.25 Gsps. It includes internal biasing to support both AC-coupling and DC-coupling. The clock can be easily connected to any LVDS, CML or PECL clock sources. Depending on the interface selected, the hardware configuration varies (see Figure 24 to Figure 26). CLKP Z = 100 Ω 100 Ω LVDS DAC CLKN a. DC-coupling 100 nF CLKP Z = 100 Ω LVDS 100 Ω 100 nF DAC CLKN b. AC-coupling Fig 24. DAC core clock: LVDS configuration DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 25 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 50 Ω 3.3 V 100 nF CLKP Z = 50 Ω DAC CML 100 nF CLKN Z = 50 Ω 50 Ω 3.3 V Fig 25. DAC core clock: CML configuration with AC-coupling 200 Ω 100 nF CLKP Z = 50 Ω PECL DAC 100 Ω 100 nF CLKN Z = 50 Ω 200 Ω Fig 26. DAC core clock: PECL configuration with AC-coupling 11.8 Timing The DAC1627D1G25 can operate at an update rate (fs) of up to 1.25 Gsps and with an input data rate (fdata) of up to 400 MHz. The sampling position of the LVDS data can be tuned using a 16-step compensation delay clock. An internal clock is generated to define the exact sampling position of the LVDS data (see Figure 27, signals LDCLKPcp and LDCLKNcp) which depends on the compensation delay. Figure 27 shows how the compensation delay helps to recover the LVDS DDR data on both the A and B paths. LDCLKN LDCLKP LD[i]N Dn[i] LD[i]P Dn + 1[i] Dn + 2[i] tcmp LDCLKNcp LDCLKPcp LDA[i] Dn − 1[i] Dn[i] Dn + 2[i] LDB[i] Dn − 1[i] Dn + 1[i] Dn + 3[i] Fig 27. LVDS DDR demux timing (LVDS A and B paths not swapped; LDAB_SWAP = 0) DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 26 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating The compensation delay time (tcmp in Figure 27) can be tuned automatically or manually. Bit CAL_CNTRL of the MAIN_CNTRL register (see Table 54) enables the switching between automatic tuning and manual tuning. In automatic tuning mode, the external LVDS data and clock signals are generated using the same reference clock (inside the Field Programmable Gate Array (FPGA)). The LDCLK clock is similar to a data bit that toggles each time (the rising edge and falling edge of the LDCLK and LVDS data occur at the same time). In automatic tuning, the internal compensation delay time (tcmp) is defined automatically to compensate the internal DAC1627D1G25 delay time optimally. The timing requirement in automatic tuning mode is defined in Figure 28 and in Table 5. VIH VIH VIL VIL LVDS data tsk(min) tsk(max) LVDS clock tsk(min) = minimum skew time tsk(max) = maximum skew time Fig 28. Timing requirement automatic tuning Use manual tuning mode if the LVDS data and the LDCLK clock signals provided to the DAC1627D1G25 device have a systematic delay. Adjust the compensation delay time to compensate for the systematic delay. The compensation delay time (tcmp in Figure 27), can be defined using bits LDCLK_DEL[3:0] of register MAN_LDCLKDEL (see Table 55). The timing requirement in manual tuning mode is defined in Figure 29 and in Table 5. sampling window LVDS data sampling window tsu (negative) LDCLK thold Fig 29. Timing requirement in manual tuning mode DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 27 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.9 Operating modes The DAC1627D1G25 requires two differential clocks: • The LVDS clock (LDCLKP, LDCLKN) for the LVDS DDR interface • The data clock (CLKP, CLKN) for the internal PLL and the dual DAC core In Normal mode, provide both the DAC clock and the LVDS clock to the DAC1627. Align the ratio frequency between these two clocks needs with selected ×2, ×4 or ×8 interpolation filters. The clocks provided to the DAC1627 must respect the LVDS input timing and the DAC output timing specifications as defined in Table 5. In PLL mode, provide the LVDS clock to pins LDCLKP/LDCLKN and pins CLKP/CLKN. Depending on selected interpolation filter, the internal PLL can be set to generate the right DAC core clock frequency internally. The clocks provided to the DAC1627 pins must respect the LVDS input timing and the DAC output timing specifications as defined in Table 5. The PLL settings must also respect the maximum sampling rate of the PLL (see the sampling rate (fs) in subsection Internal PLL timing of Table 5). The main function of the Clock Domain Interface (CDI) is to resynchronize the input data streams to the internal clock the digital processing uses. The CDI also performs the required reformatting of the input data streams. Set PLL, CDI, and the interpolation filters, which depend on the targeted application, accordingly. Section 11.9.1 (×2), Section 11.9.2 (×4), and Section 11.9.3 (×8) explain how to set the DAC1627D1G25 to support the different upsampling modes. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 28 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.9.1 CDI mode 0 (x2 interpolation) CDI mode 0 (×2 interpolation) is required when the value of the LVDS DDR clock is twice the internal maximum CDI frequency. Table 11 shows examples of applications using an internal PLL or an external clock for the DAC core. Table 11. CDI mode 0: operating modes examples LVDS DDR rate (MHz) I rate; Q rate (Msps) CDI mode[1] FIR mode[2] 320 320 0 320 320 0 SSBM rate[3] (Msps) DAC rate (Msps) ×2 640 ×2 640 PLL configuration DAC input clock[4] (MHz) PLL status[5] PLL divider[6] 640 320 enabled 2 640 640 disabled n.a. [1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61). [2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 23). [3] If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23). [4] Pins CLKP and CLKN (see Figure 2). [5] Bit PLL_PD of register PLLCFG (see Table 24). [6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 24). 11.9.2 CDI mode 1 (x4 interpolation) CDI mode 1 (×4 interpolation) is required when the values of the LVDS DDR clock and the internal CDI frequency are equal. Table 12 shows examples of applications using an internal PLL or an external clock for the DAC core. Table 12. CDI mode 1: operating modes examples LVDS DDR rate (MHz) I rate; Q rate (Msps) CDI mode[1] FIR mode[2] 250 250 1 250 250 1 [1] SSBM rate[3] (Msps) DAC rate (Msps) ×4 1000 ×4 1000 PLL configuration DAC input clock[4] (MHz) PLL status[5] PLL divider[6] 1000 250 enabled 4 1000 1000 disabled n.a. Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61). [2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 23). [3] If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23). [4] Pins CLKP and CLKN (see Figure 2). [5] Bit PLL_PD of register PLLCFG (see Table 24). [6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 24). DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 29 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.9.3 CDI mode 2 (x8 interpolation) CDI mode 2 (×8 interpolation) is required when the LVDS DDR clock is half the maximum CDI frequency or less. Table 13 shows examples of applications using an internal PLL or an external clock for the DAC core. Table 13. CDI mode 2: operating modes examples LVDS DDR rate (MHz) I rate; Q rate (Msps) CDI mode[1] FIR mode[2] 125 125 2 125 125 2 SSBM rate[3] (Msps) DAC rate (Msps) ×8 1000 ×8 1000 [1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 61). [2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 23). PLL configuration DAC input clock[4] (MHz) PLL status[5] PLL divider[6] 1000 125 enabled 4 1000 1000 disabled n.a. [3] If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 23). [4] Pins CLKP and CLKN (see Figure 2). [5] Bit PLL_PD of register PLLCFG (see Table 24). [6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 24). 11.10 FIR filters The DAC1627D1G25 integrates three selectable Finite Impulse Response (FIR) filters. These FIRs enable the use of the device with ×2, ×4 or ×8 interpolation rates. All three interpolation FIR filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. Table 14 shows the coefficients of the interpolation filters. 0 magnitude (dB) -20 -40 -60 -80 -100 0 0.1 0.2 0.3 0.4 0.5 NF (fs) Fig 30. First stage half-band filter response DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 30 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 0 magnitude (dB) -20 -40 -60 -80 -100 0 0.1 0.2 0.3 0.4 0.5 NF (fs) Fig 31. Second stage half-band filter response 0 magnitude (dB) -20 -40 -60 -80 -100 0 0.1 0.2 0.3 0.4 0.5 NF (fs) Fig 32. Third stage half-band filter response Table 14: Interpolation filter coefficients First interpolation filter Second interpolation filter Third interpolation filter Lower Upper Value Lower Upper Value Lower Upper Value - H(27) +65536 H(11) - +32768 H(7) - +1024 H(26) H(28) +41501 H(10) H(12) +20272 H(6) H(8) +615 H(25) H(29) 0 H(9) H(13) 0 H(5) H(9) 0 H(24) H(30) −13258 H(8) H(14) −5358 H(4) H(10) −127 H(23) H(31) 0 H(7) H(15) 0 H(3) H(11) 0 H(22) H(32) +7302 H(6) H(16) +1986 H(2) H(12) +27 H(21) H(33) 0 H(5) H(17) 0 H(1) H(13) 0 H(20) H(34) −4580 H(4) H(18) −654 H(0) H(14) −3 DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 31 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 14: Interpolation filter coefficients …continued First interpolation filter Second interpolation filter Third interpolation filter Lower Upper Value Lower Upper Value Lower Upper Value H(19) H(35) 0 H(3) H(19) 0 - - - H(18) H(36) +2987 H(2) H(20) +159 - - - H(17) H(37) 0 H(1) H(21) 0 - - - H(16) H(38) −1951 H(0) H(22) −21 - - - H(15) H(39) 0 - - - - - - H(14) H(40) +1250 - - - - - - H(13) H(41) 0 - - - - - - H(12) H(42) -773 - - - - - - H(11) H(43) 0 - - - - - - H(10) H(44) +456 - - - - - - H(9) H(45) 0 - - - - - - H(8) H(46) −252 - - - - - - H(7) H(47) 0 - - - - - - H(6) H(48) +128 - - - - - - H(5) H(49) 0 - - - - - - H(4) H(50) −58 - - - - - - H(3) H(51) 0 - - - - - - H(2) H(52) +22 - - - - - - H(1) H(53) 0 - - - - - - H(0) H(54) −6 - - - - - - Equation 1 defines the dependency of the FIR1 output Y(m) on its inputs X(m): n = 54 1 Y ( m ) = --------------- × H ( 27 ) ∑ (1) [ H ( n ):X ( m – n ) ] n=0 Equation 2 defines the dependency of the FIR2 output Y(m) on its inputs X(m): n = 22 1 Y ( m ) = --------------- × H ( 11 ) ∑ (2) [ H ( n ):X ( m – n ) ] n=0 Equation 3 defines the dependency of the FIR3 output Y(m) on its inputs X(m): n = 14 1 Y ( m ) = ------------ × H(7) ∑ [ H ( n ):X ( m – n ) ] (3) n=0 DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 32 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.11 Single SideBand Modulator (SSBM) The SSBM is a quadrature modulator that enables mixing the I data and Q data with the sine and cosine signals generated by the NCO to generate path A and path B (see Figure 33). cos A I sin +/− sin +/− B Q cos +/− Fig 33. SSBM principle The frequency of the NCO is programmed over 40 bits. NCO enables inverting the sine component to operate a positive or negative, lower or upper SSB conversion (see register TXCFG in Table 23). 11.11.1 NCO in 40 bits When using NCO, the frequency can be set over 40 bits by five registers, FREQNCO_B0 to FREQNCO_B4 (see Table 25). The frequency is calculated with Equation 4. M × fs f NCO = -------------40 2 (4) Where: • M is the two’s complement coding representation of FREQ_NCO[39:0] • fs is the DAC clock sampling frequency The default settings are: • fNCO = 96 MHz • fs = 640 Msps Registers PHINCO_LSB and PHINCO_MSB (over 16 bits from 0° to 360°; see Table 26) can set the phase of the NCO. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 33 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.11.2 NCO low power The five MSB-bits of register FREQNCO_B4 (bits FREQ_NCO[39:35]; see Table 25) can set the frequency when using NCO low power (bit NCO_LP_SEL; see Table 23). The frequency is calculated with Equation 5. M × fs f NCO = -------------5 2 (5) Where: • M is the two’s complement coding representation of FREQ_NCO[39:35] • fs is the DAC clock sampling frequency Five MSB-bits of register PHINCO_MSB (see Table 31) can set the phase of the NCO low power. 11.11.3 Complex modulator The complex modulator upconverts the single side band by mixing NCO signals and I and Q input signals. Table 15 shows the various possibilities set by bits MODULATION[2:0] of register TXCFG (see Table 23). The effect of the MODULATION parameter is better viewed after mixing the A and B signal with a LO frequency through an IQ modulator: negative upper 0 positive lower LO-NCO lower LO upper LO+NCO frequency Fig 34. Complex modulation after LO mixing Table 15. Complex modulator operation mode MODULATION[2:0] Mode 000 bypass 001 Path A Path B I(t) Q( t) positive upper sob I ( t ) × cos ( ω NCO × t ) – Q ( t ) × sin ( ω NCO × t ) I ( t ) × sin ( ω NCO × t ) + Q ( t ) × cos ( ω NCO × t ) 010 positive lower ssb I ( t ) × cos ( ω NCO × t ) + Q ( t ) × sin ( ωNCO × t ) I ( t ) × sin ( ω NCO × t ) – Q ( t ) × cos ( ω NCO × t ) 011 negative upper ssb I ( t ) × cos ( ω NCO × t ) – Q ( t ) × sin ( ω NCO × t ) 100 negative lower ssb I ( t ) × cos ( ω NCO × t ) + Q ( t ) × sin ( ωNCO × t ) – I ( t ) × sin ( ω NCO × t ) + Q ( t ) × cos ( ω NCO × t ) others not defined - - DAC1627D1G25 Product data sheet – I ( t ) × sin ( ω NCO × t ) – Q ( t ) × cos ( ω NCO × t ) © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 34 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.11.4 Minus 3dB In normal use, a full-scale pattern is also full-scale at the DAC output. Nevertheless, when the I data and Q data come close to full-scale simultaneously, some clipping can occur. The Minus 3dB function (bit MINUS_3DB of register DAC_OUT_CTRL; see Table 28) can be used to reduce the 3 dB gain in the modulator. It retains a full-scale range at the DAC output without added interferers. 11.12 Inverse sin x / x A selectable FIR filter is incorporated to compensate the sin x / x effect caused by the roll-off effect of the DAC. This filter has no effect at DC. It introduces a gain for high frequency. The coefficients are represented in Table 16. The filter response is presented in Figure 35. Table 16. Inversion filter coefficients First interpolation filter Lower Upper Value H(1) H(9) +1 H(2) H(8) −4 H(3) H(7) +13 H(4) H(6) −51 H(5) - +610 6 Magnitude (dB) 2 -2 -6 0 0.2 0.4 0.6 0.8 1.0 Normalized Frequency = 2 x fout / fs Fig 35. Inverse sin(x)/x response 11.13 Multiple Devices Synchronization (MDS) Several DAC channels can be sampled synchronously and phase coherently using the MDS feature. When all DAC slave devices of one system receive the same MDS signal (or at least a synchronous version of this reference), all the devices are time-aligned at ±1 DAC clock accuracy at the end of the synchronization process. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 35 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.13.1 MDS concept The FPGA(s) has(have) to activate the ALIGN pins to identify the LVDS data flow start (see Figure 36). align LVDS data ln-2 Qn-2 ln-1 Qn-1 ln Qn ln+1 Qm lm+1 Qm+1 lm+2 Qm+2 lm+3 Qm+3 lm+4 Qm+4 lm+5 Fig 36. ALIGN LVDS data The ALIGN signal is used to generate a local reference inside the DAC1627D1G25 which is 'aligned' with the IQ-data. The DAC1627D1G25 devices use the MDS signals to do the output synchronization (see Figure 37). DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 36 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating MDS internal ref early MDS DAC CLK EARLY/LATE DETECTOR late window DAC MASTER MDS CONTROL AND GENERATION align MDS adj delay LVDS align DAC A DATA FLOW DELAY LVDS data DAC A MDS internal ref early MDS DAC CLK EARLY/LATE DETECTOR late window DAC SLAVE MDS CONTROL AND GENERATION align MDS adj delay LVDS align DAC A DATA FLOW DELAY LVDS data DAC A Fig 37. MDS synchronization The signal detector of the DAC1627D1G25 detects the presence of the MDS signals. Once detected, an internal copy process of this reference starts. The MDS early/late detector block then compares the phase difference of these two signals to align the copy to its reference accurately. The alignment is done inside an "enabling window" that avoids the misinterpretation of the signal edges. This alignment process is done by moving the internal pointer of register MDS_ADJDELAY (see Table 39) (so inserting/removing a delay in data flow). This pointer can have a preset offset, which register MDS_OFFSET_DLY (see Table 42) specifies. Using the MDS_MAN and MDS_MAN_ADJDELAY bits in register MDS_MAN_ADJUSTLY register (see Table 39), the alignment can also be set manually. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 37 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating During the whole alignment process, the MDS controller tries to adjust the delay to get the internal copy signal aligned to the external MDS signal. Once aligned, the MDS signal is not required anymore. It can be switched off at system level. The alignment is done just in front of the analog DACs cores ensuring the ±1 DAC clock sample accuracy. At the end of the MDS process, the MDS circuitry is disabled to avoid any analog disturbances. The MDS feature can be used in two modes: • All slaves mode • Master/slaves mode The mode can be set using the MD_MASTER bit of register MDS_MAIN (see Table 36). 11.13.1.1 MDS in All slaves mode In this mode, each device uses its ALIGN pins signal to identify the LVDS data flow start (see Figure 36). The FPGA(s) has(have) to generate these ALIGN signals The FPGA is also used to generate the different MDS reference signals to enable the DAC1627D1G25 devices to do the synchronization of the output. Use this mode when two or more DAC1627D1G25 devices must be synchronized. Figure 38 shows the MDS all slave mode schematic. system start reference all output are aligned align DAC A LD[15:0] FPGA2 DAC DEVICE 2 LCLK DAC B MDS to DEVn MDS REFERENCE GENERATOR MDS DAC A align FPGA1 DAC DEVICE 1 LD[15:0] DAC B LCLK DAC CLK1 CLOCK DAC CLK2 DISTRIBUTION to FPGAn ref to device n Fig 38. MDS in All slaves mode DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 38 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.13.1.2 MDS in Master/slaves mode In this mode, one DAC1627D1G25 device is used as master, the other one is used as slave. The FPGA(s) still has(have) to provide the ALIGN signal to the DAC devices to identify the LVDS data flow start (see Figure 36). However, the master generates the reference MDS signal. The slave uses this signal to do the synchronization of the output. This mode is recommended when only two DAC1627D1G25 devices must be synchronized. Figure 38 shows the MDS Master/slaves mode schematic. system start reference all output are aligned align DAC A LD[15:0] FPGA2 DAC SLAVE DEVICE LCLK DAC B MDS (input) MDS (output) FPGA1 DAC A align LD[15:0] DAC MASTER DEVICE DAC B LCLK ref DAC CLK1 CLOCK DISTRIBUTION DAC CLK2 Fig 39. MDS Master/slaves mode 11.13.2 MDS flexibility and constraints Getting a ±1 clock period alignment can become very difficult without the MDS feature. There are many sources of misalignment: • At 1.25 GHz, two signals with only 12 cm PCB length difference have a 1 clock period skew. So the PCB traces off the FPGA reference clock, the LVDS data/clock, or the DAC clock introduce delay. • The clock generation circuit can cause delay between the different clocks. • The most important delay comes from the internal FPGA design that can cause 1 or 2 LVDS clock delays between the different LVDS data patterns. The DAC1627D1G25 MDS feature compensates these delays when: • The overall delay compensated by the DAC1627D1G25 remains below ±64 DAC clock. • Each FPGA has to activate its ALIGN signal with the beginning of the LVDS data flow start (even if the different ALIGN signals are mis-aligned) DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 39 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating • All slave devices use the MDS signals for the fine alignment. Any misalignment between these signals causes misalignment on the output. Minimize the delay between the different MDS signals to avoid misalignment: – In All slave mode: Use a low skew buffer on the FPGA to generate this signal. Use the same PCB length for all MDS signal trace distributions. – In Master/slave mode: Minimize the MDS PCB length between the master and the slave (or compensate the introduced MDS PCB delay manually). 11.14 DAC transfer function The full-scale output current for each DAC is the sum of the two complementary current outputs: • I OA ( fs ) = I IOUTAP + IIOUTAN • I OB ( fs ) ) = I IOUTBP + I IOUTBN The output current of DAC A depends on the digital input data. Bits DAC_A_DGAIN[11:0] of register DAC_A_DGAIN_LSB (see Table 27) define the gain factor. ( DAC_A_DGAIN ) DATA I IOUTAP = I OA ( fs ) × ------------------------------------------------ ×  ----------------  4096 65535  (6) ( DAC_A_DGAIN ) DATA I IOUTAN = I OA ( fs ) ×  1 – ------------------------------------------------ ×  ----------------    65535   4096 (7) The output current of DAC B depends on the digital input data. bits DAC_B_DGAIN[11:0] of register DAC_B_DGAIN_LSB (see Table 27) define the gain factor. ( DAC_B_DGAIN ) DATA I IOUTBP = I OB ( fs ) × ------------------------------------------------ ×  ----------------  65535  4096 (8) ( DAC_B_DGAIN ) DATA I IOUTBN = I OB ( fs ) ×  1 – ------------------------------------------------ ×  ----------------    65535   4096 (9) It is possible to define if the DAC1627D1G25 operates with a binary input or a two's complement input (bit CODING; see Table 22). Table 17 shows the output current as a function of the input data, when IOA(fs) = IOB(fs) = 20 mA. Table 17. DAC transfer function Data I15 to I0/Q15 to Q0 (binary coding) I15 to I0/Q15 to Q0 (two’s complement coding IOUTAP/IOUTBP IOUTAN/IOUTBN 0 0000 0000 0000 0000 1000 0000 0000 0000 0 mA 20 mA ... ... ... ... .... 32768 1000 0000 0000 0000 0000 0000 0000 0000 10 mA 10 mA ... ... ... ... ... 65535 1111 1111 1111 1111 0111 1111 1111 1111 20 mA 0 mA DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 40 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.15 Full-scale current 11.15.1 Regulation The DAC1627D1G25 reference circuitry integrates an internal band gap reference voltage which delivers a 1.25 V reference on the GAPOUT pin. Decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 910 Ω (1 %) connected to VIRES. A control amplifier sets the appropriate full-scale current (IOA(fs) and IOB(fs)) for both DACs (see Figure 40)). DAC BAND GAP REFERENCE 100 nF AGND 910 Ω (1 %) AGND GAPOUT VIRES DAC CURRENT SOURCES ARRAY Fig 40. Internal reference configuration Figure 40 shows the optimal configuration for temperature drift compensation because the band gap reference voltage can be matched to the voltage across the feedback resistor. Applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal band gap reference voltage (bit GAP_PON of the COMMON register; see Table 22) can also adjust the DAC current. 11.15.2 Full-scale current adjustment The default full-scale current (IO(fs)) is 20 mA. However, further adjustments, ranging from 8.1 mA to 34 mA, can be made to both DACs independently using the serial interface. The settings applied to DAC_A_GAIN[9:0] (registers 17h and 18h; see Table 32;) define the full-scale current of DAC A: I O ( fs ) ( µA ) = 8100 + DAC_A_GAIN[9:0] × 25.3 (10) The DAC_B_GAIN[9:0] (registers 19h and 1Ah; see Table 32;) define the full-scale current of DAC B: I O ( fs ) ( µA ) = 8100 + DAC_B_GAIN[9:0] × 25.3 (11) 11.16 Limiter/clip control A limiter at the end of the data path saturates the output signal in case the signal does not fit the output range. This feature is activated using the CLIPPING_ENA bit in register DAC_OUT_CTRL (see Table 28). DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 41 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating The clipping level can be programmed using the CLIPPING_LEVEL register (see Table 29.). The output range is limited (or clipped) to between −128x CLIPPING_LEVEL and +128x CLIPPING_LEVEL. At the DAC analog output, the AC current range is limited to: I O ( FS ) I O ( FS ) CLIPPING_LEVEL CLIPPING_LEVEL –  -------------- ×  ---------------------------------------------------- ≤ I IOUT ≤ +  -------------- ×  ----------------------------------------------------  2     2    256 256 (12) 11.17 Digital offset adjustment The DAC1627D1G25 provides digital offset correction (bits DAC_A_OFFSET[15:0] and bits DAC_B_OFFSET[15:0]; see Table 30). This offset correction can be used to adjust the common-mode level at the output of each DAC. It adds an offset at the end of the digital part, just before the DACs. Table 18 shows the range of variation of the digital offset. This offset can be used to remove the LO image at the IQ modulator output. Table 18. Digital offset adjustment DAC_A_OFFSET[15:0] DAC_B_OFFSET[15:0] (two’s complement) Offset applied 1000 0000 0000 0000 −32768 1000 0000 0000 0001 −32767 ... ... 1111 1111 1111 1111 −1 0000 0000 0000 0000 0 0000 0000 0000 0001 +1 ... ... 0111 1111 1111 1110 +32766 0111 1111 1111 1111 +32767 11.18 Analog output The device has two output channels, producing two complementary current outputs, which enable the reduction of even-order harmonics and noise. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN. Connect them using a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). Figure 41 shows the equivalent analog output circuit of one DAC. This circuit includes a parallel combination of NMOS current sources and associated switches for each segment. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 42 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 3.3 V 3.3 V RL IOUTAP/IOUTBP GND RL IOUTAN/IOUTBN GND Fig 41. Equivalent analog output circuit The cascode source configuration increases the output impedance of the source, which improves the dynamic performance of the DAC because there is less distortion. Depending on the application, the various stages and the targeted performances, the device can be used for an output level of up to 2 V (p-p). 11.19 Auxiliary DACs The DAC1627D1G25 integrates two auxiliary DACs, which are used to compensate any offset between the DACs and the next stage in the transmission path. Both auxiliary DACs have a 10-bit resolution and are current sources (referenced to ground). The full-scale output current for each DAC is the sum of the two complementary current outputs: • I OAUXA ( fs ) = I AUXAP + I AUXAN • I OAUXB ( fs ) = I AUXBP + I AUXBN The output current depends on the digital input data set by SPI registers DAC_A_Aux_MSB (bits AUX_A[9:0]) and DAC_B_Aux_MSB (bits AUX_B[9:0]; see Table 33)). DATAA I AUXAP = I OAUXA ( fs ) ×  --------------------  1023  (13) 1023 – DATAA I AUXAN = I OAUXA ( fs ) ×  --------------------------------------   1023 (14) DATAB I AUXBP = I OAUXB ( fs ) ×  --------------------  1023  (15) 1023 – DATAB I AUXBN = I OAUXB ( fs ) ×  --------------------------------------   1023 (16) DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 43 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 19 shows the output current as a function of the auxiliary DACs data DATAA and DATAB. Table 19. Auxiliary DAC transfer function DATAA; DATAB AUX_A[9:2]/AUX_A[1:0]; IAUXAP; IAUXBP (mA) AUX_B[9:0]/AUX_B[1:0] (binary coding) IAUXAN; IAUXBN (mA) 0 00 0000 0000 0 3.1 ... ... ... ... 512 10 0000 0000 1.55 1.55 ... ... ... ... 1023 11 1111 1111 3.1 0 11.20 Output configuration The DAC1627D1G25 supports various output configurations. The system application must check that for IOUTA/IOUTB output, the output compliance range (Vo) and the common-mode output voltage (Vo(cm)) specification points are respected to define other configurations. Similarly, the system application must check that the output compliance range (Vo) specification point is respected for AUXA/AUXB DAC (if used). The common-mode output voltage (Vo(cm)) value for each IOUTA/IOUTB pin depends on the DC resistor(s) connected to these pins and the IOUT DC sink currents on these pins. Equation 17 defines The DC sink output current: I O ( fs ) I O ( sin k ) ( DC ) = I bias ( DC ) + -----------2 (17) Where: • IO(fs) = full-scale output current • Ibias (DC) = DC bias current The common-mode voltage (Vo(cm)) value for each AUXA/AUXB pins depend on the DC resistor(s) connected to these pins and the AUX DC source currents. Equation 18 defines these AUX DC source currents: I O ( fs ) I O ( source ) ( DC ) = -----------2 (18) Where: • IO(fs) = full-scale output current The output compliance range (Vo) of all DAC outputs depends on the AC resistor load connected to the DAC: DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 44 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating I O ( fs ) V O ( max ) = V O ( cm ) + ------------ × R AC 2 (19) I O ( fs ) V O ( min ) = V O ( cm ) – ------------ × R AC 2 (20) Where: • VO(cm) = common-mode output voltage • IO(fs) = full-scale output current • RAC = DAC outputs AC resistor load 11.20.1 Basic output configuration The use of a differentially coupled transformer outputs (see Figure 42) provides optimum distortion performance. In addition, it helps to match the impedance and provides electrical isolation. 3.3 V 3.3 V DAC 50 Ω 22 Ω 0 mA to 20 mA IOUTAP/IOUTBP 2:1 1:1 0 mA to 20 mA 50 Ω IOUTAN/IOUTBN 50 Ω 3.3 V IOUTAP/IOUTAN IOUTBP/IOUTBN VO(cm) = 3 V VO(dif) = 1 V Fig 42. 1 V (p-p) differential output with transformers The DAC1627D1G25 can operate a differential output of up to 2 V (p-p). In this configuration, connect the center tap of the transformer to a 33 Ω resistor, which is connected to the 3.3 V analog power supply. This adjusts the DC common-mode to around 2.8 V (see Figure 43). DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 45 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 3.3 V 3.3 V DAC 33 Ω 100 Ω 0 mA to 20 mA 4:1 50 Ω 1:1 0 mA to 20 mA 100 Ω 3.3 V IOUTAP/IOUTAN IOUTBP/IOUTBN VO(cm) = 2.8 V VO(dif) = 2 V Fig 43. 2 V (p-p) differential output with transformer 11.20.2 Low input impedance IQ-modulator interface The DAC1627D1G25 can be easily connected to the low input impedance IQ-modulators. The image of the local oscillator can be canceled using the digital offset control in the device. Figure 44 shows an example of a connection between the DAC1627D1G25 and the low input impedance IQ modulator. 3.3 V DAC IQ Mod Rint=100/200 ohm 50 50 Low Pass IOUTAP/IOUTBP BBAP/BBBP Filter Rint Rext IOUTAN/IOUTBN BBAN/BBBN 0 to 20 mA AUXAP/AUXBP AUXAN/AUXBN IOUTAP/IOUTAN IOUTBP/IOUTBN VO(cm) = 2.7 V VO(dif) = 1 V If Rint=100 ohm then Rext = not connected. If Rint=200 ohm then Rext = 200 ohm. Fig 44. DAC1627D1G25 with low input impedant IQ-modulator interface DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 46 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.20.3 IQ-modulator - DC interface When the system operation requires to keep the DC component of the spectrum, the DAC1627D1G25 can use a DC interface to connect an IQ-modulator. In this case, the image of the local oscillator can be canceled using the digital offset control in the device. Figure 45 shows an example of a connection to an IQ modulator with a 1.7 V common input level. 5V IQ modulator (VI(cm) = 1.7 V) DAC 68 Ω 68 Ω low pass filter 54.9 Ω IOUTAP/IOUTBP IOUTAN/IOUTBN BBAP/BBBP 100 Ω 0 mA to 20 mA 54.9 Ω BBAN/BBBN 84.5 Ω 84.5 Ω BBAP/BBAN BBBP/BBBN VI(cm) = 1.7 V VI(dif) = 0.92 V IOUTAP/IOUTAN IOUTBP/IOUTBN VO(cm) = 2.78 V VO(dif) = 1.52 V Fig 45. IQ-modulator: DC interface with a 1.7 V common input level Figure 46 shows an example of a connection to an IQ-modulator with a 3.3 V common input level. 5V IQ modulator (VI(cm) = 3.3 V) DAC 64.9 Ω 15 Ω IOUTAP/IOUTBP IOUTAN/IOUTBN 64.9 Ω low pass filter BBAP/BBBP 100 Ω 0 mA to 20 mA 205 Ω 15 Ω BBAN/BBBN 205 Ω AUXAP/AUXBP AUXAN/AUXBN IOUTAP/IOUTAN IOUTBP/IOUTBN VO(cm) = 2.9 V VO(dif) = 1.43 V BBAP/BBAN BBBP/BBBN VI(cm) = 3.3 V VI(dif) = 0.93 V Fig 46. IQ-modulator: DC interface with a 3.3 V common input level DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 47 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating The auxiliary DACs can be used to control the offset within an accurate range or with accurate steps. Figure 47 shows an example of a connection to an IQ-modulator with a 1.7 V common input level and auxiliary DACs. 5V IQ modulator (VI(cm) = 1.7 V) DAC 69.8 Ω 69.8 Ω 57.6 Ω low pass filter BBAP/BBBP 100 Ω 0 mA to 20 mA 57.6 Ω 3.9 Ω BBAN/BBBN 3.9 Ω 1.59 mA (typical) 78.7 Ω IOUTAP/IOUTAN IOUTBP/IOUTBN VO(cm) = 2.8 V VO(dif) = 1.56 V 78.7 Ω BBAP/BBAN BBBP/BBBN VI(cm) = 1.7 V VI(dif) = 0.92 V offset correction = up to 147 mV Fig 47. IQ-modulator: DC interface with a 1.7 V common input level and auxiliary DACs The constraints to adjust the interface are: • • • • The output compliance range of the DAC The output compliance range of the auxiliary DACs The input common-mode level of the IQ-modulator The range of offset correction DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 48 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.20.4 IQ-modulator - AC interface When the IQ-modulator common-mode voltage is close to ground, use the DAC1627D1G25 AC-coupled. The auxiliary DACs are required for local oscillator cancelation. Figure 48 shows an example of a connection to an IQ-modulator with a 0.5 V common input level and auxiliary DACs. 5V 5V IQ modulator (VI(cm) = 0.5 V) DAC 91 Ω 91 Ω 0 mA to 20 mA 2.4 kΩ 2.4 kΩ low pass filter 10 nF IOUTAP/IOUTBP IOUTAN/IOUTBN BBAP/BBBP 105 Ω 10 nF 270 Ω 270 Ω BBAN/BBBN 147 Ω 147 Ω AUXAP/AUXBP AUXAN/AUXBN 68 Ω IOUTAP/IOUTAN IOUTBP/IOUTBN VO(cm) = 2.9 V VO(dif) = 1 V 68 Ω BBAP/BBAN BBBP/BBBN VI(cm) = 0.5 V VI(dif) = 1 V offset correction = up to 190 mV Fig 48. IQ-modulator: AC interface with a 0.5 V common input level and auxiliary DACs 11.21 Design recommendations 11.21.1 Power and grounding Use a separate power supply regulator for the generation of the analog power (pins 65, 62, 55, 58, 69 and 72) and the digital power (pins 12, 19, 26, 36 and 43) to ensure optimal performance. Also, include individual LC decoupling for the following six sets of power pins: • • • • • VDDA(1V8)_P1 (pin 62) VDDA(1V8)_P2 (pin 65) VDDA(1V8) (pins 55, 69, 72 and 58) VDDD (pins 12, 19, 26, 36, and 43) VDDA(3V3) (pins 59 and 68) Use at least two capacitors for each power pin decoupling. place these capacitors as close as possible to the DAC1627D1G25 power pins. The die pad is used for both the power dissipation and electrical grounding. Insert several vias (typically 7 × 7) to connect the internal ground plane to the top layer die area. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 49 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.22 Configuration interface 11.22.1 Register description The DAC1627D1G25 incorporates more than the 32 SPI registers allowed by the address value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each containing 32 registers. The 32nd register of each page indicates which page is currently addressed (00h, 01h or 0Ah). Page 00h (see Table 21) is dedicated to the main control of the DAC1627D1G25: • • • • • Mode selection NCO control Auxiliary DAC control Gain/phase/offset control Power-down control Page 01h (see Table 35) is dedicated to: • Multi-Device Synchronization (MDS) • DAC analog core control (biasing current, Sleep mode) Page 0Ah (see Table 53) is dedicated to the LVDS input interface configuration. 11.22.2 SPI start-up sequence The following SPI sequence shows the list of commands to be used to start the DAC1627D1G25 in interpolation ×4 mode with NCO frequency = 153.6 MHz (fDAC = 983.04 MHz), PLL bypass mode, and without inverse (sin x) / x. Other start-up sequences can be easily derived from this sequence: Table 20. SPI start-up sequence Step SPI (address, data) Comment 1 Write(0x1F, 0x00) select SPI (page 0) 2 Write(0x00, 0x47) reset SPI 3 Write(0x01, 0x86) set NCO on with positive upper sideband conversion, interpolation ×4, No inverse (sin x) / x 4 Write(0x02, 0xA0) PLL in bypass mode 5 Write(0x04, 0xFF) select NCO frequency (FREQ_NCO[7:0]) 6 Write(0x05, 0xFC) select NCO frequency (FREQ_NCO[15:8]) 7 Write(0x06, 0xFF) select NCO frequency (FREQ_NCO[23:16]) 8 Write(0x07, 0xFF) select NCO frequency (FREQ_NCO[31:24]) 9 Write(0x08, 0x27) select NCO frequency (FREQ_NCO[39:32]) 10 Write(0x1F, 0x01) select SPI (page 1) 11 Write(0x15,0x0A) set DAC_current_6 to 0X0A in order to guaranty good performance over process/temperature/voltage 12 Write(0x1F, 0x0A) select SPI (page A) DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 50 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 20. SPI start-up sequence …continued Step SPI (address, data) Comment 13 Write(0x0A, 0x33) specify LVDS interface setting (no DAC A/B swapping, no parity check, no data enable, …) 14 Write(0x0B, 0x01) set CDI block setting (interpolation ×4, CDI mode) 15 Write(0x00, 0x00) release LVDS reset (start of the DAC1627) DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 51 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Integrated Device Technology DAC1627D1G25 Product data sheet 11.22.3 Page 0 register allocation map Table 21 shows an overview of all registers on page 0 (00h in hexadecimal). Table 21. Page_00 register allocation map Address Register name R/W Bit definition Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 - - CODING IC_PON 00h COMMON R/W 3W_SPI SPI_RST - 1 01h TXCFG R/W NCO_ON NCO_LP _SEL INV_SIN _SEL 2 02h PLLCFG R/W PLL_BP PLL_BUF _PD PLL_PLL _PD 4 04h FREQNCO_B0 R/W 5 05h FREQNCO_B1 6 06h 7 MODULATION[2:0] Hex Dec GAP_PON 1000 0111 87h 135 INTERPOLATION[1:0] 0000 0001 01h 1 A1h 161 FREQ_NCO[7:0] 0110 0110 66h 102 R/W FREQ_NCO[15:8] 0110 0110 66h 102 FREQNCO_B2 R/W FREQ_NCO[23:16] 0110 0110 66h 102 07h FREQNCO_B3 R/W FREQ_NCO[31:24] 0010 0110 66h 102 8 08h FREQNCO_B4 R/W FREQ_NCO[39:32] 0010 0110 26h 38 9 09h PH_CORR_CTL0 R/W PHASE_COR[7:0] 0000 0000 00h 0 10 0Ah PH_CORR_CTL1 R/W 0000 0000 00h 0 11 0Bh DAC_A_DGAIN_LSB R/W 1101 0100 50h 80 12 0Ch DAC_A_DGAIN_MSB R/W 0000 1011 0Bh 11 13 0Dh DAC_B_DGAIN_LSB R/W 1101 0100 50h 14 0Eh DAC_B_DGAIN_MSB R/W - - - - 0000 0010 0Bh 11 15 0Fh DAC_OUT_CTRL R/W - - - - - - PLL_PHASE[1:0] PHASE_COR[12:8] DAC_A_DGAIN[7:0] - - - - DAC_A_DGAIN[11:8] DAC_B_DGAIN[7:0] DAC_B_DGAIN[11:8] A_DGAIN_E B_DGAIN_E MINUS _3DB PLL_ OSC_PD CLIPPING 0000 _ENA 0000 00h 80 0 DAC1627D1G25 52 of 81 © IDT 2012. All rights reserved. 1010 0001 PH_COR _ENA PLL_DIV[1:0] Bin Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 0 Bit 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Page_00 register allocation map …continued Address Register name R/W Bit definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Default Bit 2 Bit 1 Bit 0 Bin Hex Dec R/W CLIPPING_LEVEL[7:0] 1111 1111 FFh 255 17 11h DAC_A_OFFSET_LSB R/W DAC_A_OFFSET[7:0] 0000 0000 00h 0 18 12h DAC_A_OFFSET_MSB R/W DAC_A_OFFSET[15:8] 0000 0000 00h 0 19 13h DAC_B_OFFSET_LSB R/W DAC_B_OFFSET[7:0] 0000 0000 00h 0 20 14h DAC_B_OFFSET_MSB R/W DAC_B_OFFSET[15:8] 0000 0000 00h 0 21 15h PHINCO_LSB R/W PH_NCO[7:0] 0000 0000 00h 0 22 16h PHINCO_MSB R/W PH_NCO[15:8] 0000 0000 00h 0 23 17h DAC_A_GAIN1 R/W DAC_A_GAIN[7:0] 1101 1000 D8h 216 24 18h DAC_A_GAIN2 R/W 0100 0000 40h 25 19h DAC_B_GAIN1 R/W 1100 1000 D8h 216 26 1Ah DAC_B_GAIN2 R/W 0100 0000 40h 64 27 1Bh DAC_A_AUX_MSB R/W 1000 0000 80h 128 28 1Ch DAC_A_AUX_LSB R/W 1000 0000 80h 128 29 1Dh DAC_B_AUX_MSB R/W 1000 0000 80h 128 30 1Eh DAC_B_AUX_LSB R/W AUX_B _PON - - - - 1000 0000 80h 128 31 1Fh PAGE_ADDRESS R/W - - - - - 0000 0000 00h 0 - - - - - - DAC_B_GAIN[7:0] DAC_B_GAIN[9:8] - - - - - - AUX_A[9:2] AUX_A _PON - - - - - AUX_A[1:0] AUX_B[9:2] - AUX_B[1:0] PAGE_ADD[2:0] 64 DAC1627D1G25 53 of 81 © IDT 2012. All rights reserved. DAC_CLIPPING Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 16 10h DAC_A_GAIN[9:8] Integrated Device Technology DAC1627D1G25 Product data sheet Table 21. DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.22.4 Page 0 bit definition detailed description The tables in this section contain detailed descriptions of the page 0 registers. Table 22. Register COMMON (address 00h) bit description Default values are shown highlighted. Bit Symbol Access 7 3W_SPI R/W Value serial interface bus type 0 1 6 2 1 0 SPI_RST CODING IC_PON GAP_PON Description R/W 4-wire SPI 3-wire SPI serial interface reset 0 no reset 1 performs a reset on all registers except address 00h R/W coding of input word 0 two’s complement coding 1 unsigned format R/W IC power control 0 all circuits (digital and analog, except SPI) are in power-down 1 all circuits (digital and analog, except SPI) are switched on R/W internal band gap power control 0 band gap is power-down 1 internal band gap references are switched on Table 23. Register TXCFG (address 01h) bit description Default values are shown highlighted. Bit Symbol Access 7 NCO_ON R/W 6 5 4 to 2 NCO_LP_SEL INV_SIN_SEL MODULATION[2:0] Value Description NCO 0 NCO disabled, the NCO phase is reset to 0 1 NCO enabled R/W NCO low-power selection 0 low-power NCO disabled 1 low-power NCO enabled (frequency and phase given by the five MSB of the registers 06h and 08h, respectively) R/W inverse (sin x) / x function selection 0 disable 1 enable R/W modulation 000 dual DAC: no modulation 001 positive upper single sideband conversion 010 positive lower single sideband conversion 011 negative upper single sideband conversion 100 negative lower single sideband conversion others not defined DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 54 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 23. Register TXCFG (address 01h) bit description …continued Default values are shown highlighted. Bit Symbol Access 1 to 0 INTERPOLATION[1:0] R/W Value Description interpolation 00 no interpolation 01 ×2 interpolation 10 ×4 interpolation 11 ×8 interpolation Table 24. Register PLLCFG (address 02h) bit description Default values are shown highlighted. Bit Symbol Access 7 PLL_BP R/W 6 PLL_BUF_PD Value PLL bypass 0 DAC clock generated by PLL 1 DAC clock provided via external pins CLKN and CLKP (PLL bypass mode) R/W PLL test buffer control 0 1 5 PLL_PLL_PD 4 to 3 PLL_DIV[1:0] R/W 0 PLL_OSC_PD Power-down mode enabled PLL and CKGEN control 0 Power-down mode 1 enable R/W PLL divider factor 00 fs = 2 × fdata 01 fs = 4 × fdata 10 fs = 8 × f 11 2 to 1 PLL_PHASE[1:0] Description R/W undefined PLL phase shift 00 0 degrees phase shift of fs 01 120 degrees phase shift of fs 10 240 degrees phase shift of fs 11 240 degrees phase shift of fs R/W PLL oscillator output power-down 0 Power-down mode 1 enabled DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 55 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 25. NCO frequency registers (address 04h to 08h) bit description Default values are shown highlighted. Address Register Bit 04h FREQNCO_B0 7 to 0 Symbol Access FREQ_NCO[7:0] R/W Value Description NCO frequency (two’s complement coding) - least significant 8 bits for the NCO frequency setting 05h FREQNCO_B1 7 to 0 FREQ_NCO[15:8] - intermediate 8 bits for the NCO frequency setting 06h FREQNCO_B2 7 to 0 FREQ_NCO[23:16] - intermediate 8 bits for the NCO frequency setting 07h FREQNCO_B3 7 to 0 FREQ_NCO[31:24] - intermediate 8 bits for the NCO frequency setting 08h FREQNCO_B4 7 to 0 FREQ_NCO[39:32] - most significant 8 bits for the NCO frequency setting Table 26. DAC output phase correction registers (address 09h to 0Ah) bit description Default values are shown highlighted. Address Register 09h Bit Symbol PH_CORR_CTL0 7 to 0 PHASE_COR[7:0] Access Value Description R/W DAC output phase correction factor (LSB) - 0Ah PH_CORR_CTL1 7 PH_COR_ENA least significant 8 bits for the DAC output phase correction factor R/W DAC output phase correction control 0 DAC output phase correction disabled 1 DAC output phase correction enabled 4 to 0 PHASE_COR[12:8] R/W DAC output phase correction factor MSB 00000 most significant 5 bits for the DAC output phase correction factor Table 27. Digital gain control registers (address 0Bh to 0Eh) bit description Default values are shown highlighted. Address Register Bit Symbol Access Value Description 0Bh DAC_A_DGAIN_LSB 7 to 0 DAC_A_DGAIN[7:0] R/W 0Ch DAC_A_DGAIN_MSB 3 to 0 DAC_A_DGAIN[11:8] 0Dh DAC_B_DGAIN_LSB DAC_B_DGAIN[7:0] 0Eh 7 to 0 DAC_B_DGAIN_MSB 3 to 0 - least significant 8 bits for the DAC A digital gain - most significant 4 bits for the DAC A digital gain R/W DAC_B_DGAIN[11:8] DAC1627D1G25 Product data sheet DAC A digital gain control DAC B digital gain control - least significant 8 bits for the DAC B digital gain - most significant 4 bits for the DAC B digital gain © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 56 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 28. Register DAC_OUT_CTRL (address 0Fh) Default values are shown highlighted. Bit Symbol Access 3 A_DGAIN_E R/W 2 1 B_DGAIN_E MINUS_3DB Value Description DAC A digital gain control 0 disable 1 enable R/W DAC B digital gain control 0 disable 1 enable R/W DAC attenuation control 0 unity gain 1 0 CLIPPING_ENA R/W −3 dB gain Digital DAC output clipping control 0 disable 1 enable Table 29. Register DAC_CLIPPING (address 10h) Default values are shown highlighted. Bit Symbol Access Value Description 7 to 0 CLIPPING_LEVEL[7:0] R/W - Digital DAC output clipping level value Table 30. Digital offset value registers (address 11h to 14h) bit description Default values are shown highlighted. Address Register Bit Symbol Access Value Description 11h 7 to 0 DAC_A_OFFSET[7:0] R/W DAC A digital offset value DAC_A_OFFSET_LSB 12h DAC_A_OFFSET_MSB 7 to 0 DAC_A_OFFSET[15:8] 13h DAC_B_OFFSET_LSB DAC_B_OFFSET[7:0] 14h 7 to 0 DAC_B_OFFSET_MSB 7 to 0 - least significant 8 bits for the DAC A digital offset - most significant 8 bits for the DAC A digital offset R/W DAC B digital offset value DAC_B_OFFSET[15:8] - least significant 8 bits for the DAC B digital offset - most significant 8 bits for the DAC B digital offset Table 31. NCO phase offset registers (address 15h to 16h) bit description Default values are shown highlighted. Address Register Bit Symbol Access Value Description 15h 7 to 0 PH_NCO[7:0] R/W NCO phase offset 16h PHINCO_LSB PHINCO_MSB 7 to 0 PH_NCO[15:8] - least significant 8 bits for the NCO phase setting - most significant 8 bits for the NCO phase setting DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 57 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 32. Analog gain control (address 17h to 1Ah) bit description Default values are shown highlighted. Address Register Bit Symbol Access Value Description 17h DAC_A_GAIN1 7 to 0 DAC_A_GAIN[7:0] R/W - DAC A analog gain control (LSB) 18h DAC_A_GAIN2 7 to 6 DAC_A_GAIN[9:8] R/W - DAC A analog gain control (MSB) 19h DAC_B_GAIN1 7 to 0 DAC_B_GAIN[7:0] R/W - DAC B analog gain control (LSB) 1Ah DAC_B_GAIN2 7 to 6 DAC_B_GAIN[9:8] R/W - DAC B analog gain control (MSB) Table 33. Auxiliary DAC registers (address 1Bh to 1Eh) bit description Default values are shown highlighted. Address Register Bit Symbol Access Value Description 1Bh DAC_A_AUX_MSB 7 to 0 AUX_A[9:2] R/W - most significant 8 bits for auxiliary DAC A 1Ch DAC_A_AUX_LSB 7 AUX_A_PON R/W 1 to 0 AUX_A[1:0] 1 on - DAC_B_AUX_MSB 7 to 0 AUX_B[9:2] R/W 1Eh DAC_B_AUX_LSB 7 AUX_B_PON R/W AUX_B[1:0] off R/W 1Dh 1 to 0 auxiliary DAC A power 0 R/W least significant 2 bits for auxiliary DAC A most significant 8 bits for auxiliary DAC B auxiliary DAC B power 0 off 1 on - least significant 2 bits for auxiliary DAC B Table 34. SPI_PAGE register (address 1Fh) bit description Default values are shown highlighted. Bit Symbol Access Value Description 2 to 0 PAGE[2:0] R/W - SPI page address DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 58 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Integrated Device Technology DAC1627D1G25 Product data sheet 11.22.5 Page 1 allocation map Table 35 shows an overview of all registers on page 1 (01h in hexadecimal). Table 35. Page 1 register allocation map Address Register name R/W Default[1] Bit definition Bit 7 Bit 6 MDS_EQCHECK[1:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MDS_ RUN MDS_ NCO MDS_ NCO_ PULSE MDS_ SREF_ DIS MDS_ MASTER MDS_ ENA Bin Hex 0000 0100 04h MDS_MAIN R/W 1 01h MDS_WIN_ PERIOD_A R/W MDS_WIN_PERIOD_A[7:0] 1000 0000 80h 2 02h MDS_WIN_ PERIOD_B R/W MDS_WIN_PERIOD_B[7:0] 0100 0000 40h 3 03h MDS_MISCCNTRL0 R/W 0001 0000 10h 4 04h MDS_MAN_ ADJUSTDLY R/W 0100 0000 40h 5 05h MDS_AUTO_ CYCLES R/W MDS_AUTO_CYCLES[7:0] 1000 0000 80h 6 06h MDS_MISCCNTRL1 R/W MDS_ RELOCK 0000 1111 0Fh 7 07h MDS_OFFSET_DLY RW - 0000 0000 00h 8 08h MDS_ADJDELAY RW - 0000 0000 00h 9 09h MDS_STATUS0 R EARLY LATE EQUAL 10 0Ah MDS_STATUS1 R - - ADD_ERR 11 0Bh INTR_CTRL RW - - - - - INTR_ CLEAR 12 0Ch INTR_EN RW AUTO_ DL_EN AUTO_ CAL_EN FLAG_ DL_EN LCLKSAMP_ EN PARBER_ EN 13 0Dh INTR_FLAGS R FLAG_DL_ ERR LCLKSAMP_ ERR 14 0Eh DAC_CURRENT_ AUX R/W - - - MDS_ EVAL_ ENA MDS_ MAN MDS_ PRERUN_E MDS_PULSEWIDTH[2:0] MDS_MAN_ADJUSTDLY[6:0] MDS_SR_ MDS_SR_ MDS_ CKEN LOCKOUT SR_LOCK - MDS_LOCK_DELAY[3:0] - MDS_OFFSET_DLY[4:0] MDS_ADJDELAY[6:0] MAQB_EN MAQA_EN MDS_EQ EARLY_ ERROR MDS_EN_PHASE[1:0] MAQB_ RDY MAQA_ RDY AUTO_ DL_RDY AUTO_ CAL_RDY - - - - LATE_ ERROR EQUAL_ FOUND MDS_ ACTIVE uuuu uuuu uuh MDS_ PRERUN MDS_ LOCKOUT MDS_ LOCK uuuu uuuu uuh 0000 0100 04h 0000 0000 00h PARBER_ MON_ uuuu ERR DCLK_ERR uuuu uuh INTR_MON_DCLK_ RANGE DAC_AUX_BIAS[3:0] MON_ DCLK_EN 0000 0111 07h DAC1627D1G25 59 of 81 © IDT 2012. All rights reserved. 00h Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Page 1 register allocation map …continued Address Register name R/W Default[1] Bit definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex 0Fh DAC_CURRENT_0 R/W - - - - DAC_DIG_BIAS[3:0] 0000 0111 07h 16 10h DAC_CURRENT_1 R/W - - - - DAC_MST_BIAS[3:0] 0000 0111 07h 17 11h DAC_CURRENT_2 R/W - - - - DAC_DRV_BIAS[3:0] 0000 0111 07h 18 12h DAC_CURRENT_3 R/W - - - - DAC_SLV_BIAS[3:0] 0000 0111 07h 19 13h DAC_CURRENT_4 R/W - - - - DAC_CK_BIAS[3:0] 0000 0111 07h 20 14h DAC_CURRENT_5 R/W - - - - DAC_CAS_BIAS[3:0] 0000 0111 07h 21 15h DAC_CURRENT_6 R/W - - - - DAC_COM_BIAS[3:0] 0000 0111 07h 22 16h DAC_PON_SLEEP R/W DAC_B_ PON DAC_B_ SLEEP DAC_B_ COM_PD DAC_B_ BLEED_ PD DAC_A_ PD 1011 1011 BBh 23 17h DAC_CLKDIG_ DELAY R/W - - - - - PLL_DIG_DELAY[2:0] 0000 0010 02h 31 1Fh PAGE_ADDRESS R/W - - - - - PAGE[2:0] 0000 0000 00h u = undefined at power-up or after reset. DAC_A_ SLEEP DAC_A_ COM_PD DAC_A_ BLEED_ PD DAC1627D1G25 60 of 81 © IDT 2012. All rights reserved. Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 15 [1] Integrated Device Technology DAC1627D1G25 Product data sheet Table 35. DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.22.6 Page 1 bit definition detailed description The tables in this section contain detailed descriptions of the page 1 registers. Table 36. MDS_MAIN register (address 00h) bit description Default values are shown highlighted. Bit Symbol Access 7 to 6 MDS_EQCHECK[1:0] R/W 5 4 MDS_RUN MDS_NCO Value Description lock mode 00 lock when (early = 1 and late = 1) 01 lock when (early = 1, late = 1 and equal = 1) 10 lock when equal = 1 11 force lock (equal-check = 1) R/W evaluation process restart control 0 no action 1 (0 ≥ 1) transition restarts evaluation_counter R/W NCO synchronization 0 no action 1 3 2 1 0 MDS_NCO_PULSE MDS_SREF_DIS MDS_MASTER MDS_ENA enable R/W NCO pulse 0 no action 1 manual control NCO tuning R/W internal pulse generation 0 normal mode 1 disable R/W MDS mode selection 0 slave mode 1 master mode R/W MDS function control 0 disable 1 enable Table 37. MDS window time registers (address 01h to 02h) bit description Default values are shown highlighted. Address Register Bit Symbol 01h MDS_WIN_PERIOD_A 7 to 0 02h MDS_WIN_PERIOD_B 7 to 0 Access Value Description MDS_WIN_ R/W PERIOD_A[7:0] - determines MDS window LOW time MDS_WIN_ R/W PERIOD_B[7:0] - determines MDS window HIGH time Table 38. MDS_MISCCNTRL0 register (address 03h) bit description Default values are shown highlighted. Bit Symbol Access 4 MDS_EVAL_ENA R/W Value Description MDS evaluation 0 disable 1 enable DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 61 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 38. MDS_MISCCNTRL0 register (address 03h) bit description …continued Default values are shown highlighted. Bit Symbol Access 3 MDS_PRERUN_ENA R/W Value Description automatic MDS start-up 0 no mds_win/mds_ref generation in advance 1 2 to 0 mds_win/mds_ref run-in before mds_evaluation MDS_PULSEWIDTH[2:0] R/W width of MDS (in output clock periods) 000 1 DAC clock period 001 2 DAC clock periods 010 to 111 (mds_pulsewidth − 1) × 4 DAC clock periods Table 39. MDS_MAN_ADJUSTDLY register (address 04h) bit description Default values are shown highlighted. Bit Symbol Access 7 MDS_MAN R/W 6 to 0 Value Description adjustment delays mode 0 auto-control adjustment delays 1 manual control adjustment delays MDS_MAN_ADJUSTDLY[6:0] R/W adjustment delay value - if MDS_MAN = 0 then initial value adjustment delay - if MDS_MAN = 1 then controls adjustment delay Table 40. MDS_AUTO_CYCLES register (address 05h) bit description Default values are shown highlighted. Bit Symbol 7 to 0 MDS_AUTO_CYCLES[7:0] Access Value Description R/W - number of evaluation cycles applied for MDS. If set to 255, then IC continuously generates/monitors the MDS pulse Table 41. MDS_MISCCNTRL1 register (address 06h) bit description Default values are shown highlighted. Bit Symbol Access Value Description 7 MDS_SR_CKEN R/W - lock mode 0 1 6 5 4 3 to 0 MDS_SR_LOCKOUT MDS_SR_LOCK MDS_RELOCK MDS_LOCK_DELAY[3:0] R/W MDS_SR_CKEN forced low lockout detector soft reset 0 MDS_SR_LOCKOUT in use 1 MDS_SR_LOCKOUT forced low R/W lock detector soft reset 0 MDS_SR_LOCK in use 1 MDS_SR_LOCK forced low R/W R/W free-running MDS_SR_CKEN relock mode 0 no action 1 relock when lockout occurs - number of succeeding 'equal' detections until lock DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 62 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 42. MDS_OFFSET_DLY register (address 07h) bit description Default values are shown highlighted. Bit Symbol 4 to 0 MDS_OFFSET_DLY[6:0] Access Value Description R/W - delay offset for dataflow (two’s complement [−16 to 15] Table 43. MDS_ADJDELAY register (address 08h) bit description Default values are shown highlighted. Bit Symbol 6 to 0 MDS_ADJDELAY[6:0] Access Value Description R - actual value adjustment delay Table 44. MDS status registers (address 09h to 0Ah) bit description Default values are shown highlighted. Address Register Bit Symbol Access 09h 7 EARLY R MDS_STATUS0 6 5 4 3 2 1 0 LATE Value early signal (sampled) from early-to-late detector 0 false 1 true R EQUAL late signal (sampled) from early-to-late detector 0 false 1 true R MDS_LOCK EARLY_ERROR LATE_ERROR EQUAL_FOUND MDS_ACTIVE equal signal (sampled) from early-to-late detector 0 false 1 true R result equal-check 0 false 1 true R adjustment delay maximum value stops the search 0 false 1 true R adjustment delay minimum value stops the search 0 false 1 true R evaluation logic has detected equal condition 0 false 1 true R evaluation logic active 0 false 1 true DAC1627D1G25 Product data sheet Description © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 63 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 44. MDS status registers (address 09h to 0Ah) bit description …continued Default values are shown highlighted. Address Register Bit Symbol Access 0Ah 5 ADD_ERR R MDS_STATUS1 4 to 3 MDS_EN_PHASE[1:0] Value adjustment delay error detection 0 OK 1 delay offset cannot be applied in available range R MDS enable phase 00 2 1 MDS_PRERUN MDS_LOCKOUT 01 enable phase = 1 (only for ×2) enable phase = 2 (only for ×2 and ×4) 11 enable phase = 3 (only for ×2) R MDS-PRERUN phase active flag 0 false 1 true R MDS_LOCKOUT detected flag 1 MDS_LOCK enable phase = 0 10 0 0 Description R false true MDS_LOCK flag 0 false 1 true Table 45. Interrupt control register (address 0Bh) bit description Default values are shown highlighted. Bit Symbol Access 3 INTR_CTRL R/W 2 to 0 INTR_MON_DCLK_RANGE Value Description internal interrupt and flags clearance 0 disabled 1 enabled R/W Interrupt condition as related to the DCLK monitoring 00 mon_dclk_flag when mon_dclk drifts to (1 or 5) (detect small drift) 01 mon_dclk_flag when mon_dclk drifts to (2 or 4) (detect large drift) 10 mon_dclk_flag when mon_dclk drifts to (3) (detect maximum drift) 11 mon_dclk_flag disabled DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 64 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 46. Interrupt enable register (address 0Ch) bit description Default values are shown highlighted. Bit Symbol Access 7 MAQB_EN R/W 6 5 MAQA_EN AUTO_DL_EN Value acquisition module B interrupt 0 disabled 1 enabled R/W acquisition module A interrupt 0 disabled 1 enabled R/W automatic download MTP interrupt 0 1 4 3 2 1 AUTO_CAL_EN FLAG_DL_EN LCLKSAMP_EN PARBER_EN R/W enabled 0 disabled 1 enabled R/W MTP download error interrupt 0 disabled 1 enabled R/W lclk sampling monitor error interrupt 0 disabled 1 enabled R/W LVDS parity or ber error interrupt 1 MON_DCLK_EN disabled LVDS automatic calibration interrupt 0 0 Description R/W disabled enabled dclk monitor error interrupt 0 disabled 1 enabled Table 47. INTR_FLAGS register (address 0Dh) bit description Default values are shown highlighted. Bit Symbol Access 7 MAQB_RDY R 6 MAQA_RDY Value acquisition module B status 0 not ready 1 ready R acquisition module A status 0 1 5 4 AUTO_DL_RDY AUTO_CAL_RDY Description R not ready ready automatic download MTP status 0 not ready 1 ready R LVDS automatic calibration status 0 not ready 1 ready DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 65 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 47. INTR_FLAGS register (address 0Dh) bit description …continued Default values are shown highlighted. Bit Symbol Access 3 FLAG_DL_ERR R Value error during MTP download 0 1 2 LCLKSAMP_ERR 1 PARBER_ERR 0 R no error error detected error on lclk sampling monitor 0 no error 1 error detected R MON_DCLK_ERR Description error on LVDS parity or ber error 0 no error 1 error detected R error on dclk monitor 0 no error 1 error detected Table 48. Bias current control registers (address 0Eh to 15h) bit description Default values are shown highlighted. Address Register Bit Symbol Access Value Description [1] 0Eh DAC_CURRENT_AUX 3 to 0 DAC_AUX_BIAS[3:0] 0Fh DAC_CURRENT_0 DAC_DIG_BIAS[3:0] 3 to 0 R/W - bias current control (see Table 49) - 10h DAC_CURRENT_1 3 to 0 DAC_MST_BIAS[3:0] - 11h DAC_CURRENT_2 3 to 0 DAC_DRV_BIAS[3:0] - 12h DAC_CURRENT_3 3 to 0 DAC_SLV_BIAS[3:0] - 13h DAC_CURRENT_4 3 to 0 DAC_CK_BIAS[3:0] - 14h DAC_CURRENT_5 3 to 0 DAC_CAS_BIAS[3:0] - 15h DAC_CURRENT_6[2] 3 to 0 DAC_COM_BIAS[3:0] - [1] All default values (except for register DAC_current_6) are OK for good performance over Process Voltage and Temperature. [2] The register DAC_current_6 (address 0X15) must be set to 0X0A. Table 49. BIAS[3:0] Bias current control table Deviation from nominal current 0000 −35 % 0001 −30 % 0010 −25 % 0011 −20 % 0100 −15 % 0101 −10 % 0110 −5 % 0111 +0 % (default) 1000 +5 % 1001 +10 % 1010 +15 % DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 66 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 49. Bias current control table …continued BIAS[3:0] Deviation from nominal current 1011 +20 % 1100 +25 % 1101 +30 % 1110 +35 % 1111 +40 % Table 50. DAC_PON_SLEEP register (address 16h) bit description Default values are shown highlighted. Bit Symbol Access Value Description 7 DAC_B_PON R/W - DAC B power control 6 DAC_B_SLEEP 0 power-down 1 power on R DAC B mode selection 0 normal operation 1 5 4 3 2 DAC_B_COM_PD Sleep mode R commutator B control 0 disable (power-down) 1 enable DAC_B_BLEED_PD R DAC_A_PON DAC_A_SLEEP DAC B bleed current control 0 disable (power-down) 1 enable R DAC A power control 0 power-down 1 power on R DAC B mode selection 0 normal operation 1 1 0 DAC_A_COM_PD Sleep mode R commutator A control 0 disable (power-down) 1 enable DAC_A_BLEED_PD R DAC A bleed current control 0 disable (power-down) 1 enable Table 51. DAC_TEST_8 register (address 17h) bit description Default values are shown highlighted. Bit Symbol Access Value Description 2 to 0 PLL_DIG_DELAY[2:0] R/W - digital clock delay offset of PLL/CKGEN_DIV8 DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 67 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 52. SPI_PAGE register (address 1Fh) bit description Default values are shown highlighted. Bit Symbol Access Value Description 2 to 0 PAGE[2:0] R/W - SPI page address DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 68 of 81 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Integrated Device Technology DAC1627D1G25 Product data sheet 11.22.7 Page A register allocation map Table 53 shows an overview of all registers on page A (0Ah in hexadecimal). Table 53. Page_0A register allocation map Address Register name R/W Bit definition Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Hex Dec PD_CNTRL CAL_ CNTRL RST_ DCKL RST_ LCKL 0000 03h 3 0011 MAIN_CNTRL R/W - - - LD_PD 1 01h MAN_LDCLKDEL R/W - - - - 2 02h DBG_LVDS R/W - - - - 4 04h RST_EXT_LDCLK R/W RST_EXT_LCLK_TIME[7:0] 0011 3Fh 63 1111 5 05h RST_EXT_DCLK R/W RST_EXT_DCLK_TIME[7:0] 0010 20h 32 0000 6 06h DCMSU_PREDIV R/W DCMSU_PREDIVIDER[7:0] 0001 1Dh 29 1101 8 08h LD_POL_LSB R/W LD_POL[7:0] 0000 00h 0 0000 9 09h LD_POL_MSB R/W LD_POL[15:8] 0000 00h 0 0000 10 0Ah LD_CNTRL R/W PARITYC DESCRAMBLE SEL_EN[1:0] 11 MISC_CNTRL R/W SR_CDI I_LEV_ CNTRL[1:0] 12 0Ch I_DC_LVL_LSB R/W I_DC_LEVEL[7:0] 1111 FFh 255 1111 13 0Dh I_DC_LVL_MSB R/W I_DC_LEVEL[15:8] 1000 80h 128 0000 14 0Eh Q_DC_LVL_LSB R/W Q_DC_LEVEL[7:0] 0000 00h 0 0000 15 0Fh Q_DC_LVL_MSB R/W Q_DC_LEVEL[15:8] 1000 80h 128 0000 16 10h IO_MUX0 R/W IO_SELECT0[7:0] 1000 80h 128 0000 0Bh RESERVED LDCLK_DEL[3:0] SBER WORD_SWAP 0000 00h 0 0000 RESERVED LDAB_ SWAP Q_LEV_CNTRL[1:0] IQ_ FORMAT 0000 00h 0 0000 EDGE_ LDCLK CDI_MODE[1:0] 1111 FFh 255 1111 1111 FFh 255 1111 DAC1627D1G25 69 of 81 © IDT 2012. All rights reserved. 00h Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Page_0A register allocation map …continued Address Register name R/W Bit definition Bit 7 Bit 6 Bit 5 Bit 4 Default Bit 3 Bit 2 Bit 1 Bit 0 IO_SELECT1[7:0] Bin Hex Dec IO_MUX1 R/W 18 12h IO_MUX2 R/W 27 1Bh TYPE_ID R 28 1Ch DAC_VERSION R DAC_VERSION_ID[7:0] 0010 29h 41 1001 29 1Dh DIG_VERSION R DIG_VERSION_ID[7:0] 0000 04h 4 0100 30 1Eh LD_VERSION R LVDS_VERSION_ID[7:0] 0000 09h 9 1001 31 1Fh PAGE_ADDRESS R/W DAC - - FRONTEND[1:0] - - - IO_SELECT0[9:8] DUAL DSP[1:0] - - 1000 80h 128 0000 - - BIT_RES[1:0] PAGE_ADD[2:0] 1000 80h 128 0000 0011 3Ch 60 1010 0000 00h 0 0000 DAC1627D1G25 70 of 81 © IDT 2012. All rights reserved. Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Rev. 4 — 12 December 2012 17 11h IO_SELECT1[9:8] Integrated Device Technology DAC1627D1G25 Product data sheet Table 53. DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 11.22.8 Page A bit definition detailed description The tables in this section contain detailed descriptions of the page A registers. Table 54. Register MAIN_CNTRL (address 00h) Default values are shown highlighted. Bit Symbol Access 4 LD_PD R/W Value Description LVDS interface power-down (control possible only when PD_CNTRL = 1) 0 switched on 1 3 2 1 0 PD_CNTRL CAL_CNTRL RST_DCLK RST_LCLK switched off R/W power-down modes controlled by 0 DCMSU block 1 SPI registers R/W compensation delay controlled by 0 DCMSU block (automatic calibration) 1 SPI registers (manual control) R/W reset DCLK 0 disable 1 enable R/W reset LVDS clock 0 disable 1 enable Table 55. Register MAN_LDCLKDEL (address 01h) Default values are shown highlighted. Bit Symbol Access 3 to 0 LDCLK_DEL[3:0] Value Description R/W LVDS clock compensation delay (control only if CAL_CNTRL = 1) - 4-bit compensation delay for LVDS clock Table 56. Register DBG_LVDS (address 02h) Default values are shown highlighted. Bit Symbol Access 3 SBER R/W Value simple BER control 0 1 2 to 0 RESERVED Description R/W 000 no action simple BER active reserved Table 57. Extension time reset registers (address 04h to 05h) bit description Default values are shown highlighted. Address Register 04h Bit RST_EXT_LCLK 7 to 0 Symbol Access Value RST_EXT_LCLK_TIME[7:0] R/W specifies extension time reset, expressed in LVDS clock period - 05h RST_EXT_DCLK 7 to 0 RST_EXT_DCLK_TIME[7:0] R/W Product data sheet 8 bits for the extension time reset specifies extension time reset, expressed in DCLK period DAC1627D1G25 Description 8 bits for the extension time reset © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 71 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 58. Register DCSMU_PREDIV (address 06h) Default values are shown highlighted. Bit Symbol Access Value 7 to 0 DCMSU_PREDIVIDER[7:0] R/W Description predivider value for the DCMSU, expressed in LVDS clock period - 8 bits for the predivider value Table 59. LSB/MSB of polarity registers (address 08h to 09h) bit description Default values are shown highlighted. Address Register Bit 08h 7 to 0 LD_POL[7:0] LD_POL_LSB 09h Symbol Access Value Description R/W toggles polarity of corresponding bit pair within LD[7:0] LD_POL_MSB 7 to 0 LD_POL[15:8] - least significant 6 bits for the polarity toggle - most significant 6 bits for the polarity toggle Table 60. Register LD_CNTRL (address 0Ah) Default values are shown highlighted. Bit Symbol Access Value Description 7 PARITYC R/W parity check 6 DESCRAMBLE 5 to 4 SEL_EN[1:0] 3 2 WORD_SWAP LDAB_SWAP 0 disable 1 enable R/W Descramble control 0 disable descrambling 1 enable descrambling R/W LVDS data enable 00 LVDS data enable = align signal from channel A 01 LVDS data enable = align signal from channel B 10 LVDS data enable = 0 11 LVDS data enable = 1 R/W reverse order for LVDS path 0 normal operation 1 MSB to LSB order reversed R/W swaps LVDS A and LVDS B paths 0 1 1 0 IQ_FORMAT EDGE_LDCLK R/W normal operation LVDS A and LVDS B paths are swapped specify IQ supplied format 0 folded 1 interleaved R/W specify sampling edge for LVDS data path 0 falling edge of LDCLK 1 rising edge of LDCLK DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 72 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 61. Register MISC_CNTRL (address 0Bh) Default values are shown highlighted. Bit Symbol Access 7 SR_CDI R/W 6 RESERVED R/W 5 to 4 I_LEV_CNTRL[1:0] R/W Value CDI block software reset control 0 no action 1 perform a software reset on CDI 0 reserved specifies output from CDI for I path 00 normal operation (CDI data output sent to digital signal processing input) 01 if LVDS data enable = 1, then normal operation; if LVDS data enable = 0, then digital signal processing input = I_DC_LEVEL register value 10 digital signal processing input = I_DC_LEVEL 11 digital signal processing input = I_DC_LEVEL 3 to 2 Q_LEV_CNTRL[1:0] R/W 1 to 0 CDI_MODE[1:0] Description specifies output from CDI for Q path 00 normal operation (CDI data output sent to digital signal processing input) 01 if LVDS data enable = 1, then normal operation; if LVDS data enable = 0, then digital signal processing input = Q_DC_LEVEL register value 10 digital signal processing input = Q_DC_LEVEL 11 digital signal processing input = Q_DC_LEVEL R/W specifies CDI mode 00 cdi_mode 0 (× ×2 mode) 01 cdi_mode 1 (×4 mode) 10 cdi_mode 2 (×8 mode) 11 not used Table 62. LDS/MDS of I/Q DC levels registers (address 0Ch to 0Fh) bit description Default values are shown highlighted. Address Register Bit Symbol Access 0Ch 7 to 0 I_DC_LEVEL[7:0] R/W I_DC_LVL_LSB 0Dh I_DC_LVL_MSB 7 to 0 I_DC_LEVEL[15:8] 0Eh Q_DC_LVL_LSB 7 to 0 Q_DC_LEVEL[7:0] 0Fh Q_DC_LVL_MSB 7 to 0 Q_DC_LEVEL[15:8] Value I_DC_LEVEL - least significant 8 bits for I_DC_LEVEL - most significant 8 bits for I_DC_LEVEL R/W Q_DC_LEVEL - least significant 8 bits for Q_DC_LEVEL - most significant 8 bits for Q_DC_LEVEL DAC1627D1G25 Product data sheet Description © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 73 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 63. Register IO_MUX0 and IO_MUX2 (address 10h and 12h) Default values are shown highlighted. IO_SELECT0[9:0] Signal on pin IO0 Description 00 0000 0000 lclk internal LVDS lclk clock 00 0000 0001 ringo internal low frequency oscillator (approximately 1 MHz) 01 0000 nnnn Ldout_A internal LVDS data bit of channel A ( = 15 to 0; enabling the selection of the bit number to be observed) 10 0000 1111 AND (Ldout_B bits) AND result of the 16 LVDS data bits of channel B 10 0001 1111 OR (Ldout_B bits) OR result of the 16 LVDS data bits of channel B 10 0010 1111 AND (Ldout_A bits) AND result of the 16 LVDS data bits of channel A 10 0011 1111 OR (Ldout_A bits) OR result of the 16 LVDS data bits of channel A 11 1100 0000 INTR active low interrupt signal 11 1100 0001 INTR active high interrupt signal 11 1111 1110 1 set the general-purpose IO to high level 11 1111 1111 0 set the general-purpose IO to low level Table 64. Register IO_MUX1 and IO_MUX2 (address 11h and 12h) Default values are shown highlighted. IO_SELECT1[9:0] Signal on pin IO1 Description 00 0000 0000 dclk internal dclk clock (fs / 8 frequency) 01 0000 nnnn Ldout_B internal LVDS data bit of channel B ( = 15 to 0; enabling the selection bit number to be observed) 10 0000 1111 AND (Ldout_B bits) AND result of the 16 LVDS data bits of channel B 10 0001 1111 OR (Ldout_B bits) OR result of the 16 LVDS data bits of channel B 10 0010 1111 AND (Ldout_A bits) AND result of the 16 LVDS data bits of channel A 10 0011 1111 OR (Ldout_A bits) OR result of the 16 LVDS data bits of channel A 11 1100 0000 INTR active low interrupt signal 11 1100 0001 INTR active high interrupt signal 11 1111 1110 0 set the general-purpose IO to low level 11 1111 1111 1 set the general-purpose IO to high level DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 74 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating Table 65. Register TYPE_ID (address 1Bh) Default values are shown highlighted. Bit Symbol Access 7 DAC R Value Description calibration 0 uncalibrated device 1 calibrated device 6 to 5 FRONTEND R 01 LVDS input interface 4 0 DUAL 3 to 2 DSP 1 to 0 BIT_RES R dual DAC R internal digital signal processing 11 interpolation filter + SSBM 10 SSBM 01 interpolation filter 00 none R DAC bit resolution 00 16 bits 01 14 bits 10 12 bits 11 10 bits Table 66. Register DAC_VERSION (address 1Ch) Default values are shown highlighted. Bit Symbol Access 7 to 0 DAC_VERSION_ID[7:0] R Value Description DAC version number - 8 bits for the DAC version number Table 67. Register DIG_VERSION (address 1Dh) Default values are shown highlighted. Bit Symbol 7 to 0 DIG_VERSION_ID[7:0] Access Value R Description digital version number - 8 bits for the digital version number Table 68. Register LVDS_VERSION (address 1Eh) Default values are shown highlighted. Bit Symbol 7 to 0 LVDS_VERSION_ID[7:0] Access Value R Description LVDS receiver version number - 8 bits for the LVDS receiver version number Table 69. Register PAGE_ADD (address 1Fh) Default values are shown highlighted. Bit Symbol Access 2 to 0 PAGE_ADD[2:0] R/W Value Description Page address - current page address DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 75 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 12. Package outline HVQFN72: plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 x 10 x 0.85 mm B D SOT813-3 A terminal 1 index area A E A1 c detail X e1 e 1/2 e 19 36 L C C A B C v w b y1 C y 37 18 e e2 Eh 1/2 e 1 terminal 1 index area 54 72 55 X Dh 0 5 Dimensions Unit A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 mm 10 mm scale c D(1) Dh E(1) Eh e e1 e2 L v 0.2 10.1 10.0 9.9 7.2 7.1 7.0 10.1 10.0 9.9 7.2 7.1 7.0 0.5 8.5 8.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT813-3 --- --- --- sot813-3_po European projection Issue date 10-04-02 11-06-20 Fig 49. Package outline SOT813-3 (HVQFN72) DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 76 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 13. Abbreviations Table 70. Abbreviations Acronym Description BW BandWidth BWA Broadband Wireless Access CDI Clock Domain Interface CDMA Code Division Multiple Access CML Current Mode Logic CMOS Complementary Metal Oxide Semiconductor DAC Digital-to-Analog Converter EDGE Enhanced Data rates for GSM Evolution FIR Finite Impulse Response FPGA Field Programmable Gate Array GSM Global System for Mobile communications IF Intermediate Frequency IMD3 Third Order InterMoDulation LMDS Local Multipoint Distribution Service LO Local Oscillator LVDS Low-Voltage Differential Signaling NCO Numerically Controlled Oscillator NMOS Negative Metal-Oxide Semiconductor PLL Phase-Locked Loop SFDR Spurious-Free Dynamic Range SPI Serial Peripheral Interface WCDMA Wide band Code Division Multiple Access WLL Wireless Local Loop DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 77 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 14. Glossary 14.1 Static parameters INL — The deviation of the transfer function from a best fit straight line (linear regression computation). DNL — The difference between the ideal and the measured output value between successive DAC codes. 14.2 Dynamic parameters Spurious-Free Dynamic Range (SFDR) — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Decibels relative to full-scale (dBFS) — Unit used in a digital system to measure the amplitude level in decibel relative to the maximum peak value. InterModulation Distortion (IMD) — From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (second-order and third-order components) are defined below. IMD2 — The ratio between the RMS value of either tone and the RMS value of the worst second order intermodulation product. IMD3 — The ratio between the RMS value of either tone and the RMS value of the worst third order Intermodulation product. Total Harmonic Distortion (THD) — The ratio between the RMS value of the harmonics of the output frequency and the RMS value of the output sine wave. Usually, the calculation of THD is done on the first five harmonics. Signal-to-Noise Ratio (SNR) — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the noise excluding the harmonics and the DC component. Restricted BandWidth Spurious-Free Dynamic Range (SFDRRBW) — the ratio between the RMS value of the reconstructed output sine wave and the RMS value of the noise, including the harmonics, in a given bandwidth centered around foffset. DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 78 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 15. Revision history Table 71. Revision history Document ID Release date Data sheet status Change notice Supersedes DAC1627D1G25 v.4 20121113 Product data sheet - DAC1627D1G25 v.3 DAC1627D1G25 v.3 20120702 Rebranded/updated - DAC1627D1G25 v.2 DAC1627D1G25 v.2 20120331 Preliminary data sheet - DAC1627D1G25 v.1 DAC1627D1G25 v.1 20110429 Objective data sheet - - Contact information 6024 Silver Creek Valley Road San Jose, California 95138 DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 79 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 16. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14: Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6 Thermal characteristics . . . . . . . . . . . . . . . . . . .7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8 Read or Write mode access description . . . . .19 Number of bytes to be transferred . . . . . . . . . .19 SPI timing characteristics . . . . . . . . . . . . . . . .20 Input LVDS bus swapping . . . . . . . . . . . . . . . .22 Folded and interleaved format mapping . . . . . .23 CDI mode 0: operating modes examples . . . .29 CDI mode 1: operating modes examples . . . .29 CDI mode 2: operating modes examples . . . .30 Interpolation filter coefficients . . . . . . . . . . . . .31 Complex modulator operation mode . . . . . . . .34 Inversion filter coefficients . . . . . . . . . . . . . . . .35 DAC transfer function . . . . . . . . . . . . . . . . . . .40 Digital offset adjustment . . . . . . . . . . . . . . . . .42 Auxiliary DAC transfer function . . . . . . . . . . . .44 SPI start-up sequence . . . . . . . . . . . . . . . . . . .50 Page_00 register allocation map . . . . . . . . . . .52 Register COMMON (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Register TXCFG (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Register PLLCFG (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 NCO frequency registers (address 04h to 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .56 DAC output phase correction registers (address 09h to 0Ah) bit description . . . . . . . .56 Digital gain control registers (address 0Bh to 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .56 Register DAC_OUT_CTRL (address 0Fh) . . .57 Register DAC_CLIPPING (address 10h) . . . . .57 Digital offset value registers (address 11h to 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .57 NCO phase offset registers (address 15h to 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .57 Analog gain control (address 17h to 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 Auxiliary DAC registers (address 1Bh to 1Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 SPI_PAGE register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 Page 1 register allocation map . . . . . . . . . . . .59 MDS_MAIN register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .61 MDS window time registers (address 01h to 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .61 MDS_MISCCNTRL0 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .61 MDS_MAN_ADJUSTDLY register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .62 MDS_AUTO_CYCLES register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .62 Table 41. MDS_MISCCNTRL1 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 42. MDS_OFFSET_DLY register (address 07h)| bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 43. MDS_ADJDELAY register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 44. MDS status registers (address 09h to 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 45. Interrupt control register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 46. Interrupt enable register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 47. INTR_FLAGS register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 48. Bias current control registers (address 0Eh to 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 49. Bias current control table . . . . . . . . . . . . . . . . 66 Table 50. DAC_PON_SLEEP register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 51. DAC_TEST_8 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 52. SPI_PAGE register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 53. Page_0A register allocation map . . . . . . . . . . 69 Table 54. Register MAIN_CNTRL (address 00h) . . . . . . 71 Table 55. Register MAN_LDCLKDEL (address 01h) . . . 71 Table 56. Register DBG_LVDS (address 02h) . . . . . . . . 71 Table 57. Extension time reset registers (address 04h to 05h) bit description . . . . . . . . 71 Table 58. Register DCSMU_PREDIV (address 06h) . . . 72 Table 59. LSB/MSB of polarity registers (address 08h to 09h) bit description . . . . . . . . 72 Table 60. Register LD_CNTRL (address 0Ah) . . . . . . . . 72 Table 61. Register MISC_CNTRL (address 0Bh) . . . . . . 73 Table 62. LDS/MDS of I/Q DC levels registers (address 0Ch to 0Fh) bit description . . . . . . . . 73 Table 63. Register IO_MUX0 and IO_MUX2 (address 10h and 12h) . . . . . . . . . . . . . . . . . . 74 Table 64. Register IO_MUX1 and IO_MUX2 (address 11h and 12h) . . . . . . . . . . . . . . . . . . 74 Table 65. Register TYPE_ID (address 1Bh) . . . . . . . . . . 75 Table 66. Register DAC_VERSION (address 1Ch) . . . . 75 Table 67. Register DIG_VERSION (address 1Dh) . . . . . 75 Table 68. Register LVDS_VERSION (address 1Eh) . . . . 75 Table 69. Register PAGE_ADD (address 1Fh) . . . . . . . . 75 Table 70. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 71. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 79 DAC1627D1G25 Product data sheet © IDT 2012. All rights reserved. Rev. 4 — 12 December 2012 80 of 81 DAC1627D1G25 Integrated Device Technology Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 11.2 11.2.1 11.2.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 11.7 11.7.1 11.7.2 11.8 11.9 11.9.1 11.9.2 11.9.3 11.10 11.11 11.11.1 11.11.2 11.11.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical characteristics . . . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 18 General description . . . . . . . . . . . . . . . . . . . . 18 Serial Peripheral Interface (SPI) . . . . . . . . . . . 19 Protocol description . . . . . . . . . . . . . . . . . . . . 19 SPI timing description . . . . . . . . . . . . . . . . . . . 20 Power-on sequence . . . . . . . . . . . . . . . . . . . . 20 LVDS Data Input Format (DIF) block . . . . . . . 21 Input port polarity . . . . . . . . . . . . . . . . . . . . . . 21 Input port mapping . . . . . . . . . . . . . . . . . . . . . 22 Input port swapping . . . . . . . . . . . . . . . . . . . . 22 Input port formatting . . . . . . . . . . . . . . . . . . . . 23 Data parity/data enable. . . . . . . . . . . . . . . . . . 24 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 24 General-purpose IO pins . . . . . . . . . . . . . . . . 24 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LVDS DDR clock. . . . . . . . . . . . . . . . . . . . . . . 25 DAC core clock . . . . . . . . . . . . . . . . . . . . . . . . 25 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating modes . . . . . . . . . . . . . . . . . . . . . . 28 CDI mode 0 (x2 interpolation). . . . . . . . . . . . . 29 CDI mode 1 (x4 interpolation). . . . . . . . . . . . . 29 CDI mode 2 (x8 interpolation). . . . . . . . . . . . . 30 FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Single SideBand Modulator (SSBM). . . . . . . . 33 NCO in 40 bits . . . . . . . . . . . . . . . . . . . . . . . . 33 NCO low power . . . . . . . . . . . . . . . . . . . . . . . 34 Complex modulator . . . . . . . . . . . . . . . . . . . . 34 11.11.4 11.12 11.13 11.13.1 11.13.1.1 11.13.1.2 11.13.2 11.14 11.15 11.15.1 11.15.2 11.16 11.17 11.18 11.19 11.20 11.20.1 11.20.2 11.20.3 11.20.4 11.21 11.21.1 11.22 11.22.1 11.22.2 11.22.3 11.22.4 11.22.5 11.22.6 11.22.7 11.22.8 12 13 14 14.1 14.2 15 16 17 Minus 3dB . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverse sin x / x . . . . . . . . . . . . . . . . . . . . . . . Multiple Devices Synchronization (MDS). . . . MDS concept . . . . . . . . . . . . . . . . . . . . . . . . . MDS in All slaves mode . . . . . . . . . . . . . . . . . MDS in Master/slaves mode . . . . . . . . . . . . . MDS flexibility and constraints . . . . . . . . . . . . DAC transfer function. . . . . . . . . . . . . . . . . . . Full-scale current . . . . . . . . . . . . . . . . . . . . . . Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . Full-scale current adjustment. . . . . . . . . . . . . Limiter/clip control . . . . . . . . . . . . . . . . . . . . . Digital offset adjustment. . . . . . . . . . . . . . . . . Analog output. . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . Output configuration. . . . . . . . . . . . . . . . . . . . Basic output configuration . . . . . . . . . . . . . . . Low input impedance IQ-modulator interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IQ-modulator - DC interface. . . . . . . . . . . . . . IQ-modulator - AC interface . . . . . . . . . . . . . . Design recommendations . . . . . . . . . . . . . . . Power and grounding. . . . . . . . . . . . . . . . . . . Configuration interface. . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . SPI start-up sequence . . . . . . . . . . . . . . . . . . Page 0 register allocation map . . . . . . . . . . . Page 0 bit definition detailed description . . . . Page 1 allocation map . . . . . . . . . . . . . . . . . . Page 1 bit definition detailed description . . . . Page A register allocation map . . . . . . . . . . . Page A bit definition detailed description . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static parameters . . . . . . . . . . . . . . . . . . . . . . Dynamic parameters . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 36 38 39 39 40 41 41 41 41 42 42 43 44 45 46 47 49 49 49 50 50 50 52 54 59 61 69 71 76 77 78 78 78 79 80 81 Disclaimer Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright, 2012. All rights reserved.