DF2623FA20JV

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2626 Group, H8S/2623 Group, H8S/2626F-ZTATTM, H8S/2623F-ZTATTM Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series H8S/2626 H8S/2625 H8S/2623 H8S/2622 H8S/2621 HD6432626 HD64F2626 HD6432625 HD6432623 HD64F2623 HD6432622 HD64F2621 Rev.5.00 2006.01 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 5.00 Jan 10, 2006 page ii of xxiv General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product’s state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Address Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these address. Do not access these registers: the system’s operation is not guaranteed if they are accessed. Rev. 5.00 Jan 10, 2006 page iii of xxiv Rev. 5.00 Jan 10, 2006 page iv of xxiv Preface The H8S/2626 Group and H8S/2623 Group are series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for system configuration. The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. Single-power-supply flash memory (F-ZTAT™*), and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), controller area network (HCAN), A/D converter, D/A converter (H8S/2626 Group only), and I/O ports. In addition, data transfer controller (DTC) is provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2626 Group or H8S/2623 Group enables easy implementation of compact, highperformance systems capable of processing large volumes of data. This manual describes the hardware of the H8S/2626 Group and H8S/2623 Group. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp. Rev. 5.00 Jan 10, 2006 page v of xxiv Rev. 5.00 Jan 10, 2006 page vi of xxiv Main Revisions in This Edition Item Page Revision (See Manual for Details) All — • All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. • Designation for categories changed from “series” to “group” 19.13 Flash Memory Programming and Erasing Precautions 682 Figure 19.26 amended Figure 19.26 Power-On/Off Timing (Boot Mode) Wait time: x Programming/ erasing possible Wait time: 100 µs φ Min 0 µs tOSC1 VCC tMDS*3 FWE Min 0 µs MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Rev. 5.00 Jan 10, 2006 page vii of xxiv Item Page Revision (See Manual for Details) 19.13 Flash Memory Programming and Erasing Precautions 683 Figure 19.27 amended Figure 19.27 Power-On/Off Timing (User Program Mode) Wait time: x Programming/ erasing possible Wait time: 100 µs φ Min 0 µs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Wait time: 100 µs Programming/ erasing possible Wait time: x Wait time: x Programming/ erasing possible Wait time: 100 µs Wait time: 100 µs Wait time: x Programming/ erasing possible Wait time: 100 µs Figure 19.28 amended Wait time: x Programming/ erasing possible Figure 19.28 684 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode) φ tOSC1 VCC Min 0µs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE1 cleared SWE1 set SWE1 bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Rev. 5.00 Jan 10, 2006 page viii of xxiv User program mode Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Overview........................................................................................................................... 1 Internal Block Diagram..................................................................................................... 6 Pin Descriptions ................................................................................................................ 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Functions in Each Operating Mode ............................................................... 10 1.3.3 Pin Functions ....................................................................................................... 18 Section 2 CPU ...................................................................................................................... 23 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU ............................................................................ 2.1.4 Differences from H8/300H CPU.......................................................................... CPU Operating Modes ...................................................................................................... Address Space................................................................................................................... Register Configuration...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers ................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial Register Values.......................................................................................... Data Formats..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Overview.............................................................................................................. 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Table of Instructions Classified by Function ....................................................... 2.6.4 Basic Instruction Formats .................................................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Mode................................................................................................. 2.7.2 Effective Address Calculation ............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Reset State............................................................................................................ 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Program Execution State...................................................................................... 23 23 24 25 25 26 31 32 32 33 34 36 37 37 39 40 40 41 42 51 53 53 56 60 60 61 62 65 Rev. 5.00 Jan 10, 2006 page ix of xxiv 2.8.5 Bus-Released State............................................................................................... 2.8.6 Power-Down State ............................................................................................... 2.9 Basic Timing ..................................................................................................................... 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 On-Chip HCAN Module Access Timing ............................................................. 2.9.5 External Address Space Access Timing .............................................................. 2.10 Usage Note........................................................................................................................ 2.10.1 TAS Instruction.................................................................................................... 65 65 66 66 66 68 70 72 72 72 Section 3 MCU Operating Modes .................................................................................. 73 3.1 3.2 3.3 3.4 3.5 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 3.2.1 Mode Control Register (MDCR) ......................................................................... 3.2.2 System Control Register (SYSCR) ...................................................................... 3.2.3 Pin Function Control Register (PFCR) ................................................................ Operating Mode Descriptions ........................................................................................... 3.3.1 Mode 4 ................................................................................................................. 3.3.2 Mode 5 ................................................................................................................. 3.3.3 Mode 6 ................................................................................................................. 3.3.4 Mode 7 ................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Address Map in Each Operating Mode ............................................................................. 73 73 74 75 75 75 77 79 79 79 79 79 80 80 Section 4 Exception Handling ......................................................................................... 85 4.1 4.2 4.3 4.4 4.5 4.6 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation............................................................................. 4.1.3 Exception Vector Table ....................................................................................... Reset.................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Sequence .................................................................................................... 4.2.3 Interrupts after Reset............................................................................................ 4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. Traces................................................................................................................................ Interrupts ........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Rev. 5.00 Jan 10, 2006 page x of xxiv 85 85 86 86 88 88 88 90 90 91 92 93 94 4.7 Notes on Use of the Stack ................................................................................................. 95 Section 5 Interrupt Controller .......................................................................................... 97 5.1 5.2 5.3 5.4 5.5 5.6 Overview........................................................................................................................... 5.1.1 Features................................................................................................................ 5.1.2 Block Diagram ..................................................................................................... 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 5.2.3 IRQ Enable Register (IER) .................................................................................. 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 5.2.5 IRQ Status Register (ISR).................................................................................... Interrupt Sources............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts................................................................................................. 5.3.3 Interrupt Exception Handling Vector Table......................................................... Interrupt Operation............................................................................................................ 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.4.2 Interrupt Control Mode 0 ..................................................................................... 5.4.3 Interrupt Control Mode 2 ..................................................................................... 5.4.4 Interrupt Exception Handling Sequence .............................................................. 5.4.5 Interrupt Response Times .................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling..................................... 5.5.2 Instructions that Disable Interrupts ...................................................................... 5.5.3 Times when Interrupts are Disabled .................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... DTC Activation by Interrupt............................................................................................. 5.6.1 Overview.............................................................................................................. 5.6.2 Block Diagram ..................................................................................................... 5.6.3 Operation ............................................................................................................. 97 97 98 99 99 100 100 101 103 104 105 106 106 108 108 112 112 116 118 120 121 122 122 123 123 124 124 124 125 125 Section 6 PC Break Controller (PBC) ........................................................................... 127 6.1 6.2 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 Break Address Register A (BARA) ..................................................................... 127 127 128 129 129 129 Rev. 5.00 Jan 10, 2006 page xi of xxiv 6.3 6.2.2 Break Address Register B (BARB)...................................................................... 6.2.3 Break Control Register A (BCRA) ...................................................................... 6.2.4 Break Control Register B (BCRB)....................................................................... 6.2.5 Module Stop Control Register C (MSTPCRC).................................................... Operation .......................................................................................................................... 6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 6.3.2 PC Break Interrupt Due to Data Access............................................................... 6.3.3 Notes on PC Break Interrupt Handling ................................................................ 6.3.4 Operation in Transitions to Power-Down Modes ................................................ 6.3.5 PC Break Operation in Continuous Data Transfer............................................... 6.3.6 When Instruction Execution is Delayed by One State ......................................... 6.3.7 Additional Notes .................................................................................................. 130 130 132 132 133 133 134 134 135 136 137 138 Section 7 Bus Controller ................................................................................................... 139 7.1 7.2 7.3 7.4 7.5 Overview........................................................................................................................... 7.1.1 Features................................................................................................................ 7.1.2 Block Diagram ..................................................................................................... 7.1.3 Pin Configuration................................................................................................. 7.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 7.2.1 Bus Width Control Register (ABWCR)............................................................... 7.2.2 Access State Control Register (ASTCR) ............................................................. 7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 7.2.4 Bus Control Register H (BCRH).......................................................................... 7.2.5 Bus Control Register L (BCRL) .......................................................................... 7.2.6 Pin Function Control Register (PFCR) ................................................................ Overview of Bus Control .................................................................................................. 7.3.1 Area Partitioning.................................................................................................. 7.3.2 Bus Specifications................................................................................................ 7.3.3 Memory Interfaces ............................................................................................... 7.3.4 Interface Specifications for Each Area ................................................................ Basic Bus Interface ........................................................................................................... 7.4.1 Overview.............................................................................................................. 7.4.2 Data Size and Data Alignment............................................................................. 7.4.3 Valid Strobes........................................................................................................ 7.4.4 Basic Timing........................................................................................................ 7.4.5 Wait Control ........................................................................................................ Burst ROM Interface......................................................................................................... 7.5.1 Overview.............................................................................................................. 7.5.2 Basic Timing........................................................................................................ 7.5.3 Wait Control ........................................................................................................ Rev. 5.00 Jan 10, 2006 page xii of xxiv 139 139 140 141 142 143 143 144 145 149 151 152 154 154 155 156 157 158 158 158 160 161 169 171 171 171 173 7.6 Idle Cycle .......................................................................................................................... 7.6.1 Operation ............................................................................................................. 7.6.2 Pin States in Idle Cycle ........................................................................................ 7.7 Write Data Buffer Function .............................................................................................. 7.8 Bus Release....................................................................................................................... 7.8.1 Overview.............................................................................................................. 7.8.2 Operation ............................................................................................................. 7.8.3 Pin States in External Bus Released State............................................................ 7.8.4 Transition Timing ................................................................................................ 7.8.5 Usage Note........................................................................................................... 7.9 Bus Arbitration.................................................................................................................. 7.9.1 Overview.............................................................................................................. 7.9.2 Operation ............................................................................................................. 7.9.3 Bus Transfer Timing ............................................................................................ 7.10 Resets and the Bus Controller ........................................................................................... 174 174 176 177 178 178 178 179 180 181 181 181 181 182 182 Section 8 Data Transfer Controller (DTC) ................................................................... 183 8.1 8.2 8.3 Overview........................................................................................................................... 8.1.1 Features................................................................................................................ 8.1.2 Block Diagram ..................................................................................................... 8.1.3 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 8.2.1 DTC Mode Register A (MRA) ............................................................................ 8.2.2 DTC Mode Register B (MRB)............................................................................. 8.2.3 DTC Source Address Register (SAR).................................................................. 8.2.4 DTC Destination Address Register (DAR).......................................................... 8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 8.2.6 DTC Transfer Count Register B (CRB)............................................................... 8.2.7 DTC Enable Registers (DTCER) ......................................................................... 8.2.8 DTC Vector Register (DTVECR)........................................................................ 8.2.9 Module Stop Control Register A (MSTPCRA) ................................................... Operation .......................................................................................................................... 8.3.1 Overview.............................................................................................................. 8.3.2 Activation Sources ............................................................................................... 8.3.3 DTC Vector Table................................................................................................ 8.3.4 Location of Register Information in Address Space ............................................ 8.3.5 Normal Mode....................................................................................................... 8.3.6 Repeat Mode ........................................................................................................ 8.3.7 Block Transfer Mode ........................................................................................... 8.3.8 Chain Transfer ..................................................................................................... 8.3.9 Operation Timing................................................................................................. 183 183 184 185 186 186 188 189 189 190 190 191 192 193 193 193 195 197 200 201 202 203 205 206 Rev. 5.00 Jan 10, 2006 page xiii of xxiv 8.4 8.5 8.3.10 Number of DTC Execution States........................................................................ 8.3.11 Procedures for Using DTC................................................................................... 8.3.12 Examples of Use of the DTC ............................................................................... Interrupts ........................................................................................................................... Usage Notes ...................................................................................................................... 207 209 210 213 213 Section 9 I/O Ports .............................................................................................................. 215 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Overview........................................................................................................................... Port 1................................................................................................................................. 9.2.1 Overview.............................................................................................................. 9.2.2 Register Configuration......................................................................................... 9.2.3 Pin Functions ....................................................................................................... Port 4................................................................................................................................. 9.3.1 Overview.............................................................................................................. 9.3.2 Register Configuration......................................................................................... 9.3.3 Pin Functions ....................................................................................................... Port 9................................................................................................................................. 9.4.1 Overview.............................................................................................................. 9.4.2 Register Configuration......................................................................................... 9.4.3 Pin Functions ....................................................................................................... Port A................................................................................................................................ 9.5.1 Overview.............................................................................................................. 9.5.2 Register Configuration......................................................................................... 9.5.3 Pin Functions ....................................................................................................... 9.5.4 MOS Input Pull-Up Function............................................................................... Port B ................................................................................................................................ 9.6.1 Overview.............................................................................................................. 9.6.2 Register Configuration......................................................................................... 9.6.3 Pin Functions ....................................................................................................... 9.6.4 MOS Input Pull-Up Function............................................................................... Port C ................................................................................................................................ 9.7.1 Overview.............................................................................................................. 9.7.2 Register Configuration......................................................................................... 9.7.3 Pin Functions ....................................................................................................... 9.7.4 MOS Input Pull-Up Function............................................................................... Port D................................................................................................................................ 9.8.1 Overview.............................................................................................................. 9.8.2 Register Configuration......................................................................................... 9.8.3 Pin Functions ....................................................................................................... 9.8.4 MOS Input Pull-Up Function............................................................................... Port E ................................................................................................................................ Rev. 5.00 Jan 10, 2006 page xiv of xxiv 215 219 219 220 222 234 234 235 235 236 236 237 237 237 237 238 242 245 246 246 247 249 258 259 259 260 263 268 269 269 270 272 273 274 9.9.1 Overview.............................................................................................................. 9.9.2 Register Configuration......................................................................................... 9.9.3 Pin Functions ....................................................................................................... 9.9.4 MOS Input Pull-Up Function............................................................................... 9.10 Port F................................................................................................................................. 9.10.1 Overview.............................................................................................................. 9.10.2 Register Configuration......................................................................................... 9.10.3 Pin Functions ....................................................................................................... 274 275 277 278 279 279 280 282 Section 10 16-Bit Timer Pulse Unit (TPU) .................................................................. 285 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram ..................................................................................................... 10.1.3 Pin Configuration................................................................................................. 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 Timer Control Register (TCR) ............................................................................. 10.2.2 Timer Mode Register (TMDR) ............................................................................ 10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 10.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 10.2.5 Timer Status Register (TSR)................................................................................ 10.2.6 Timer Counter (TCNT)........................................................................................ 10.2.7 Timer General Register (TGR) ............................................................................ 10.2.8 Timer Start Register (TSTR)................................................................................ 10.2.9 Timer Synchro Register (TSYR) ......................................................................... 10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... 10.3 Interface to Bus Master ..................................................................................................... 10.3.1 16-Bit Registers ................................................................................................... 10.3.2 8-Bit Registers ..................................................................................................... 10.4 Operation .......................................................................................................................... 10.4.1 Overview.............................................................................................................. 10.4.2 Basic Functions.................................................................................................... 10.4.3 Synchronous Operation........................................................................................ 10.4.4 Buffer Operation .................................................................................................. 10.4.5 Cascaded Operation ............................................................................................. 10.4.6 PWM Modes ........................................................................................................ 10.4.7 Phase Counting Mode .......................................................................................... 10.5 Interrupts ........................................................................................................................... 10.5.1 Interrupt Sources and Priorities............................................................................ 10.5.2 DTC Activation.................................................................................................... 10.5.3 A/D Converter Activation.................................................................................... 285 285 289 290 292 294 294 299 301 314 316 320 320 321 321 322 323 323 323 325 325 326 331 334 338 340 345 351 351 353 353 Rev. 5.00 Jan 10, 2006 page xv of xxiv 10.6 Operation Timing.............................................................................................................. 10.6.1 Input/Output Timing ............................................................................................ 10.6.2 Interrupt Signal Timing........................................................................................ 10.7 Usage Notes ...................................................................................................................... 354 354 358 362 Section 11 Programmable Pulse Generator (PPG) .................................................... 373 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Pin Configuration................................................................................................. 11.1.4 Registers............................................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 11.2.4 Notes on NDR Access.......................................................................................... 11.2.5 PPG Output Control Register (PCR).................................................................... 11.2.6 PPG Output Mode Register (PMR)...................................................................... 11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 11.2.8 Module Stop Control Register A (MSTPCRA) ................................................... 11.3 Operation .......................................................................................................................... 11.3.1 Overview.............................................................................................................. 11.3.2 Output Timing...................................................................................................... 11.3.3 Normal Pulse Output............................................................................................ 11.3.4 Non-Overlapping Pulse Output............................................................................ 11.3.5 Inverted Pulse Output .......................................................................................... 11.3.6 Pulse Output Triggered by Input Capture ............................................................ 11.4 Usage Notes ...................................................................................................................... 373 373 374 375 376 377 377 378 379 379 381 383 385 386 387 387 388 389 391 394 395 396 Section 12 Watchdog Timer ............................................................................................. 399 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Timer Counter (TCNT)........................................................................................ 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Pin Function Control Register (PFCR) ................................................................ 12.2.5 Notes on Register Access..................................................................................... Rev. 5.00 Jan 10, 2006 page xvi of xxiv 399 399 400 402 402 403 403 404 408 410 410 12.3 Operation .......................................................................................................................... 12.3.1 Watchdog Timer Operation ................................................................................. 12.3.2 Interval Timer Operation ..................................................................................... 12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 12.4 Interrupts ........................................................................................................................... 12.5 Usage Notes ...................................................................................................................... 12.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 12.5.2 Changing Value of PSS and CKS2 to CKS0 ....................................................... 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 12.5.4 System Reset by WDTOVF Signal...................................................................... 12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 12.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 412 412 415 415 416 417 417 417 418 418 418 418 419 Section 13 Serial Communication Interface (SCI) .................................................... 421 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram ..................................................................................................... 13.1.3 Pin Configuration................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 Receive Shift Register (RSR) .............................................................................. 13.2.2 Receive Data Register (RDR) .............................................................................. 13.2.3 Transmit Shift Register (TSR) ............................................................................. 13.2.4 Transmit Data Register (TDR)............................................................................. 13.2.5 Serial Mode Register (SMR)................................................................................ 13.2.6 Serial Control Register (SCR).............................................................................. 13.2.7 Serial Status Register (SSR) ................................................................................ 13.2.8 Bit Rate Register (BRR) ...................................................................................... 13.2.9 Smart Card Mode Register (SCMR) .................................................................... 13.2.10 Module Stop Control Register B (MSTPCRB).................................................... 13.3 Operation .......................................................................................................................... 13.3.1 Overview.............................................................................................................. 13.3.2 Operation in Asynchronous Mode ....................................................................... 13.3.3 Multiprocessor Communication Function............................................................ 13.3.4 Operation in Clocked Synchronous Mode ........................................................... 13.4 SCI Interrupts.................................................................................................................... 13.5 Usage Notes ...................................................................................................................... 421 421 423 424 425 426 426 426 427 427 428 431 435 439 447 448 450 450 452 463 471 480 482 Section 14 Smart Card Interface ..................................................................................... 491 14.1 Overview........................................................................................................................... 491 Rev. 5.00 Jan 10, 2006 page xvii of xxiv 14.1.1 Features................................................................................................................ 14.1.2 Block Diagram ..................................................................................................... 14.1.3 Pin Configuration................................................................................................. 14.1.4 Register Configuration......................................................................................... 14.2 Register Descriptions ........................................................................................................ 14.2.1 Smart Card Mode Register (SCMR) .................................................................... 14.2.2 Serial Status Register (SSR) ................................................................................ 14.2.3 Serial Mode Register (SMR)................................................................................ 14.2.4 Serial Control Register (SCR).............................................................................. 14.3 Operation .......................................................................................................................... 14.3.1 Overview.............................................................................................................. 14.3.2 Pin Connections ................................................................................................... 14.3.3 Data Format ......................................................................................................... 14.3.4 Register Settings .................................................................................................. 14.3.5 Clock.................................................................................................................... 14.3.6 Data Transfer Operations..................................................................................... 14.3.7 Operation in GSM Mode ..................................................................................... 14.3.8 Operation in Block Transfer Mode ...................................................................... 14.4 Usage Notes ...................................................................................................................... 491 492 493 494 495 495 496 498 500 501 501 501 503 505 507 509 516 517 518 Section 15 Controller Area Network (HCAN)............................................................ 523 15.1 Overview........................................................................................................................... 15.1.1 Features................................................................................................................ 15.1.2 Block Diagram ..................................................................................................... 15.1.3 Pin Configuration................................................................................................. 15.1.4 Register Configuration......................................................................................... 15.2 Register Descriptions ........................................................................................................ 15.2.1 Master Control Register (MCR)........................................................................... 15.2.2 General Status Register (GSR) ............................................................................ 15.2.3 Bit Configuration Register (BCR) ....................................................................... 15.2.4 Mailbox Configuration Register (MBCR) ........................................................... 15.2.5 Transmit Wait Register (TXPR) .......................................................................... 15.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 15.2.8 Abort Acknowledge Register (ABACK) ............................................................. 15.2.9 Receive Complete Register (RXPR) .................................................................... 15.2.10 Remote Request Register (RFPR)........................................................................ 15.2.11 Interrupt Register (IRR) ....................................................................................... 15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 15.2.13 Interrupt Mask Register (IMR) ............................................................................ 15.2.14 Receive Error Counter (REC) .............................................................................. Rev. 5.00 Jan 10, 2006 page xviii of xxiv 523 523 524 525 526 528 528 530 531 534 535 536 537 538 539 540 541 545 546 549 15.2.15 Transmit Error Counter (TEC)............................................................................. 15.2.16 Unread Message Status Register (UMSR) ........................................................... 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 15.2.18 Message Control (MC0 to MC15) ....................................................................... 15.2.19 Message Data (MD0 to MD15) ........................................................................... 15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 15.3 Operation .......................................................................................................................... 15.3.1 Hardware and Software Resets ............................................................................ 15.3.2 Initialization after Hardware Reset ...................................................................... 15.3.3 Transmit Mode..................................................................................................... 15.3.4 Receive Mode ...................................................................................................... 15.3.5 HCAN Sleep Mode .............................................................................................. 15.3.6 HCAN Halt Mode ................................................................................................ 15.3.7 Interrupt Interface ................................................................................................ 15.3.8 DTC Interface ...................................................................................................... 15.4 CAN Bus Interface............................................................................................................ 15.5 Usage Notes ...................................................................................................................... 549 550 551 553 557 559 560 560 563 568 574 579 582 583 584 585 585 Section 16 A/D Converter ................................................................................................. 589 16.1 Overview........................................................................................................................... 16.1.1 Features................................................................................................................ 16.1.2 Block Diagram ..................................................................................................... 16.1.3 Pin Configuration................................................................................................. 16.1.4 Register Configuration......................................................................................... 16.2 Register Descriptions ........................................................................................................ 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 16.2.2 A/D Control/Status Register (ADCSR) ............................................................... 16.2.3 A/D Control Register (ADCR) ............................................................................ 16.2.4 Module Stop Control Register A (MSTPCRA) ................................................... 16.3 Interface to Bus Master ..................................................................................................... 16.4 Operation .......................................................................................................................... 16.4.1 Single Mode (SCAN = 0) .................................................................................... 16.4.2 Scan Mode (SCAN = 1)....................................................................................... 16.4.3 Input Sampling and A/D Conversion Time ......................................................... 16.4.4 External Trigger Input Timing............................................................................. 16.5 Interrupts ........................................................................................................................... 16.6 Usage Notes ...................................................................................................................... 589 589 590 591 592 593 593 594 597 598 599 600 600 602 604 605 606 607 Section 17 D/A Converter [Provided in the H8S/2626 Group only] .................... 613 17.1 Overview........................................................................................................................... 613 17.1.1 Features................................................................................................................ 613 Rev. 5.00 Jan 10, 2006 page xix of xxiv 17.1.2 Block Diagram ..................................................................................................... 17.1.3 Pin Configuration................................................................................................. 17.1.4 Register Configuration......................................................................................... 17.2 Register Descriptions ........................................................................................................ 17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3) ................................................. 17.2.2 D/A Control Register 23 (DACR23).................................................................... 17.2.3 Module Stop Control Register C (MSTPCRC).................................................... 17.3 Operation .......................................................................................................................... 614 615 615 616 616 616 618 618 Section 18 RAM .................................................................................................................. 621 18.1 Overview........................................................................................................................... 18.1.1 Block Diagram ..................................................................................................... 18.1.2 Register Configuration......................................................................................... 18.2 Register Descriptions ........................................................................................................ 18.2.1 System Control Register (SYSCR) ...................................................................... 18.3 Operation .......................................................................................................................... 18.4 Usage Notes ...................................................................................................................... 621 621 622 622 622 623 623 Section 19 ROM (Preliminary)........................................................................................ 625 19.1 Features ............................................................................................................................. 19.2 Overview........................................................................................................................... 19.2.1 Block Diagram ..................................................................................................... 19.2.2 Mode Transitions ................................................................................................. 19.2.3 On-Board Programming Modes........................................................................... 19.2.4 Flash Memory Emulation in RAM ...................................................................... 19.2.5 Differences between Boot Mode and User Program Mode ................................. 19.2.6 Block Configuration ............................................................................................ 19.3 Pin Configuration.............................................................................................................. 19.4 Register Configuration...................................................................................................... 19.5 Register Descriptions ........................................................................................................ 19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 19.5.5 RAM Emulation Register (RAMER)................................................................... 19.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 19.5.7 Serial Control Register X (SCRX)....................................................................... 19.6 On-Board Programming Modes........................................................................................ 19.6.1 Boot Mode ........................................................................................................... 19.6.2 User Program Mode............................................................................................. 19.7 Flash Memory Programming/Erasing ............................................................................... Rev. 5.00 Jan 10, 2006 page xx of xxiv 625 626 626 627 628 630 631 632 632 633 633 633 637 638 638 639 641 641 642 643 647 649 19.8 19.9 19.10 19.11 19.12 19.13 19.14 19.7.1 Program Mode ..................................................................................................... 19.7.2 Program-Verify Mode.......................................................................................... 19.7.3 Erase Mode .......................................................................................................... 19.7.4 Erase-Verify Mode .............................................................................................. Protection .......................................................................................................................... 19.8.1 Hardware Protection ............................................................................................ 19.8.2 Software Protection.............................................................................................. 19.8.3 Error Protection.................................................................................................... Flash Memory Emulation in RAM ................................................................................... Interrupt Handling when Programming/Erasing Flash Memory....................................... Flash Memory Programmer Mode .................................................................................... 19.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 19.11.2 Programmer Mode Operation .............................................................................. 19.11.3 Memory Read Mode ............................................................................................ 19.11.4 Auto-Program Mode ............................................................................................ 19.11.5 Auto-Erase Mode................................................................................................. 19.11.6 Status Read Mode ................................................................................................ 19.11.7 Status Polling ....................................................................................................... 19.11.8 Programmer Mode Transition Time .................................................................... 19.11.9 Notes on Memory Programming.......................................................................... Flash Memory and Power-Down States............................................................................ 19.12.1 Note on Power-Down States ................................................................................ Flash Memory Programming and Erasing Precautions..................................................... Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 651 652 656 656 658 658 659 660 662 664 664 665 667 668 672 674 676 677 677 678 679 679 680 685 Section 20 Clock Pulse Generator .................................................................................. 687 20.1 Overview........................................................................................................................... 20.1.1 Block Diagram ..................................................................................................... 20.1.2 Register Configuration......................................................................................... 20.2 Register Descriptions ........................................................................................................ 20.2.1 System Clock Control Register (SCKCR) ........................................................... 20.2.2 Low-Power Control Register (LPWRCR) ........................................................... 20.3 Oscillator........................................................................................................................... 20.3.1 Connecting a Crystal Resonator........................................................................... 20.3.2 External Clock Input ............................................................................................ 20.4 PLL Circuit ....................................................................................................................... 20.5 Medium-Speed Clock Divider .......................................................................................... 20.6 Bus Master Clock Selection Circuit .................................................................................. 20.7 Subclock Oscillator (H8S/2626 Group Only) ................................................................... 20.8 Subclock Waveform Shaping Circuit (H8S/2626 Group Only)........................................ 20.9 Note on Crystal Resonator ................................................................................................ 687 688 688 689 689 690 691 691 694 696 696 697 697 698 698 Rev. 5.00 Jan 10, 2006 page xxi of xxiv Section 21A Power-Down Modes [H8S/2623 Group] ............................................. 699 21A.1 21A.2 21A.3 21A.4 21A.5 21A.6 21A.7 21A.8 Overview ....................................................................................................................... 21A.1.1 Register Configuration.................................................................................. Register Descriptions..................................................................................................... 21A.2.1 Standby Control Register (SBYCR) ............................................................. 21A.2.2 System Clock Control Register (SCKCR) .................................................... 21A.2.3 Low-Power Control Register (LPWRCR) .................................................... 21A.2.4 Module Stop Control Register (MSTPCR) ................................................... Medium-Speed Mode .................................................................................................... Sleep Mode.................................................................................................................... 21A.4.1 Sleep Mode ................................................................................................... 21A.4.2 Exiting Sleep Mode ...................................................................................... Module Stop Mode........................................................................................................ 21A.5.1 Module Stop Mode ....................................................................................... 21A.5.2 Usage Notes .................................................................................................. Software Standby Mode ................................................................................................ 21A.6.1 Software Standby Mode................................................................................ 21A.6.2 Clearing Software Standby Mode................................................................. 21A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode............................................................................................... 21A.6.4 Software Standby Mode Application Example............................................. 21A.6.5 Usage Notes .................................................................................................. Hardware Standby Mode............................................................................................... 21A.7.1 Hardware Standby Mode .............................................................................. 21A.7.2 Hardware Standby Mode Timing.................................................................. φ Clock Output Disabling Function............................................................................... 699 702 702 702 704 705 706 707 708 708 708 708 708 710 710 710 710 711 712 713 713 713 714 714 Section 21B Power-Down Modes [H8S/2626 Group].............................................. 715 21B.1 21B.2 21B.3 21B.4 21B.5 Overview ....................................................................................................................... 21B.1.1 Register Configuration.................................................................................. Register Descriptions..................................................................................................... 21B.2.1 Standby Control Register (SBYCR) ............................................................. 21B.2.2 System Clock Control Register (SCKCR) .................................................... 21B.2.3 Low-Power Control Register (LPWRCR) .................................................... 21B.2.4 Timer Control/Status Register (TCSR)......................................................... 21B.2.5 Module Stop Control Register (MSTPCR) ................................................... Medium-Speed Mode .................................................................................................... Sleep Mode.................................................................................................................... 21B.4.1 Sleep Mode ................................................................................................... 21B.4.2 Exiting Sleep Mode ...................................................................................... Module Stop Mode........................................................................................................ Rev. 5.00 Jan 10, 2006 page xxii of xxiv 715 719 719 719 721 722 725 726 727 728 728 728 728 21B.5.1 Module Stop Mode ....................................................................................... 21B.5.2 Usage Notes .................................................................................................. Software Standby Mode ................................................................................................ 21B.6.1 Software Standby Mode................................................................................ 21B.6.2 Clearing Software Standby Mode................................................................. 21B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode............................................................................................... 21B.6.4 Software Standby Mode Application Example............................................. 21B.6.5 Usage Notes .................................................................................................. Hardware Standby Mode............................................................................................... 21B.7.1 Hardware Standby Mode .............................................................................. 21B.7.2 Hardware Standby Mode Timing.................................................................. Watch Mode .................................................................................................................. 21B.8.1 Watch Mode.................................................................................................. 21B.8.2 Exiting Watch Mode..................................................................................... 21B.8.3 Notes............................................................................................................. Sub-Sleep Mode ............................................................................................................ 21B.9.1 Sub-Sleep Mode............................................................................................ 21B.9.2 Exiting Sub-Sleep Mode............................................................................... Sub-Active Mode .......................................................................................................... 21B.10.1 Sub-Active Mode......................................................................................... 21B.10.2 Exiting Sub-Active Mode ............................................................................ Direct Transitions.......................................................................................................... 21B.11.1 Overview of Direct Transitions.................................................................... φ Clock Output Disabling Function .............................................................................. Usage Notes................................................................................................................... 731 732 733 733 733 734 734 734 735 735 736 736 736 737 737 737 738 738 738 739 Section 22 Electrical Characteristics (Preliminary) ................................................... 22.1 Absolute Maximum Ratings ............................................................................................. 22.2 DC Characteristics ............................................................................................................ 22.3 AC Characteristics ............................................................................................................ 22.3.1 Clock Timing ....................................................................................................... 22.3.2 Control Signal Timing ......................................................................................... 22.3.3 Bus Timing .......................................................................................................... 22.3.4 Timing of On-Chip Supporting Modules............................................................. 22.4 A/D Conversion Characteristics........................................................................................ 22.5 D/A Conversion Characteristics........................................................................................ 22.6 Flash Memory Characteristics........................................................................................... 22.7 Usage Note........................................................................................................................ 741 741 742 745 746 747 749 756 760 760 761 762 21B.6 21B.7 21B.8 21B.9 21B.10 21B.11 21B.12 21B.13 728 730 730 730 730 Rev. 5.00 Jan 10, 2006 page xxiii of xxiv Appendix A Instruction Set .............................................................................................. 763 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List .................................................................................................................. Instruction Codes .............................................................................................................. Operation Code Map......................................................................................................... Number of States Required for Instruction Execution ...................................................... Bus States during Instruction Execution ........................................................................... Condition Code Modification ........................................................................................... 763 787 802 806 817 831 Appendix B Internal I/O Register ................................................................................... 837 B.1 B.2 Address ............................................................................................................................. 837 Functions........................................................................................................................... 852 Appendix C I/O Port Block Diagrams......................................................................... 1008 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Port 1 Block Diagrams.................................................................................................... Port 4 Block Diagram ..................................................................................................... Port 9 Block Diagram ..................................................................................................... Port A Block Diagrams ................................................................................................... Port B Block Diagram..................................................................................................... Port C Block Diagrams ................................................................................................... Port D Block Diagram..................................................................................................... Port E Block Diagram ..................................................................................................... Port F Block Diagrams.................................................................................................... 1008 1014 1014 1015 1020 1021 1025 1026 1027 Appendix D Pin States ...................................................................................................... 1036 D.1 Port States in Each Mode ................................................................................................ 1036 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ............................................................................................. 1039 Appendix F Product Code Lineup ................................................................................ 1040 Appendix G Package Dimensions ................................................................................. 1041 Rev. 5.00 Jan 10, 2006 page xxiv of xxiv Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2626 Group and H8S/2623 Group are series of microcomputers (MCUs) that integrate peripheral functions required for system configuration together with an H8S/2600 CPU employing an original Renesas architecture. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include a data transfer controller (DTC) bus master, ROM and RAM, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), controller area network (HCAN), A/D converter, D/A converter (H8S/2626 Group only), and I/O ports. The on-chip ROM is 256-kbyte flash memory (F-ZTAT™)* or 256-, 128-, or 64-kbyte mask ROM. The ROM is connected to the CPU by a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. The features of the H8S/2626 Group and H8S/2623 Group are shown in table 1.1. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Rev. 5.00 Jan 10, 2006 page 1 of 1042 REJ09B0275-0500 Section 1 Overview Table 1.1 Overview Item Specifications CPU • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum operating frequency: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ns 16 × 16-bit register-register multiply: 200 ns 16 × 16 + 42-bit multiply and accumulate: 200 ns 32 ÷ 16-bit register-register divide: 1000 ns • Instruction set suitable for high-speed operation  69 basic instructions  8/16/32-bit move/arithmetic and logic instructions  Unsigned/signed multiply and divide instructions  Multiply-and accumulate instruction  Powerful bit-manipulation instructions • Two CPU operating modes  Normal mode: 64-kbyte address space (Not available in the H8S/2626 Group or H8S/2623 Group)  Advanced mode: 16-Mbyte address space Bus controller PC break controller • Address space divided into 8 areas, with bus specifications settable independently for each area • Choice of 8-bit or 16-bit access space for each area • 2-state or 3-state access space can be designated for each area • Number of program wait states can be set for each area • Burst ROM directly connectable • External bus release function • Supports debugging functions by means of PC break interrupts • Two break channels Rev. 5.00 Jan 10, 2006 page 2 of 1042 REJ09B0275-0500 Section 1 Overview Item Specifications Data transfer controller (DTC) • Can be activated by internal interrupt or software • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc. • Request can be sent to CPU for interrupt that activated DTC • 6-channel 16-bit timer • Pulse input/output processing capability for up to 16 pins • Automatic 2-phase encoder count capability • Maximum 8-bit pulse output possible with TPU as time base • Output trigger selectable in 4-bit groups • Non-overlap margin can be set • Direct output or inverse output setting Watchdog timer (WDT), 2 channels (H8S/2626 Group) • Watchdog timer or interval timer selectable • Subclock operation possible (one channel only) Watchdog timer (WDT), 1 channel (H8S/2623 Group) • Watchdog timer or interval timer selectable Serial communication interface (SCI), 3 channels (SCI0 to SCI2) • Asynchronous mode or synchronous mode selectable • Multiprocessor communication function • Smart card interface function Controller area network (HCAN), 1 channel • CAN: Ver. 2.0B compliant • Buffer size: 15 transmit/receive buffers, one transmit-only buffer • Receive message filtering • Resolution: 10 bits • Input: 16 channels • 13.3 µs minimum conversion time (at 20 MHz operation) • Single or scan mode selectable • Sample-and-hold function • A/D conversion can be activated by external trigger or timer trigger 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG) A/D converter Rev. 5.00 Jan 10, 2006 page 3 of 1042 REJ09B0275-0500 Section 1 Overview Item Specifications D/A converter (H8S/2626 Group only) • Resolution: 8 bits • Output: 2 channels I/O ports (H8S/2626 Group) • 51 input/output pins, 17 input-only pins I/O ports (H8S/2623 Group) • 53 input/output pins, 17 input-only pins Memory • Flash memory or masked ROM • High-speed static RAM Interrupt controller Product Name ROM RAM H8S/2626, H8S/2623 256 kbytes 12 kbytes H8S/2625, H8S/2622 128 kbytes 8 kbytes H8S/2624, H8S/2621 64 kbytes 4 kbytes • Seven external interrupt pins (NMI, IRQ0 to IRQ5) • Internal interrupt sources H8S/2626: 48 H8S/2623: 47 Power-down state • Eight priority levels settable • Medium-speed mode • Sleep mode • Module stop mode • Software standby mode • Hardware standby mode • Subclock operation (H8S/2626 Group only) Rev. 5.00 Jan 10, 2006 page 4 of 1042 REJ09B0275-0500 Section 1 Overview Item Specifications Operating modes • Four MCU operating modes Mode CPU Operating Mode 4 Advanced External Data Bus On-Chip ROM Initial Width Max. Width On-chip ROM disabled expansion mode Disabled 16 bits 16 bits 5 On-chip ROM disabled expansion mode Disabled 8 bits 16 bits 6 On-chip ROM enabled expansion mode Enabled 8 bits 16 bits 7 Single-chip mode Enabled — — Description Clock pulse generator • Built-in PLL circuit (×1, ×2, ×4) • Input clock frequency: 2 to 20 MHz Package • 100-pin plastic QFP (FP-100B) Product lineup Model Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Package HD6432626 HD6432623 HD64F2626 HD64F2623 256 k/12 k FP-100B HD6432625 HD6432622 — 128 k/8 k FP-100B HD6432624 HD6432621 — 64 k/4 k FP-100B Rev. 5.00 Jan 10, 2006 page 5 of 1042 REJ09B0275-0500 Section 1 Overview 1.2 Internal Block Diagram Port A WDT × 1 channel Port B ROM (Mask ROM, flash memory) PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C Peripheral data bus PC break controller (2 channels) PA5 PA4 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 Port 9 Bus controller DTC Peripheral address bus PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Internal address bus Port E Internal data bus PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port D H8S/2600 CPU Interrupt controller Port F PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 PLL MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY RES WDTOVF NMI FWE* Clock pulse generator PVCC1 PVCC2 PVCC3 PVCC4 VCC VCC VSS VSS VSS VSS VSS Figures 1.1 and 1.2 show internal block diagrams of the H8S/2623 Group and H8S/2626 Group. P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8 RAM SCI × 3 channels HCAN × 1 channel TPU A/D converter PPG P47/ AN7 P46/ AN6 P45/ AN5 P44/ AN4 P43/ AN3 P42/ AN2 P41/ AN1 P40/ AN0 Port 4 HRxD HTxD Vref AVCC AVSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 Port 1 Note: * The FWE pin is used only in the flash memory version. Figure 1.1 Internal Block Diagram (H8S/2623 Group) Rev. 5.00 Jan 10, 2006 page 6 of 1042 REJ09B0275-0500 Port B WDT × 2 channels PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 Port C ROM (mask ROM or flash memory) PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 Port 9 PC break controller (2 channels) Peripheral address bus DTC Peripheral data bus Bus controller Internal address bus H8S/2600 CPU Port A PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 Port E Internal data bus PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port D Interrupt controller Port F PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 PLL MD2 MD1 MD0 OSC1 OSC2 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY RES WDTOVF NMI FWE* Clock pulse generator PVCC1 PVCC2 PVCC3 PVCC4 VCC VCC VSS VSS VSS VSS VSS Section 1 Overview P97/AN15/DA3 P96/AN14/DA2 P95/AN13 P94/AN12 P93 /AN11 P92 /AN10 P91 /AN9 P90 /AN8 RAM SCI × 3 channels HCAN × 1 channel TPU D/A converter PPG A/D converter P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port 4 HRxD HTxD Vref AVCC AVSS P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 Port 1 Note: * The FWE pin is provided in the flash memory version only. Figure 1.2 Internal Block Diagram (H8S/2626 Group) Rev. 5.00 Jan 10, 2006 page 7 of 1042 REJ09B0275-0500 Section 1 Overview 1.3 Pin Descriptions 1.3.1 Pin Arrangement 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Top view (FP-100B) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 PA4 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PVCC2 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 PD7/D15 PD6/D14 P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/A20 P11/PO9/TIOCB0/A21 P12/PO10/TIOCC0/TCLKA/A22 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF0/BREQ/IRQ2 PF1/BACK PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/PD PF6/AS PF7/φ FWE EXTAL VSS XTAL VCC STBY NMI RES PLLVCC PLLCAP PLLVSS MD2 MD1 VSS MD0 PVCC3 PA5 Figures 1.3 and 1.4 show pin arrangements of the H8S/2623 Group and H8S/2626 Group. Figure 1.3 Pin Arrangement (FP-100B: Top View) (H8S/2623 Group) Rev. 5.00 Jan 10, 2006 page 8 of 1042 REJ09B0275-0500 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Top view (FP-100B) OSC1 PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PVCC2 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5/SCK1/IRQ5 PC4/A4/RxD1 PC3/A3/TxD1 PC2/A2/SCK0/IRQ4 PC1/A1/RxD0 PC0/A0/TxD0 PD7/D15 PD6/D14 P13/PO11/TIOCD0/TCLKB/A23 P14/PO12/TIOCA1/IRQ0 P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/IRQ1 P17/PO15/TIOCB2/TCLKD VCC HTxD VSS HRxD PE0/D0 PE1/D1 PE2/D2 PE3/D3 PE4/D4 VSS PE5/D5 PVCC1 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14/DA2 P97/AN15/DA3 AVSS VSS WDTOVF PVCC4 P10/PO8/TIOCA0/A20 P11/PO9/TIOCB0/A21 P12/PO10/TIOCC0/TCLKA/A22 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/PD PF6/AS PF7/φ FWE EXTAL VSS XTAL VCC STBY NMI RES PLLVCC PLLCAP PLLVSS MD2 MD1 VSS MD0 PVCC3 OSC2 Section 1 Overview Figure 1.4 Pin Arrangement (FP-100B: Top View) (H8S/2626 Group) Rev. 5.00 Jan 10, 2006 page 9 of 1042 REJ09B0275-0500 Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Tables 1.2 and 1.3 show the pin functions in each of the operating modes of the H8S/2623 Group and H8S/2626 Group. Table 1.2 Pin Functions in Each Operating Mode Pin No. Pin Name FP-100B Mode 4 Mode 5 Mode 6 Mode 7 1 P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB 2 P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ IRQ0 IRQ0 IRQ0 IRQ0 3 P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ TCLKC TCLKC TCLKC TCLKC 4 P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ IRQ1 IRQ1 IRQ1 IRQ1 5 P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ TCLKD TCLKD TCLKD TCLKD 6 VCC VCC VCC VCC 7 HTxD HTxD HTxD HTxD 8 VSS VSS VSS VSS 9 HRxD HRxD HRxD HRxD 10 PE0/D0 PE0/D0 PE0/D0 PE0 11 PE1/D1 PE1/D1 PE1/D1 PE1 12 PE2/D2 PE2/D2 PE2/D2 PE2 13 PE3/D3 PE3/D3 PE3/D3 PE3 14 PE4/D4 PE4/D4 PE4/D4 PE4 15 VSS VSS VSS VSS 16 PE5/D5 PE5/D5 PE5/D5 PE5 17 PVCC1 PVCC1 PVCC1 PVCC1 18 PE6/D6 PE6/D6 PE6/D6 PE6 19 PE7/D7 PE7/D7 PE7/D7 PE7 20 D8 D8 D8 PD0 21 D9 D9 D9 PD1 22 D10 D10 D10 PD2 Rev. 5.00 Jan 10, 2006 page 10 of 1042 REJ09B0275-0500 Section 1 Overview Pin No. Pin Name FP-100B Mode 4 Mode 5 Mode 6 Mode 7 23 D11 D11 D11 PD3 24 D12 D12 D12 PD4 25 D13 D13 D13 PD5 26 D14 D14 D14 PD6 27 D15 D15 D15 PD7 28 A0 A0 PC0/A0/TxD0 PC0/TxD0 29 A1 A1 PC1/A1/RxD0 PC1/RxD0 30 A2 A2 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4 31 A3 A3 PC3/A3/TxD1 PC3/TxD1 32 A4 A4 PC4/A4/RxD1 PC4/RxD1 33 A5 A5 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5 34 A6 A6 PC6/A6 35 A7 A7 PC7/A7 PC7 36 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/TIOCA3 37 VSS VSS VSS VSS 38 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/TIOCB3 39 PVCC2 PVCC2 PVCC2 PVCC2 40 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/TIOCC3 41 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/TIOCD3 42 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/TIOCA4 43 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/TIOCB4 44 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/TIOCA5 45 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/TIOCB5 PC6 46 PA0/A16 PA0/A16 PA0/A16 PA0 47 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2 48 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2 49 PA3/A19/SCK2 PA3/A19/SCK2 PA3/A19/SCK2 PA3/SCK2 50 PA4 PA4 PA4 PA4 51 PA5 PA5 PA5 PA5 52 PVCC3 PVCC3 PVCC3 PVCC3 53 MD0 MD0 MD0 MD0 Rev. 5.00 Jan 10, 2006 page 11 of 1042 REJ09B0275-0500 Section 1 Overview Pin No. Pin Name FP-100B Mode 4 Mode 5 Mode 6 Mode 7 54 VSS VSS VSS VSS 55 MD1 MD1 MD1 MD1 56 MD2 MD2 MD2 MD2 57 PLLVSS PLLVSS PLLVSS PLLVSS 58 PLLCAP PLLCAP PLLCAP PLLCAP 59 PLLVCC PLLVCC PLLVCC PLLVCC 60 RES RES RES RES 61 NMI NMI NMI NMI 62 STBY STBY STBY STBY 63 VCC VCC VCC VCC 64 XTAL XTAL XTAL XTAL 65 VSS VSS VSS VSS 66 EXTAL EXTAL EXTAL EXTAL 67 FWE FWE FWE FWE 68 PF7/φ PF7/φ PF7/φ PF7/φ 69 AS AS AS PF6 70 RD RD RD PF5 71 HWR HWR HWR PF4 72 PF3/LWR/ADTRG/ IRQ3 PF3/LWR/ADTRG/ IRQ3 PF3/LWR/ADTRG/ IRQ3 PF3/ADTRG/ IRQ3 73 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2 74 PF1/BACK PF1/BACK PF1/BACK PF1 75 PF0/BREQ/IRQ2 PF0/BREQ/IIRQ2 PF0/BREQ/IIRQ2 PF0/IRQ2 76 AVCC AVCC AVCC AVCC 77 Vref Vref Vref Vref 78 P40/AN0 P40/AN0 P40/AN0 P40/AN0 79 P41/AN1 P41/AN1 P41/AN1 P41/AN1 80 P42/AN2 P42/AN2 P42/AN2 P42/AN2 81 P43/AN3 P43/AN3 P43/AN3 P43/AN3 82 P44/AN4 P44/AN4 P44/AN4 P44/AN4 83 P45/AN5 P45/AN5 P45/AN5 P45/AN5 Rev. 5.00 Jan 10, 2006 page 12 of 1042 REJ09B0275-0500 Section 1 Overview Pin No. Pin Name FP-100B Mode 4 Mode 5 Mode 6 Mode 7 84 P46/AN6 P46/AN6 P46/AN6 P46/AN6 85 P47/AN7 P47/AN7 P47/AN7 P47/AN7 86 P90/AN8 P90/AN8 P90/AN8 P90/AN8 87 P91/AN9 P91/AN9 P91/AN9 P91/AN9 88 P92/AN10 P92/AN10 P92/AN10 P92/AN10 89 P93/AN11 P93/AN11 P93/AN11 P93/AN11 90 P94/AN12 P94/AN12 P94/AN12 P94/AN12 91 P95/AN13 P95/AN13 P95/AN13 P95/AN13 92 P96/AN14 P96/AN14 P96/AN14 P96/AN14 93 P97/AN15 P97/AN15 P97/AN15 P97/AN15 94 AVSS AVSS AVSS AVSS 95 VSS VSS VSS VSS 96 WDTOVF WDTOVF WDTOVF WDTOVF 97 PVCC4 PVCC4 PVCC4 PVCC4 98 P10/PO8/TIOCA0/ A20 P10/PO8/TIOCA0/ A20 P10/PO8/TIOCA0/ A20 P10/PO8/TIOCA0 99 P11/PO9/TIOCB0/ A21 P11/PO9/TIOCB0/ A21 P11/PO9/TIOCB0/ A21 P11/PO9/TIOCB0 100 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA Note: NC pins should be connected to VSS or left open. Rev. 5.00 Jan 10, 2006 page 13 of 1042 REJ09B0275-0500 Section 1 Overview Table 1.3 Pin Functions in Each Operating Mode Pin No. Pin Name FP-100B Mode 4 Mode 5 1 P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ P13/PO11/TIOCD0/ TCLKB/A23 TCLKB/A23 TCLKB/A23 TCLKB 2 P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ P14/PO12/TIOCA1/ IRQ0 IRQ0 IRQ0 IRQ0 3 P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ P15/PO13/TIOCB1/ TCLKC TCLKC TCLKC TCLKC 4 P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ P16/PO14/TIOCA2/ IRQ1 IRQ1 IRQ1 IRQ1 5 P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ P17/PO15/TIOCB2/ TCLKD TCLKD TCLKD TCLKD 6 VCC VCC VCC VCC 7 HTxD HTxD HTxD HTxD 8 VSS VSS VSS VSS 9 HRxD HRxD HRxD HRxD 10 PE0/D0 PE0/D0 PE0/D0 PE0 11 PE1/D1 PE1/D1 PE1/D1 PE1 12 PE2/D2 PE2/D2 PE2/D2 PE2 13 PE3/D3 PE3/D3 PE3/D3 PE3 14 PE4/D4 PE4/D4 PE4/D4 PE4 15 VSS VSS VSS VSS 16 PE5/D5 PE5/D5 PE5/D5 PE5 17 PVCC1 PVCC1 PVCC1 PVCC1 18 PE6/D6 PE6/D6 PE6/D6 PE6 19 PE7/D7 PE7/D7 PE7/D7 PE7 20 D8 D8 D8 PD0 21 D9 D9 D9 PD1 22 D10 D10 D10 PD2 23 D11 D11 D11 PD3 24 D12 D12 D12 PD4 25 D13 D13 D13 PD5 26 D14 D14 D14 PD6 Rev. 5.00 Jan 10, 2006 page 14 of 1042 REJ09B0275-0500 Mode 6 Mode 7 Section 1 Overview Pin No. Pin Name FP-100B Mode 4 Mode 5 Mode 6 Mode 7 27 D15 D15 D15 PD7 28 A0 A0 PC0/A0/TxD0 PC0/TxD0 29 A1 A1 PC1/A1/RxD0 PC1/RxD0 30 A2 A2 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4 31 A3 A3 PC3/A3/TxD1 PC3/TxD1 32 A4 A4 PC4/A4/RxD1 PC4/RxD1 33 A5 A5 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5 34 A6 A6 PC6/A6 PC6 35 A7 A7 PC7/A7 PC7 36 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/TIOCA3 37 VSS VSS VSS VSS 38 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/TIOCB3 39 PVCC2 PVCC2 PVCC2 PVCC2 40 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/TIOCC3 41 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/TIOCD3 42 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/TIOCA4 43 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/TIOCB4 44 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/TIOCA5 45 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/TIOCB5 46 PA0/A16 PA0/A16 PA0/A16 PA0 47 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2 48 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2 49 PA3/A19/SCK2 PA3/A19/SCK2 PA3/A19/SCK2 PA3/SCK2 50 OSC1 OSC1 OSC1 OSC1 51 OSC2 OSC2 OSC2 OSC2 52 PVCC3 PVCC3 PVCC3 PVCC3 53 MD0 MD0 MD0 MD0 54 VSS VSS VSS VSS 55 MD1 MD1 MD1 MD1 56 MD2 MD2 MD2 MD2 57 PLLVSS PLLVSS PLLVSS PLLVSS Rev. 5.00 Jan 10, 2006 page 15 of 1042 REJ09B0275-0500 Section 1 Overview Pin No. Pin Name FP-100B Mode 4 Mode 5 Mode 6 Mode 7 58 PLLCAP PLLCAP PLLCAP PLLCAP 59 PLLVCC PLLVCC PLLVCC PLLVCC 60 RES RES RES RES 61 NMI NMI NMI NMI 62 STBY STBY STBY STBY 63 VCC VCC VCC VCC 64 XTAL XTAL XTAL XTAL 65 VSS VSS VSS VSS 66 EXTAL EXTAL EXTAL EXTAL 67 FWE FWE FWE FWE 68 PF7/φ PF7/φ PF7/φ PF7/φ 69 AS AS AS PF6 70 RD RD RD PF5 71 HWR HWR HWR PF4 72 PF3/LWR/ADTRG/ IRQ3 PF3/LWR/ADTRG/ IRQ3 PF3/LWR/ADTRG/ IRQ3 PF3/ADTRG/ IRQ3 73 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2 74 PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BUZZ 75 PF0/BREQ/IRQ2 PF0/BREQ/IIRQ2 PF0/BREQ/IIRQ2 PF0/IRQ2 76 AVCC AVCC AVCC AVCC 77 Vref Vref Vref Vref 78 P40/AN0 P40/AN0 P40/AN0 P40/AN0 79 P41/AN1 P41/AN1 P41/AN1 P41/AN1 80 P42/AN2 P42/AN2 P42/AN2 P42/AN2 81 P43/AN3 P43/AN3 P43/AN3 P43/AN3 82 P44/AN4 P44/AN4 P44/AN4 P44/AN4 83 P45/AN5 P45/AN5 P45/AN5 P45/AN5 84 P46/AN6 P46/AN6 P46/AN6 P46/AN6 85 P47/AN7 P47/AN7 P47/AN7 P47/AN7 86 P90/AN8 P90/AN8 P90/AN8 P90/AN8 87 P91/AN9 P91/AN9 P91/AN9 P91/AN9 Rev. 5.00 Jan 10, 2006 page 16 of 1042 REJ09B0275-0500 Section 1 Overview Pin No. Pin Name FP-100B Mode 4 Mode 5 Mode 6 Mode 7 88 P92/AN10 P92/AN10 P92/AN10 P92/AN10 89 P93/AN11 P93/AN11 P93/AN11 P93/AN11 90 P94/AN12 P94/AN12 P94/AN12 P94/AN12 91 P95/AN13 P95/AN13 P95/AN13 P95/AN13 92 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2 93 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3 94 AVSS AVSS AVSS AVSS 95 VSS VSS VSS VSS 96 WDTOVF WDTOVF WDTOVF WDTOVF 97 PVCC4 PVCC4 PVCC4 PVCC4 98 P10/PO8/TIOCA0/ A20 P10/PO8/TIOCA0/ A20 P10/PO8/TIOCA0/ A20 P10/PO8/TIOCA0 99 P11/PO9/TIOCB0/ A21 P11/PO9/TIOCB0/ A21 P11/PO9/TIOCB0/ A21 P11/PO9/TIOCB0 100 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ TCLKA/A22 TCLKA/A22 TCLKA/A22 TCLKA Note: NC pins should be connected to VSS or left open. Rev. 5.00 Jan 10, 2006 page 17 of 1042 REJ09B0275-0500 Section 1 Overview 1.3.3 Pin Functions Table 1.4 summarizes the pin functions. Table 1.4 Pin Functions Type Symbol I/O Pin Name Function Power supply VCC Input Power supply For connection to the power supply. Connect all VCC pins to the system power supply. PVCC1 Input PVCC2 Input Port power supply Port power supply pins. Connect all Port power supply these pins to the same power supply. PVCC3 Input Port power supply PVCC4 Input Port power supply VSS Input Ground PLLVCC Input PLL power supply On-chip PLL oscillator power supply PLLVSS Input PLL ground On-chip PLL oscillator ground PLLCAP Input PLL capacitance On-chip PLL oscillator external capacitance pin XTAL Input Crystal For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 20, Clock Pulse Generator. EXTAL Input External clock For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 20, Clock Pulse Generator. Clock For connection to the power supply (0 V). Connect all VSS pins to the system power supply (0 V). OSC1* 1 Input Subclock For connection to a recommended 32.768 kHz resonator. For examples of crystal resonator connection, see section 20, Clock Pulse Generator. OSC2* 1 Input Subclock For connection to a recommended 32.768 kHz resonator. For examples of crystal resonator connection, see section 20, Clock Pulse Generator. Output System clock Supplies the system clock to external devices. φ Rev. 5.00 Jan 10, 2006 page 18 of 1042 REJ09B0275-0500 Section 1 Overview Type Symbol I/O Pin Name Function Operating mode control MD2 to MD0 Input Mode pins These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. Inputs at these pins should not be changed during operation. MD2 MD1 MD0 Operating Mode 0 0 0 — 1 — 0 — 1 — 0 Mode 4 1 Mode 5 0 Mode 6 1 Mode 7 1 1 0 1 System control Interrupts Address bus RES Input Reset input When this pin is driven low, the chip is reset. STBY Input Standby When this pin is driven low, a transition is made to hardware standby mode. BREQ Input Bus request Used by an external bus master to issue a bus request to the chip. BREQO Output Bus request output External bus request signal used when an internal bus master accesses external space in the external busreleased state. BACK Output Bus request acknowledge Indicates that the bus has been released to an external bus master. FWE Input Flash write enable Pin for use by flash memory NMI Input Nonmaskable interrupt Requests a nonmaskable interrupt. If this pin is not used, it should be fixed high. IRQ5 to IRQ0 Input Interrupt request 5 to 0 These pins request a maskable interrupt. A23 to A0 Output Address bus These pins output address signals. Rev. 5.00 Jan 10, 2006 page 19 of 1042 REJ09B0275-0500 Section 1 Overview Type Symbol I/O Pin Name Function Data bus D15 to D0 Input/ output Data bus Bidirectional data bus Bus control AS Output Address strobe Goes low to indicate valid address output on the address bus. RD Output Read Goes low to indicate reading from the external address space. HWR Output High write Strobe signal indicating writing to the external address space; indicates valid data on the upper data bus (D15 to D8). LWR Output Low write Strobe signal indicating writing to the external address space; indicates valid data on the lower data bus (D7 to D0). WAIT Input Wait Requests insertion of wait states in bus cycles during access to 3-state external address space. TCLKD to TCLKA Input Clock input D to A These pins input an external clock. TIOCA0, TIOCB0, TIOCC0, TIOCD0 Input/ output Input capture/ output compare match A0 to D0 The TGR0A to TGR0D input capture input/output compare output/PWM output pins TIOCA1, TIOCB1 Input/ output Input capture/ output compare match A1 and B1 The TGR1A and TGR1B input capture input/output compare output/PWM output pins TIOCA2, TIOCB2 Input/ output Input capture/ output compare match A2 and B2 The TGR2A and TGR2B input capture input/output compare output/PWM output pins TIOCA3, TIOCB3, TIOCC3, TIOCD3 Input/ output Input capture/ output compare match A3 to D3 The TGR3A to TGR3D input capture input/output compare output/PWM output pins TIOCA4, TIOCB4 Input/ output Input capture/ output compare match A4 and B4 The TGR4A and TGR4B input capture input/output compare output/PWM output pins TIOCA5, TIOCB5 Input/ output Input capture/ output compare match A5 and B5 The TGR5A and TGR5B input capture input/output compare output/PWM output pins 16-bit timerpulse unit (TPU) Rev. 5.00 Jan 10, 2006 page 20 of 1042 REJ09B0275-0500 Section 1 Overview Type Symbol Programmable PO15 to pulse PO8 generator (PPG) I/O Pin Name Function Output Pulse output 15 to 8 Pulse output pins Watchdog timer (WDT) WDTOVF Output Watchdog timer overflow The counter overflow signal output pin in watchdog timer mode Serial communication interface (SCI)/ smart card interface TxD2, TxD1, TxD0 Output Transmit data Data output pins RxD2, RxD1, RxD0 Input Receive data Data input pins SCK2, SCK1, SCK0 Input/ output Serial clock Clock input/output pins HTxD Output HCAN transmit data The CAN bus transmission pin HRxD Input HCAN receive data The CAN bus reception pin AN15 to AN0 Input Analog 15 to 0 Analog input pins ADTRG Input A/D conversion external trigger input Pin for input of an external trigger to start A/D conversion D/A converter pin DA3, DA2 Output Analog output D/A converter analog output pins A/D converter/ D/A converter AVCC Input Analog power supply The power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not used, connect this pin to the system power supply (+5 V). AVSS Input Analog ground The ground pin and reference voltage for the A/D and D/A converters. Connect this pin to the system power supply (0 V). Vref Input Analog reference power supply The reference voltage input pin for the A/D and D/A converters. When the A/D and D/A converters are not used, connect this pin to the system power supply (+5 V). Controller area network (HCAN) A/D converter Rev. 5.00 Jan 10, 2006 page 21 of 1042 REJ09B0275-0500 Section 1 Overview Type Symbol I/O Pin Name Function I/O ports P17 to P10 Input/ output Port 1 Eight input/output pins. Input or output can be selected for each pin in the port 1 data direction register (P1DDR). P47 to P40 Input Port 4 Eight input pins P97 to P90 Input Port 9 Eight input pins PA5 to 2 PA0* Input/ output Port A Six input/output pins. Input or output can be selected for each pin in the port A data direction register (PADDR). PB7 to PB0 Input/ output Port B Eight input/output pins. Input or output can be selected for each pin in the port B data direction register (PBDDR). PC7 to PC0 Input/ output Port C Eight input/output pins. Input or output can be selected for each pin in the port C data direction register (PCDDR). PD7 to PD0 Input/ output Port D Eight input/output pins. Input or output can be selected for each pin in the port D data direction register (PDDDR). PE7 to PE0 Input/ output Port E Eight input/output pins. Input or output can be selected for each pin in the port E data direction register (PEDDR). PF7 to PF0 Input/ output Port F Eight input/output pins. Input or output can be selected for each pin in the port F data direction register (PFDDR). Notes: 1. Applies to the H8S/2626 Group only. 2. PA3 to PA0 in the H8S/2626 Group. Rev. 5.00 Jan 10, 2006 page 22 of 1042 REJ09B0275-0500 Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2600 CPU has the following features. • Upward-compatible with H8/300 and H8/300H CPUs  Can execute H8/300 and H8/300H object programs • General-register architecture  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • Sixty-nine basic instructions  8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions  Multiply-and-accumulate instruction • Eight addressing modes  Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]  Immediate [#xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8,PC) or @(d:16,PC)]  Memory indirect [@@aa:8] • 16-Mbyte address space  Program: 16 Mbytes  Data: 16 Mbytes (4 Gbytes architecturally) Rev. 5.00 Jan 10, 2006 page 23 of 1042 REJ09B0275-0500 Section 2 CPU • High-speed operation  All frequently-used instructions execute in one or two states  Maximum clock rate: 20 MHz  8/16/32-bit register-register add/subtract: 50 ns  8 × 8-bit register-register multiply: 150 ns  16 ÷ 8-bit register-register divide: 600 ns  16 × 16-bit register-register multiply: 200 ns  32 ÷ 16-bit register-register divide: 1000 ns • Two CPU operating modes  Normal mode*  Advanced mode Note: * Not available in the H8S/2626 Group or H8S/2623 Group. • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. • Number of execution states The number of execution states of the MULXU and MULXS instructions is different in each CPU. Execution States Instruction MULXU MULXS Mnemonic H8S/2600 H8S/2000 MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 Rev. 5.00 Jan 10, 2006 page 24 of 1042 REJ09B0275-0500 Section 2 CPU In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space  Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2626 Group or H8S/2623 Group. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  Signed multiply and divide instructions have been added.  A multiply-and-accumulate instruction has been added.  Two-bit shift instructions have been added.  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register  One 8-bit and two 32-bit control registers have been added. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced.  A multiply-and-accumulate instruction has been added.  Two-bit shift instructions have been added. Rev. 5.00 Jan 10, 2006 page 25 of 1042 REJ09B0275-0500 Section 2 CPU  Instructions for saving and restoring multiple registers have been added.  A test and set instruction has been added. • Higher speed  Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Normal mode* Maximum 64 kbytes, program and data areas combined CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Figure 2.1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2626 Group or H8S/2623 Group) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) Rev. 5.00 Jan 10, 2006 page 26 of 1042 REJ09B0275-0500 Section 2 CPU or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2.2). The exception vector table differs depending on the microcontroller. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector Manual reset exception vector* (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Rev. 5.00 Jan 10, 2006 page 27 of 1042 REJ09B0275-0500 Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) EXR*1 Reserved*1 *3 CCR CCR*3 SP *2 (SP ) PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. Rev. 5.00 Jan 10, 2006 page 28 of 1042 REJ09B0275-0500 Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector* H'00000007 H'00000008 Exception vector table H'0000000B (Reserved for system use) H'0000000C H'00000010 Reserved Exception vector 1 Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as Rev. 5.00 Jan 10, 2006 page 29 of 1042 REJ09B0275-0500 Section 2 CPU H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. EXR*1 Reserved*1 *3 CCR SP SP Reserved PC (24 bits) (a) Subroutine Branch *2 (SP ) PC (24 bits) (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.5 Stack Structure in Advanced Mode Rev. 5.00 Jan 10, 2006 page 30 of 1042 REJ09B0275-0500 Section 2 CPU 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2626 Group or H8S/2623 Group H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Figure 2.6 Memory Map Rev. 5.00 Jan 10, 2006 page 31 of 1042 REJ09B0275-0500 Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 07 07 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 EXR T — — — — I2 I1 I0 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C 63 MAC 32 41 MACH Sign extension MACL 31 Legend: SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Note: * Cannot be used as an interrupt mask bit in the H8S/2626 Group or H8S/2623 Group. Figure 2.7 CPU Registers Rev. 5.00 Jan 10, 2006 page 32 of 1042 REJ09B0275-0500 Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. • Address registers • 32-bit registers • 16-bit registers • 8-bit registers E registers (extended registers) (E0 to E7) RH registers (R0H to R7H) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Rev. 5.00 Jan 10, 2006 page 33 of 1042 REJ09B0275-0500 Section 2 CPU Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3—Reserved: They are always read as 1. Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. Rev. 5.00 Jan 10, 2006 page 34 of 1042 REJ09B0275-0500 Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, refer to section 5, Interrupt Controller. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction List. Rev. 5.00 Jan 10, 2006 page 35 of 1042 REJ09B0275-0500 Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 5.00 Jan 10, 2006 page 36 of 1042 REJ09B0275-0500 Section 2 CPU 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 7 6 5 4 3 2 1 0 Don’t care Don’t care 7 0 7 6 5 4 3 2 1 0 1-bit data 4-bit BCD data RnL RnH 4 3 7 Upper 4-bit BCD data 0 Lower Don’t care RnL Byte data RnH 4 3 7 Upper Don’t care 7 0 Lower 0 Don’t care MSB Byte data LSB RnL 7 0 Don’t care MSB LSB Figure 2.10 General Register Data Formats Rev. 5.00 Jan 10, 2006 page 37 of 1042 REJ09B0275-0500 Section 2 CPU Data Type Register Number Word data Rn Word data En Data Format 15 0 MSB 15 0 MSB Longword data LSB ERn 31 MSB LSB 16 15 En 0 Rn Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.10 General Register Data Formats (cont) Rev. 5.00 Jan 10, 2006 page 38 of 1042 REJ09B0275-0500 LSB Section 2 CPU 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Data Format Address 7 1-bit data Address L Byte data Address L MSB Word data 7 0 6 5 4 2 1 0 LSB Address 2M MSB Address 2M + 1 Longword data 3 LSB Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2.11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 5.00 Jan 10, 2006 page 39 of 1042 REJ09B0275-0500 Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer MOV 1 1 POP* , PUSH* BWL 5 Arithmetic operations WL LDM, STM 3 3 MOVFPE* , MOVTPE* L B ADD, SUB, CMP, NEG BWL ADDX, SUBX, DAA, DAS B INC, DEC BWL 23 ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS BW EXTU, EXTS 4 TAS* WL B MAC, LDMAC, STMAC, CLRMAC — Logic operations AND, OR, XOR, NOT BWL 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8 Bit manipulation B 14 Branch BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR 2 Bcc* , JMP, BSR, JSR, RTS — 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9 Block data transfer EEPMOV — 1 Total: 69 B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Not available in the H8S/2626 Group or H8S/2623 Group. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Legend: Rev. 5.00 Jan 10, 2006 page 40 of 1042 REJ09B0275-0500 Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes @aa:24 @aa:32 BWL BWL B BWL — BWL — — — — — — — — — — — — — — WL LDM, STM — — — — — — — — — — — — — L MOVEPE*1, MOVTPE*1 — — — — — — — B — — — — — — Arithmetic operations ADD, CMP BWL BWL — — — — — — — — — — — — WL BWL — — — — — — — — — — — — ADDX, SUBX B B — — — — — — — — — — — — ADDS, SUBS — L — — — — — — — — — — — — INC, DEC — BWL — — — — — — — — — — — — DAA, DAS — B — — — — — — — — — — — — MULXU, DIVXU — BW — — — — — — — — — — — — MULXS, DIVXS — BW — — — — — — — — — — — — NEG — BWL — — — — — — — — — — — — EXTU, EXTS — WL — — — — — — — — — — — — TAS*2 — — B — — — — — — — — — — — MAC — — — — — — — — — — — — — CLRMAC — — — — — — — — — — — — — SUB LDMAC, STMAC — @–ERn/@ERn+ BWL — @@aa:8 @(d:32,ERn) BWL — @(d:16,PC) @(d:16,ERn) BWL — MOV @(d:8,PC) @ERn Data transfer Instruction @aa:16 Rn BWL POP, PUSH Function @aa:8 #xx Addressing Modes — L — — — — — — — — — — — — BWL BWL — — — — — — — — — — — — — BWL — — — — — — — — — — — — Shift — BWL — — — — — — — — — — — — Bit manipulation — B B — — — B B — B — — — — Branch Bcc, BSR — — — — — — — — — — — — JMP, JSR — — — — — — — — RTS — — — — — — — — TRAPA — — — — — — — RTE — — — — — — — SLEEP — — — — — — LDC B B W W W STC — B W W ANDC, ORC, XORC B — — NOP — — Block data transfer — — Logic operations System control Legend: B: W: L: Notes: 1. 2. AND, OR, XOR NOT — — — — — — — — — — — — — — — — — — — — — — — — — — — — W — W — W — — — W W — W — W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BW Byte Word Longword Not available in the H8S/2626 Group or H8S/2623 Group. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 5.00 Jan 10, 2006 page 41 of 1042 REJ09B0275-0500 Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rs General register (destination)* General register (source)* Rn General register* Rd ERn General register (32-bit register) MAC Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Move ¬ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 5.00 Jan 10, 2006 page 42 of 1042 REJ09B0275-0500 Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Size* Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead) 1 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2626 Group or H8S/2623 Group. MOVTPE B Cannot be used in the H8S/2626 Group or H8S/2623 Group. POP W/L @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn → @–SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP. LDM L @SP+ → Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) → @–SP Pushes two or more general registers onto the stack. Rev. 5.00 Jan 10, 2006 page 43 of 1042 REJ09B0275-0500 Section 2 CPU Type Instruction Size* Function Arithmetic operations ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd ADDX SUBX B INC DEC B/W/L ADDS SUBS L DAA DAS B MULXU B/W 1 Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd ± 1 → Rd, Rd ± 2 → Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust → Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd × Rs → Rd Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. MULXS B/W Rd × Rs → Rd Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits. DIVXU B/W Rd ÷ Rs → Rd Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. Rev. 5.00 Jan 10, 2006 page 44 of 1042 REJ09B0275-0500 Section 2 CPU Type Instruction Size* Function Arithmetic operations DIVXS B/W Rd ÷ Rs → Rd 1 Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 – Rd → Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) → Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS TAS W/L Rd (sign extension) → Rd B Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. 2 @ERd – 0, 1 → ( of @ERd)* Tests memory contents, and sets the most significant bit (bit 7) to 1. MAC — (EAs) × (EAd) + MAC → MAC Performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. The following operations can be performed: 16 bits × 16 bits + 32 bits → 32 bits, saturating 16 bits × 16 bits + 42 bits → 42 bits, non-saturating CLRMAC — 0 → MAC Clears the multiply-accumulate register to zero. LDMAC STMAC L Rs → MAC, MAC → Rd Transfers data between a general register and a multiply-accumulate register. Rev. 5.00 Jan 10, 2006 page 45 of 1042 REJ09B0275-0500 Section 2 CPU Type Instruction Size* Function Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd 1 Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L ¬ (Rd) → (Rd) Takes the one's complement of general register contents. Shift operations SHAL SHAR B/W/L SHLL SHLR B/W/L ROTL ROTR B/W/L ROTXL ROTXR B/W/L Rd (shift) → Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) → Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) → Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rev. 5.00 Jan 10, 2006 page 46 of 1042 REJ09B0275-0500 Rd (rotate) → Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. Section 2 CPU Type Instruction Size* Function Bitmanipulation instructions BSET B 1 → ( of ) 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ ( of ) → ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ¬ ( of ) → Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ∧ ( of ) → C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C ∧ ¬ ( of ) → C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ∨ ( of ) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C ∨ ¬ ( of ) → C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Rev. 5.00 Jan 10, 2006 page 47 of 1042 REJ09B0275-0500 Section 2 CPU Type Instruction Size* Function Bitmanipulation instructions BXOR B C ⊕ ( of ) → C 1 Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) → C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ¬ ( of ) → C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C → ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B ¬ C → ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Rev. 5.00 Jan 10, 2006 page 48 of 1042 REJ09B0275-0500 Section 2 CPU Type Instruction Size* Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. 1 Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High C∨Z=0 BLS Low or same C∨Z=1 BCC(BHS) Carry clear (high or same) C=0 BCS(BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal N⊕V=0 BLT Less than N⊕V=1 BGT Greater than Z∨(N ⊕ V) = 0 BLE Less or equal Z∨(N ⊕ V) = 1 JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine Rev. 5.00 Jan 10, 2006 page 49 of 1042 REJ09B0275-0500 Section 2 CPU Type Instruction Size* Function System control instructions TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. 1 SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR → (EAd), EXR → (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP — PC + 2 → PC Only increments the program counter. Rev. 5.00 Jan 10, 2006 page 50 of 1042 REJ09B0275-0500 Section 2 CPU Type Instruction Size* Function Block data transfer instruction EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; 1 Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.4 Basic Instruction Formats The H8S/2626 Group and H8S/2623 Group instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. Rev. 5.00 Jan 10, 2006 page 51 of 1042 REJ09B0275-0500 Section 2 CPU Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.12 Instruction Formats (Examples) Rev. 5.00 Jan 10, 2006 page 52 of 1042 REJ09B0275-0500 Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.4 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 (1) Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). Rev. 5.00 Jan 10, 2006 page 53 of 1042 REJ09B0275-0500 Section 2 CPU (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.5 indicates the accessible absolute address ranges. Rev. 5.00 Jan 10, 2006 page 54 of 1042 REJ09B0275-0500 Section 2 CPU Table 2.5 Absolute Address Access Ranges Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF Absolute Address Data address 32 bits (@aa:32) Program instruction address Note: * H'000000 to H'FFFFFF 24 bits (@aa:24) Not available in the H8S/2626 Group or H8S/2623 Group. (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode* the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Rev. 5.00 Jan 10, 2006 page 55 of 1042 REJ09B0275-0500 Section 2 CPU Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Specified by @aa:8 Branch address Reserved Specified by @aa:8 Branch address (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: * Cannot be set in the H8S/2626 Group or H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 56 of 1042 REJ09B0275-0500 4 3 rm rn r r disp r op r • Register indirect with pre-decrement @–ERn op Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ op Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) op Register indirect (@ERn) op Register direct (Rn) Addressing Mode and Instruction Format disp 1 2 4 0 1, 2, or 4 General register contents Byte Word Longword 0 0 0 0 1, 2, or 4 General register contents Sign extension General register contents General register contents Operand Size Value added 31 31 31 31 31 Effective Address Calculation 24 23 24 23 24 23 24 23 Don’t care 31 Don’t care 31 Don’t care 31 Don’t care 31 Operand is general register contents. Effective Address (EA) 0 0 0 0 Table 2.6 2 1 No. Section 2 CPU Effective Address Calculation Rev. 5.00 Jan 10, 2006 page 57 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 58 of 1042 REJ09B0275-0500 6 op op abs abs abs op IMM Immediate #xx:8/#xx:16/#xx:32 @aa:32 op @aa:24 @aa:16 op abs Absolute address 5 @aa:8 Addressing Mode and Instruction Format No. Effective Address Calculation 24 23 24 23 24 23 24 23 87 16 15 Sign extension H'FFFF Operand is immediate data. Don’t care 31 Don’t care 31 Don’t care 31 Don’t care 31 Effective Address (EA) 0 0 0 0 Section 2 CPU abs op abs • Advanced mode op • Normal mode* Memory indirect @@aa:8 op @(d:8, PC)/@(d:16, PC) Program-counter relative disp Addressing Mode and Instruction Format 31 31 31 87 abs 87 abs Memory contents 15 Memory contents H'000000 H'000000 disp PC contents Sign extension 23 23 Effective Address Calculation Note: * Not available in the H8S/2626 Group or H8S/2623 Group. 8 7 No. 0 0 0 0 0 0 24 23 24 23 24 23 Don’t care 31 Don’t care 31 Don’t care 31 H'00 16 15 Effective Address (EA) 0 0 0 Section 2 CPU Rev. 5.00 Jan 10, 2006 page 59 of 1042 REJ09B0275-0500 Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in the H8S/2623 Group, but are available in the H8S/2626 Group. Figure 2.14 Processing States Rev. 5.00 Jan 10, 2006 page 60 of 1042 REJ09B0275-0500 Section 2 CPU End of bus request Bus request Program execution state SLEEP instruction with SSBY = 0 ha nd lin g d o ha f ex nd ce lin pti g on Re qu es tf or ex ce pt ion s bu t of est es d u qu En req re s Bu Bus-released state Sleep mode upt req SLEEP instruction with SSBY = 1 En rr Inte t ues Exception handling state External interrupt request Software standby mode RES= High STBY= High, RES= Low Reset state*1 Hardware standby mode*2 Reset state Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode in the H8S/2626 Group. See section 21B, Power-Down Modes [H8S/2626 Group]. Figure 2.15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12, Watchdog Timer. Rev. 5.00 Jan 10, 2006 page 61 of 1042 REJ09B0275-0500 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.7 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Trace End of instruction execution or end of exception-handling 1 sequence* When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence Interrupt End of instruction execution or end of exception-handling 2 sequence* When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Trap instruction When TRAPA instruction is executed Exception handling starts when a trap (TRAPA) instruction is 3 executed* Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. Rev. 5.00 Jan 10, 2006 page 62 of 1042 REJ09B0275-0500 Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES pin goes high again, reset exception handling starts. The CPU enters the reset state when the RES is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2.16 shows the stack after exception handling ends. Rev. 5.00 Jan 10, 2006 page 63 of 1042 REJ09B0275-0500 Section 2 CPU Normal mode*2 SP SP EXR Reserved*1 CCR CCR*1 CCR CCR*1 PC (16 bits) PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP EXR Reserved*1 CCR CCR PC (24 bits) PC (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: 1. Ignored when returning. 2. Not available in the H8S/2626 Group or H8S/2623 Group. Figure 2.16 Stack Structure after Exception Handling (Examples) Rev. 5.00 Jan 10, 2006 page 64 of 1042 REJ09B0275-0500 Section 2 CPU 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU are data transfer controller (DTC). For further details, refer to section 7, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode*, and watch mode*. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode*. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode*, subsleep mode*, and watch mode* are power-down states using subclock input. For details, refer to section 21B, Power-Down Modes [H8S/2626 Group]. Note: * Supported only in the H8S/2626 Group; not available in the H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 65 of 1042 REJ09B0275-0500 Section 2 CPU 2.9 Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows the pin states. Bus cycle T1 φ Internal address bus Read access Address Internal read signal Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 On-Chip Memory Access Cycle Rev. 5.00 Jan 10, 2006 page 66 of 1042 REJ09B0275-0500 Section 2 CPU Bus cycle T1 φ Address bus Retained AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.18 Pin States during On-Chip Memory Access Rev. 5.00 Jan 10, 2006 page 67 of 1042 REJ09B0275-0500 Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the access timing for the on-chip supporting modules. Figure 2.20 shows the pin states. Bus cycle T1 T2 φ Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.19 On-Chip Supporting Module Access Cycle Rev. 5.00 Jan 10, 2006 page 68 of 1042 REJ09B0275-0500 Section 2 CPU Bus cycle T1 T2 φ Address bus Retained AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.20 Pin States during On-Chip Supporting Module Access Cycle Rev. 5.00 Jan 10, 2006 page 69 of 1042 REJ09B0275-0500 Section 2 CPU 2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access timing is shown in figures 2.21 and 2.22, and the pin states in figure 2.23. Bus cycle T1 T2 T3 T4 φ Internal address bus Address HCAN read signal Read Internal data bus Read data HCAN write signal Write Internal data bus Write data Figure 2.21 On-Chip HCAN Module Access Cycle (No Wait State) Rev. 5.00 Jan 10, 2006 page 70 of 1042 REJ09B0275-0500 Section 2 CPU Bus cycle T2 T1 T3 Tw Tw T4 φ Internal address bus Address HCAN read signal Read Internal data bus Read data HCAN write signal Write Internal data bus Write data Figure 2.22 On-Chip HCAN Module Access Cycle (Wait States Inserted) Bus cycle T1 T2 T3 T4 φ Address bus Retained AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.23 Pin States in On-Chip HCAN Module Access Rev. 5.00 Jan 10, 2006 page 71 of 1042 REJ09B0275-0500 Section 2 CPU 2.9.5 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 7, Bus Controller. 2.10 Usage Note 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. Rev. 5.00 Jan 10, 2006 page 72 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2626 Group and H8S/2623 Group have four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection External Data Bus MCU CPU Operating Operating MD2 MD1 MD0 Mode Description Mode 0* 1* 0 2* 0 1 3* — 1 — — Initial Width — — Max. Width 0 1 4 1 0 5 0 1 6 1 7 Note: 0 On-Chip ROM * Advanced On-chip ROM disabled, Disabled expanded mode 16 bits 16 bits 8 bits 16 bits 16 bits 0 On-chip ROM enabled, Enabled expanded mode 8 bits 1 Single-chip mode — Not available in the H8S/2626 Group or H8S/2623 Group. The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2626 Group and H8S/2623 Group actually access a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Rev. 5.00 Jan 10, 2006 page 73 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The H8S/2626 Group and H8S/2623 Group can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration The H8S/2626 Group and H8S/2623 Group have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2626 Group or H8S/2623 Group chip. Table 3.2 summarizes these registers. Table 3.2 MCU Registers Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undetermined H'FDE7 System control register SYSCR R/W H'01 H'FDE5 Pin function control register PFCR R/W H'0D/H'00 H'FDEB Note: * Lower 16 bits of the address. Rev. 5.00 Jan 10, 2006 page 74 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes 3.2 Register Descriptions 3.2.1 Mode Control Register (MDCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 — — — — — MDS2 MDS1 MDS0 1 0 0 0 0 —* —* —* R/W — — — — R R R Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register that indicates the current operating mode of the H8S/2626 Group or H8S/2623 Group chip. Bit 7—Reserved: Only 1 should be written to this bit. Bits 6 to 3—Reserved: These bits are always read as 0 and cannot be modified. Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. 3.2.2 Bit System Control Register (SYSCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 MACS — INTM1 INTM0 NMIEG — — RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W — R/W SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM. SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Rev. 5.00 Jan 10, 2006 page 75 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the MAC instruction. Bit 7 MACS Description 0 Non-saturating calculation for MAC instruction 1 Saturating calculation for MAC instruction (Initial value) Bit 6—Reserved: This bit is always read as 0 and cannot be modified. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 Bit 4 INTM1 INTM0 Interrupt Control Mode Description 0 0 0 Control of interrupts by I bit 1 — Setting prohibited 0 2 Control of interrupts by I2 to I0 bits and IPR 1 — Setting prohibited 1 (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description 0 An interrupt is requested at the falling edge of NMI input 1 An interrupt is requested at the rising edge of NMI input Bit 2—Reserved: Only 0 should be written to this bit. Bit 1—Reserved: This bit is always read as 0 and cannot be modified. Rev. 5.00 Jan 10, 2006 page 76 of 1042 REJ09B0275-0500 (Initial value) Section 3 MCU Operating Modes Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit must be set to 1. 3.2.3 Bit Pin Function Control Register (PFCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 — — BUZZE — AE3 AE2 AE1 AE0 0 0 0 0 1/0 1/0 0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous state in software standby mode. Bits 7 to 4—Reserved: Only 0 should be written to these bits. Bit 5—BUZZE Output Enable (BUZZE): This bit is for use only in the H8S/2626. Only 0 should be writtn to this bit. Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Rev. 5.00 Jan 10, 2006 page 77 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 Description 0 0 0 0 A8–A23 address output disabled 1 A8 address output enabled; A9–A23 address output disabled 0 A8, A9 address output enabled; A10–A23 address output disabled 1 A8–A10 address output enabled; A11–A23 address output disabled 0 A8–A11 address output enabled; A12–A23 address output disabled 1 A8–A12 address output enabled; A13–A23 address output disabled 0 A8–A13 address output enabled; A14–A23 address output disabled 1 A8–A14 address output enabled; A15–A23 address output disabled 0 A8–A15 address output enabled; A16–A23 address output disabled 1 A8–A16 address output enabled; A17–A23 address output disabled 0 A8–A17 address output enabled; A18–A23 address output disabled 1 A8–A18 address output enabled; A19–A23 address output disabled 0 A8–A19 address output enabled; A20–A23 address output disabled 1 A8–A20 address output enabled; A21–A23 address output disabled (Initial value*) 0 A8–A21 address output enabled; A22, A23 address output disabled 1 A8–A23 address output enabled 1 1 0 1 1 0 0 1 1 0 1 Note: * (Initial value*) In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. Rev. 5.00 Jan 10, 2006 page 78 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports 1, A, B, and C, function as input port pins immediately after a reset. Address output can be performed by setting the corresponding DDR (data direction register) bits to 1. Port D function as a data bus, and part of port F carries data bus signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. Rev. 5.00 Jan 10, 2006 page 79 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes All I/O ports are available for use as input-output ports. 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 and A to F vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 4 Mode 5 Mode 6 Mode 7 A P*/A P*/A P*/A P P Port 1 P10 P11 to P13 A P*/A Port A PA4 to PA0 A A A A P*/A P*/A P P Port B Port C A A P*/A Port D D Port E D P*/D D P*/D PF7 P/D* P/C* P/C* P/C* PF6 to PF4 C PF3 P/C* P*/C C P*/C C P*/C P*/C P*/C Port F PF2 to PF0 P P P P*/C P Legend: P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O Note: * After reset 3.5 Address Map in Each Operating Mode An address map of the H8S/2623 and H8S/2626 is shown in figure 3.1, and an address map of the H8S/2622, and H8S/2625 in figure 3.2, and an address map of the H8S/2621 and H8S/2624 in figure 3.3. The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus Controller. Rev. 5.00 Jan 10, 2006 page 80 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 External address space Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'03FFFF H'040000 H'FFB000 H'FFC000 Reserved area On-chip RAM* H'FFB000 H'FFC000 External address space Reserved area On-chip RAM* H'FFC000 On-chip RAM H'FFEFBF H'FFEFC0 External area H'FFEFC0 External area H'FFF800 H'FFF800 Internal I/O registers H'FFF800 Internal I/O registers Internal I/O registers H'FFFF3F H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.1 Memory Map in Each Operating Mode in the H8S/2623 and H8S/2626 Rev. 5.00 Jan 10, 2006 page 81 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space On-chip ROM H'01FFFF H'020000 Reserved area H'040000 H'FFB000 H'FFD000 Reserved area On-chip RAM* H'FFB000 H'FFD000 External address space Reserved area On-chip RAM* H'FFD000 On-chip RAM H'FFEFBF H'FFEFC0 External area H'FFEFC0 External area H'FFF800 H'FFF800 Internal I/O registers H'FFF800 Internal I/O registers Internal I/O registers H'FFFF3F H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.2 Memory Map in Each Operating Mode in the H8S/2622 and H8S/2625 Rev. 5.00 Jan 10, 2006 page 82 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'00FFFF H'010000 External address space Reserved area H'040000 External address space H'FFB000 H'FFB000 Reserved area Reserved area H'FFE000 On-chip RAM* H'FFE000 On-chip RAM* H'FFEFC0 External area H'FFEFC0 External area H'FFF800 H'FFF800 Internal I/O registers H'FFE000 H'FFEFBF On-chip RAM H'FFF800 Internal I/O registers Internal I/O registers H'FFFF3F H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM* H'FFFFFF H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.3 Memory Map in Each Operating Mode in the H8S/2621 and H8S/2624 Rev. 5.00 Jan 10, 2006 page 83 of 1042 REJ09B0275-0500 Section 3 MCU Operating Modes Rev. 5.00 Jan 10, 2006 page 84 of 1042 REJ09B0275-0500 Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Low 1 Trace* Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Direct transition Starts when a direction transition occurs as the result of SLEEP instruction execution. Interrupt Starts when execution of the current instruction or exception 2 handling ends, if an interrupt request has been issued* Trap instruction 3 (TRAPA)* Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. Rev. 5.00 Jan 10, 2006 page 85 of 1042 REJ09B0275-0500 Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Reset Manual reset*1 Trace Exception sources External interrupts: NMI, IRQ5 to IRQ0 Interrupts Internal interrupts: 47 interrupt sources*2 in on-chip supporting modules Trap instruction Notes: 1. Not available in the H8S/2626 Group or H8S/2623 Group. 2. 48 interrupt sources in the H8S/2626 Group. Figure 4.1 Exception Sources Rev. 5.00 Jan 10, 2006 page 86 of 1042 REJ09B0275-0500 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Reset 0 H'0000 to H'0003 3 Manual reset* 1 H'0004 to H'0007 Reserved 2 H'0008 to H'000B 3 H'000C to H'000F 4 H'0010 to H'0013 5 H'0014 to H'0017 Direct transitions* (H8S/2626 only) 6 H'0018 to H'001B External interrupt 7 H'001C to H'001F Trace 4 NMI Trap instruction (4 sources) Reserved External interrupt Reserved 2 Internal interrupt* 8 H'0020 to H'0023 9 H'0024 to H'0027 10 H'0028 to H'002B 11 H'002C to H'002F 12 H'0030 to H'0033 13 H'0034 to H'0037 1 14 H'0038 to H'003B 15 H'003C to H'003F IRQ0 16 H'0040 to H'0043 IRQ1 17 H'0044 to H'0047 IRQ2 18 H'0048 to H'004B IRQ3 19 H'004C to H'004F IRQ4 20 H'0050 to H'0053 IRQ5 21 H'0054 to H'0057 22 H'0058 to H'005B 23 H'005C to H'005F 24  127 H'0060 to H'0063  H'01FC to H'01FF Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. 3. Not available in the H8S/2626 Group or H8S/2623 Group. 4. See section 21B.11, Direct Transitions, for details. Rev. 5.00 Jan 10, 2006 page 87 of 1042 REJ09B0275-0500 Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2626 Group or H8S/2623 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The chip can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Sequence The chip enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.2 and 4.3 show examples of the reset sequence. Rev. 5.00 Jan 10, 2006 page 88 of 1042 REJ09B0275-0500 Section 4 Exception Handling Internal Prefetch of first processing program instruction Vector fetch φ * * * (1) (3) (5) RES Address bus RD High HWR, LWR D15 to D0 (1) (3) (2) (4) (5) (6) (2) (4) (6) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Note: * Three program wait states are inserted. Figure 4.2 Reset Sequence (Modes 4 and 5) Rev. 5.00 Jan 10, 2006 page 89 of 1042 REJ09B0275-0500 Section 4 Exception Handling Prefetch of Internal first program processing instruction Vector fetch φ RES (3) (1) Internal address bus (5) Internal read signal Internal write signal High Internal data bus (2) (4) (6) (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Figure 4.3 Reset Sequence (Modes 6 and 7) 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively, and all modules except the DTC enter module stop mode. Consequently, on-chip supporting Rev. 5.00 Jan 10, 2006 page 90 of 1042 REJ09B0275-0500 Section 4 Exception Handling module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4.3 Status of CCR and EXR after Trace Exception Handling Interrupt Control Mode CCR I 0 2 EXR UI I2 to I0 T Trace exception handling cannot be used. 1 — — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. Rev. 5.00 Jan 10, 2006 page 91 of 1042 REJ09B0275-0500 Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and internal sources (H8S/2626 Group: 48, H8S/2623 Group: 47) in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), PC break controller (PBC), controller area network (HCAN), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts Interrupts Internal interrupts Notes: NMI (1) IRQ5 to IRQ0 (6) WDT* H8S/2626 Group (2), H8S/2623 Group (1) TPU (26) SCI (12) DTC (1) PBC (1) HCAN (5) A/D converter (1) Numbers in parentheses are the numbers of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 4.4 Interrupt Sources and Number of Interrupts Rev. 5.00 Jan 10, 2006 page 92 of 1042 REJ09B0275-0500 Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling Interrupt Control Mode CCR EXR I UI I2 to I0 T 0 1 — — — 2 1 — — 0 Legend: 1: Set to 1 0: Cleared to 0 —: Retains value prior to execution. Rev. 5.00 Jan 10, 2006 page 93 of 1042 REJ09B0275-0500 Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figures 4.5 (1) and 4.5 (2) show the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) (a) Interrupt control mode 0 EXR Reserved* CCR CCR* PC (16 bits) (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the H8S/2626 Group or H8S/2623 Group) SP SP CCR EXR Reserved* CCR PC (24 bits) PC (24 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4.5 (2) Stack Status after Exception Handling (Advanced Modes) Rev. 5.00 Jan 10, 2006 page 94 of 1042 REJ09B0275-0500 Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2626 Group or H8S/2623 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what happens when the SP value is odd. CCR SP R1L SP PC PC SP H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF TRAP instruction executed MOV.B R1L, @–ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.6 Operation when SP Value is Odd Rev. 5.00 Jan 10, 2006 page 95 of 1042 REJ09B0275-0500 Section 4 Exception Handling Rev. 5.00 Jan 10, 2006 page 96 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2626 Group and H8S/2623 Group control interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR  An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.  NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses  All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Seven external interrupts  NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI.  Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5 to IRQ0. • DTC control  DTC activation is performed by means of interrupts. Rev. 5.00 Jan 10, 2006 page 97 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. CPU INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ISCR IER Interrupt request Vector number Priority determination I Internal interrupt request SWDTEND to SLE0 CCR I2 to I0 IPR Interrupt controller Legend: ISCR IER ISR IPR SYSCR : IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 5.00 Jan 10, 2006 page 98 of 1042 REJ09B0275-0500 EXR Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 5 to 0 IRQ5 to IRQ0 Input Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 5.1.4 Register Configuration Table 5.2 summarizes the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers 1 Address* Name Abbreviation R/W Initial Value System control register SYSCR R/W H'01 H'FDE5 IRQ sense control register H ISCRH R/W H'00 H'FE12 IRQ sense control register L ISCRL R/W H'00 H'FE13 IRQ enable register IER R/W H'00 H'FE14 IRQ status register ISR 2 R/(W)* H'00 H'FE15 Interrupt priority register A IPRA R/W H'77 H'FEC0 Interrupt priority register B IPRB R/W H'77 H'FEC1 Interrupt priority register C IPRC R/W H'77 H'FEC2 Interrupt priority register D IPRD R/W H'77 H'FEC3 Interrupt priority register E IPRE R/W H'77 H'FEC4 Interrupt priority register F IPRF R/W H'77 H'FEC5 Interrupt priority register G IPRG R/W H'77 H'FEC6 Interrupt priority register H IPRH R/W H'77 H'FEC7 Interrupt priority register I IPRI R/W H'77 H'FEC8 Interrupt priority register J IPRJ R/W H'77 H'FEC9 Interrupt priority register K IPRK R/W H'77 H'FECA Interrupt priority register M IPRM R/W H'77 H'FECC Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. Rev. 5.00 Jan 10, 2006 page 99 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 MACS — INTM1 INTM0 NMIEG — — RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W — R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in software standby mode. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 Bit 4 INTM1 INTM0 Interrupt Control Mode Description 0 0 0 Interrupts are controlled by I bit 1 — Setting prohibited 0 2 Interrupts are controlled by bits I2 to I0, and IPR 1 — Setting prohibited 1 (Initial value) Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG Description 0 Interrupt request generated at falling edge of NMI input 1 Interrupt request generated at rising edge of NMI input Rev. 5.00 Jan 10, 2006 page 100 of 1042 REJ09B0275-0500 (Initial value) Section 5 Interrupt Controller 5.2.2 Bit Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM) : 7 6 5 4 3 2 1 0 — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : 0 1 1 1 0 1 1 1 R/W — R/W R/W R/W — R/W R/W R/W : The IPR registers are twelve 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified. Rev. 5.00 Jan 10, 2006 page 101 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Table 5.3 Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ4 IRQ5 IPRC IRQ2 IRQ3 1 —* IPRD WDT0 DTC 1 —* IPRE PC break A/D converter, WDT1* IPRF TPU channel 0 TPU channel 1 IPRG TPU channel 2 TPU channel 3 IPRH TPU channel 4 TPU channel 5 IPRI —* IPRJ —* 1 —* IPRK SCI channel 1 IPRM HCAN SCI channel 2 1 —* 1 2 1 SCI channel 0 Notes: 1. Reserved bits. These bits are always read as 1 and cannot be modified. 2. Valid only in the H8S/2626 Group. As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. Rev. 5.00 Jan 10, 2006 page 102 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.2.3 Bit IRQ Enable Register (IER) : Initial value : R/W : 7 6 5 4 3 2 1 0 — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IER is initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 6—Reserved: Only 0 should be written to these bits. Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ5 to IRQ0 are enabled or disabled. Bit n IRQnE Description 0 IRQn interrupts disabled 1 IRQn interrupts enabled (Initial value) (n = 5 to 0) Rev. 5.00 Jan 10, 2006 page 103 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit 15 14 13 12 — — — — 0 0 0 0 0 0 0 0 : R/W R/W R/W R/W R/W R/W R/W R/W : 7 6 5 4 3 2 1 0 : Initial value : R/W 11 10 9 8 IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA ISCRL Bit IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 15 to 12—Reserved: Only 0 should be written to these bits. Bits 11 to 0: IRQ7 Sense Control A and B (IRQ5SCA, IRQ5SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 11 to 0 IRQ5SCB to IRQ0SCB IRQ5SCA to IRQ0SCA 0 0 Interrupt request generated at IRQ5 to IRQ0 input low level (Initial value) 1 Interrupt request generated at falling edge of IRQ5 to IRQ0 input 0 Interrupt request generated at rising edge of IRQ5 to IRQ0 input 1 Interrupt request generated at both falling and rising edges of IRQ5 to IRQ0 input 1 Description Rev. 5.00 Jan 10, 2006 page 104 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.2.5 Bit IRQ Status Register (ISR) : Initial value : R/W : 7 6 5 4 3 2 1 0 — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. Bits 7 and 6—Reserved: Only 0 should be written to these bits. Bits 5 to 0—IRQ5 to IRQ0 flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Rev. 5.00 Jan 10, 2006 page 105 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Bit n IRQnF Description 0 [Clearing conditions] (Initial value) 1 • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high • When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) • When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 [Setting conditions] • When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) • When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) • When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) • When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 5 to 0) 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts (48 sources: H8S/2626 Group, 47 sources: H8S/2623 Group). 5.3.1 External Interrupts There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to restore the H8S/2626 Group or H8S/2623 Group chip from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. Rev. 5.00 Jan 10, 2006 page 106 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5 to IRQ0. Interrupts IRQ5 to IRQ0 have the following features: • Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ5 to IRQ0. • Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER. • The interrupt priority level can be set with IPR. • The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn interrupt S Q request R IRQn input Clear signal Note: n = 5 to 0 Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16. Rev. 5.00 Jan 10, 2006 page 107 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. 5.3.2 Internal Interrupts There are 48 sources for internal interrupts from on-chip supporting modules in the H8S/2626 Group, and 47 in the H8S/2623 Group. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. • The interrupt priority level can be set by means of IPR. • The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. Rev. 5.00 Jan 10, 2006 page 108 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI Origin of Interrupt Source External pin Vector Address* Vector Number Advanced Mode IPR 7 H'001C 16 H'0040 IPRA6 to 4 IRQ1 17 H'0044 IPRA2 to 0 IRQ2 IRQ3 18 19 H'0048 H'004C IPRB6 to 4 IRQ4 IRQ5 20 21 H'0050 H'0054 IPRB2 to 0 IRQ0 High Reserved — 22 23 H'0058 H'005C IPRC6 to 4 SWDTEND (software activation interrupt end) DTC 24 H'0060 IPRC2 to 0 WOVI0 (interval timer) Watchdog timer 0 25 H'0064 IPRD6 to 4 Reserved — 26 H'0068 IPRD2 to 0 PC break PC break 27 H'006C IPRE6 to 4 ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to 0 WOVI1 (interval timer) (H8S/2626 Group only) Watchdog timer 1 29 H'0074 Reserved — 30 31 H'0078 H'007C TGI0A (TGR0A input capture/ compare match) TPU channel 0 32 H'0080 TGI0B (TGR0B input capture/ compare match) 33 H'0084 TGI0C (TGR0C input capture/ compare match) 34 H'0088 TGI0D (TGR0D input capture/ compare match) 35 H'008C TCI0V (overflow 0) 36 H'0090 37 38 39 H'0094 H'0098 H'009C Reserved — Priority IPRF6 to 4 Low Rev. 5.00 Jan 10, 2006 page 109 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source TGI1A (TGR1A input capture/ compare match) TPU channel 1 Vector Address* Vector Number Advanced Mode IPR Priority 40 H'00A0 IPRF2 to 0 High TGI1B (TGR1B input capture/ compare match) 41 H'00A4 TCI1V (overflow 1) 42 H'00A8 TCI1U (underflow 1) 43 H'00AC 44 H'00B0 TGI2B (TGR2B input capture/ compare match) 45 H'00B4 TCI2V (overflow 2) 46 H'00B8 TCI2U (underflow 2) 47 H'00BC 48 H'00C0 TGI3B (TGR3B input capture/ compare match) 49 H'00C4 TGI3C (TGR3C input capture/ compare match) 50 H'00C8 TGI3D (TGR3D input capture/ compare match) 51 H'00CC TGI2A (TGR2A input capture/ compare match) TGI3A (TGR3A input capture/ compare match) TPU channel 2 TPU channel 3 52 H'00D0 Reserved — 53 54 55 H'00D4 H'00D8 H'00DC TGI4A (TGR4A input capture/ compare match) TPU channel 4 56 H'00E0 TGI4B (TGR4B input capture/ compare match) 57 H'00E4 TCI4V (overflow 4) 58 H'00E8 TCI4U (underflow 4) 59 H'00EC TCI3V (overflow 3) Rev. 5.00 Jan 10, 2006 page 110 of 1042 REJ09B0275-0500 IPRG6 to 4 IPRG2 to 0 IPRH6 to 4 Low Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source TGI5A (TGR5A input capture/ compare match) TPU channel 5 Vector Address* Vector Number Advanced Mode IPR Priority 60 H'00F0 IPRH2 to 0 High TGI5B (TGR5B input capture/ compare match) 61 H'00F4 TCI5V (overflow 5) 62 H'00F8 TCI5U (underflow 5) 63 H'00FC 64 65 66 H'0100 H'0104 H'0108 67 H'010C 68 69 70 H'0110 H'0114 H'0118 71 72 73 74 75 H'011C H'0120 H'0124 H'0128 H'012C 76 77 78 79 H'0130 H'0134 H'0138 H'013C 80 H'0140 81 H'0144 TXI0 (transmit data empty 0) 82 H'0148 TEI0 (transmission end 0) 83 H'014C 84 H'0150 85 H'0154 TXI1 (transmit data empty 1) 86 H'0158 TEI1 (transmission end 1) 87 H'015C 88 H'0160 89 H'0164 TXI2 (transmit data empty 2) 90 H'0168 TEI2 (transmission end 2) 91 H'016C Reserved ERI0 (receive error 0) RXI0 (reception completed 0) ERI1 (receive error 1) RXI1 (reception completed 1) ERI2 (receive error 2) RXI2 (reception completed 2) — SCI channel 0 SCI channel 1 SCI channel 2 IPRI6 to 4 IPRI2 to 0 IPRJ6 to 4 IPRJ2 to 0 IPRK6 to 4 IPRK2 to 0 Low Rev. 5.00 Jan 10, 2006 page 111 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority ERS0 HCAN 104 H'01A0 IPRM6 to 4 High OVR0 105 H'01A4 RM0 106 H'01A8 RM1 107 H'01AC SLE0 108 H'01B0 IPRM2 to 0 Low Note: * Lower 16 bits of the start address. 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2626 Group and H8S/2623 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR. Rev. 5.00 Jan 10, 2006 page 112 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Table 5.5 Interrupt Control Modes SYSCR Interrupt Control Mode Priority Setting INTM1 INTM0 Registers Interrupt Mask Bits 0 0 — 2 1 — Description 0 — I Interrupt mask control is performed by the I bit. 1 — — Setting prohibited 0 IPR I2 to I0 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. 1 — — Setting prohibited Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Default priority determination Interrupt source Vector number 8-level mask control IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation Rev. 5.00 Jan 10, 2006 page 113 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts 1 NMI interrupts * All interrupts 2 *: Don't care (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.7 Interrupts Selected in Each Interrupt Control Mode (2) Interrupt Control Mode Selected Interrupts 0 All interrupts 2 Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Rev. 5.00 Jan 10, 2006 page 114 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5.8 shows operations and control signal functions in each interrupt control mode. Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control Interrupt Control Mode INTM1 INTM0 I 0 0 0 2 1 0 IM 1 —* Setting X 8-Level Control X Default Priority Determination I2 to I0 IPR — —* IM PR 2 T (Trace) — T Legend: : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR: Sets priority. — : Not used. Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting. Rev. 5.00 Jan 10, 2006 page 115 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 5.00 Jan 10, 2006 page 116 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No No I=0 Hold pending Yes No IRQ0 Yes No IRQ1 Yes SLE0 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 5.00 Jan 10, 2006 page 117 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 5.00 Jan 10, 2006 page 118 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes No Level 6 interrupt? No Yes Level 1 interrupt? No Mask level 5 or below? No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 5.00 Jan 10, 2006 page 119 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 120 of 1042 REJ09B0275-0500 (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (1) Internal data us Internal write signal Internal read signal Internal address bus Interrupt request signal φ Instruction prefetch (5) (7) (8) (9) (10) Vector fetch (12) (11) Internal operation (14) (13) Interrupt service routine instruction prefetch (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine (6) Stack 5.4.4 Interrupt level determination Wait for end of instruction Interrupt acceptance Section 5 Interrupt Controller Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5.7 Interrupt Exception Handling Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The H8S/2626 Group and H8S/2623 Group are capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 5.9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.9 Interrupt Response Times Normal Mode* 5 Advanced Mode No. Execution Status INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1 1 1 Interrupt priority determination* 3 3 3 3 2 Number of wait states until 2 executing instruction ends* 1 to (19+2·SI) 1 to (19+2·SI) 1 to (19+2·SI) 1 to (19+2·SI) 3 PC, CCR, EXR stack save 2·SK 3·SK 2·SK 3·SK 4 Vector fetch SI SI 2·SI 2·SI 5 3 Instruction fetch* 2·SI 2·SI 2·SI 2·SI 6 4 Internal processing* 2 2 2 2 11 to 31 12 to 32 12 to 32 13 to 33 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in the H8S/2626 Group or H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 121 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16 Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6+2m 2 3+m Legend: m: Number of wait states in an external device access. 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.8 shows an example in which the TCIEV bit in the TPU’s TIER0 register is cleared to 0. Rev. 5.00 Jan 10, 2006 page 122 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller TIER0 write cycle by CPU TCIV exception handling φ Internal address bus TIER0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. Rev. 5.00 Jan 10, 2006 page 123 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1 5.6 DTC Activation by Interrupt 5.6.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 8, Data Transfer Controller (DTC). Rev. 5.00 Jan 10, 2006 page 124 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC interrupt controller. Interrupt request IRQ interrupt On-chip supporting module Interrupt source clear signal DTC activation request vector number Selection circuit Select signal Clear signal DTCER Control logic DTC Clear signal DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Figure 5.9 Interrupt Control for DTC 5.6.3 Operation The interrupt controller has three main functions in DTC control. (1) Selection of Interrupt Source Interrupt sources can be specified as DTC activation requests or CPU interrupt requests by means of the DTCE bit of DTCERA to DTCERG in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. Rev. 5.00 Jan 10, 2006 page 125 of 1042 REJ09B0275-0500 Section 5 Interrupt Controller (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 8.3.3, DTC Vector Table, for the respective priorities. (3) Operation Order If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTCE bit of DTCERA to DTCERG in the DTC, and the DISEL bit of MRB in the DTC. Table 5.11 Interrupt Source Selection and Clearing Control Settings DTC Interrupt Source Selection/Clearing Control DTCE DISEL DTC CPU 0 * X ∆ 1 0 ∆ X 1 O ∆ Legend: ∆ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) O: The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don’t care (4) Notes on Use SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register. Rev. 5.00 Jan 10, 2006 page 126 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) Section 6 PC Break Controller (PBC) 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write. 6.1.1 Features The PC break controller has the following features: • Two break channels (A and B) • The following can be set as break compare conditions:  24 address bits Bit masking possible  Bus cycle Instruction fetch Data access: data read, data write, data read/write  Bus master Either CPU or CPU/DTC can be selected • The timing of PC break exception handling after the occurrence of a break condition is as follows:  Immediately before execution of the instruction fetched at the set address (instruction fetch)  Immediately after execution of the instruction that accesses data at the set address (data access) • Module stop mode can be set  The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. Rev. 5.00 Jan 10, 2006 page 127 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the PC break controller. BARA Mask control Output control BCRA Control logic Comparator Match signal Internal address Control logic Comparator Match signal Mask control BARB Output control Access status PC break interrupt BCRB Figure 6.1 Block Diagram of PC Break Controller Rev. 5.00 Jan 10, 2006 page 128 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) 6.1.3 Register Configuration Table 6.1 shows the PC break controller registers. Table 6.1 PC Break Controller Registers Initial Value Address* Name Abbreviation R/W Reset Manual Reset* Break address register A BARA R/W H'000000 Retained H'FE00 Break address register B BARB R/W H'000000 Retained H'FE04 Break control register A BCRA H'00 Retained H'FE08 Break control register B BCRB R/(W)* 2 R/(W)* H'00 Retained H'FE09 Module stop control register C MSTPCRC R/W H'FF Retained H'FDEA 2 3 1 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. 3. Not available in the H8S/2626 Group or H8S/2623 Group. 6.2 Register Descriptions 6.2.1 Break Address Register A (BARA) Bit 31 ••• 24 — ••• — Initial value Undefined — R/W ••• ••• 23 22 21 20 19 18 17 16 BAA BAA BAA BAA BAA BAA BAA BAA 23 22 21 20 19 18 17 16 Unde- 0 0 0 0 0 0 0 0 fined — R/W R/W R/W R/W R/W R/W R/W R/W ••• ••• ••• ••• 7 6 5 4 3 2 1 0 BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W BARA is a 32-bit readable/writable register that specifies the channel A break address. BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode. Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified. Bits 23 to 0—Break Address A23 to A0 (BAA23 to BAA0): These bits hold the channel A PC break address. Rev. 5.00 Jan 10, 2006 page 129 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) Bit Initial value R/W 7 6 5 4 3 2 1 CMFA CDA 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 BIEA Note: * Only 0 can be written, for flag clearing. BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. It also contains a condition match flag. BCRA is initialized to H'00 by a reset and in hardware standby mode. Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0. Bit 7 CMFA Description 0 [Clearing condition] When 0 is written to CMFA after reading CMFA = 1 1 (Initial value) [Setting condition] When a condition set for channel A is satisfied Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus master. Bit 6 CDA Description 0 PC break is performed when CPU is bus master 1 PC break is performed when CPU or DTC is bus master Rev. 5.00 Jan 10, 2006 page 130 of 1042 REJ09B0275-0500 (Initial value) Section 6 PC Break Controller (PBC) Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description 0 0 1 1 0 1 0 All BARA bits are unmasked and included in break conditions (Initial value) 1 BAA0 (lowest bit) is masked, and not included in break conditions 0 BAA1–0 (lower 2 bits) are masked, and not included in break conditions 1 BAA2–0 (lower 3 bits) are masked, and not included in break conditions 0 BAA3–0 (lower 4 bits) are masked, and not included in break conditions 1 BAA7–0 (lower 8 bits) are masked, and not included in break conditions 0 BAA11–0 (lower 12 bits) are masked, and not included in break conditions 1 BAA15–0 (lower 16 bits) are masked, and not included in break conditions Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits select an instruction fetch, data read, data write, or data read/write cycle as the channel A break condition. Bit 2 Bit 1 CSELA1 CSELA0 Description 0 0 Instruction fetch is used as break condition 1 Data read cycle is used as break condition 0 Data write cycle is used as break condition 1 Data read/write cycle is used as break condition 1 (Initial value) Rev. 5.00 Jan 10, 2006 page 131 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts. Bit 0 BIEA Description 0 PC break interrupts are disabled 1 PC break interrupts are enabled 6.2.4 (Initial value) Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Module Stop Control Register C (MSTPCRC) Bit 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value R/W 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a power on reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode. Bit 4 MSTPC4 Description 0 PC break controller module stop mode is cleared 1 PC break controller module stop mode is set Rev. 5.00 Jan 10, 2006 page 132 of 1042 REJ09B0275-0500 (Initial value) Section 6 PC Break Controller (PBC) 6.3 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch (1) Initial settings  Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address.  Set the break conditions in BCRA. BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must be the CPU. Set 0 to select the CPU. BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked. BCRA bits 2, 1 (CSELA1, 0): Set 00 to specify an instruction fetch as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition  When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. (3) Interrupt handling  After priority determination by the interrupt controller, PC break interrupt exception handling is started. Rev. 5.00 Jan 10, 2006 page 133 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) 6.3.2 PC Break Interrupt Due to Data Access (1) Initial settings  Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses.  Set the break conditions in BCRA. BCRA bit 6 (CDA): Select the bus master. BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked. BCRA bits 2, 1 (CSELA1, 0): Set 01, 10, or 11 to specify data access as the break condition. BCRA bit 0 (BIEA): Set to 1 to enable break interrupts. (2) Satisfaction of break condition  After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. (3) Interrupt handling  After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.3 Notes on PC Break Interrupt Handling (1) The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. (2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has been transferred to the CPU by the bus controller. Rev. 5.00 Jan 10, 2006 page 134 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. (1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode to subsleep mode: After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep mode, and PC break interrupt handling is executed. After execution of PC break interrupt handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)). (2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to subactive mode: After execution of the SLEEP instruction, a transition is made to subactive mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (B)) (Supported only in the H8S/2626 Group). (3) When the SLEEP instruction causes a transition from subactive mode to high-speed (mediumspeed) mode: After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (C)) (Supported only in the H8S/2626 Group). (4) When the SLEEP instruction causes a transition to software standby mode or watch mode: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (D)). Rev. 5.00 Jan 10, 2006 page 135 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock → subclock Subclock → system clock, oscillation settling time Transition to respective mode (D) Execution of instruction after sleep instruction Direct transition exception handling (A) PC break exception handling Direct transition exception handling Subactive mode PC break exception handling Execution of instruction after sleep instruction Execution of instruction after sleep instruction (B)* (C)* High-speed (medium-speed) mode Note: * Supported only in the H8S/2626 Group. Figure 6.2 Operation in Power-Down Mode Transitions 6.3.5 PC Break Operation in Continuous Data Transfer If a PC break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction: PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. (2) When a PC break interrupt is generated at a DTC transfer address: PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. Rev. 5.00 Jan 10, 2006 page 136 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) 6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in onchip ROM or RAM is always delayed by one state. (2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. (3) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, and that address is used for data access, the instruction will be one state later than in normal operation. @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 (4) When break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. Rev. 5.00 Jan 10, 2006 page 137 of 1042 REJ09B0275-0500 Section 6 PC Break Controller (PBC) 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. (2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt becomes valid two states after the end of the executing instruction. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction is always executed. For details, see section 5, Interrupt Controller. (3) When a PC break is set for an instruction fetch at the address following a Bcc instruction: A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc instruction: A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed. Rev. 5.00 Jan 10, 2006 page 138 of 1042 REJ09B0275-0500 Section 7 Bus Controller Section 7 Bus Controller 7.1 Overview The H8S/2626 Group and H8S/2623 Group have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC). 7.1.1 Features The features of the bus controller are listed below. • Manages external address space in area units  Manages the external space as 8 areas of 2 Mbytes  Bus specifications can be set independently for each area  Burst ROM interface can be set • Basic bus interface  8-bit access or 16-bit access can be selected for each area  2-state access or 3-state access can be selected for each area  Program wait states can be inserted for each area • Burst ROM interface  Burst ROM interface can be set for area 0  Choice of 1- or 2-state burst access • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle • Write buffer functions  External write cycle and internal access can be executed in parallel • Bus arbitration function  Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC • Other features  External bus release function Rev. 5.00 Jan 10, 2006 page 139 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the bus controller. Internal address bus Area decoder ABWCR External bus control signals ASTCR BCRH BREQ BACK BREQO Bus controller Wait controller WAIT Internal data bus BCRL Internal control signals Bus mode signal WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal Legend: ABWCR: ASTCR: BCRH: BCRL: WCRH: WCRL: Bus width control register Access state control register Bus control register H Bus control register L Wait control register H Wait control register L Figure 7.1 Block Diagram of Bus Controller Rev. 5.00 Jan 10, 2006 page 140 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.1.3 Pin Configuration Table 7.1 summarizes the pins of the bus controller. Table 7.1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write HWR Output Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Low write LWR Output Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Wait WAIT Input Wait request signal when accessing external 3-state access space. Bus request BREQ Input Request signal that releases bus to external device. Bus request acknowledge BACK Output Acknowledge signal indicating that bus has been released. Bus request output BREQO Output External bus request signal used when internal bus master accesses external space when external bus is released. Rev. 5.00 Jan 10, 2006 page 141 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.1.4 Register Configuration Table 7.2 summarizes the registers of the bus controller. Table 7.2 Bus Controller Registers Initial Value Manual Reset* 3 Address* 1 Name Abbreviation R/W Reset Bus width control register ABWCR R/W 2 H'FF/H'00* Retained H'FED0 Access state control register ASTCR R/W H'FF Retained H'FED1 Wait control register H WCRH R/W H'FF Retained H'FED2 Wait control register L WCRL R/W H'FF Retained H'FED3 Bus control register H BCRH R/W H'D0 Retained H'FED4 Bus control register L BCRL R/W H'08 Retained H'FED5 Pin function control register PFCR R/W H'0D/H'00 Retained H'FDEB Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. 3. Not available in the H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 142 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.2 Register Descriptions 7.2.1 Bus Width Control Register (ABWCR) Bit : Modes 5 to 7 Initial value : R/W : 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Mode 4 Initial value : R/W : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7, and to H'00 in mode 4. It is not initialized in software standby mode. Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. Bit n ABWn Description 0 Area n is designated for 16-bit access 1 Area n is designated for 8-bit access (n = 7 to 0) Rev. 5.00 Jan 10, 2006 page 143 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.2.2 Bit Access State Control Register (ASTCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. Wait state insertion is enabled or disabled at the same time. Bit n ASTn Description 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) Rev. 5.00 Jan 10, 2006 page 144 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. (1) WCRH Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 Bit 6 W71 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (Initial value) 1 Rev. 5.00 Jan 10, 2006 page 145 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 Bit 4 W61 W60 Description 0 0 Program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (Initial value) 1 Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 W51 W50 Description 0 0 Program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (Initial value) 1 Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 Bit 0 W41 W40 Description 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (Initial value) 1 Rev. 5.00 Jan 10, 2006 page 146 of 1042 REJ09B0275-0500 Section 7 Bus Controller (2) WCRL Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 Bit 6 W31 W30 Description 0 0 Program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (Initial value) 1 Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 Bit 4 W21 W20 Description 0 0 Program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (Initial value) 1 Rev. 5.00 Jan 10, 2006 page 147 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 W11 W10 Description 0 0 Program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (Initial value) 1 Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 Bit 0 W01 W00 Description 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (Initial value) 1 Rev. 5.00 Jan 10, 2006 page 148 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.2.4 Bit Bus Control Register H (BCRH) : Initial value : R/W : 7 6 ICIS1 ICIS0 5 4 3 BRSTRM BRSTS1 BRSTS0 2 1 0 — — — 1 1 0 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . Bit 6 ICIS0 Description 0 Idle cycle not inserted in case of successive external read and external write cycles 1 Idle cycle inserted in case of successive external read and external write cycles (Initial value) Rev. 5.00 Jan 10, 2006 page 149 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM Description 0 Area 0 is basic bus interface 1 Area 0 is burst ROM interface (Initial value) Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access Bits 2 to 0—Reserved: Only 0 should be written to these bits. Rev. 5.00 Jan 10, 2006 page 150 of 1042 REJ09B0275-0500 (Initial value) Section 7 Bus Controller 7.2.5 Bit Bus Control Register L (BCRL) : Initial value : R/W : 7 6 5 4 3 2 1 0 BRLE BREQOE — — — — WDBE WAITE 0 0 0 0 1 0 0 0 R/W R/W — R/W R/W R/W R/W R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE Description 0 External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports. (Initial value) 1 External bus release is enabled. Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE Description 0 BREQO output disabled. BREQO can be used as I/O port. 1 BREQO output enabled. (Initial value) Bit 5—Reserved: This bit cannot be modified and is always read as 0. Bit 4—Reserved: Only 0 should be written to this bit. Bit 3—Reserved: Only 1 should be written to this bit. Bit 2—Reserved: Only 0 should be written to this bit. Rev. 5.00 Jan 10, 2006 page 151 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle. Bit 1 WDBE Description 0 Write data buffer function not used 1 Write data buffer function used (Initial value) Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE Description 0 Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. 1 Wait input by WAIT pin enabled 7.2.6 Bit Pin Function Control Register (PFCR) : Initial value : R/W (Initial value) : 7 6 5 4 3 2 1 0 — — BUZZE — AE3 AE2 AE1 AE0 0 0 0 0 1/0 1/0 0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W PFCR is an 8-bit readable/writable register that performs address output control in external expanded mode. PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous state in software standby mode. Bits 7 and 6—Reserved: Only 0 should be written to these bits. Bit 5—BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin. For details, see section 12.2.4, Pin Function Control Register (PFCR). Bit 4—Reserved: Only 0 should be written to this bit. Bits 3 to 0—Address Output Enable 3 to 0 (AE3 to AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR Rev. 5.00 Jan 10, 2006 page 152 of 1042 REJ09B0275-0500 Section 7 Bus Controller setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 Description 0 0 0 0 A8–A23 address output disabled 1 A8 address output enabled; A9–A23 address output disabled 0 A8, A9 address output enabled; A10–A23 address output disabled 1 A8–A10 address output enabled; A11–A23 address output disabled 0 A8–A11 address output enabled; A12–A23 address output disabled 1 A8–A12 address output enabled; A13–A23 address output disabled 0 A8–A13 address output enabled; A14–A23 address output disabled 1 A8–A14 address output enabled; A15–A23 address output disabled 0 A8–A15 address output enabled; A16–A23 address output disabled 1 A8–A16 address output enabled; A17–A23 address output disabled 0 A8–A17 address output enabled; A18–A23 address output disabled 1 A8–A18 address output enabled; A19–A23 address output disabled 0 A8–A19 address output enabled; A20–A23 address output disabled 1 A8–A20 address output enabled; A21–A23 address output disabled (Initial value*) 0 A8–A21 address output enabled; A22, A23 address output disabled 1 A8–A23 address output enabled 1 1 0 1 1 0 0 1 1 0 1 Note: * (Initial value*) In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. Rev. 5.00 Jan 10, 2006 page 153 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.3 Overview of Bus Control 7.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7.2 shows an outline of the memory map. Note: * Not available in the H8S/2626 Group or H8S/2623 Group. H'0000 H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'FFFF H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF (1) Advanced mode (2) Normal mode* Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Figure 7.2 Overview of Area Partitioning Rev. 5.00 Jan 10, 2006 page 154 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 7.3 shows the bus specifications for each basic bus interface area. Rev. 5.00 Jan 10, 2006 page 155 of 1042 REJ09B0275-0500 Section 7 Bus Controller Table 7.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR ABWn ASTn Wn1 Wn0 Bus Width Program Wait Access States States 0 0 — — 16 2 0 1 0 0 3 0 1 1 1 0 2 1 3 1 7.3.3 WCRH, WCRL Bus Specifications (Basic Bus Interface) 0 — — 8 2 0 1 0 0 3 0 1 1 1 0 2 1 3 Memory Interfaces The H8S/2626 Group and H8S/2623 Group memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. Rev. 5.00 Jan 10, 2006 page 156 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (7.4, Basic Bus Interface, and 7.5, Burst ROM Interface) should be referred to for further details. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external space. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space. Only the basic bus interface can be used for areas 1 to 6. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. Only the basic bus interface can be used for the area 7. Rev. 5.00 Jan 10, 2006 page 157 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.4 Basic Bus Interface 7.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7.3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 7.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev. 5.00 Jan 10, 2006 page 158 of 1042 REJ09B0275-0500 Section 7 Bus Controller 16-Bit Access Space: Figure 7.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Lower data bus Upper data bus D15 D8 D7 D0 Byte size • Even address Byte size • Odd address Word size Longword size 1st bus cycle 2nd bus cycle Figure 7.4 Access Sizes and Data Alignment Control (16-Bit Access Space) Rev. 5.00 Jan 10, 2006 page 159 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.4.3 Valid Strobes Table 7.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 7.4 Area 8-bit access space Data Buses Used and Valid Strobes Access Size Read/ Write Address Valid Strobe Upper Data Bus (D15 to D8) Lower data bus (D7 to D0) Byte Read — RD Valid Invalid Write — HWR Even RD 16-bit access Byte space Read Odd Valid Invalid Invalid Valid Even HWR Valid Hi-Z Odd LWR Hi-Z Valid Read — RD Valid Valid Write — HWR, LWR Valid Valid Write Word Hi-Z Notes: Hi-Z: High impedance. Invalid: Input state; input value is ignored. Rev. 5.00 Jan 10, 2006 page 160 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7.5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T2 T1 φ Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Figure 7.5 Bus Timing for 8-Bit 2-State Access Space Rev. 5.00 Jan 10, 2006 page 161 of 1042 REJ09B0275-0500 Section 7 Bus Controller 8-Bit 3-State Access Space: Figure 7.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Figure 7.6 Bus Timing for 8-Bit 3-State Access Space Rev. 5.00 Jan 10, 2006 page 162 of 1042 REJ09B0275-0500 Section 7 Bus Controller 16-Bit 2-State Access Space: Figures 7.7 to 7.9 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Figure 7.7 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) Rev. 5.00 Jan 10, 2006 page 163 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bus cycle T2 T1 φ Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Figure 7.8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev. 5.00 Jan 10, 2006 page 164 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bus cycle T2 T1 φ Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 7.9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev. 5.00 Jan 10, 2006 page 165 of 1042 REJ09B0275-0500 Section 7 Bus Controller 16-Bit 3-State Access Space: Figures 7.10 to 7.12 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Figure 7.10 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) Rev. 5.00 Jan 10, 2006 page 166 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bus cycle T1 T2 T3 φ Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Figure 7.11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev. 5.00 Jan 10, 2006 page 167 of 1042 REJ09B0275-0500 Section 7 Bus Controller Bus cycle T1 T2 T3 φ Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev. 5.00 Jan 10, 2006 page 168 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.4.5 Wait Control When accessing external space, the H8S/2626 Group or H8S/2623 Group can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the WAIT pin is low at the falling edge of φ in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. Rev. 5.00 Jan 10, 2006 page 169 of 1042 REJ09B0275-0500 Section 7 Bus Controller Figure 7.13 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Note: Write data indicates the timing of WAIT pin sampling. Figure 7.13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. Rev. 5.00 Jan 10, 2006 page 170 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.5 Burst ROM Interface 7.5.1 Overview With the H8S/2626 Group and H8S/2623 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 7.5.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 7.14 (a) and (b). The timing shown in figure 7.14 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 7.14 (b) is for the case where both these bits are cleared to 0. Rev. 5.00 Jan 10, 2006 page 171 of 1042 REJ09B0275-0500 Section 7 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Only lower address changed Address bus AS RD Data bus Read data Read data Read data Figure 7.14 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev. 5.00 Jan 10, 2006 page 172 of 1042 REJ09B0275-0500 Section 7 Bus Controller Full access T1 T2 Burst access T1 T1 φ Only lower address changed Address bus AS RD Data bus Read data Read data Read data Figure 7.14 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 7.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. Rev. 5.00 Jan 10, 2006 page 173 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.6 Idle Cycle 7.6.1 Operation When the H8S/2626 Group or H8S/2623 Group accesses external space , it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. Figure 7.15 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ T1 T2 Bus cycle B T3 T1 Bus cycle A T2 φ Address bus Address bus CS* (area A) CS* (area A) CS* (area B) CS* (area B) RD RD Data bus Data bus Long output floating time T1 T2 T3 TI T1 Data collision (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Note: * The CS signals are generated off-chip. Figure 7.15 Example of Idle Cycle Operation (1) Rev. 5.00 Jan 10, 2006 page 174 of 1042 REJ09B0275-0500 Bus cycle B T2 Section 7 Bus Controller (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7.16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A φ T1 T2 T3 Bus cycle B T1 T2 Bus cycle A φ Address bus Address bus CS* (area A) CS* (area A) CS* (area B) CS* (area B) RD RD T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Note: * The CS signals are generated off-chip. Figure 7.16 Example of Idle Cycle Operation (2) Rev. 5.00 Jan 10, 2006 page 175 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.6.2 Pin States in Idle Cycle Table 7.5 shows pin states in an idle cycle. Table 7.5 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 High impedance AS High RD High HWR High LWR High Rev. 5.00 Jan 10, 2006 page 176 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.7 Write Data Buffer Function The H8S/2626 Group and H8S/2623 Group have a write data buffer function in the external data bus. Using the write data buffer function enables external writes to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 7.17 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal I/O register address Internal read signal A23 to A0 External space write External address HWR, LWR D15 to D0 Figure 7.17 Example of Timing when Write Data Buffer Function is Used Rev. 5.00 Jan 10, 2006 page 177 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.8 Bus Release 7.8.1 Overview The H8S/2626 Group and H8S/2623 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, it can issue a bus request off-chip. 7.8.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2626 Group or H8S/2623 Group. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the highimpedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and internal bus master external access occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) Rev. 5.00 Jan 10, 2006 page 178 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.8.3 Pin States in External Bus Released State Table 7.6 shows pin states in the external bus released state. Table 7.6 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance AS High impedance RD High impedance HWR High impedance LWR High impedance Rev. 5.00 Jan 10, 2006 page 179 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.8.4 Transition Timing Figure 7.18 shows the timing for transition to the bus-released state. CPU cycle T0 T1 CPU cycle External bus released state T2 φ High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO * Minimum 1 state [1] [1] [2] [3] [4] [5] [6] [2] [3] [4] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. BREQO signal goes high 1.5 clocks after BACK signal goes high. Note: * Output only when BREQOE is set to 1. Figure 7.18 Bus-Released State Transition Timing Rev. 5.00 Jan 10, 2006 page 180 of 1042 REJ09B0275-0500 [5] [6] Section 7 Bus Controller 7.8.5 Usage Note If MSTPCR is set to H'FFFFFF or H'EFFFFF and a transition is made to sleep mode, the external bus release function will halt. Therefore, these values should not be set in MSTPCR if the external bus release function is to be used in sleep mode. 7.9 Bus Arbitration 7.9.1 Overview The H8S/2626 Group and H8S/2623 Group have a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 7.9.2 Operation The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) An internal bus access by an internal bus master, and external bus release, can be executed in parallel. In the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) Rev. 5.00 Jan 10, 2006 page 181 of 1042 REJ09B0275-0500 Section 7 Bus Controller 7.9.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See appendix A.5, Bus States During Instruction Execution, for timings at which the bus is not transferred. • If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 7.10 Resets and the Bus Controller In a reset, the H8S/2626 Group or H8S/2623 Group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. Rev. 5.00 Jan 10, 2006 page 182 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) 8.1 Overview The H8S/2626 Group and H8S/2623 Group include a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features The features of the DTC are: • Transfer possible over any number of channels  Transfer information is stored in memory  One activation source can trigger a number of data transfers (chain transfer) • Wide range of transfer modes  Normal, repeat, and block transfer modes available  Incrementing, decrementing, and fixing of source and destination addresses can be selected • Direct specification of 16-Mbyte address space possible  24-bit transfer source and destination addresses can be specified • Transfer can be set in byte or word units • A CPU interrupt can be requested for the interrupt that activated the DTC  An interrupt request can be issued to the CPU after one data transfer ends  An interrupt request can be issued to the CPU after the specified data transfers have completely ended • Activation by software is possible • Module stop mode can be set  The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. Rev. 5.00 Jan 10, 2006 page 183 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus On-chip RAM CPU interrupt request Register information MRA MRB CRA CRB DAR SAR DTC Control logic DTC service request DTVECR Interrupt request DTCERA to DTCERG Interrupt controller Internal data bus Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERG DTVECR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to G : DTC vector register Figure 8.1 Block Diagram of DTC Rev. 5.00 Jan 10, 2006 page 184 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.1.3 Register Configuration Table 8.1 summarizes the DTC registers. Table 8.1 DTC Registers Name Abbreviation R/W Initial Value 1 Address* DTC mode register A MRA Undefined DTC mode register B MRB —* 2 —* 3 —* 3 —* DTC source address register SAR 2 —* Undefined DTC destination address register DAR Undefined DTC transfer count register A CRA 2 —* 2 —* DTC transfer count register B CRB —* Undefined 3 —* 3 —* DTC enable registers DTCER R/W H'00 H'FE16 to H'FE1C DTC vector register DTVECR R/W H'00 H'FE1F Module stop control register MSTPCRA R/W H'3F H'FDE8 2 2 Undefined Undefined 3 —* 3 —* Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot be located in external memory space. When the DTC is used, the RAME bit in SYSCR must be set to 1. Rev. 5.00 Jan 10, 2006 page 185 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.2 Register Descriptions 8.2.1 DTC Mode Register A (MRA) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 Bit 6 SM1 SM0 Description 0 — SAR is fixed 1 0 SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 Bit 4 DM1 DM0 Description 0 — DAR is fixed 1 0 DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Rev. 5.00 Jan 10, 2006 page 186 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 MD1 MD0 Description 0 0 Normal mode 1 Repeat mode 0 Block transfer mode 1 — 1 Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS Description 0 Destination side is repeat area or block area 1 Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz Description 0 Byte-size transfer 1 Word-size transfer Rev. 5.00 Jan 10, 2006 page 187 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.2.2 Bit DTC Mode Register B (MRB) : Initial value: R/W : 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — Undefined — MRB is an 8-bit register that controls the DTC operating mode. Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE Description 0 End of DTC data transfer (activation waiting state is entered) 1 DTC chain transfer (new register information is read, then data is transferred) Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL Description 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) 1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2626 Group and H8S/2623 Group, and should always be written with 0. Rev. 5.00 Jan 10, 2006 page 188 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.2.3 Bit DTC Source Address Register (SAR) 23 : 21 20 19 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — Initial value: R/W 22 : 4 3 2 1 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 Bit DTC Destination Address Register (DAR) : Initial value : R/W : 23 22 21 20 19 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — 4 3 2 1 0 Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev. 5.00 Jan 10, 2006 page 189 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.2.5 Bit DTC Transfer Count Register A (CRA) : Initial value: R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 8.2.6 Bit DTC Transfer Count Register B (CRB) : Initial value: R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev. 5.00 Jan 10, 2006 page 190 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.2.7 Bit DTC Enable Registers (DTCER) : Initial value: R/W : 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERG, with bits corresponding to the interrupt sources that can control enabling and disabling of DTC activation. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn Description 0 DTC activation by this interrupt is disabled (Initial value) [Clearing conditions] 1 • When the DISEL bit is 1 and the data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8.4, together with the vector number generated for each interrupt controller. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. Rev. 5.00 Jan 10, 2006 page 191 of 1042 REJ09B0275-0500 Section 8 Data Transfer Controller (DTC) 8.2.8 Bit DTC Vector Register (DTVECR) : 7 6 5 4 3 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : 0 R/(W)*1 0 0 0 0 0 0 0 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 Notes: 1. Only 1 can be written to the SWDTE bit. 2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE Description 0 DTC software activation is disabled (Initial value) [Clearing conditions] 1 • When the DISEL bit is 0 and the specified number of transfers have not ended • When 0 s written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU DTC software activation is enabled [Holding conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended • During data transfer due to software activation Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) 4 clocks. Figure 13.22 Example of Clocked Synchronous Transmission by DTC Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. If a transition is made during transmission, the data being transmitted will be undefined. When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read -> TDR write -> TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. Figure 13.23 shows a sample flowchart for mode transition during transmission. Port pin states are shown in figures 13.24 and 13.25. Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a transition from transmission by DTC transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start DTC transmission. Rev. 5.00 Jan 10, 2006 page 485 of 1042 REJ09B0275-0500 Section 13 Serial Communication Interface (SCI) • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception. To receive with a different receive mode, the procedure must be started again from initialization. Figure 13.26 shows a sample flowchart for mode transition during reception. No All data transmitted? [1] Yes Read TEND flag in SSR No TEND = 1 Yes TE = 0 [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] If TIE and TEIE are set to 1, clear them to 0 in the same way. [2] Transition to software standby mode, etc. [3] [3] Includes module stop mode, watch mode, subactive mode, and subsleep mode. Exit from software standby mode, etc. Change operating mode? No Yes Initialization TE = 1 Figure 13.23 Sample Flowchart for Mode Transition during Transmission Rev. 5.00 Jan 10, 2006 page 486 of 1042 REJ09B0275-0500 Section 13 Serial Communication Interface (SCI) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 13.24 Asynchronous Transmission Using Internal Clock Start of transmission End of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output Last TxD bit held Marking output Port SCI TxD output Port input/output Port High output* SCI TxD output Note: * Initialized by software standby. Figure 13.25 Synchronous Transmission Using Internal Clock Rev. 5.00 Jan 10, 2006 page 487 of 1042 REJ09B0275-0500 Section 13 Serial Communication Interface (SCI) Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode, watch mode, subactive mode, and subsleep mode. Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? No Yes Initialization RE = 1 Figure 13.26 Sample Flowchart for Mode Transition during Reception Rev. 5.00 Jan 10, 2006 page 488 of 1042 REJ09B0275-0500 Section 13 Serial Communication Interface (SCI) Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (highlevel output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.27) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A Bit 6 4. Low-level output Bit 7 2. TE = 0 3. C/A = 0 CKE1 CKE0 Figure 13.27 Operation when Switching from SCK Pin Function to Port Pin Function Rev. 5.00 Jan 10, 2006 page 489 of 1042 REJ09B0275-0500 Section 13 Serial Communication Interface (SCI) • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level output SCK/port 1. End of transmission Data TE Bit 6 Bit 7 2. TE = 0 4. C/A = 0 C/A 3. CKE1 = 1 CKE1 5. CKE1 = 0 CKE0 Figure 13.28 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output) Rev. 5.00 Jan 10, 2006 page 490 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Section 14 Smart Card Interface 14.1 Overview The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 14.1.1 Features Features of the Smart Card interface supported by the H8S/2626 Group and H8S/2623 Group are as follows. • Asynchronous mode  Data length: 8 bits  Parity bit generation and checking  Transmission of error signal (parity error) in receive mode  Error signal detection and automatic data retransmission in transmit mode  Direct convention and inverse convention both supported • On-chip baud rate generator allows any bit rate to be selected • Three interrupt sources  Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently  The transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (DTC) to execute data transfer Rev. 5.00 Jan 10, 2006 page 491 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.1.2 Block Diagram Bus interface Figure 14.1 shows a block diagram of the Smart Card interface. Module data bus RDR RxD TxD RSR TDR SCMR SSR SCR SMR TSR BRR φ Baud rate generator Transmission/ reception control Parity generation φ/4 φ/16 φ/64 Clock Parity check SCK Legend: SCMR : Smart Card mode register RSR : Receive shift register RDR : Receive data register TSR : Transmit shift register TDR : Transmit data register SMR : Serial mode register SCR : Serial control register SSR : Serial status register BRR : Bit rate register TXI RXI ERI Figure 14.1 Block Diagram of Smart Card Interface Rev. 5.00 Jan 10, 2006 page 492 of 1042 REJ09B0275-0500 Internal data bus Section 14 Smart Card Interface 14.1.3 Pin Configuration Table 14.1 shows the Smart Card interface pin configuration. Table 14.1 Smart Card Interface Pins Channel Pin Name Symbol I/O Function 0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output Serial clock pin 1 SCK1 I/O SCI1 clock input/output Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output 1 2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output Receive data pin 2 RxD2 Input SCI2 receive data input Transmit data pin 2 TxD2 Output SCI2 transmit data output Rev. 5.00 Jan 10, 2006 page 493 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.1.4 Register Configuration Table 14.2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 13, Serial Communication Interface (SCI). Table 14.2 Smart Card Interface Registers Channel Name Abbreviation R/W Initial Value Address* 0 Serial mode register 0 SMR0 R/W H'00 H'FF78 Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A 1 2 Transmit data register 0 TDR0 R/W Serial status register 0 SSR0 R/(W)* Receive data register 0 RDR0 Smart card mode register 0 H'FF H'FF7B H'84 H'FF7C R H'00 H'FF7D SCMR0 R/W H'F2 H'FF7E Serial mode register 1 SMR1 R/W H'00 H'FF80 Bit rate register 1 BRR1 R/W H'FF H'FF81 2 Serial control register 1 SCR1 R/W H'00 H'FF82 Transmit data register 1 TDR1 R/W H'FF H'FF83 Serial status register 1 SSR1 R/(W)* H'84 H'FF84 Receive data register 1 RDR1 R H'00 H'FF85 Smart card mode register 1 SCMR1 R/W H'F2 H'FF86 2 Serial mode register 2 SMR2 R/W H'00 H'FF88 Bit rate register 2 BRR2 R/W H'FF H'FF89 Serial control register 2 SCR2 R/W H'00 H'FF8A Transmit data register 2 TDR2 R/W H'FF H'FF8B SSR2 2 R/(W)* H'84 H'FF8C Serial status register 2 All 1 Receive data register 2 RDR2 R H'00 H'FF8D Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E Module stop control register B MSTPCRB R/W H'FF H'FDE9 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. Rev. 5.00 Jan 10, 2006 page 494 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 14.2.1 Bit Smart Card Mode Register (SCMR) : 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 R/W — — — — R/W R/W — R/W : SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset and in standby mode. Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified. Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR Description 0 TDR contents are transmitted LSB-first (Initial value) Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 14.3.4, Register Settings. Rev. 5.00 Jan 10, 2006 page 495 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Bit 2 SINV Description 0 TDR contents are transmitted as they are (Initial value) Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Bit 1—Reserved: This bit is always read as 1 and cannot be modified. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF Description 0 Smart Card interface function is disabled 1 Smart Card interface function is enabled 14.2.2 Serial Status Register (SSR) Bit : Initial value : R/W Note: (Initial value) : * 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Only 0 can be written, for flag clearing. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Rev. 5.00 Jan 10, 2006 page 496 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Bit 4 ERS Description 0 Normal reception, with no error signal [Clearing conditions] 1 (Initial value) • Upon reset, and in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 Error signal sent from receiver indicating detection of parity error [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND Description 0 Transmission is in progress [Clearing conditions] 1 • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and write data to TDR Transmission has ended (Initial value) [Setting conditions] • Upon reset, and in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is also 0 • When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 • When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 5.00 Jan 10, 2006 page 497 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.2.3 Serial Mode Register (SMR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5. The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 GM Description 0 Normal smart card interface mode operation 1 (Initial value) • TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output ON/OFF control only GSM mode smart card interface mode operation • TEND flag generation 11.0 etu after beginning of start bit • High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) Note: etu: Elementary time unit (time for transfer of 1 bit) Rev. 5.00 Jan 10, 2006 page 498 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK Description 0 Normal Smart Card interface mode operation 1 • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) Block transfer mode operation • Error signal transmission/detection and automatic data retransmission not performed • TXI interrupt generated by TDRE flag • TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) Note: etu: Elementary Time Unit (time for transfer of 1 bit) Bits 3 and 2—Basic Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. Bit 3 Bit 2 BCP1 BCP0 Description 0 1 32 clock periods 0 64 clock periods 1 372 clock periods 0 256 clock periods 1 (Initial value) Bits 5, 4, 1, and 0: Operate in the same way as for the normal SCI. For details, see section 13.2.5, Serial Mode Register (SMR). Rev. 5.00 Jan 10, 2006 page 499 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.2.4 Bit Serial Control Register (SCR) : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 13.2.6, Serial Control Register (SCR). Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. SCMR SMR SMIF C/A A, GM SCR Setting CKE1 SCK Pin Function CKE0 0 See the SCI 1 0 0 0 Operates as port I/O pin 1 0 0 1 Outputs clock as SCK output pin 1 1 0 0 Operates as SCK output pin, with output fixed low 1 1 0 1 Outputs clock as SCK output pin 1 1 1 0 Operates as SCK output pin, with output fixed high 1 1 1 1 Outputs clock as SCK output pin Rev. 5.00 Jan 10, 2006 page 500 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.3 Operation 14.3.1 Overview The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. • If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. (except in block transfer mode) • Only asynchronous communication is supported; there is no clocked synchronous communication function. 14.3.2 Pin Connections Figure 14.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. Rev. 5.00 Jan 10, 2006 page 501 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface VCC TxD I/O RxD SCK Rx (port) H8S/2626 Group or H8S/2623 Group Data line Clock line Reset line CLK RST IC card Connected equipment Figure 14.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev. 5.00 Jan 10, 2006 page 502 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.3.3 Data Format (1) Normal Transfer Mode Figure 14.3 shows the normal Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 DE Transmitting station output Legend: Ds D0 to D7 Dp DE Receiving station output : Start bit : Data bits : Parity bit : Error signal Figure 14.3 Normal Smart Card Interface Data Format Rev. 5.00 Jan 10, 2006 page 503 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. (2) Block Transfer Mode The operation sequence in block transfer mode is as follows. [1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] After reception, a parity error check is carried out, but an error signal is not output even if an error has occurred. When an error occurs reception cannot be continued, so the error flag should be cleared to 0 before the parity bit of the next frame is received. [5] The transmitting station proceeds to transmit the next data frame. Rev. 5.00 Jan 10, 2006 page 504 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.3.4 Register Settings Table 14.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 14.3 Smart Card Interface Register Settings Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMR GM BLK 1 O/E BCP1 BCP0 CKS1 CKS0 BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR0 SCR TIE RIE TE RE 0 0 BRR1 CKE1* TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR TDRE RDRF ORER ERS PER TEND 0 0 RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 SCMR — — — — SDIR SINV — SMIF CKE0 Notes: — : Unused bit. *: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section 14.3.5, Clock. The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer mode. BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 13, Serial Communication Interface (SCI). Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. Rev. 5.00 Jan 10, 2006 page 505 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). • Direct convention (SDIR = SINV = O/E = 0) (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. • Inverse convention (SDIR = SINV = O/E = 1) (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2626 Group and H8S/2623 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). Rev. 5.00 Jan 10, 2006 page 506 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 14.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock frequency is determined by the bit rate and the setting of bits BCP1 and BCP0. B= φ S×2 2n+1 × 10 6 × (N + 1) Where: N = Value set in BRR (0 ≤ N ≤ 255) B = Bit rate (bit/s) φ = Operating frequency (MHz) n = See table 14.4 S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0 Table 14.4 Correspondence between n and CKS1, CKS0 n CKS1 CKS0 0 0 0 1 2 1 1 0 3 1 Table 14.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0 and S = 372) φ (MHz) N 10.00 10.714 13.00 14.285 16.00 18.00 20.00 0 13441 14400 17473 19200 21505 24194 26882 1 6720 7200 8737 9600 10753 12097 13441 2 4480 4800 5824 6400 7168 8065 8961 Note: Bit rates are rounded to the nearest whole number. Rev. 5.00 Jan 10, 2006 page 507 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= φ S×2 2n+1 × 10 – 1 6 ×B Table 14.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372) φ (MHz) bit/s 9600 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 N Error N Error N Error N Error N Error N Error N Error N Error 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60 Table 14.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) φ (MHz) Maximum Bit Rate (bit/s) N n 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 The bit rate error is given by the following formula: Error (%) = ( φ S×2 2n+1 × B × (N + 1) Rev. 5.00 Jan 10, 2006 page 508 of 1042 REJ09B0275-0500 × 10 – 1) × 100 6 Section 14 Smart Card Interface 14.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 bits in SMR. Set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev. 5.00 Jan 10, 2006 page 509 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14.4 shows a flowchart for transmitting, and figure 14.5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 14.6. If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operation (Except Block Transfer Mode) and Data Transfer Operation by DTC below. Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode. Rev. 5.00 Jan 10, 2006 page 510 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 14.4 Example of Transmission Processing Flow Rev. 5.00 Jan 10, 2006 page 511 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface TDR (1) Data write Data 1 (2) Transfer from TDR to TSR Data 1 (3) Serial data output Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 14.5 Relation between Transmit Operation and Internal Registers I/O data Ds D0 D1 D2 TXI (TEND interrupt) When GM = 0 When GM = 1 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu 11.0etu Legend: Ds : Start bit D0 to D7 : Data bits Dp : Parity bit DE : Error signal etu: Elementary Time Unit (time for transfer of 1 bit) Figure 14.6 TEND Flag Generation Timing in Transmission Operation Rev. 5.00 Jan 10, 2006 page 512 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 14.7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 14.7 Example of Reception Processing Flow Rev. 5.00 Jan 10, 2006 page 513 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface With the above processing, interrupt servicing or data transfer by the DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DTC are transferred. For details, see Interrupt Operation (Except Block Transfer Mode) and Data Transfer Operation by DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level: When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 14.8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 14.8 Timing for Fixing Clock Output Level Rev. 5.00 Jan 10, 2006 page 514 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 14.8. Note: For block transfer mode, see section 13.4, SCI Interrupts. Table 14.8 Smart Card Mode Operating States and Interrupt Sources Operating State Flag Enable Bit Interrupt Source DTC Activation Transmit Mode Normal operation TEND TIE TXI Possible Error ERS RIE ERI Not possible Normal operation RDRF RIE RXI Possible Error PER, ORER RIE ERI Not possible Receive Mode Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, TEND remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes, including retransmission in the event of an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller (DTC). In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be Rev. 5.00 Jan 10, 2006 page 515 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Note: For block transfer mode, see section 13.4, SCI Interrupts. 14.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. • When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Make the transition to the software standby state. • When returning to smart card interface mode from software standby mode [6] Exit the software standby state. [7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty. Software standby Normal operation [1] [2] [3] [4] [5] Normal operation [6] [7] Figure 14.9 Clock Halt and Restart Procedure Rev. 5.00 Jan 10, 2006 page 516 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 14.3.8 Operation in Block Transfer Mode Operation in block transfer mode is the same as in SCI asynchronous mode, except for the following points. For details, see section 13.3.2, Operation in Asynchronous Mode. (1) Data Format The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit or more in reception) error guard time. Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. (2) Transmit/Receive Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 14.3.5, Clock. (3) ERS (FER) Flag As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0. Rev. 5.00 Jan 10, 2006 page 517 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface 14.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock. Figure 14.10 shows the receive data sampling timing when using a clock of 372 times the transfer rate. 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 Synchronization sampling timing Data sampling timing Figure 14.10 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) Rev. 5.00 Jan 10, 2006 page 518 of 1042 REJ09B0275-0500 D1 Section 14 Smart Card Interface Thus the reception margin in asynchronous mode is given by the following formula. Formula for reception margin in smart card interface mode M = (0.5 – Where M: N: D: L: F: 1 2N ) – (L – 0.5) F –  D – 0.5 N (1 + F) × 100% Reception margin (%) Ratio of bit rate to clock (N = 32, 64, 372, and 256) Clock duty (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 – 1/2 × 372) × 100% = 49.866% Rev. 5.00 Jan 10, 2006 page 519 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 14.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RDRF [2] [4] [1] [3] PER Figure 14.11 Retransfer Operation in SCI Receive Mode Rev. 5.00 Jan 10, 2006 page 520 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface • Retransfer operation when SCI is in transmit mode Figure 14.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is automatically cleared to 0. nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND [7] [9] FER/ERS [6] [8] Figure 14.12 Retransfer Operation in SCI Transmit Mode Rev. 5.00 Jan 10, 2006 page 521 of 1042 REJ09B0275-0500 Section 14 Smart Card Interface Rev. 5.00 Jan 10, 2006 page 522 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Section 15 Controller Area Network (HCAN) 15.1 Overview The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. The H8S/2626 Group and H8S/2623 Group have a single-channel on-chip HCAN module. Reference: BOSCH CAN Specification Version 2.0 1991, Robert Bosch GmbH 15.1.1 Features • CAN version: Bosch 2.0B active compatible  Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system  Transmission path: Bidirectional 2-wire serial communication  Communication speed: Max. 1 Mbps  Data length: 0 to 8 bytes • Number of channels: 1 • Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) • Data transmission: Choice of two methods:  Mailbox (buffer) number order (low-to-high)  Message priority (identifier) high-to-low order • Data reception: Two methods:  Message identifier match (transmit/receive-setting buffers)  Reception with message identifier masked (receive-only) • CPU interrupts: Five interrupt vectors:  Error interrupt  Reset processing interrupt  Message reception interrupt (mailboxes 1 to 15)  Message reception interrupt (mailbox 0)  Message transmission interrupt • HCAN operating modes: Support for various modes:  Hardware reset  Software reset Rev. 5.00 Jan 10, 2006 page 523 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN)  Normal status (error-active, error-passive)  Bus off status  HCAN configuration mode  HCAN sleep mode  HCAN halt mode • Other features: DTC can be activated by message reception mailbox (HCAN mailbox 0 only) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the HCAN. MBI Message buffer Peripheral data bus Peripheral address bus HCAN Mailboxes Message control Message data MC0–MC15, MD0–MD15 LAFM (CDLC) CAN Data Link Controller Bosch CAN 2.0B active Tx buffer MPI Microprocessor interface Rx buffer HTxD HRxD CPU interface Control register Status register Figure 15.1 HCAN Block Diagram Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, statuses, and so forth. CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and other functions. Rev. 5.00 Jan 10, 2006 page 524 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.1.3 Pin Configuration Table 15.1 shows the HCAN’s pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 15.1 HCAN Pins Name Abbreviation Input/Output Function HCAN transmit data pin HTxD Output CAN bus transmission pin HCAN receive data pin HRxD Input CAN bus reception pin A bus driver is necessary between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended. Rev. 5.00 Jan 10, 2006 page 525 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.1.4 Register Configuration Table 15.2 lists the HCAN’s registers. Table 15.2 HCAN Registers Name Abbreviation R/W Initial Value Address* Access Size Master control register MCR R/W H'01 H'F800 8 bits 16 bits General status register GSR R/W H'0C H'F801 8 bits Bit configuration register BCR R/W H'0000 H'F802 8/16 bits Mailbox configuration register MBCR R/W H'0100 H'F804 8/16 bits Transmit wait register TXPR R/W H'0000 H'F806 8/16 bits Transmit wait cancel register TXCR R/W H'0000 H'F808 8/16 bits Transmit acknowledge register TXACK R/W H'0000 H'F80A 8/16 bits Abort acknowledge register ABACK R/W H'0000 H'F80C 8/16 bits Receive complete register RXPR R/W H'0000 H'F80E 8/16 bits Remote request register RFPR R/W H'0000 H'F810 8/16 bits Interrupt register IRR R/W H'0100 H'F812 8/16 bits Mailbox interrupt mask register MBIMR R/W H'FFFF H'F814 8/16 bits Interrupt mask register IMR R/W H'FEFF H'F816 8/16 bits Receive error counter REC R H'00 H'F818 8 bits 16 bits Transmit error counter TEC R H'00 H'F819 8 bits Unread message status register UMSR R/W H'0000 H'F81A 8/16 bits Local acceptance filter mask L LAFML R/W H'0000 H'F81C 8/16 bits Local acceptance filter mask H LAFMH R/W H'0000 H'F81E 8/16 bits Rev. 5.00 Jan 10, 2006 page 526 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Name Abbreviation R/W Initial Value Address* Access Size Message control 0 [1:8] MC0 [1:8] R/W Undefined H'F820 8/16 bits Message control 1 [1:8] MC1 [1:8] R/W Undefined H'F828 8/16 bits Message control 2 [1:8] MC2 [1:8] R/W Undefined H'F830 8/16 bits Message control 3 [1:8] MC3 [1:8] R/W Undefined H'F838 8/16 bits Message control 4 [1:8] MC4 [1:8] R/W Undefined H'F840 8/16 bits Message control 5 [1:8] MC5 [1:8] R/W Undefined H'F848 8/16 bits Message control 6 [1:8] MC6 [1:8] R/W Undefined H'F850 8/16 bits Message control 7 [1:8] MC7 [1:8] R/W Undefined H'F858 8/16 bits Message control 8 [1:8] MC8 [1:8] R/W Undefined H'F860 8/16 bits Message control 9 [1:8] MC9 [1:8] R/W Undefined H'F868 8/16 bits Message control 10 [1:8] MC10 [1:8] R/W Undefined H'F870 8/16 bits Message control 11 [1:8] MC11 [1:8] R/W Undefined H'F878 8/16 bits Message control 12 [1:8] MC12 [1:8] R/W Undefined H'F880 8/16 bits Message control 13 [1:8] MC13 [1:8] R/W Undefined H'F888 8/16 bits Message control 14 [1:8] MC14 [1:8] R/W Undefined H'F890 8/16 bits Message control 15 [1:8] MC15 [1:8] R/W Undefined H'F898 8/16 bits Message data 0 [1:8] MD0 [1:8] R/W Undefined H'F8B0 8/16 bits Message data 1 [1:8] MD1 [1:8] R/W Undefined H'F8B8 8/16 bits Message data 2 [1:8] MD2 [1:8] R/W Undefined H'F8C0 8/16 bits Message data 3 [1:8] MD3 [1:8] R/W Undefined H'F8C8 8/16 bits Message data 4 [1:8] MD4 [1:8] R/W Undefined H'F8D0 8/16 bits Message data 5 [1:8] MD5 [1:8] R/W Undefined H'F8D8 8/16 bits Message data 6 [1:8] MD6 [1:8] R/W Undefined H'F8E0 8/16 bits Message data 7 [1:8] MD7 [1:8] R/W Undefined H'F8E8 8/16 bits Message data 8 [1:8] MD8 [1:8] R/W Undefined H'F8F0 8/16 bits Message data 9 [1:8] MD9 [1:8] R/W Undefined H'F8F8 8/16 bits Message data 10 [1:8] MD10 [1:8] R/W Undefined H'F900 8/16 bits Message data 11 [1:8] MD11 [1:8] R/W Undefined H'F908 8/16 bits Message data 12 [1:8] MD12 [1:8] R/W Undefined H'F910 8/16 bits Message data 13 [1:8] MD13 [1:8] R/W Undefined H'F918 8/16 bits Message data 14 [1:8] MD14 [1:8] R/W Undefined H'F920 8/16 bits Message data 15 [1:8] MD15 [1:8] R/W Undefined H'F928 8/16 bits Module stop control register C MSTPCRC R/W H'FF H'FDEA 8/16 bits Note: * Lower 16 bits of the address. Rev. 5.00 Jan 10, 2006 page 527 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2 Register Descriptions 15.2.1 Master Control Register (MCR) The master control register (MCR) is an 8-bit readable/writable register that controls the CAN interface. MCR Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 MCR7 — MCR5 — — MCR2 MCR1 MCR0 0 0 0 0 0 0 0 1 R/W R R/W R R R/W R/W R/W Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by bus operation. Bit 7 MCR7 Description 0 HCAN sleep mode release by CAN bus operation disabled 1 HCAN sleep mode release by CAN bus operation enabled (Initial value) Bit 6—Reserved: This bit always reads 0. The write value should always be 0. Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition. Bit 5 MCR5 Description 0 HCAN sleep mode released 1 Transition to HCAN sleep mode enabled (Initial value) Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0. Rev. 5.00 Jan 10, 2006 page 528 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit messages. Bit 2 MCR2 Description 0 Transmission order determined by message identifier priority 1 Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) (Initial value) Bit 1—Halt Request (MCR1): Controls halting of the HCAN module. Bit 1 MCR1 Description 0 HCAN normal operating mode 1 HCAN halt mode transition request (Initial value) Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module. Bit 0 MCR0 Description 0 Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset 1 HCAN reset mode transition request (Initial value) In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0 is cleared to 0. Rev. 5.00 Jan 10, 2006 page 529 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.2 General Status Register (GSR) The general status register (GSR) is an 8-bit readable register that indicates the status of the CAN bus. GSR Bit: 7 6 5 4 3 2 1 0 — — — — GSR3 GSR2 GSR1 GSR0 Initial value: 0 0 0 0 1 1 0 0 R/W: R R R R R R R R Bits 7 to 4—Reserved: These bits always read 0. Bit 3—Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating state or the reset state. Writes are invalid. Bit 3 GSR3 Description 0 Normal operating state [Setting condition] After an HCAN internal reset 1 Configuration mode [Reset condition] MCR0 reset mode and sleep mode (Initial value) Bit 2—Message Transmission Status Flag (GSR2): Flag that indicates whether the module is currently in the message transmission period. The “message transmission period” is the period from the start of message transmission (SOF) until the end of a 3-bit intermission interval after EOF (End of Frame). Writes are invalid. Bit 2 GSR2 Description 0 Message transmission period 1 [Reset Condition] Idle period Rev. 5.00 Jan 10, 2006 page 530 of 1042 REJ09B0275-0500 (Initial value) Section 15 Controller Area Network (HCAN) Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. Writes are invalid. Bit 1 GSR1 Description 0 [Reset condition] When TEC < 96 and REC < 96 or TEC ≥ 256 (Initial value) When TEC ≥ 96 or REC ≥ 96 1 Bit 0—Bus Off Flag (GSR0): Flag that indicates the bus off state. Writes are invalid. Bit 0 GSR0 Description 0 [Reset condition] Recovery from bus off state 15.2.3 (Initial value) When TEC ≥ 256 (bus off state) 1 Bit Configuration Register (BCR) The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN bit timing parameters and the baud rate prescaler. BCR Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 531 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bits 15 and 14—Resynchronization Jump Width (SJW): These bits set the bit synchronization range. Bit 15 Bit 14 BCR7 BCR6 Description 0 0 Bit synchronization width = 1 time quantum 1 Bit synchronization width = 2 time quanta 1 0 Bit synchronization width = 3 time quanta 1 Bit synchronization width = 4 time quanta (Initial value) Bits 13 to 8—Baud Rate Prescaler (BRP): These bits are used to set the CAN bus baud rate. Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 Description 0 0 0 0 0 0 2 × system clock 0 0 0 0 0 1 4 × system clock 0 0 0 0 1 0 6 × system clock ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 1 1 1 1 1 1 (Initial value) ⋅ ⋅ ⋅ 128 × system clock Bit 7—Bit Sample Point (BSP): Sets the point at which data is sampled. Bit 7 BCR15 Description 0 Bit sampling at one point (end of time segment 1 (TSEG1)) 1 Bit sampling at three points (end of TSEG1 and preceding and following time quantum) Rev. 5.00 Jan 10, 2006 page 532 of 1042 REJ09B0275-0500 (Initial value) Section 15 Controller Area Network (HCAN) Bits 6 to 4—Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1bit time error. A value from 2 to 8 can be set. Bit 6 Bit 5 Bit 4 BCR14 BCR13 BCR12 Description 0 0 0 Setting prohibited 1 TSEG2 = 2 time quanta 1 1 0 1 (Initial value) 0 TSEG2 = 3 time quanta 1 TSEG2 = 4 time quanta 0 TSEG2 = 5 time quanta 1 TSEG2 = 6 time quanta 0 TSEG2 = 7 time quanta 1 TSEG2 = 8 time quanta Bits 3 to 0—Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 1 to 16 can be set. Bit 3 Bit 2 Bit 1 Bit 0 BCR11 BCR10 BCR9 BCR8 Description 0 0 0 0 Setting prohibited 0 0 0 1 Setting prohibited 0 0 1 0 Setting prohibited 0 0 1 1 TSEG1 = 4 time quanta 0 1 0 0 TSEG1 = 5 time quanta ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 1 1 1 1 (Initial value) ⋅ ⋅ ⋅ TSEG1 = 16 time quanta Rev. 5.00 Jan 10, 2006 page 533 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.4 Mailbox Configuration Register (MBCR) The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set mailbox (buffer) transmission/reception. MBCR Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 — 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 MBCR9 MBCR8 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 15 to 9 and 7 to 0—Mailbox Setting Register (MBCR7 to MBCR1, MBCR15 to MBCR8): These bits set the polarity of the corresponding mailboxes. Bit x MBCRx Description 0 Corresponding mailbox is set for transmission 1 Corresponding mailbox is set for reception Bit 8—Reserved: This bit always reads 1. The write value should always be 1. Rev. 5.00 Jan 10, 2006 page 534 of 1042 REJ09B0275-0500 (Initial value) Section 15 Controller Area Network (HCAN) 15.2.5 Transmit Wait Register (TXPR) The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). TXPR Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 Initial value: R/W: TXPR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 15 to 9 and 7 to 0—Transmit Wait Register (TXPR7 to TXPR1, TXPR15 to TXPR8): These bits set a transmit wait for the corresponding mailboxes. Bit x TXPRx Description 0 Transmit message idle state in corresponding mailbox (Initial value) [Clearing condition] Message transmission completion and cancellation completion 1 Transmit message transmit wait in corresponding mailbox (CAN bus arbitration) Bit 8—Reserved: This bit always reads 0. The write value should always be 0. Rev. 5.00 Jan 10, 2006 page 535 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.6 Transmit Wait Cancel Register (TXCR) The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls cancellation of transmit wait messages in mailboxes (buffers). TXCR Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 Initial value: R/W: TXCR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register (TXCR7 to TXCR1, TXCR15 to TXCR8): These bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes. Bit x TXCRx Description 0 Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing condition] Completion of TXPR clearing (when transmit message is canceled normally) 1 TXPR cleared for corresponding mailbox (transmit message cancellation) Bit 8—Reserved: This bit always reads 0. The write value should always be 0. Rev. 5.00 Jan 10, 2006 page 536 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.7 Transmit Acknowledge Register (TXACK) The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing status flags that indicate normal transmission of mailbox (buffer) transmit messages. TXACK Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 — 0 R/(W)* 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R 7 6 5 4 3 2 1 0 Bit: TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 Initial value: R/W: Note: * TXACK8 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Can only be written with 1 for flag clearing. Bits 15 to 9 and 7 to 0—Transmit Acknowledge Register (TXACK7 to TXACK1, TXACK15 to TXACK8): These bits indicate that a transmit message in the corresponding HCAN mailbox has been transmitted normally. Bit x TXACKx Description 0 [Clearing condition] Writing 1 1 (Initial value) Completion of message transmission for corresponding mailbox Bit 8—Reserved: This bit always reads 0. The write value should always be 0. Rev. 5.00 Jan 10, 2006 page 537 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.8 Abort Acknowledge Register (ABACK) The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages. ABACK Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 — 0 R/(W)* 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R 7 6 5 4 3 2 1 0 Bit: ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value: R/W: Note: * 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Can only be written with 1 for flag clearing. Bits 15 to 9 and 7 to 0—Abort Acknowledge Register (ABACK7 to ABACK1, ABACK15 to ABACK8): These bits indicate that a transmit message in the corresponding mailbox has been canceled (aborted) normally. Bit x ABACKx Description 0 [Clearing condition] Writing 1 1 Completion of transmit message cancellation for corresponding mailbox Bit 8—Reserved: This bit always reads 0. The write value should always be 0. Rev. 5.00 Jan 10, 2006 page 538 of 1042 REJ09B0275-0500 (Initial value) Section 15 Controller Area Network (HCAN) 15.2.9 Receive Complete Register (RXPR) The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers). In the case of remote frame reception, the corresponding remote request register (RFPR) is also set simultaneously. RXPR Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 0 R/(W)* 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 Bit: RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 Initial value: R/W: Note: * RXPR8 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Can only be written with 1 for flag clearing. Bits 15 to 0—Receive Complete Register (RXPR7 to RXPR0, RXPR15 to RXPR8): These bits indicate that a receive message has been received normally in the corresponding mailbox. Bit x RXPRx Description 0 [Clearing condition] Writing 1 1 (Initial value) Completion of message (data frame or remote frame) reception in corresponding mailbox Rev. 5.00 Jan 10, 2006 page 539 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.10 Remote Request Register (RFPR) The remote request register (RFPR) is a 16-bit readable/writable register containing status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set, the corresponding reception complete bit is set simultaneously. RFPR Bit: 15 14 13 12 11 10 9 8 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 Initial value: R/W: Bit: RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 Initial value: R/W: Note: * RFPR8 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Can only be written with 1 for flag clearing. Bits 15 to 0—Remote Request Register (RFPR7 to PFPR0, RFPR15 to PFDR8): These bits indicate that a remote frame has been received normally in the corresponding mailbox. Bit x RFPRx Description 0 [Clearing condition] Writing 1 1 Completion of remote frame reception in corresponding mailbox Rev. 5.00 Jan 10, 2006 page 540 of 1042 REJ09B0275-0500 (Initial value) Section 15 Controller Area Network (HCAN) 15.2.11 Interrupt Register (IRR) The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the various interrupt sources. IRR Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 0 R/(W)* 0 0 0 0 0 0 1 R/(W)* R/(W)* R/(W)* R/(W)* R R R/(W)* 7 6 5 4 3 2 1 0 — — — IRR12 — — IRR9 IRR8 Bit: Note: Initial value: 0 0 0 0 0 0 0 0 R/W: — — — R/(W)* — — R R/(W)* * Can only be written with 1 for flag clearing. Bit 15—Overload Frame/Bus Off Recovery Interrupt Flag (IRR7): Status flag indicating that the HCAN has transmitted an overload frame or recovered from the bus off state. Bit 15 IRR7 Description 0 [Clearing condition] Writing 1 1 (Initial value) Overload frame transmission or recovery from bus off state [Setting conditions] Error active/passive state • When overload frame is transmitted Bus off state • When 11 recessive bits is received 128 times (REC ≥ 128) Rev. 5.00 Jan 10, 2006 page 541 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bit 14—Bus Off Interrupt Flag (IRR6): Status flag indicating the bus off state caused by the transmit error counter. Bit 14 IRR6 Description 0 [Clearing condition] 1 Bus off state caused by transmit error Writing 1 (Initial value) [Setting condition] When TEC ≥ 256 Bit 13—Error Passive Interrupt Flag (IRR5): Status flag indicating the error passive state caused by the transmit/receive error counter. Bit 13 IRR5 Description 0 [Clearing condition] Writing 1 1 (Initial value) Error passive state caused by transmit/receive error [Setting condition] When TEC ≥ 128 or REC ≥ 128 Bit 12—Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error warning state caused by the receive error counter. Bit 12 IRR4 Description 0 [Clearing condition] Writing 1 1 Error warning state caused by receive error [Setting condition] When REC ≥ 96 Rev. 5.00 Jan 10, 2006 page 542 of 1042 REJ09B0275-0500 (Initial value) Section 15 Controller Area Network (HCAN) Bit 11—Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error warning state caused by the transmit error counter. Bit 11 IRR3 Description 0 [Clearing condition] Writing 1 1 (Initial value) Error warning state caused by transmit error [Setting condition] When TEC ≥ 96 Bit 10—Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote frame has been received in a mailbox (buffer). Bit 10 IRR2 Description 0 [Clearing condition] Clearing of all bits in RFPR (remote request register) of mailbox for which receive interrupt requests are enabled by MBIMR (Initial value) 1 Remote frame received and stored in mailbox [Setting conditions] When remote frame reception is completed, when corresponding MBIMR = 0 Bit 9—Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer) receive message has been received normally. Bit 9 IRR1 Description 0 [Clearing condition] Clearing of all bits in RXPR (receive complete register) of mailbox for which receive interrupt requests are enabled by MBIMR (Initial value) 1 Data frame or remote frame received and stored in mailbox [Setting conditions] When data frame or remote frame reception is completed, when corresponding MBIMR = 0 Rev. 5.00 Jan 10, 2006 page 543 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after reset input or recovery from software standby mode, interrupt handling will be performed as soon as interrupts are enabled by the interrupt controller. Bit 8 IRR0 Description 0 [Clearing condition] Writing 1 Hardware reset (HCAN module stop*, software standby) 1 (Initial value) [Setting condition] When reset processing is completed after a hardware reset (HCAN module stop*, software standby) Note: * After reset or hardware standby release, the module stop bit is initialized to 1, and so the HCAN enters the module stop state. Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0. Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. Bit 4 IRR12 Description 0 CAN bus idle state (Initial value) [Clearing condition] Writing 1 1 CAN bus operation in HCAN sleep mode [Setting condition] Bus operation (dominant bit detection) in HCAN sleep mode Bit 1—Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been overwritten while still unread. Rev. 5.00 Jan 10, 2006 page 544 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bit 1 IRR9 Description 0 [Clearing condition] Clearing of all bits in UMSR (unread message status register) 1 (Initial value) Unread message overwrite [Setting condition] When UMSR (unread message status register) is set Bit 0—Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit message can be stored in the mailbox. Bit 0 IRR8 Description 0 [Clearing condition] Writing 1 1 (Initial value) Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort 15.2.12 Mailbox Interrupt Mask Register (MBIMR) The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing flags that enable or disable individual mailbox (buffer) interrupt requests. MBIMR Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 Initial value: R/W: MBIMR8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 545 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bits 15 to 0—Mailbox Interrupt Mask (MBIMRx) (MBIMR7 to MBIMR0, MBIMR15 to MBIMR8): Flags that enable or disable individual mailbox interrupt requests. Bit x MBIMRx Description 0 [Transmitting] Interrupt request to CPU due to TXPR clearing [Receiving] Interrupt request to CPU due to RXPR setting 1 Interrupt requests to CPU disabled (Initial value) 15.2.13 Interrupt Mask Register (IMR) The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that enable or disable requests by individual interrupt sources. IMR Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — 1 1 1 1 1 1 1 0 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 — — — IMR12 — — IMR9 IMR8 Initial value: 1 1 1 1 1 1 1 1 R/W: R R R R/W R R R/W R/W Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables overload frame/bus off recovery interrupt requests. Bit 15 IMR7 Description 0 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 enabled 1 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 disabled (Initial value) Rev. 5.00 Jan 10, 2006 page 546 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused by the transmit error counter. Bit 14 IMR6 Description 0 Bus off interrupt request (ERS0) to CPU by IRR6 enabled 1 Bus off interrupt request (ERS0) to CPU by IRR6 disabled (Initial value) Bit 13—Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt requests caused by the transmit/receive error counter. Bit 13 IMR5 Description 0 Error passive interrupt request (ERS0) to CPU by IRR5 enabled 1 Error passive interrupt request (ERS0) to CPU by IRR5 disabled (Initial value) Bit 12—Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning interrupt requests caused by the receive error counter. Bit 12 IMR4 Description 0 REC error warning interrupt request (OVR0) to CPU by IRR4 enabled 1 REC error warning interrupt request (OVR0) to CPU by IRR4 disabled (Initial value) Bit 11—Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error warning interrupt requests caused by the transmit error counter. Bit 11 IMR3 Description 0 TEC error warning interrupt request (OVR0) to by IRR3 CPU enabled 1 TEC error warning interrupt request (OVR0) to by IRR3 CPU disabled (Initial value) Rev. 5.00 Jan 10, 2006 page 547 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bit 10—Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame reception interrupt requests. Bit 10 IMR2 Description 0 Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled 1 Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled (Initial value) Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception interrupt requests. Bit 9 IMR1 Description 0 Message reception interrupt request (RM1) to CPU by IRR1 enabled 1 Message reception interrupt request (RM1) to CPU by IRR1 disabled (Initial value) Bit 8—Reserved: This bit always reads 0. The write value should always be 0. Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1. Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to bus operation in sleep mode. Bit 4 IMR12 Description 0 Bus operation interrupt request (OVR0) to CPU by IRR12 enabled 1 Bus operation interrupt request (OVR0) to CPU by IRR12 disabled (Initial value) Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite interrupt requests. Bit 1 IMR9 Description 0 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 enabled 1 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 disabled (Initial value) Rev. 5.00 Jan 10, 2006 page 548 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt requests. Bit 0 IMR8 Description 0 Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled 1 Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled (Initial value) 15.2.14 Receive Error Counter (REC) The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. REC Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R 15.2.15 Transmit Error Counter (TEC) The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. TEC Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Rev. 5.00 Jan 10, 2006 page 549 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.16 Unread Message Status Register (UMSR) The unread message status register (UMSR) is a 16-bit readable/writable register containing status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new receive message before being read. When a message is overwritten by a new receive message, the old data is lost. UMSR Bit: Initial value: R/W: Bit: Initial value: R/W: Note: * 15 14 13 12 11 10 9 8 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 0 R/(W)* 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 0 R/(W)* 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Can only be written with 1 for flag clearing. Bits 15 to 0—Unread Message Status Flags (UMSR7 to UMSR0, UMSR15 to UMSR8): Status flags indicating that an unread receive message has been overwritten. Bit x UMSRx Description 0 [Clearing condition] Writing 1 1 (Initial value) Unread receive message is overwritten by a new message [Setting condition] When a new message is received before RXPR is cleared x = 0 to 15 Rev. 5.00 Jan 10, 2006 page 550 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that filter receive messages to be stored in the receive-only mailbox (MC0, MD0) according to the identifier. In these registers, consist of LAFMH15 (MSB) to LAFMH5 (LSB) are 11 standard/extended identifier bits, and LAFMH1 (MSB) to LAFML0 (LSB) are 18 extended identifier bits. LAFML Bit: Initial value: R/W: Bit: 15 14 13 12 11 10 9 8 LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 Initial value: R/W: 0 LAFML8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 — — — LAFMH Bit: LAFMH7 LAFMH6 LAFMH5 Initial value: R/W: Bit: LAFMH1 LAFMH0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R R/W R/W 7 6 5 4 3 2 1 0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 551 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) LAFMH Bits 7 to 0 and 15 to 13—11-Bit Identifier Filter (LAFMH7 to LAFMH5, LAFMH15 to LAFMH8): Filter mask bits for the first 11 bits of the receive message identifier (for both standard and extended identifiers). Bit x LAFMHx Description 0 Stored in MC0, MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) 1 Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be 0. LAFMH Bits 9 and 8, LAFML Bits 15 to 0—18-Bit Identifier Filter (LAFMH1, LAFMH0, LAFML7 to LAFML0, LAFML15 to LAFML8): Filter mask bits for the 18 bits of the receive message identifier (extended). Bit x LAFMHx LAFMLx Description 0 Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Initial value) 1 Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier Rev. 5.00 Jan 10, 2006 page 552 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.18 Message Control (MC0 to MC15) The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers (MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MCx [1] Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 — — — — DLC3 DLC2 DLC1 DLC0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — — — — — — — * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — — — — — — — MCx [2] Bit: Initial value: R/W: MCx [3] Bit: Initial value: R/W: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W MCx [4] Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 — — — — — — — — * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 553 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) MCx [5] Bit: 7 6 5 R/W: 3 2 1 0 RTR IDE — * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 STD_ID2 STD_ID1 STD_ID0 Initial value: 4 EXD_ID17 EXD_ID16 MCx [6] Bit: STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 Initial value: R/W: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MCx [7] Bit: EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value: R/W: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MCx [8] Bit: EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value: R/W: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined x = 0 to 15 MCx[1] Bits 7 to 4—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). Rev. 5.00 Jan 10, 2006 page 554 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) MCx[1] Bits 3 to 0—Data Length Code (DLC): These bits indicate the required length of data frames and remote frames. Bit 3 Bit 2 Bit 1 Bit 0 DLC3 DLC2 DLC1 DLC0 Description 0 0 0 0 Data length = 0 bytes 1 Data length = 1 byte 0 Data length = 2 bytes 1 Data length = 3 bytes 0 Data length = 4 bytes 1 Data length = 5 bytes 0 Data length = 6 bytes 1 Data length = 7 bytes 0/1 Data length = 8 bytes 1 1 0 1 1 0/1 0/1 MCx[2] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[3] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[4] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). MCx[6] Bits 7 to 0—Standard Identifier (STD_ID10 to STD_ID3): MCx[5] Bits 7 to 5—Standard Identifier (STD_ID2 to STD_ID0): These bits set the identifier (standard identifier) of data frames and remote frames. Standard identifier SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR SRR IDE STD_IDxx Figure 15.2 Standard Identifier Rev. 5.00 Jan 10, 2006 page 555 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) MCx[5] Bit 4—Remote Transmission Request (RTR): Used to distinguish between data frames and remote frames. Bit 4 RTR Description 0 Data frame 1 Remote frame MCx[5] Bit 3—Identifier Extension (IDE): Used to distinguish between the standard format and extended format of data frames and remote frames. Bit 3 IDE Description 0 Standard format 1 Extended format MCx[5] Bit 2—Reserved: The initial value of this bit is undefined; it must be initialized (by writing 0 or 1). MCx[5] Bits 1 and 0—Extended Identifier (EXD_ID17, EXD_ID16): MCx[8] Bits 7 to 0—Extended Identifier (EXD_ID15 to EXD_ID8): MCx[7] Bits 7 to 0—Extended Identifier (EXD_ID7 to EXD_ID0): These bits set the identifier (extended identifier) of data frames and remote frames. Extended Identifier IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 EXD_IDxx ID4 ID3 ID2 ID1 ID0 RTR EXD_IDxx Figure 15.3 Extended Identifier Rev. 5.00 Jan 10, 2006 page 556 of 1042 REJ09B0275-0500 R1 ID7 ID6 ID5 Section 15 Controller Area Network (HCAN) 15.2.19 Message Data (MD0 to MD15) The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers (MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15). The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1). MDx [1] Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W: MDx [2] R/W: MDx [3] Bit: Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx [4] R/W: Rev. 5.00 Jan 10, 2006 page 557 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) MDx [5] Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R/W: MDx [6] R/W: MDx [7] Bit: Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W: MDx [8] R/W: *: Undefined x = 0 to 15 Rev. 5.00 Jan 10, 2006 page 558 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.2.20 Module Stop Control Register C (MSTPCRC) Bit: 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value: R/W: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC3 bit is set to 1, HCAN operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bit 3—Module Stop (MSTPC3): Specifies the HCAN module stop mode. Bit 3 MSTPC3 Description 0 HCAN module stop mode is cleared 1 HCAN module stop mode is set (Initial value) Rev. 5.00 Jan 10, 2006 page 559 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.3 Operation 15.3.1 Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization is performed by automatic setting of the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR within the HCAN (hardware reset). At the same time, all internal registers are initialized. However mailbox contents are retained. A flowchart of this reset is shown in figure 15.4. Note: * In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the HCAN enters the module stop state. Software Reset (Write to MCR0): In normal operation initialization is performed by setting the MCR reset request bit (MCR0) in MCR (Software reset). With this kind of reset, if the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until the message has been completed. During initialization, the reset state bit (GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are initialized but other registers and RAM (mailboxes) are not. A flowchart of this reset is shown in figure 15.5. Rev. 5.00 Jan 10, 2006 page 560 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Hardware reset MCR0 = 1 (automatic) IRR0 = 1 (automatic)*1 GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Period in which BCR, MBCR, etc., are initialized Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? No Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Notes: 1. When IRR0 is set to 1 (automatically) due to a hardware reset*2, a "hardware reset initiated reset processing" interrupt is generated. 2. In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the HCAN enters the module stop state. Figure 15.4 Hardware Reset Flowchart Rev. 5.00 Jan 10, 2006 page 561 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) MCR0 = 1 Bus idle? No Yes GSR3 = 1 (automatic) Initialization of REC and TEC only BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? Correction No Yes MCR0 = 0 GSR3 = 0? No Yes IMR setting MBIMR setting MC[x] setting LAFM setting OK? Correction No Yes GSR3 = 0 & 11 recessive bits received? Yes CAN bus communication enabled No : Settings by user : Processing by hardware Figure 15.5 Software Reset Flowchart Rev. 5.00 Jan 10, 2006 page 562 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.3.2 Initialization after Hardware Reset After a hardware reset, the following initialization processing should be carried out: • Clearing of IRR0 bit in interrupt register (IRR) • Bit rate setting • Mailbox transmit/receive settings • Mailbox (RAM) initialization • Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up sequence then begins, and communication with the CAN bus is possible as soon as the sequence ends. The power-up sequence consists of the detection of 11 consecutive recessive bits. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR). a. Note BCR can be written to at all times, but should only be modified in configuration mode. Settings should be made so that all CAN controllers connected to the CAN bus have the same baud rate and bit width. Refer to table 15.3 for the range of values that can be used as settings (TSEG1, TSEG2, BRP, sample point, and SJW) for BCR. Rev. 5.00 Jan 10, 2006 page 563 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Table 15.3 BCR Register Value Setting Ranges Name Abbreviation Min. Value Max. Value Time segment 1 TSEG1 B'0000 B'1111 Time segment 2 TSEG2 B'000 B'111 Baud rate prescaler BRP B'000000 B'111111 Sample point SAM B'0 B'1 Re-synchronization jump width SJW B'00 B'11 b. Value Setting Ranges • The bit width consists of the total of the settable Time Quanta (TQ). TQ (number of system clocks) is determined by the baud rate prescaler (BRP). TQ = 2 × (BRP + 1) fCLK • The value of SJW is stipulated in the CAN specifications. 3 ≥ SJW ≥ 0 • The minimum value of TSEG1 is stipulated in the CAN specifications. TSEG1 > TSEG2 • The minimum value of TSEG2 is stipulated in the CAN specifications. TSEG2 ≥ SJW The following formula is used to calculate the baud rate. Bit rate [b/s] = fCLK 2 × (BRP + 1) × (3 + TSEG1 + TSEG2) Note: fCLK = φ (system clock) The BCR values are used for BRP, TSEG1, and TSEG2. Example: With a 1 Mb/s baud rate and a 20 MHz input clock: 1 Mb/s = 20 MHz 2 × (0 + 1) × (3 + 4 + 3) Rev. 5.00 Jan 10, 2006 page 564 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Item Set Values Actual Values fCLK 20 MHz — BRP 0 (B'000000) System clock × 2 TSEG1 4 (B'0100) 5TQ TSEG2 3 (B'011) 4TQ 1-bit time 1-bit time (8–25 time quanta) SYNC_SEG PRSEG PHSEG1 TSEG1 (time segment 1)* 2 to 16 1 PHSEG2 TSEG2 (time segment 2)* Quantum 2 to 8 Legend: SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for compensating for physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (resynchronization) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (resynchronization) is established.) Note: * The Time Quanta value for TSEG1 and TSEG2 is the TSEG value + 1. Figure 15.6 Detailed Description of One Bit HCAN bit rate calculation: Bit rate = fCLK 2 × (BRP + 1) × (3 + TSEG1 + TSEG2) Note: fCLK = φ (system clock) The BCR values are used for BRP, TSEG1, and TSEG2. BCR Setting Constraints TSEG1 > TSEG2 ≥ SJW (SJW = 0 to 3) TSEG2 > B'001 (BRP = B'000000) TSEG2 > B'000 (BRP > B'000000) Rev. 5.00 Jan 10, 2006 page 565 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) These constraints allow the setting range shown in table 15.4 for TSEG1 and TSEG2 in BCR. Table 15.4 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR [14:12]) TSEG1 (BCR [11:8]) 0011 0100 001 010 011 100 101 110 111 No Yes* Yes No No No No No Yes Yes No No No No Yes Yes Yes No No No 0110 Yes* Yes* Yes Yes Yes Yes No No 0111 Yes* Yes Yes Yes Yes Yes No 1000 Yes* Yes Yes Yes Yes Yes Yes 1001 Yes* Yes Yes Yes Yes Yes Yes 1010 Yes Yes Yes Yes Yes Yes 1011 Yes* Yes* Yes Yes Yes Yes Yes Yes 1100 Yes* Yes Yes Yes Yes Yes Yes 1101 Yes* Yes Yes Yes Yes Yes Yes 1110 Yes* Yes Yes Yes Yes Yes Yes 1111 Yes* Yes Yes Yes Yes Yes Yes 0101 Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1. * Setting is enabled except when BRP [13:8] = B'000000. Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receiveonly, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set for transmission or reception must be designated either for transmission use or for reception use before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software reset. • Setting for transmission Transmit mailbox setting (mailboxes 1 to 15) Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so this setting is not necessary. • Setting for reception Transmit/receive mailbox setting (mailboxes 1 to 15) Rev. 5.00 Jan 10, 2006 page 566 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding mailbox for reception use. When setting mailboxes for reception, to improve message transmission efficiency, high-priority messages should be set in low-to-high mailbox order (priority order: mailbox 1 (MCx[1]) > mailbox 15 (MCx[15]). • Receive-only mailbox (mailbox 0) No setting is necessary, as this mailbox is always used for reception. Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings: After power is supplied, all registers and RAM (message control/data, control registers, status registers, etc.) are initialized. Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: Either of the following message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority When a is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found and stored in the transmit buffer. When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. Rev. 5.00 Jan 10, 2006 page 567 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.3.3 Transmit Mode Message transmission is performed using mailboxes 1 to 15. The transmission procedure is described below, and a transmission flowchart is shown in figure 15.7. Initialization (after hardware reset only) a. Clearing of IRR0 bit in interrupt register (IRR) b. Bit rate settings c. Mailbox transmit/receive settings d. Mailbox initialization e. Message transmission method setting Interrupt and transmit data settings a. CPU interrupt source setting b. Arbitration field setting c. Control field setting d. Data field setting Message transmission and interrupts a. Message transmission wait b. Message transmission completion and interrupt c. Message transmission abort d. Message retransmission Rev. 5.00 Jan 10, 2006 page 568 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Initialization (After Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. • IRR0 clearing The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. • Bit rate settings Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit Rate and Bit Timing Settings in 15.3.2, Initialization after Hardware Reset, for details. • Mailbox transmit/receive settings Mailbox transmit/receive settings should be made in advance. A total of 15 mailboxes can be set for transmission or reception (mailboxes 1 to 15). To set a mailbox for transmission, clear the corresponding bit to 0 in the mailbox configuration register (MBCR). Refer to Mailbox Transmit/Receive Settings in 15.3.2, Initialization after Hardware Reset, for details. • Mailbox initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings in 15.3.2, Initialization after Hardware Reset, for details. • Message transmission method setting Set the transmission method for mailboxes designated for transmission. The following two transmission methods can be used. Refer to Setting the Message Transmission Method in 15.3.2, Initialization after Hardware Reset, for details. a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority Rev. 5.00 Jan 10, 2006 page 569 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Initialization (after hardware reset only) IRR0 clearing BCR setting MBCR setting Mailbox initialization Message transmission method setting Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle? No Yes Message transmission GSR2 = 0 (during transmission only) Transmission completed? No Yes TXACK = 1 IRR8 = 1 IMR8 = 1? Yes No Interrupt to CPU Clear TXACK Clear IRR8 : Settings by user End of transmission Figure 15.7 Transmission Flowchart Rev. 5.00 Jan 10, 2006 page 570 of 1042 REJ09B0275-0500 : Processing by hardware Section 15 Controller Area Network (HCAN) Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt source settings and data settings must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are made by writing the necessary data from the arbitration field, control field, and data field, described below, in the corresponding message control (MCx[1]–MCx[8]) and message data (MDx[1]–MDx[8]). • CPU interrupt source settings Transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). • Arbitration field setting In the arbitration field, the 11-bit identifier (STD_ID0–STD_ID10) and RTR bit (standard format) or 29-bit identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) and IDE.RTR bit (extended format) are set. The registers to be set are MCx[5]–MCx[8]. • Control field setting In the control field, the byte length of the data to be transmitted is set in DLC0–DLC3. The register to be set is MCx[1]. • Data field setting In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The registers to be set are MDx[1]–MDx[8]. The number of bytes in the data actually transmitted depends on the data length code (DLC) in the control field. If a value exceeding the value set in DLC is set in the data field, only the number of bytes set in DLC will actually be transmitted. Message Transmission and Interrupts: • Message transmission wait If message transmission is to be performed after completion of the message control (MCx[1]– MCx[8]) and message data (MDx[1]–MDx[8]) settings, transmission is started by setting the corresponding mailbox transmit wait bit (TXPR1–TXPR15) to 1 in the transmit wait register (TXPR). The following two transmission methods can be used: a. Transmission order determined by message identifier priority b. Transmission order determined by mailbox number priority When a is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order: Rev. 5.00 Jan 10, 2006 page 571 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit buffer, and message transmission is performed when the bus is acquired. When b is selected, if a number of messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit buffer, and message transmission is performed when the transmission right is acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the same way, and message transmission is performed when the transmission right is acquired. • Message transmission completion and interrupt When a message is transmitted error-free using the above procedure, the corresponding acknowledge bit (TXACK1–TXACK15) in the transmit acknowledge register (TXACK) and transmit wait bit (TXPR1–TXPR15) in the transmit wait register (TXPR) are automatically initialized. Also, if the corresponding bit (MBIMR1–MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the interrupt enable state at the same time, an interrupt can be sent to the CPU. • Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1–TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested. Also, if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1–MBIMR15) corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: a. During internal arbitration or CAN bus arbitration b. During data frame or remote frame transmission Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure 15.8 shows a flowchart of transmit message cancellation. • Message retransmission If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: a. CAN bus arbitration failure (failure to acquire the bus) b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error) Rev. 5.00 Jan 10, 2006 page 572 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Message transmit wait TXPR setting Set TXCR bit corresponding to message to be canceled Cancellation possible? No Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 IMR8 = 1? Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1 Yes No Interrupt to CPU Clear TXACK Clear ABACK Clear IRR8 : Settings by user End of transmission/transmission cancellation : Processing by hardware Figure 15.8 Transmit Message Cancellation Flowchart Rev. 5.00 Jan 10, 2006 page 573 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.3.4 Receive Mode Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is described below, and a reception flowchart is shown in figure 15.9. Initialization (after hardware reset only) a. Clearing of IRR0 bit in interrupt register (IRR) b. Bit rate settings c. Mailbox transmit/receive settings d. Mailbox (RAM) initialization Interrupt and receive message settings a. CPU interrupt source setting b. Arbitration field setting c. Local acceptance filter mask (LAFM) settings Message reception and interrupts a. Message reception CRC check b. Data frame reception c. Remote frame reception d. Unread message reception Initialization (After Hardware Reset Only): These settings should be made while the HCAN is in bit configuration mode. • IRR0 clearing The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. • Bit rate settings Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit Rate and Bit Timing Setting in 15.3.2, Initialization after Hardware Reset, for details. • Mailbox transmit/receive settings Each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for reception. Thus a total of 16 mailboxes can be used for reception. To set a mailbox for reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The Rev. 5.00 Jan 10, 2006 page 574 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) initial setting for mailboxes is 0, designating transmission use. Refer to Mailbox transmit/receive settings in 15.3.2, Initialization after Hardware Reset, for details. • Mailbox (RAM) initialization As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings in 15.3.2, Initialization after a Hardware Reset, for details. Rev. 5.00 Jan 10, 2006 page 575 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) : Settings by user Initialization IRR0 clearing BCR setting MBCR setting Mailbox (RAM) initialization : Processing by hardware Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings Message reception (Match of identifier in mailbox?) No Yes Same RXPR = 1? Yes No Unread message No Data frame? Yes RXPR IRR1 = 1 RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 Yes IMR1 = 1? IMR2 = 1? No No Interrupt to CPU Interrupt to CPU Message control read Message data read Message control read Message data read Clear all RXPRn bits of mailbox for which receive interrupt requests are enabled by MBIMR Clear all RXPRn bits of mailbox for which receive interrupt requests are enabled by MBIMR IRR1 = 0 IRR2 = 0, IRR1 = 0 Transmission of data frame corresponding to remote frame End of reception Figure 15.9 Reception Flowchart Rev. 5.00 Jan 10, 2006 page 576 of 1042 REJ09B0275-0500 Yes Section 15 Controller Area Network (HCAN) Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt source settings and receive message specifications must be made. Interrupt source settings are made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a message, the identifier must be set in advance in the message control (MCx[1]–MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox 0 (MC0[x], MD0[x]) has a local acceptance filter mask (LAFM) that allows Don’t care settings to be made. • CPU interrupt source settings When transmitting, transmission acknowledge and transmission abort acknowledge interrupts can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR). When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt register (IRR) interrupts can be masked in the interrupt mask register (IMR). • Arbitration field setting In the arbitration field, the identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) of the message to be received is set. If all the bits in the set identifier do not match, the message is not stored in a mailbox. Example: Mailbox 1 010_1010_1010 (standard identifier) Only one kind of message identifier can be received by MB1 Identifier 1: 010_1010_1010 • Local acceptance filter mask (LAFM) setting The local acceptance filter mask is provided for mailbox 0 (MC0[x], MD0[x]) only, enabling a Don’t care specification to be made for all bits in the received identifier. This allows various kinds of messages to be received. Example: Mailbox 0 LAFM 010_1010_1010 (standard identifier) 000_0000_0011 (0: Care, 1: Don’t care) A total of four kinds of message identifiers can be received by MB0 Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011 Rev. 5.00 Jan 10, 2006 page 577 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Message Reception and Interrupts: • Message reception CRC check When a message is received, a CRC check is performed automatically (by hardware). If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether or not the message can be received. • Data frame reception If the received message is confirmed to be error-free by the CRC check, etc., the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared, and if a complete match is found, the message is stored in the mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0–RXPR15) is set in the receive complete register (RXPR). However, when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received by another mailbox (however, the same message cannot be stored in more than one of mailboxes 1 to 15). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox interrupt mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. • Remote frame reception Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A remote frame differs from a data frame in that the remote reception request bit (RTR) in the message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned in a data frame must be stored in the data length code (DLC) in the control field. When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote request wait register (RFPR). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. • Unread message reception When the identifier in a mailbox matches a receive message, the message is stored in the mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding bit (UMSR0–UMSR15) is set in the unread message register (UMSR). In overwriting of an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the Rev. 5.00 Jan 10, 2006 page 578 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Figure 15.10 shows a flowchart of unread message overwriting. Unread message overwrite UMSR = 1 IRR9 = 1 IMR9 = 1? Yes No Interrupt to CPU Clear IRR9 Message control/message data read : Settings by user End : Processing by hardware Figure 15.10 Unread Message Overwrite Flowchart 15.3.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state to reduce current dissipation. Figure 15.11 shows a flowchart of the HCAN sleep mode. Rev. 5.00 Jan 10, 2006 page 579 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) MCR5 = 1 Bus idle? No Yes Initialize TEC and REC Bus operation? No Yes IRR12 = 1 IMR12 = 1? No CPU interrupt Yes Sleep mode clearing method MCR7 = 0? No (automatic) Yes (manual) MCR5 = 0 Clear sleep mode? No Yes MCR5=0 11 recessive bits? Yes CAN bus communication possible No : Settings by user : Processing by hardware Figure 15.11 HCAN Sleep Mode Flowchart Rev. 5.00 Jan 10, 2006 page 580 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected by making a setting in the MCR7 bit. 1. Clearing by software 2. Clearing by CAN bus operation Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus communication is enabled again. Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not received in the mailbox, and normal reception starts from the next message. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Rev. 5.00 Jan 10, 2006 page 581 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.3.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 15.12 shows a flowchart of the HCAN halt mode. MCR1 = 1 Bus idle? No Yes MBCR setting MCR1 = 0 : Settings by user CAN bus communication possible : Processing by hardware Figure 15.12 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. Rev. 5.00 Jan 10, 2006 page 582 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.3.7 Interrupt Interface There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned. Table 15.5 lists the HCAN interrupt sources. With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). Table 15.5 HCAN Interrupt Sources IPR Bits Vector Vector Number IRR Bit Description IPRM (6–4) ERS0 104 IRR5 Error passive interrupt (TEC ≥ 128 or REC ≥ 128) IRR6 Bus off interrupt (TEC ≥ 256) OVR0 105 IRR0 Hardware reset processing interrupt IRR2 Remote frame reception interrupt IRR3 Error warning interrupt (TEC ≥ 96) IRR4 Error warning interrupt (REC ≥ 96) IRR7 Overload frame transmission interrupt/bus off recovery interrupt (11 recessive bits × 128 times) IRR9 Unread message overwrite interrupt IRR12 HCAN sleep mode CAN bus operation interrupt IPRM (2–0) RM0 106 IRR1 Mailbox 0 message reception interrupt RM1 107 IRR1 Mailbox 1–15 message reception interrupt SLE0 108 IRR8 Message transmission/cancellation interrupt Rev. 5.00 Jan 10, 2006 page 583 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 15.3.8 DTC Interface The DTC can be activated by reception of a message in the HCAN’s mailbox 0. When DTC transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent to the CPU in this case. Figure 15.13 shows a DTC transfer flowchart. DTC initialization DTC enable register setting DTC register information setting Message reception in HCAN’s mailbox 0 DTC activation End of DTC transfer? No Yes RXPR and RFPR clearing Transfer counter = 0 or DISEL = 1? No Yes Interrupt to CPU : Settings by user End Figure 15.13 DTC Transfer Flowchart Rev. 5.00 Jan 10, 2006 page 584 of 1042 REJ09B0275-0500 : Processing by hardware Section 15 Controller Area Network (HCAN) 15.4 CAN Bus Interface A bus transceiver IC is necessary to connect the H8S/2626 Group or H8S/2623 Group chip to a CAN bus. A Philips PCA82C250 transceiver IC, or compatible device, is recommended. Figure 15.14 shows a sample connection diagram. H8S/2626 Group or H8S/2623 Group 124 Ω Vcc PCA82C250 RS Vcc HRxD RxD CANH HTxD TxD CANL Vref CAN bus GND No connection 124 Ω Figure 15.14 High-Speed Interface Using PCA82C250 15.5 Usage Notes 1. Reset The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data (MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization must always be carried out after a reset or a transition to hardware standby mode or software standby mode. Also, the reset interrupt flag (IRR0) is always set after reset input or recovery from software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if HCAN interrupts are set as enabled by the interrupt controller without this flag having been cleared, an HCAN interrupt will be initiated immediately. IRR0 must therefore be cleared during initialization. 2. HCAN sleep mode The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode Rev. 5.00 Jan 10, 2006 page 585 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode. 3. Interrupts When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8.2.1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. 4. Error counters In the case of error active and error passive, REC and TEC normally count up and down. In the bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set. 5. Register access Byte or word access can be used on all HCAN registers. Longword access cannot be used. 6. HCAN medium-speed mode HCAN registers cannot be read or written to in medium-speed mode. 7. Register retention during standby All HCAN registers are initialized in hardware standby mode and software standby mode. 8. Using bit operation instructions Start flags in HCAN are cleared by writing 1 to them; there is no need to use bit operation instructions to clear them. To clear a flag, use the MOV instruction to write a 1 to the bit to be cleared. 9. HTxD pin output in error passive state If the HRxD pin becomes fixed at 1 during message transmission or reception when the HCAN is in the error active state, the HTxD pin will output 0 continuously while in the error passive state. To stop continuous 0 output to the CAN bus, disable the HCAN by means of an error warning interrupt or by setting the HCAN module stop mode through detection of a fixed 1 state by the HxRD pin monitor. 10. Transition to HCAN sleep mode The HCAN stops (transmission/reception stops) when MCR0 is cleared to 0 immediately after an HCAN sleep mode transition effected by setting TXPR of the HCAN to 1 and setting MCR5 to 1. When a transition is made to the HCAN sleep mode by means of the above steps, a 10-cycle wait should be inserted after the TxPR setting. After an HCAN sleep mode transition, release the HCAN sleep mode by clearing MCR5 to 0. Rev. 5.00 Jan 10, 2006 page 586 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) 11. Message transmission cancellation (TxCR) If all the following conditions are met when cancellation of a transmission message is performed by means of TxCR of the HCAN, the TxCR or TxPR bit indicating cancellation is not cleared even though internal transmission is canceled. When canceling a message using TxCR, 1 should be written continuously until TxCR or TxPR becomes 0. 12. TxCR in the bus off state If TxPR is set before the HCAN goes to the bus off state, and a transition is made to the bus off state with transmission incomplete, cancellation will be performed even if TxCR is set during the bus off period, and the message will be transmitted after a transition to the error active state. Rev. 5.00 Jan 10, 2006 page 587 of 1042 REJ09B0275-0500 Section 15 Controller Area Network (HCAN) Rev. 5.00 Jan 10, 2006 page 588 of 1042 REJ09B0275-0500 Section 16 A/D Converter Section 16 A/D Converter 16.1 Overview The H8S/2626 Group and H8S/2623 Group include a successive approximation type 10-bit A/D converter that allows up to sixteen analog input channels to be selected. 16.1.1 Features A/D converter features are listed below. • 10-bit resolution • Sixteen input channels • Settable analog conversion voltage range  Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference voltage • High-speed conversion  Minimum conversion time: 13.3 µs per channel (at 20-MHz operation) • Choice of single mode or scan mode  Single mode: Single-channel A/D conversion  Scan mode: Continuous A/D conversion on 1 to 4 channels • Four data registers  Conversion results are held in a 16-bit data register for each channel • Sample and hold function • Three kinds of conversion start  Choice of software or timer conversion start trigger (TPU), or ADTRG pin • A/D conversion end interrupt generation  A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion • Module stop mode can be set  As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. Rev. 5.00 Jan 10, 2006 page 589 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the A/D converter. Module data bus Vref 10-bit D/A AVSS A D D R A A D D R B A D D R C A D D R D A D C S R A D C R φ/2 + – Multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Bus interface Successive approximations register AVCC Internal data bus Comparator φ/4 Control circuit φ/8 Sample-andhold circuit φ/16 ADI interrupt ADTRG Conversion start trigger from TPU ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 16.1 Block Diagram of A/D Converter Rev. 5.00 Jan 10, 2006 page 590 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.1.3 Pin Configuration Table 16.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The 16 analog input pins are divided into two channel sets and two groups, with analog input pins 0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 15 (AN8 to AN15) comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11) comprising group 0, and analog input pins 4 to 7 and 12 to 15 (AN4 to AN7, AN12 to AN15) comprising group 1. Table 16.1 A/D Converter Pins Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and reference voltage Reference voltage pin Vref Input A/D conversion reference voltage Analog input pin 0 AN0 Input Channel set 0 (CH3 = 0) group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input pin 8 AN8 Input Analog input pin 9 AN9 Input Analog input pin 10 AN10 Input Analog input pin 11 AN11 Input Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog input pin 14 AN14 Input Analog input pin 15 AN15 Input A/D external trigger input pin ADTRG Input Channel set 0 (CH3 = 0) group 1 analog inputs Channel set 1 (CH3 = 1) group 0 analog inputs Channel set 1 (CH3 = 1) group 1 analog inputs External trigger input for starting A/D conversion Rev. 5.00 Jan 10, 2006 page 591 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.1.4 Register Configuration Table 16.2 summarizes the registers of the A/D converter. Table 16.2 A/D Converter Registers Name Abbreviation R/W Initial Value 1 Address* A/D data register AH ADDRAH R H'00 H'FF90 A/D data register AL ADDRAL R H'00 H'FF91 A/D data register BH ADDRBH R H'00 H'FF92 A/D data register BL ADDRBL R H'00 H'FF93 A/D data register CH ADDRCH R H'00 H'FF94 A/D data register CL ADDRCL R H'00 H'FF95 A/D data register DH ADDRDH R H'00 H'FF96 A/D data register DL ADDRDL R H'00 H'FF97 ADCSR 2 R/(W)* H'00 H'FF98 A/D control register ADCR R/W H'33 H'FF99 Module stop control register A MSTPCRA R/W H'3F H'FDE8 A/D control/status register Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 592 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.2 Register Descriptions 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 16.3. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 16.3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1) Group 0 Group 1 Group 0 Group 1 A/D Data Register AN0 AN4 AN8 AN12 ADDRA AN1 AN5 AN9 AN13 ADDRB AN2 AN6 AN10 AN14 ADDRC AN3 AN7 AN11 AN15 ADDRD Rev. 5.00 Jan 10, 2006 page 593 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.2.2 A/D Control/Status Register (ADCSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF Description 0 [Clearing conditions] 1 • When 0 is written to the ADF flag after reading ADF = 1 • When the DTC is activated by an ADI interrupt and ADDR is read (Initial value) [Setting conditions] • Single mode: When A/D conversion ends • Scan mode: When A/D conversion ends on all specified channels Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE Description 0 A/D conversion end interrupt (ADI) request disabled 1 A/D conversion end interrupt (ADI) request enabled Rev. 5.00 Jan 10, 2006 page 594 of 1042 REJ09B0275-0500 (Initial value) Section 16 A/D Converter Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description 0 • A/D conversion stopped 1 • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends • Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. (Initial value) Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 16.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN Description 0 Single mode 1 Scan mode (Initial value) Bit 3—Channel Select 3 (CH3): Switches the analog input pins assigned to group 0 or group 1. Setting CH3 to 1 enables AN8 to AN15 to be used instead of AN0 to AN7. Bit 3 CH3 Description 0 AN8 to AN11 are group 0 analog input pins, AN12 to AN15 are group 1 analog input pins 1 AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins (Initial value) Rev. 5.00 Jan 10, 2006 page 595 of 1042 REJ09B0275-0500 Section 16 A/D Converter Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Channel Selection Description CH3 CH2 CH1 CH0 Single Mode (SCAN = 0) Scan Mode (SCAN = 1) 0 0 0 0 AN0 AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 0 AN8 AN8 1 AN9 AN8, AN9 1 1 0 1 1 0 0 1 1 0 1 (Initial value) 0 AN10 AN8 to AN10 1 AN11 AN8 to AN11 0 AN12 AN12 1 AN13 AN12, AN13 0 AN14 AN12 to AN14 1 AN15 AN12 to AN15 Rev. 5.00 Jan 10, 2006 page 596 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.2.3 A/D Control Register (ADCR) Bit 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — CKS1 CKS0 — — : 0 0 1 1 0 0 1 1 R/W R/W — — R/W R/W — — Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations and sets the A/D conversion time. ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 Bit 6 TRGS1 TRGS0 Description 0 0 A/D conversion start by software is enabled 1 A/D conversion start by TPU conversion start trigger is enabled 1 (Initial value) 0 Setting prohibited 1 A/D conversion start by external trigger pin (ADTRG) is enabled Bits 5, 4, 1, and 0—Reserved: These bits are always read as 1 and cannot be modified. Bits 3 and 2—Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time. The conversion time should be changed only when ADST = 0. Make a setting that gives a value not lower than that shown in table 22-8. Bit 3 Bit 2 CKS1 CKS0 Description 0 0 Conversion time = 530 states (max.) 1 Conversion time = 266 states (max.) 0 Conversion time = 134 states (max.) 1 Conversion time = 68 states (max.) 1 (Initial value) Rev. 5.00 Jan 10, 2006 page 597 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.2.4 Bit Module Stop Control Register A (MSTPCRA) : 7 6 5 4 3 2 0 1 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 8-bit readable/writable register that performs module stop mode control. When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see sections 21A.5, 21B.5, Module Stop Mode. MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 1—Module Stop (MSTPA1): Specifies the A/D converter module stop mode. Bit 1 MSTPA1 Description 0 A/D converter module stop mode cleared 1 A/D converter module stop mode set Rev. 5.00 Jan 10, 2006 page 598 of 1042 REJ09B0275-0500 (Initial value) Section 16 A/D Converter 16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 16.2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 16.2 ADDR Access Operation (Reading H'AA40) Rev. 5.00 Jan 10, 2006 page 599 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 16.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 16.3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH3 = 0, CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. Rev. 5.00 Jan 10, 2006 page 600 of 1042 REJ09B0275-0500 Section 16 A/D Converter Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 16.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 5.00 Jan 10, 2006 page 601 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 16.4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 5.00 Jan 10, 2006 page 602 of 1042 REJ09B0275-0500 Section 16 A/D Converter Continuous A/D conversion execution Clear*1 Set*1 ADST Clear*1 ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) Idle Idle A/D conversion 1 Idle Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer ADDRA A/D conversion result 4 A/D conversion result 1 ADDRB A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 16.4 Example of A/D Converter Operation (Scan Mode, 3 Channels AN0 to AN2 Selected) Rev. 5.00 Jan 10, 2006 page 603 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16.5 shows the A/D conversion timing. Table 16.4 indicates the A/D conversion time. As indicated in figure 16.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 16.4. In scan mode, the values given in table 16.4 apply to the first conversion time. The values given in table 16.5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0 in ADCR to give a value not lower than that shown in table 22-8. (1) φ (2) Address Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1) : (2) : tD : tSPL : tCONV : ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time Figure 16.5 A/D Conversion Timing Rev. 5.00 Jan 10, 2006 page 604 of 1042 REJ09B0275-0500 Section 16 A/D Converter Table 16.4 A/D Conversion Time (Single Mode) CKS1 = 0 Item Symbol CKS0 = 0 Min CKS1 = 0 CKS0 = 1 Typ Max Min CKS0 = 0 Typ Max Min CKS0 = 1 Typ Max Min Typ Max A/D conversion start delay tD 18 — 33 10 — 17 6 — 9 4 — 5 Input sampling time tSPL — 127 — — 63 — — 31 — — 15 — A/D conversion time tCONV 515 — 530 259 — 266 131 — 134 67 — 68 Note: Values in the table are the number of states. Table 16.5 A/D Conversion Time (Scan Mode) CKS1 CKS0 Conversion Time (State) 0 0 512 (Fixed) 1 256 (Fixed) 0 128 (Fixed) 1 64 (Fixed) 1 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 16.6 shows the timing. Rev. 5.00 Jan 10, 2006 page 605 of 1042 REJ09B0275-0500 Section 16 A/D Converter φ ADTRG Internal trigger signal ADST A/D conversion Figure 16.6 External Trigger Input Timing 16.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 16.6. Table 16.6 A/D Converter Interrupt Source Interrupt Source Description DTC Activation ADI Interrupt due to end of conversion Possible Rev. 5.00 Jan 10, 2006 page 606 of 1042 REJ09B0275-0500 Section 16 A/D Converter 16.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the Vref pin set in the range Vref ≤ AVCC. If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), analog reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 16.7. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN15 must be connected to AVSS. If a filter capacitor is connected as shown in figure 16.7, the input currents at the analog input pins (AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the Rev. 5.00 Jan 10, 2006 page 607 of 1042 REJ09B0275-0500 Section 16 A/D Converter sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref 100 Ω Rin* 2 *1 AN0 to AN15 *1 0.1 µF AVSS Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 16.7 Example of Analog Input Protection Circuit Table 16.7 Analog Pin Specifications Item Min Max Unit Analog input capacitance — 20 pF Permissible signal source impedance — 5 kΩ Rev. 5.00 Jan 10, 2006 page 608 of 1042 REJ09B0275-0500 Section 16 A/D Converter 10 kΩ AN0 to AN15 To A/D converter 20 pF Note: Values are reference values. Figure 16.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2626 Group and H8S/2623 Group A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'00) to B'0000000001 (H'01) (see figure 16.10). • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see figure 16.10). • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.9). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. • Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 5.00 Jan 10, 2006 page 609 of 1042 REJ09B0275-0500 Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 Quantization error 010 001 000 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 16.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 16.10 A/D Conversion Precision Definitions (2) Rev. 5.00 Jan 10, 2006 page 610 of 1042 REJ09B0275-0500 Section 16 A/D Converter Permissible Signal Source Impedance: H8S/2626 Group and H8S/2623 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less. This specification is provided to enable the A/D converter’s sampleand-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8S/2626 Group or H8S/2623 Group Sensor output impedance to 5 kΩ A/D converter equivalent circuit 10 kΩ Sensor input Low-pass filter C to 0.1 µF Cin = 15 pF 20 pF Figure 16.11 Example of Analog Input Circuit Rev. 5.00 Jan 10, 2006 page 611 of 1042 REJ09B0275-0500 Section 16 A/D Converter Rev. 5.00 Jan 10, 2006 page 612 of 1042 REJ09B0275-0500 Section 17 D/A Converter [Provided in the H8S/2626 Group only] Section 17 D/A Converter [Provided in the H8S/2626 Group only] 17.1 Overview The H8S/2626 Group has an on-chip two-channel D/A converter. 17.1.1 Features The D/A converter has the following features. • 8-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20 pF capacitive load) • Output voltage: 0 V to Vref • D/A output retention in software standby mode • Module stop mode setting possible  The initial setting is for D/A converter operation to be halted. Register access is enabled by clearing module stop mode. Rev. 5.00 Jan 10, 2006 page 613 of 1042 REJ09B0275-0500 Section 17 D/A Converter [Provided in the H8S/2626 Group only] 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the D/A converter. Internal data bus Bus interface Module data bus 8-bit D/A DA2 DACR23 DA3 DADR3 AVCC DADR2 Vref AVSS Control circuit Legend: DACR23: D/A control register 23 DADR2, DADR3: D/A data registers 2 and 3 Figure 17.1 Block Diagram of D/A Converter Rev. 5.00 Jan 10, 2006 page 614 of 1042 REJ09B0275-0500 Section 17 D/A Converter [Provided in the H8S/2626 Group only] 17.1.3 Pin Configuration Table 17.1 summarizes the input and output pins used by the D/A converter. Table 17.1 D/A Converter Pins Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog power supply Analog ground pin AVSS Input Analog ground and reference voltage Analog output pin 2 DA2 Output Channel 2 analog output Analog output pin 3 DA3 Output Channel 3 analog output Reference voltage pin Vref Input Analog reference voltage 17.1.4 Register Configuration Table 17.2 summarizes the registers of the D/A converter. Table 17.2 D/A Converter Registers Channel Name Abbreviation R/W Initial Value Address* 2, 3 D/A data register 2 DADR2 R/W H'00 H'FDAC All Note: * D/A data register 3 DADR3 R/W H'00 H'FDAD D/A control register 23 DACR23 R/W H'1F H'FDAE Module stop control register C MSTPCRC R/W H'FF H'FDEA Lower 16 bits of the address Rev. 5.00 Jan 10, 2006 page 615 of 1042 REJ09B0275-0500 Section 17 D/A Converter [Provided in the H8S/2626 Group only] 17.2 Register Descriptions 17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DADR2 and DADR3 are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the values in DADR2 and DADR3 are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset and in hardware standby mode. 17.2.2 Bit D/A Control Register 23 (DACR23) : Initial value : R/W : 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — 0 0 0 1 1 1 1 1 R/W R/W R/W — — — — — DACR23 is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR23 is initialized to H'1F by a reset and in hardware standby mode. Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description 0 DA3 analog output is disabled 1 Channel 3 D/A conversion and DA3 analog output are enabled Rev. 5.00 Jan 10, 2006 page 616 of 1042 REJ09B0275-0500 (Initial value) Section 17 D/A Converter [Provided in the H8S/2626 Group only] Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 DA2 analog output is disabled 1 Channel 2 D/A conversion and DA2 analog output are enabled (Initial value) Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 2 and 3. When the DAE bit is set to 1, D/A conversion is controlled together in channels 2 and 3. Output of the conversion result is always controlled independently by bits DAOE0 and DAOE1. Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE Description 0 0 * D/A conversion is disabled in channels 2 and 3 (Initial value) 1 0 D/A conversion is enabled in channel 2 D/A conversion is disabled in channel 3 0 0 1 D/A conversion is enabled in channels 2 and 3 0 D/A conversion is disabled in channel 2 D/A conversion is enabled in channel 3 1 1 D/A conversion is enabled in channels 2 and 3 * D/A conversion is enabled in channels 2 and 3 *: Don’t care If the chip enters software standby mode while D/A conversion is enabled, the D/A output is retained and the analog power supply current is the same as the analog power supply current during D/A conversion. If it is necessary to reduce the analog power supply current in software standby mode, D/A output should be disabled by clearing both the DAOE0 bit and the DAOE1 bit to 0. Bits 4 to 0—Reserved: These bits are always read as 1, and cannot be modified. Rev. 5.00 Jan 10, 2006 page 617 of 1042 REJ09B0275-0500 Section 17 D/A Converter [Provided in the H8S/2626 Group only] 17.2.3 Bit Module Stop Control Register C (MSTPCRC) : 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCRC is an 8-bit readable/writable register that performs module stop mode control. When the MSTPC5 bit is set to 1, D/A converter operation is stopped at the end of the bus cycle, and module stop mode is entered. Register read/write accesses are not possible in module stop mode. For details, see section 21B.5, Module Stop Mode. MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 5—Module Stop (MSTPC5): Specifies module stop mode for the D/A converter (channels 2 and 3). Bit 5 MSTPC5 Description 0 D/A converter (channels 2 and 3) module stop mode is cleared 1 D/A converter (channels 2 and 3) module stop mode is set 17.3 (Initial value) Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR23. If the DADR2 or DADR3 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 2 is given below. The timing is shown in figure 17.2. 1. Data to be converted is written in DADR2. 2. Bit DAOE0 is set to 1 in DACR23. D/A conversion starts and DA2 becomes an output pin. The conversion result is output after the conversion time. The output value is (DADR2 contents/256) × Vref. Output of this conversion result continues until the value in DADR2 is modified or the DAOE0 bit is cleared to 0. Rev. 5.00 Jan 10, 2006 page 618 of 1042 REJ09B0275-0500 Section 17 D/A Converter [Provided in the H8S/2626 Group only] 3. If the DADR2 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA2 becomes an input pin. DADR2 write cycle DADR2 write cycle DACR23 write cycle DACR23 write cycle φ Address DADR2 Conversion data 1 Conversion data 2 DAOE0 DA2 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 17.2 Example of D/A Converter Operation Rev. 5.00 Jan 10, 2006 page 619 of 1042 REJ09B0275-0500 Section 17 D/A Converter [Provided in the H8S/2626 Group only] Rev. 5.00 Jan 10, 2006 page 620 of 1042 REJ09B0275-0500 Section 18 RAM Section 18 RAM 18.1 Overview The H8S/2626 and H8S/2623 have 12 kbytes of on-chip high-speed static RAM, the H8S/2625 and H8S/2622 have 8 kbytes, and the H8S/2624 and H8S/2621 have 4 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 18.1.1 Block Diagram Figure 18.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFC000 H'FFC001 H'FFC002 H'FFC003 H'FFC004 H'FFC005 H'FFEFBE H'FFEFBF H'FFFFC0 H'FFFFC1 H'FFFFFE H'FFFFFF Figure 18.1 Block Diagram of RAM (H8S/2623) Rev. 5.00 Jan 10, 2006 page 621 of 1042 REJ09B0275-0500 Section 18 RAM 18.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 18.1 shows the address and initial value of SYSCR. Table 18.1 RAM Register Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'01 H'FDE5 Note: * Lower 16 bits of the address. 18.2 Register Descriptions 18.2.1 System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 MACS — INTM1 INTM0 NMIEG — — RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W — R/W The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Note: When the DTC is used, the RAME bit must be set to 1. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled Rev. 5.00 Jan 10, 2006 page 622 of 1042 REJ09B0275-0500 (Initial value) Section 18 RAM 18.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2626 and H8S/2623, to addresses H'FFD000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2625 and H8S/2622, and to addresses H'FFE000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2624 and H8S/2621, are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 18.4 Usage Notes When Using the DTC: DTC register information can be located in addresses H'FFEBC0 to H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0. Reserved Areas: Addresses H'FFB000 to H'FFBFFF in the H8S/2626 and H8S/2623, H'FFB000 to H'FFCFFF in the H8S/2625 and H8S/2622, and H'FFB000 to H'FFDFFF in the H8S/2624 and H8S/2621, are reserved areas that cannot be read or written to. When the RAME bit is cleared to 0, external address space is accessed. Rev. 5.00 Jan 10, 2006 page 623 of 1042 REJ09B0275-0500 Section 18 RAM Rev. 5.00 Jan 10, 2006 page 624 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Section 19 ROM (Preliminary) 19.1 Features The H8S/2626 Group and H8S/2623 Group have 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can be performed. To erase the entire flash memory, each block must be erased in turn. Block erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks. • Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming, equivalent to 78 µs (typ.) per byte, and the erase time is 100 ms (typ.). • Reprogramming capability The flash memory can be reprogrammed up to 100 times. • On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board:  Boot mode  User program mode • Automatic bit rate adjustment With data transfer in boot mode, the LSI’s bit rate can be automatically adjusted to match the transfer bit rate of the host. • Flash memory emulation in RAM Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory. • Protect modes There are three protect modes, hardware, software, and error protection which allow protected status to be designated for flash memory program/erase/verify operations. Rev. 5.00 Jan 10, 2006 page 625 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. 19.2 Overview 19.2.1 Block Diagram Internal address bus Module bus Internal data bus (16 bits) FLMCR1 FLMCR2 EBR1 Bus interface/controller Operating mode EBR2 RAMER FLPWCR Flash memory (256 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 19.1 Block Diagram of Flash Memory Rev. 5.00 Jan 10, 2006 page 626 of 1042 REJ09B0275-0500 FWE pin Mode pin Section 19 ROM (Preliminary) 19.2.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. MD1 = 1, MD2 = 1, FWE = 0 *1 RES = 0 User mode (on-chip ROM enabled) FWE = 1 Reset state RES = 0 MD1 = 1, MD2 = 1, FWE = 1 RES = 0 FWE = 0 User program mode *2 MD1 = 1, MD2 = 0, FWE = 1 RES = 0 Programmer mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1 Figure 19.2 Flash Memory State Transitions Rev. 5.00 Jan 10, 2006 page 627 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.2.3 On-Board Programming Modes Boot Mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the H8S/2626 or H8S/2623 (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program LSI LSI SCI Boot program Flash memory SCI Boot program RAM RAM Flash memory Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Programming control program 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host Host New application program LSI LSI SCI Boot program Flash memory RAM Flash memory Boot program area Flash memory preprogramming erase Programming control program SCI Boot program RAM Boot program area New application program Programming control program Program execution state Rev. 5.00 Jan 10, 2006 page 628 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) User Program Mode 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Host Programming/ erase control program New application program New application program LSI LSI SCI Boot program Flash memory SCI Boot program RAM RAM Flash memory FWE assessment program FWE assessment program Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program LSI LSI SCI Boot program Flash memory RAM FWE assessment program Flash memory RAM FWE assessment program Transfer program Transfer program Programming/ erase control program Flash memory erase SCI Boot program Programming/ erase control program New application program Program execution state Rev. 5.00 Jan 10, 2006 page 629 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.2.4 Flash Memory Emulation in RAM Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory RAM Emulation block Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19.3 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten. Rev. 5.00 Jan 10, 2006 page 630 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) SCI RAM Flash memory Programming data Overlap RAM (programming data) Application program Programming control program execution state Figure 19.4 Writing Overlap RAM Data in User Program Mode 19.2.5 Differences between Boot Mode and User Program Mode Table 19.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify Total erase Program/program-verify Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 5.00 Jan 10, 2006 page 631 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.2.6 Block Configuration The flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 4 kbytes × 8 32 kbytes 64 kbytes 256 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 19.5 Flash Memory Block Configuration 19.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 19.2. Table 19.2 Pin Configuration Pin Name Abbreviation I/O Function Reset RES Reset Input Flash write enable FWE Input Flash memory program/erase protection by hardware Mode 2 MD2 Input Sets MCU operating mode Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port F0 PF0 Input Sets MCU operating mode in programmer mode Port 16 P16 Input Sets MCU operating mode in programmer mode Port 14 P14 Input Sets MCU operating mode in programmer mode Transmit data TxD2 Output Serial transmit data output Receive data RxD2 Input Serial receive data input Rev. 5.00 Jan 10, 2006 page 632 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19.3. In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER, SCRX). Table 19.3 Register Configuration Initial Value Address* H'00* 3 H'FFA8 R/W* 2 R/W* H'00* 4 H'00* H'FFAA R/W H'00 H'FEDB 6 Flash memory power control register* 5 RAMER* 5 FLPWCR* 2 R/W* 4 H'00* H'FFAC Serial control register X SCRX R/W H'00 H'FDB4 Register Name Abbreviation R/W Flash memory control register 1 FLMCR1* 5 FLMCR2* R/W* 2 R* EBR1* 5 EBR2* Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register 5 5 2 H'00 2 1 H'FFA9 4 H'FFAB Notes: 1. Lower 16 bits of the address. 2. To access these registers, set the FLSHE bit to 1 in serial control register X. Even if FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the FWE bit in FLMCR1 is not set to 1. 3. When a high level is input to the FWE pin, the initial value is H'80. 4. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers. Use byte access on these registers. 6. An invalid register in the H8S/2623. 19.5 Register Descriptions 19.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a Rev. 5.00 Jan 10, 2006 page 633 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1. Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 —* 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W Determined by the state of the FWE pin. Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. Bit 7 FWE Description 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin Bit 6—Software Write Enable Bit 1 (SWE1): This bit selects write and erase valid/invalid of the flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2. Bit 6 SWE1 Description 0 Writes disabled 1 Writes enabled [Setting condition] When FWE = 1 Rev. 5.00 Jan 10, 2006 page 634 of 1042 REJ09B0275-0500 (Initial value) Section 19 ROM (Preliminary) Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Set this bit to 1 before setting the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Set this bit to 1 before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit at the same time. Bit 4 PSU1 Description 0 Program setup cleared 1 Program setup (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time. Bit 3 EV1 Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 Rev. 5.00 Jan 10, 2006 page 635 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE1 = 1 Bit 1—Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1 E1 Description 0 Erase mode cleared 1 Transition to erase mode (Initial value) [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1, PSU1, ESU1, EV1, PV1, or E1 bit at the same time. Bit 0 P1 Description 0 Program mode cleared 1 Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 Rev. 5.00 Jan 10, 2006 page 636 of 1042 REJ09B0275-0500 (Initial value) Section 19 ROM (Preliminary) 19.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00. Bit: 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value: 0 0 0 0 0 0 0 0 R/W: R — — — — — — — Note: FLMCR2 is a read-only register, and should not be written to. Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7 FLER Description 0 Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.8.3, Error Protection Bits 6 to 0—Reserved: These bits always read 0. Rev. 5.00 Jan 10, 2006 page 637 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.4. Bit: Initial value: R/W: 19.5.4 7 EB7 0 R/W 6 EB6 0 R/W 5 EB5 0 R/W 4 EB4 0 R/W 3 EB3 0 R/W 2 EB2 0 R/W 1 EB1 0 R/W 0 EB0 0 R/W Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 19.4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 — — — — EB11 EB10 EB9 EB8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 638 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.4 Flash Memory Erase Blocks Block (Size) Addresses EB0 (4 kbytes) H'000000–H'000FFF EB1 (4 kbytes) H'001000–H'001FFF EB2 (4 kbytes) H'002000–H'002FFF EB3 (4 kbytes) H'003000–H'003FFF EB4 (4 kbytes) H'004000–H'004FFF EB5 (4 kbytes) H'005000–H'005FFF EB6 (4 kbytes) H'006000–H'006FFF EB7 (4 kbytes) H'007000–H'007FFF EB8 (32 kbytes) H'008000–H'00FFFF EB9 (64 kbytes) H'010000–H'01FFFF EB10 (64 kbytes) H'020000–H'02FFFF EB11 (64 kbytes) H'030000–H'03FFFF 19.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. RAMER settings should be made in user mode or user program mode. Flash memory area divisions are shown in table 19.5. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit: 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bits 7 and 6—Reserved: These bits always read 0. Bits 5 and 4—Reserved: Only 0 may be written to these bits. Rev. 5.00 Jan 10, 2006 page 639 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3 RAMS Description 0 Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 19.5.) Table 19.5 Flash Memory Area Divisions Addresses Block Name RAMS RAM2 RAM1 RAM0 H'FFD000–H'FFDFFF RAM area 4 kbytes 0 * * * H'000000–H'000FFF EB0 (4 kbytes) 1 0 0 0 H'001000–H'001FFF EB1 (4 kbytes) 1 0 0 1 H'002000–H'002FFF EB2 (4 kbytes) 1 0 1 0 H'003000–H'003FFF EB3 (4 kbytes) 1 0 1 1 H'004000–H'004FFF EB4 (4 kbytes) 1 1 0 0 H'005000–H'005FFF EB5 (4 kbytes) 1 1 0 1 H'006000–H'006FFF EB6 (4 kbytes) 1 1 1 0 H'007000–H'007FFF EB7 (4 kbytes) 1 1 1 1 *: Don't care Rev. 5.00 Jan 10, 2006 page 640 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Flash Memory Power Control Register (FLPWCR)* 19.5.6 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 PDWND — — — — — — — 0 0 0 0 0 0 0 0 R/W R R R R R R R FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Note: * An invalid register in the H8S/2623. Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. Bit 7 PDWND Description 0 Transition to flash memory power-down mode enabled 1 Transition to flash memory power-down mode disabled (Initial value) Bits 6 to 0—Reserved: These bits always read 0. 19.5.7 Serial Control Register X (SCRX) Bit Initial value R/W 7 6 5 4 3 2 1 0 — — — — FLSHE — — — 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCRX is an 8-bit readable/writable register that controls on-chip flash memory. SCRX is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4—Reserved: Only 0 may be written to these bits. Rev. 5.00 Jan 10, 2006 page 641 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE Description 0 Flash control registers deselected in area H'FFFFA8 to H'FFFFAC 1 Flash control registers selected in area H'FFFFA8 to H'FFFFAC (Initial value) Bits 2 to 0—Reserved: Only 0 may be written to these bits. 19.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.6. For a diagram of the transitions to the various flash memory modes, see figure 19.2. Table 19.6 Setting On-Board Programming Modes Mode Boot mode Expanded mode FWE MD2 MD1 MD0 1 0 1 0 0 1 1 1 1 0 1 1 1 Single-chip mode User program mode Expanded mode Single-chip mode Rev. 5.00 Jan 10, 2006 page 642 of 1042 REJ09B0275-0500 1 Section 19 ROM (Preliminary) 19.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The SCI channel to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2626 or H8S/2623 pins have been set to boot mode, the boot program built into the LSI is started and the programming control program prepared in the host is serially transmitted to the LSI via the SCI. In the H8S/2626 and H8S/2623, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 19.6, and the boot mode execution procedure in figure 19.7. H8S/2626 or H8S/2623 Flash memory Host Write data reception Verify data transmission RxD2 SCI2 On-chip RAM TxD2 Figure 19.6 System Configuration in Boot Mode Rev. 5.00 Jan 10, 2006 page 643 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate LSI measures low period of H'00 data transmitted by host LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, LSI transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, LSI transmits one H'AA data byte to host Host transmits number of programming control program bytes (N), upper byte followed by lower byte LSI transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits programming control program sequentially in byte units LSI transmits received programming control program to host as verify data (echo-back) n+1→n Transfer received programming control program to on-chip RAM No n = N? Yes End of transmission Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, LSI transmits one H'AA data byte to host Execute programming control program transferred to on-chip RAM Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 19.7 Boot Mode Execution Procedure Rev. 5.00 Jan 10, 2006 page 644 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 Low period (9 bits) measured (H'00 data) D7 Stop bit High period (1 or more bits) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 2,400, 4,800, 9,600 or 19,200 bps to operate the SCI properly. Table 19.7 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the LSI bit rate is possible. The boot program should be executed within this system clock range. Table 19.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency for Which Automatic Adjustment of LSI Bit Rate is Possible 2,400 bps 2 to 8 MHz 4,800 bps 4 to 16 MHz 9,600 bps 8 to 20 MHz 19,200 bps 16 to 20 MHz Rev. 5.00 Jan 10, 2006 page 645 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 19.8. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. H'FFC000 Programming control program area (8 kbytes) H'FFDFFF H'FFE000 Boot program area (4 kbytes) H'FFEFBF Note: The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note also that the boot program remains in this area of the on-chip RAM even after control branches to the programming control program. Figure 19.8 RAM Areas in Boot Mode Notes on Use of Boot Mode: • When the chip comes out of reset in boot mode, it measures the low-level period of the input at the SCI’s RxD2 pin. The reset should end with RxD2 high. After the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the RxD2 pin. • In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. • Interrupts cannot be used while the flash memory is being programmed or erased. • The RxD2 and TxD2 pins should be pulled up on the board. Rev. 5.00 Jan 10, 2006 page 646 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) • Before branching to the programming control program (RAM area H'FFC000), the chip terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1). The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. • Boot mode can be entered by making the pin settings shown in table 19.6 and executing a reset-start. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting 1 the FWE pin and mode pins, and executing reset release* . Boot mode can also be cleared by a WDT overflow reset. Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low while the boot program is being executed or while flash memory is being programmed or 2 erased* . • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) 3 will change according to the change in the microcomputer’s operating mode* . Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. For further information on FWE application and disconnection, see section 19.13, Flash Memory Programming and Erasing Precautions. 3. See appendix D, Pin States. 19.6.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. Rev. 5.00 Jan 10, 2006 page 647 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. The flash memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Figure 19.9 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 19.13, Flash Memory Programming and Erasing Precautions. Figure 19.9 User Program Mode Execution Procedure Rev. 5.00 Jan 10, 2006 page 648 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.7 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses H'000000 to H'03FFFF are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip RAM or external memory. If the program is to be located in external memory, the instruction for writing to flash memory, and the following instruction, should be placed in on-chip RAM. Also ensure that the DTC is not activated before or after execution of the flash memory write instruction. In the following operation descriptions, wait times after setting or clearing individual bits in FLMCR1 are given as parameters; for details of the wait times, see section 22.6, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 bits in FLMCR1 is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed. Rev. 5.00 Jan 10, 2006 page 649 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) *3 E1 = 1 Erase setup state Erase mode E1 = 0 Normal mode FWE = 1 ESU1 = 1 ESU1 = 0 *1 FWE = 0 EV1 = 1 *2 On-board SWE1 = 1 Software programming mode programming Software programming enable disable state SWE1 = 0 state Erase-verify mode EV1 = 0 PSU1 = 1 *4 P1 = 1 PSU1 = 0 Program setup state Program mode P1 = 0 PV1 = 1 PV1 = 0 Program-verify mode Notes: In order to perform a normal read of flash memory, SWE1 must be cleared to 0. Also note that verify-reads can be performed during the programming/erasing process. 1. : Normal mode : On-board programming mode 2. Do not make a state transition by setting or clearing multiple bits simultaneously. 3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing through the software programming enable state. 4. After a transition from program mode to the program setup state, do not enter program mode without passing through the software programming enable state. Figure 19.10 FLMCR1 Bit Settings and State Transitions Rev. 5.00 Jan 10, 2006 page 650 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.7.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 19.11 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a time. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N) are shown in table 22.10. Following the elapse of (×0) µs or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in RAM is written consecutively to the program address (the lower 8 bits of the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during which the P1 bit is set is the flash memory programming time. Refer to the table in figure 19.11 for the programming time. Rev. 5.00 Jan 10, 2006 page 651 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P1 bit in FLMCR1, then wait for at least (α) µs before clearing the PSU1 bit to exit program mode. After the elapse of at least (β) µs, the watchdog timer is cleared and the operating mode is switched to program-verify mode by setting the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.11) and transferred to RAM. After verification of 128 bytes of data has been completed, exit program-verify mode, wait for at least (η) µs, then clear the SWE1 bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. The maximum number of repetitions of the program/program-verify sequence is indicated by the maximum programming count (N). However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Notes on Program/Program-Verify Procedure 1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must be H'00 or H'80. 2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer should be used. 128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF data to the extra addresses. 3. Verify data is read in word units. 4. The write pulse is applied and a flash memory write executed while the P1 bit in FLMCR1 is set. In the H8S/2626 and H8S/2623, write pulses should be applied as follows in the program/program-verify procedure to prevent voltage stress on the device and loss of write data reliability. a. After write pulse application, perform a verify-read in program-verify mode and apply a write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write bits in the 128-byte write data are read as 0 in the verify-read operation, the program/program-verify procedure is completed. In the H8S/2626 and H8S/2623, the Rev. 5.00 Jan 10, 2006 page 652 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing should be executed. If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit. 5. The period for which the P1 bit in FLMCR1 is set (the write pulse width) should be changed according to the degree of progress through the program/program-verify procedure. For detailed wait time specifications, see section 22.6, Flash Memory Characteristics. 6. The program/program-verify flowchart for the H8S/2626 and H8S/2623 is shown in figure 19.11. To cover the points noted above, bits on which reprogramming processing is to be executed, and bits on which additional programming is to be executed, must be determined as shown below. Since reprogram data and additional-programming data vary according to the progress of the programming procedure, it is recommended that the following data storage areas (128 bytes each) be provided in RAM. Reprogram Data Computation Table (D) Result of Verify-Read after Write Pulse (X) Application (V) Result of Operation 0 0 1 Programming completed: reprogramming processing not to be executed 1 0 Programming incomplete: reprogramming processing to be executed 0 1  1 1 Comments Still in erased state: no action Legend: (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Rev. 5.00 Jan 10, 2006 page 653 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Additional-Programming Data Computation Table Result of Verify-Read after Write Pulse (Y) (X') Application (V) Result of Operation 0 1 Comments 0 0 Programming by write pulse application judged to be completed: additional programming processing to be executed 1 1 Programming by write pulse application incomplete: additional programming processing not to be executed 0 Programming already completed: additional programming processing not to be executed 1 Still in erased state: no action Legend: (Y): Data of bits on which additional programming is executed (X'): Data of bits on which reprogramming is executed in a certain reprogramming loop 7. It is necessary to execute additional programming processing during the course of the H8S/2626 or H8S/2623 program/program-verify procedure. However, once 128-byte-unit programming is finished, additional programming should not be carried out on the same address area. When executing reprogramming, an erase must be executed first. Note that normal operation of reads, etc., is not guaranteed if additional programming is performed on addresses for which a program/program-verify operation has finished. Rev. 5.00 Jan 10, 2006 page 654 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) *5 Start of programming Write pulse application subroutine Set SWE1 bit in FLMCR1 Enable WDT tsswe: Set PSU1 bit in FLMCR1 Wait (× 0) µs Store 128 bytes of program data in program data area and reprogram data area Wait (y) µs tspsu: Programming must be executed in the erased state. Do not perform additional programming on addresses that have already been programmed. START Sub-Routine Write Pulse Set P1 bit in FLMCR1 n=1 tsp10 or tsp30 or tsp200: Wait (z0) µs or (z1) µs or (z2) µs m=0 Clear P1 bit in FLMCR1 Successively write 128-byte reprogram data to flash memory Wait (α) µs tcp: *4 *1 Sub-Routine-Call Write pulse application subroutine *5 Clear PSU1 bit in FLMCR1 Set PV1 bit in FLMCR1 Wait (β) µs tspv: Wait (γ) µs Disable WDT H'FF dummy write to verify address End Sub tspur: Wait (ε) µs Note: 6. Programming Time P1 Bit Set Time (µs) Additional Number of Writes Programming Programming z0 1 z1 2 z0 z1 · · · · Read verify data · · z0 z0 z2 z2 z2 z1 z1 — — — · · · · · · · · · N1+N2–2 N1+N2–1 N1+N2 z2 z2 z2 — — — m=1 OK · · n←n+1 NG Program data = verify data? · N1–1 N1 N1+1 N1+2 N1+3 *2 Increment address N1 ≥ n ? NG OK Additional-programming data computation Transfer additional-programming data to additional-programming data area *4 Reprogram data computation *3 Transfer reprogram data to reprogram data area *4 NG 128-byte data verification completed? OK Clear PV1 bit in FLMCR1 RAM tcpv: Program data storage area (128 bytes) Wait (η) µs N1 ≥ n ? Reprogram data storage area (128 bytes) NG Successively write 128-byte data from additionalprogramming data area in RAM to flash memory *1 Sub-Routine-Call Additional programming subroutine Additional-programming data storage area (128 bytes) m=0? NG n ≥ (N1 + N2) ? NG Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first OK OK address written to must be H'00 or H'80. A 128-byte data transfer Clear SWE1 bit in FLMCR1 Clear SWE1 bit in FLMCR1 must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. tcswe: tcswe: tcswe: Wait (×1) µs Wait (×1) µs 2. Verify data is read in 16-bit (word) units. 3. Even bits for which programming has been completed in the 128-byte programming End of programming Programming failure loop will be subject to programming again if they fail the subsequent verify operation. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming data must be provided in RAM. The reprogram and additional-programming data contents are modified as programming proceeds. 5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See note *6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. Reprogram Data Computation Table Additional-Programming Data Computation Table Original Data Verify Data Reprogram Data Comments (D) (V) (X) Programming complete 0 0 1 Programming is incomplete: 0 1 0 reprogramming should be performed 1 0 1 Left in the erased state 1 1 1 Reprogram Data Verify Data Additional-Programming Comments (V) Data (X) (X') 0 0 0 Additional programming should be performed 0 1 1 Additional programming should not be performed 1 0 1 Additional programming should not be performed 1 1 1 Additional programming should not be performed Figure 19.11 Program/Program-Verify Flowchart Rev. 5.00 Jan 10, 2006 page 655 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.7.3 Erase Mode When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 19.12 should be followed. To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in erase block register 1 and 2 (EBR1, EBR2) at least (x) µs after setting the SWE1 bit to 1 in FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set 6.6 ms as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU1 bit in FLMCR1. The operating mode is then switched to erase mode by setting the E1 bit in FLMCR1 after the elapse of at least (y) µs. The time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. 19.7.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E1 bit in FLMCR1, then wait for at least (α) µs before clearing the ESU1 bit to exit erase mode. After exiting erase mode, the watchdog timer is cleared after the elapse of (β) µs or more. The operating mode is then switched to erase-verify mode by setting the EV1 bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again and repeat the erase/erase-verify sequence in the same way. The maximum number of reoperations of the erase/erase-verify sequence is indicated by the maximum erase count (N). However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/eraseverify sequence as before. Rev. 5.00 Jan 10, 2006 page 656 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Start *1 Set SWE1 bit in FLMCR1 tsswe: Wait (x) µs n=1 Set EBR1 and 2 *3 Enable WDT Set ESU1 bit in FLMCR1 tsesu: Wait (y) µs Start erase Set E1 bit in FLMCR1 tse: Wait (z) ms Clear E1 bit in FLMCR1 Halt erase tce: Wait (α) µs Clear ESU1 bit in FLMCR1 tcesu: Wait (β) µs Disable WDT n←n+1 Set EV1 bit in FLMCR1 tsev: Wait (γ) µs Set block start address to verify address H'FF dummy write to verify address tsevr: Wait (ε) µs Read verify data Increment address Verify data = all "1"? *2 NG OK NG NG Notes: 1. 2. 3. 4. Last address of block? OK Clear EV1 bit in FLMCR1 Clear EV1 bit in FLMCR1 tcev: Wait (η) µs tcev: Wait (η) µs *4 End of erasing of all erase blocks? OK n ≥ (N)? Clear SWE1 bit in FLMCR1 OK Clear SWE1 bit in FLMCR1 tcswe: Wait (× 1) µs tcswe: Wait (× 1) µs End of erasing Erase failure NG Preprogramming (setting erase block data to all "0") is not necessary. Verify data is read in 16-bit (W) units. Set only one bit in EBR1 and 2. More than 2 bits cannot be set. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn. Figure 19.12 Erase/Erase-Verify Flowchart Rev. 5.00 Jan 10, 2006 page 657 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.8 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the error-protected state. (See table 19.8.) Table 19.8 Hardware Protection Functions Item Description Program Erase FWE pin protection • When a low level is input to the FWE pin, FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. Yes Yes Reset/standby protection • In a reset (including a WDT reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered. Yes Yes • In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Rev. 5.00 Jan 10, 2006 page 658 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.8.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), does not cause a transition to program mode or erase mode. (See table 19.9.) Table 19.9 Software Protection Functions Item Description Program Erase SWE bit protection • Setting bit SWE1 in FLMCR1 to 0 will place area H'000000 to H'03FFFFF in the program/erase-protected state. (Execute the program in the on-chip RAM, external memory) Yes Yes Block specification protection • Erase protection can be set for individual blocks by settings in erase block register 1 (EBR1) and erase block register 2 (EBR2). — Yes • Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state. Yes Yes Emulation protection • Setting the RAMS bit to 1 in the RAM emulation register (RAMER) places all blocks in the program/erase-protected state. Rev. 5.00 Jan 10, 2006 page 659 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.8.3 Error Protection In error protection, an error is detected when H8S/2626 or H8S/2623 runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the H8S/2626 or H8S/2623 malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. When a SLEEP instruction (including software standby) is executed during programming/erasing Error protection is released only by a reset and in hardware standby mode. Rev. 5.00 Jan 10, 2006 page 660 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Figure 19.13 shows the flash memory state transition diagram. Program mode Erase mode Reset or standby (hardware protection) RES = 0 or HSTBY = 0 RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Error occurrence (software standby) RES = 0 or HSTBY = 0 Error occurrence RES = 0 or HSTBY = 0 Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release FLMCR1, FLMCR2, EBR1, EBR2 initialization state Error protection mode (software standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2, EBR1, EBR2 initialization state Legend: RD: Memory read possible VF: Verify-read possible PR: Programming possible ER: Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 19.13 Flash Memory State Transitions Rev. 5.00 Jan 10, 2006 page 661 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.9 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses cannot be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.14 shows an example of emulation of real-time flash memory programming. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19.14 Flowchart for Flash Memory Emulation in RAM Rev. 5.00 Jan 10, 2006 page 662 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFD000 H'FFDFFF Flash memory EB8 to EB11 On-chip RAM H'FFEFBF H'3FFFF Figure 19.15 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the area (EB0) for which real-time programming is required. 2. Real-time programming is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), will not cause a transition to program mode or erase mode. When actually programming or erasing a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. Rev. 5.00 Jan 10, 2006 page 663 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot 1 mode* , to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would 2 not be read correctly* , possibly resulting in MCU runaway. 3. If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI interrupt, must therefore be restricted inside and outside the MCU when programming or erasing flash memory. NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: 19.11 • If flash memory is read while being programmed or erased (while the P1 or E1 bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). • If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Flash Memory Programmer Mode Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, flash memory read mode, auto-program mode, autoerase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. In programmer mode, set the mode pins to programmer mode (see table 19.10) and input a 12 MHz input clock. Table 19.10 shows the pin settings for programmer mode. Rev. 5.00 Jan 10, 2006 page 664 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.10 Programmer Mode Pin Settings Pin Names Settings Mode pins: MD2, MD1, MD0 Low level input to MD2, MD1, and MD0. Mode setting pins: PF0, P16, P14 High level input to PF0, low level input to P16 and P14 FWE pin High level input (in auto-program and auto-erase modes) RES pin Reset circuit XTAL, EXTAL, PLLVCC, PLLCAP, PLLVSS pins Oscillator circuit 19.11.1 Socket Adapter Pin Correspondence Diagram Connect the socket adapter to the chip as shown in figure 19.17. This will enable conversion to a 40-pin arrangement. The on-chip ROM memory map is shown in figure 19.16, and the socket adapter pin correspondence diagram in figure 19.17. Addresses in MCU mode Addresses in programmer mode H'000000 H'00000 On-chip ROM space 256 kbytes H'03FFFF H'3FFFF Figure 19.16 On-Chip ROM Memory Map Rev. 5.00 Jan 10, 2006 page 665 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) H8S/2626 or H8S/2623 Socket Adapter (Conversion to 40-Pin Arrangement) HN27C4096HG (40 Pins) Pin No. Pin Name Pin No. Pin Name 28 A0 21 A0 29 A1 22 A1 30 A2 23 A2 31 A3 24 A3 32 A4 25 A4 33 A5 26 A5 34 A6 27 A6 35 A7 28 A7 36 A8 29 A8 38 A9 31 A9 40 A10 32 A10 41 A11 33 A11 42 A12 34 A12 43 A13 35 A13 44 A14 36 A14 45 A15 37 A15 46 A16 38 A16 47 A17 39 A17 20 D8 19 I/O0 21 D9 18 I/O1 22 D10 17 I/O2 23 D11 16 I/O3 24 D12 15 I/O4 25 D13 14 I/O5 26 D14 13 I/O6 27 D15 12 I/O7 19 CE 2 CE 16 OE 20 OE 18 WE 3 WE 67 FWE 4 FWE 1, 40 VCC 11, 30 VSS 6, 9, 13, 17, 39, 52, 61, 62, 63, 75, 76, 77, 97 VCC 2, 4, 8, 14, 15, 37, 48, 49, 53, 54, 55, 56, 65, 94, 95, 98 VSS 60 RES 64 XTAL 66 EXTAL 59 PLL VCC 58 PLLCAP 57 PLL VSS Other than the above NC (OPEN) Power-on reset circuit Oscillator circuit PLL circuit 5, 6, 7 NC 8 A20 9 A19 10 A18 Legend: FWE: I/O7–I/O0: A18–A0: CE: OE: WE: Flash write enable Data input/output Address input Chip enable Output enable Write enable Figure 19.17 Socket Adapter Pin Correspondence Diagram Rev. 5.00 Jan 10, 2006 page 666 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.11.2 Programmer Mode Operation Table 19.11 shows how the different operating modes are set when using programmer mode, and table 19.12 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. • Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. • Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-programming. • Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O6 signal. In status read mode, error information is output if an error occurs. Table 19.11 Settings for Various Operating Modes in Programmer Mode Pin Names Mode FWE CE OE WE I/O7– I/O0 A18–A0 Read H or L L L H Data output Ain Output disable H or L L H H Hi-Z X Command write 1 Chip disable* H or L* L H L Data input Ain* H X X Hi-Z X H or L 3 2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes in auto-program and auto-erase modes, input a high level to the FWE pin. Rev. 5.00 Jan 10, 2006 page 667 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.12 Programmer Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write WA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 19.11.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering on, memory read mode is entered. Rev. 5.00 Jan 10, 2006 page 668 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.13 AC Characteristics in Transition to Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle tnxtc 20 — µs CE hold time tceh 0 — ns CE setup time tces 0 — ns Data hold time tdh 50 — ns Data setup time tds 50 — ns Write pulse width twep 70 — ns WE rise time tr — 30 ns WE fall time tf — 30 ns Command write Memory read mode Address stable A18–A0 tces tceh tnxtc CE OE twep tf tr WE tds tdh I/O7–I/O0 Note: Data is latched on the rising edge of WE. Figure 19.18 Timing Waveforms for Memory Read after Memory Write Rev. 5.00 Jan 10, 2006 page 669 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.14 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle tnxtc 20 — µs CE hold time tceh 0 — ns CE setup time tces 0 — ns Data hold time tdh 50 — ns Data setup time tds 50 — ns Write pulse width twep 70 — ns WE rise time tr — 30 ns WE fall time tf — 30 ns Memory read mode A18–A0 Other mode command write Address stable tnxtc tces tceh CE OE twep tf tr WE tds tdh I/O7–I/O0 Note: Do not enable WE and OE at the same time. Figure 19.19 Timing Waveforms in Transition from Memory Read Mode to Another Mode Rev. 5.00 Jan 10, 2006 page 670 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.15 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Access time tacc — 20 µs CE output delay time tce — 150 ns OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns Address stable A18–A0 CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7–I/O0 Figure 19.20 CE and OE Enable State Read Timing Waveforms Address stable A18–A0 Address stable tce tce CE toe toe OE WE VIH tacc tacc toh tdf toh tdf I/O7–I/O0 Figure 19.21 CE and OE Clock System Read Timing Waveforms Rev. 5.00 Jan 10, 2006 page 671 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.11.4 Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 7 bits of the transfer address must be low. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 19.22). Do not perform transfer after the third cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-program operation for a 128-byte block for each address. Two or more additional programming operations cannot be performed on a previously programmed address block. 7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-program operation end decision pin). 8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Rev. 5.00 Jan 10, 2006 page 672 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.16 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle tnxtc 20 — µs CE hold time tceh 0 — ns CE setup time tces 0 — ns Data hold time tdh 50 — ns Data setup time tds 50 — ns Write pulse width twep 70 — ns Status polling start time twsts 1 — ms Status polling access time tspa — 150 ns Address setup time tas 0 — ns Address hold time tah 60 — ns Memory write time twrite 1 3000 ms Write setup time tpns 100 — ns Write end setup time tpnh 100 — ns WE rise time tr — 30 ns WE fall time tf — 30 ns Rev. 5.00 Jan 10, 2006 page 673 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) FWE tpnh Address stable A18–A0 tpns tces tceh tnxtc tnxtc CE OE tf twep tr tas tah twsts tspa WE tds tdh Data transfer 1 to 128 bytes twrite I/O7 Write operation end decision signal I/O6 Write normal end decision signal I/O5–I/O0 H'40 H'00 Figure 19.22 Auto-Program Mode Timing Waveforms 19.11.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Rev. 5.00 Jan 10, 2006 page 674 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Table 19.17 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Command write cycle tnxtc 20 — µs CE hold time tceh 0 — ns CE setup time tces 0 — ns Data hold time tdh 50 — ns Data setup time tds 50 — ns Write pulse width twep 70 — ns Status polling start time tests 1 — ms Status polling access time tspa — 150 ns Memory erase time terase 100 40000 ms Erase setup time tens 100 — ns Erase end setup time tenh 100 — ns WE rise time tr — 30 ns WE fall time tf — 30 ns FWE tpnh A18–A0 tens tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds terase tdh I/O7 Erase end decision signal I/O6 I/O5–I/O0 Erase normal end decision signal H'20 H'20 H'00 Figure 19.23 Auto-Erase Mode Timing Waveforms Rev. 5.00 Jan 10, 2006 page 675 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.11.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. The return code is retained until a command write other than a status read mode command write is executed. Table 19.18 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Read time after command write tnxtc 20 — µs CE hold time tceh 0 — ns CE setup time tces 0 — ns Data hold time tdh 50 — ns Data setup time tds 50 — ns Write pulse width twep 70 — ns OE output delay time toe — 150 ns Disable delay time tdf — 100 ns CE output delay time tce — 150 ns WE rise time tr — 30 ns WE fall time tf — 30 ns A18–A0 tces tceh tnxtc tces tceh tnxtc tnxtc CE tce OE twep tf tr twep tf tr toe WE tds I/O7–I/O0 tdh H'71 tds tdh H'71 Note: I/O2 and I/O3 are undefined. Figure 19.24 Status Read Mode Timing Waveforms Rev. 5.00 Jan 10, 2006 page 676 of 1042 REJ09B0275-0500 tdf Section 19 ROM (Preliminary) Table 19.19 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Attribute Normal end decision Command error Programming error Erase error — — Programming Effective or erase address count error exceeded Initial value 0 0 0 0 0 0 0 Indications Normal end: 0 Command error: 1 — Count exceeded: 1 Abnormal end: 1 ProgramErasing — ming error: 1 Otherwise: 0 error: 1 Otherwise: 0 Otherwise: 0 I/O0 0 Effective address Otherwise: 0 error: 1 Otherwise: 0 Note: I/O2 and I/O3 are undefined. 19.11.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 19.20 Status Polling Output Truth Table Pin Name During Internal Operation Abnormal End — Normal End I/O7 0 1 0 1 I/O6 0 0 1 1 I/O0–I/O5 0 0 0 0 19.11.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 19.21 Stipulated Transition Times to Command Wait State Item Symbol Min Max Unit Standby release (oscillation stabilization time) tosc1 30 — ms Programmer mode setup time tbmv 10 — ms VCC hold time tdwn 0 — ms Rev. 5.00 Jan 10, 2006 page 677 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) tosc1 tbmv Memory read mode Command Auto-program mode wait state Auto-erase mode Command wait state Normal/abnormal end decision tdwn VCC RES FWE Note: When using other than the automatic write mode and automatic erase mode, drive the FWE input pin low. Figure 19.25 Oscillation Stabilization Time, Boot Program Transfer Time, and Power-Down Sequence 19.11.9 Notes on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Additional programming cannot be performed on previously programmed address blocks. Rev. 5.00 Jan 10, 2006 page 678 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.12 Flash Memory and Power-Down States In addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. There are three flash memory operating states: (1) Normal operating mode: The flash memory can be read and written to. (2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating on the subclock. (3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or written to. States (2) and (3) are flash memory power-down states. Table 19.22 shows the correspondence between the operating states of the LSI and the flash memory. Table 19.22 Flash Memory Operating States LSI Operating State Flash Memory Operating State High-speed mode Normal mode (read/write) Medium-speed mode Sleep mode Subactive mode When PDWND = 0: Power-down mode (read-only) Subsleep mode When PDWND = 1: Normal mode (read-only) Watch mode Standby mode Software standby mode Hardware standby mode 19.12.1 Note on Power-Down States When the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. Therefore, a power supply circuit stabilization period must be provided when returning to normal operation. When the flash memory returns to its normal operating state from a powerdown state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 µs (power supply stabilization time), even if an oscillation stabilization period is not necessary. Rev. 5.00 Jan 10, 2006 page 679 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.13 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. Failure to observe these points may result in damage to the device. 2. Powering on and off (see figures 19.26 to 19.28) Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. 3. FWE application/disconnection (see figures 19.26 to 19.28) FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: • Apply FWE when the VCC voltage has stabilized within its rated voltage range. Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling time). • In boot mode, apply and disconnect FWE during a reset. • In user program mode, FWE can be switched between high and low level regardless of RES input. FWE input can also be switched during execution of a program in flash memory. • Do not apply FWE if program runaway has occurred. • Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in FLMCR1 are cleared. Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits are not set by mistake when applying or disconnecting FWE. Rev. 5.00 Jan 10, 2006 page 680 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 4. Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 5. Use the recommended algorithm when programming and erasing flash memory. The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. 6. Do not set or clear the SWE1 bit during execution of a program in flash memory. Do not set or clear the SWE1 bit during execution of a program in flash memory. Wait for at least 100 µs after clearing the SWE1 bit before executing a program or reading data in flash memory. When the SWE1 bit is set, data in flash memory can be rewritten, but when SWE1 = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing). Do not clear the SWE1 bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE1 bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE1 bit is set or cleared. 7. Do not use interrupts while flash memory is being programmed or erased. All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. 8. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, also, perform only one programming operation on a 128-byte programming unit block. 9. Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. 10. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. Rev. 5.00 Jan 10, 2006 page 681 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Wait time: x Programming/ erasing possible Wait time: 100 µs φ Min 0 µs tOSC1 VCC tMDS*3 FWE Min 0 µs MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2–MD0) must be fixed until poweroff by pulling the pins up or down. 2. See section 22.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns Figure 19.26 Power-On/Off Timing (Boot Mode) Rev. 5.00 Jan 10, 2006 page 682 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Wait time: x Programming/ erasing possible Wait time: 100 µs φ Min 0 µs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD2–MD0) must be fixed until poweroff by pulling the pins up or down. 2. See section 22.6, Flash Memory Characteristics. 3. Mode programming setup time tMDS (min) = 200 ns Figure 19.27 Power-On/Off Timing (User Program Mode) Rev. 5.00 Jan 10, 2006 page 683 of 1042 REJ09B0275-0500 Wait time: 100 µs Programming/ erasing possible Wait time: x Wait time: x Programming/ erasing possible Wait time: 100 µs Wait time: x Programming/ erasing possible Wait time: 100 µs Wait time: 100 µs Wait time: x Programming/ erasing possible Section 19 ROM (Preliminary) φ tOSC1 VCC Min 0µs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE1 cleared SWE1 set SWE1 bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. The state of ports with multiplexed address functions and bus control output pins (AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low), and therefore these pins should not be used as output signals during this time. 2. When making a transition from boot mode to another mode, a mode programming setup time, tMDS (min), of 200 ns is necessary with respect to the RES clearance timing. 3. See section 22.6, Flash Memory Characteristics. Figure 19.28 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode) Rev. 5.00 Jan 10, 2006 page 684 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) 19.14 Note on Switching from F-ZTAT Version to Mask ROM Version The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 19.23 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 19.23 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 19.23 have no effect. Table 19.23 Registers Present in F-ZTAT Version but Absent in Mask ROM Version Register Abbreviation Address Flash memory control register 1 FLMCR1 H'FFA8 Flash memory control register 2 FLMCR2 H'FFA9 Erase block register 1 EBR1 H'FFAA Erase block register 2 EBR2 H'FFAB RAM emulation register RAMER H'FEDB Flash memory power control register FLPWCR H'FFAC Rev. 5.00 Jan 10, 2006 page 685 of 1042 REJ09B0275-0500 Section 19 ROM (Preliminary) Rev. 5.00 Jan 10, 2006 page 686 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator Section 20 Clock Pulse Generator 20.1 Overview The H8S/2626 Group and H8S/2623 Group have an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator*, and waveform shaping circuit*. The frequency can be changed by means of the PLL circuit in the CPG. Frequency changes are performed by software by means of settings in the system clock control register (SCKCR) and low-power control register (LPWRCR). Note: * Supported only in the H8S/2626 Group; not available in the H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 687 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator 20.1.1 Block Diagram Figure 20.1 shows a block diagram of the clock pulse generator. LPWRCR SCKCR STC1, STC0 EXTAL System clock oscillator XTAL SCK2 to SCK0 Mediumspeed clock divider PLL circuit (×1, ×2, ×4) Clock selection circuit φSUB OSC1 Waveform shaping circuit* Subclock oscillator* OSC2 φ/2 to φ/32 Bus master clock selection circuit φ System clock Internal clock to to ø pin supporting modules Bus master clock to CPU and DTC WDT1 count clock Legend: LPWRCR: Low-power control register SCKCR: System clock control register Note: * Supported only in the H8S/2626 Group, not available in the H8S/2623 Group. Figure 20.1 Block Diagram of Clock Pulse Generator 20.1.2 Register Configuration The clock pulse generator is controlled by SCKCR and LPWRCR. Table 20.1 shows the register configuration. Table 20.1 Clock Pulse Generator Register Name Abbreviation R/W Initial Value Address* System clock control register SCKCR R/W H'00 H'FDE6 Low-power control register LPWRCR R/W H'00 H'FDEC Note: * Lower 16 bits of the address. Rev. 5.00 Jan 10, 2006 page 688 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator 20.2 Register Descriptions 20.2.1 System Clock Control Register (SCKCR) Bit : Initial value: R/W : 7 6 5 4 3 2 1 0 PSTOP — — — STCS SCK2 SCK1 SCK0 0 0 0 0 0 0 0 0 R/W — — — R/W R/W R/W R/W SCKCR is an 8-bit readable/writable register that performs φ clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ φ Clock Output Disable (PSTOP): Controls φ output. Description Bit 7 Software Standby Mode Hardware Standby Mode PSTOP High-speed Mode, Medium-Speed Mode 0 φ output (initial value) φ output Fixed high High impedance 1 Fixed high Fixed high Fixed high High impedance Sleep Mode Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified. Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS Description 0 Specified multiplication factor is valid after transition to software standby mode (Initial value) 1 Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock. Rev. 5.00 Jan 10, 2006 page 689 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock is φ/2 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 0 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 — — 1 1 0 1 20.2.2 (Initial value) Low-Power Control Register (LPWRCR) Bit 7 6 DTON LSON 5 4 3 NESEL SUBSTP RFCUT 2 1 0 — STC1 STC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 2—Reserved: The function of these bits differs between the H8S/2623 Group and H8S/2626 Group. For details see sections 21A.2.3, 21B.2.3, Low-Power Control Register (LPWRCR). Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the frequency multiplication factor of the PLL circuit. Bit 1 Bit 0 STC1 STC0 Description 0 0 ×1 1 ×2 0 ×4 1 Setting prohibited 1 Rev. 5.00 Jan 10, 2006 page 690 of 1042 REJ09B0275-0500 (Initial value) Section 20 Clock Pulse Generator Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in sections 21A and 21B, Electrical Characteristics. 20.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 20 MHz. 20.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20.2. Select the damping resistance Rd according to table 20.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 20.2 Connection of Crystal Resonator (Example) Table 20.2 Damping Resistance Value Frequency (MHz) 4 8 12 16 20 Rd (Ω) 500 200 0 0 0 Rev. 5.00 Jan 10, 2006 page 691 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator Crystal Resonator: Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20.3. The crystal resonator frequency should not exceed 20 MHz. CL L Rs XTAL EXTAL AT-cut parallel-resonance type C0 Figure 20.3 Crystal Resonator Equivalent Circuit Table 20.3 Crystal Resonator Parameters Frequency (MHz) 4 8 12 16 20 RS max (Ω) 120 80 60 50 40 C0 max (pF) 7 7 7 7 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 20.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B CL2 H8S/2626 Group or H8S/2623 Group XTAL EXTAL CL1 Figure 20.4 Example of Incorrect Board Design Rev. 5.00 Jan 10, 2006 page 692 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator External circuitry such as that shown below is recommended around the PLL. R1: 3 kΩ C1: 470 pF PLLCAP Rp: 200 Ω PLLVCC PLLVSS CPB: 0.1 µF* PVCC1 to PVCC4 VCC VSS CB: 1000pF* CB: 300pF* (Values are preliminary recommended values.) Note: * CB and CPB are laminated ceramic capacitors. Figure 20.5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Supply the C1 ground from PLLVSS. Separate PLLVCC and PLLVSS from the other VCC/VSS and PVCC/PVSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. Rev. 5.00 Jan 10, 2006 page 693 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator 20.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20.6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL External clock input XTAL Open (a) XTAL pin left open EXTAL External clock input XTAL (b) Complementary clock input at XTAL pin Figure 20.6 External Clock Input (Examples) Rev. 5.00 Jan 10, 2006 page 694 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator External Clock: Use an external clock frequency of 20 MHz or less. Table 20.4 and figure 20.7 show the input conditions for the external clock. Table 20.4 External Clock Input Conditions VCC = 3.0 V to 3.6 V, PVCC = 5.0 V ±10% Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 15 — ns Figure 20.7 External clock input high pulse width tEXH 15 — ns External clock rise time tEXr — 5 ns External clock fall time tEXf — 5 ns Clock low pulse width level tCL 0.4 0.6 tcyc φ ≥ 5 MHz 80 — ns φ < 5 MHz Clock high pulse width level tCH 0.4 0.6 tcyc φ ≥ 5 MHz 80 — ns φ < 5 MHz tEXH Figure 22.2 tEXL EXTAL VCC × 0.5 tEXr tEXf Figure 20.7 External Clock Input Timing Rev. 5.00 Jan 10, 2006 page 695 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator 20.4 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When setting the multiplication factor, ensure that the clock frequency after multiplication does not exceed the maximum operating frequency of the chip. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0 (initial value), the setting becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0 in SBYCR. [1] The initial PLL circuit multiplication factor is 1. [2] A value is set in bits STS2 to STS0 to give the specified transition time. [3] The target value is set in STC1 and STC0, and a transition is made to software standby mode. [4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. [5] Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS2 to STS0. [6] After the set transition time has elapsed, the LSI resumes operation using the target multiplication factor. If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in [3], software standby mode is entered and break exception handling is executed after the oscillation stabilization time. In this case, the instruction following the SLEEP instruction is executed after execution of the RTE instruction. When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits STC1 and STC0 are rewritten. 20.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32. Rev. 5.00 Jan 10, 2006 page 696 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator 20.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed clocks (φ/2, φ/4, φ/8, φ/16, and φ/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 20.7 Subclock Oscillator (H8S/2626 Group Only) (1) Connecting 32.768kHz Crystal Oscillator To supply a clock to the subclock oscillator, connect a 32.768kHz crystal oscillator, as shown in figure 20.8. See section 20.3.1, Connecting a Crystal Resonator. C1 OSC1 C2 OSC2 C1 = C2 = 15 pF (typ) Figure 20.8 Example Connection of 32.768 kHz Crystal Oscillator Figure 20.9 shows the equivalence circuit for a 32.768kHz oscillator. Ls Cs Rs OSC1 OSC2 Co Co = 1.5 pF (typ) Rs = 14 kΩ (typ) fw = 32.768 kHz Type No.: MX38T (Nihon Dempa Kogyo) Figure 20.9 Equivalence Circuit for 32.768 kHz Oscillator Rev. 5.00 Jan 10, 2006 page 697 of 1042 REJ09B0275-0500 Section 20 Clock Pulse Generator (2) Handling pins when subclock not required If no subclock is required, connect the OSC1 pin to Vcc and leave OSC2 open, as shown in figure 20.10. VCC OSC1 OSC2 Open Figure 20.10 Pin Handling When Subclock Not Required 20.8 Subclock Waveform Shaping Circuit (H8S/2626 Group Only) To eliminate noise from the subclock input to OSC1, the subclock is sampled using the dividing clock φ. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section 21B.2.3, Low Power Control Register (LPWRCR). No sampling is performed in sub-active mode, sub-sleep mode, or watch mode. 20.9 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user’s board design, thorough evaluation is necessary on the user’s part, for both the mask versions and F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. Rev. 5.00 Jan 10, 2006 page 698 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] Section 21A Power-Down Modes [H8S/2623 Group] Subclock functions are not available in the H8S/2623 Group. 21A.1 Overview In addition to the normal program execution state, the H8S/2623 Group has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2623 operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode (2) to (6) are power-down modes. Sleep mode is CPU states, medium-speed mode is a CPU and bus master state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop mode. Note: Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in the H8S/2623 Group. Table 21A.1 shows the internal state of the LSI in the respective modes. Figure 21A.1 is a mode transition diagram. Rev. 5.00 Jan 10, 2006 page 699 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] Table 21A.1 LSI Internal States in Each Mode HighSpeed MediumSpeed Sleep Module Stop Software Standby Hardware Standby System clock pulse generator Functioning Functioning Functioning Functioning Halted Halted CPU Instructions Registers Functioning Medium-speed Halted operation (retained) High/medium- Halted speed (retained) operation Halted (undefined) NMI Functioning Functioning Functioning Functioning Functioning Halted WDT0 Functioning Functioning Functioning  Halted (retained) Halted (reset) DTC Functioning Medium-speed Functioning operation Halted (retained) Halted (retained) Halted (reset) TPU Functioning Functioning Functioning (PBC mediumspeed operation) Halted (retained) Halted (retained) Halted (reset) Functioning Functioning Functioning Halted (reset) Halted (reset) Halted (reset) Functioning Functioning Functioning (DTC) Functioning Retained Retained I/O Functioning Functioning Functioning Functioning Retained High impedance HCAN Functioning Functioning* Functioning Halted (reset) Halted (reset) Halted (reset) Function External interrupts Peripheral functions IRQ0–IRQ5 PBC PPG SCI0 SCI1 SCI2 PWM A/D RAM Notes: “Halted (retained)” means that internal register values are retained. The internal state is “operation suspended.” “Halted (reset)” means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). * Note, however, that registers cannot be read or written to. Rev. 5.00 Jan 10, 2006 page 700 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] Program-halted state STBY pin = Low Reset state Hardware standby mode STBY pin = High RES pin = Low RES pin = High Program execution state SSBY = 0 Sleep mode (main clock) SLEEP command High-speed mode (main clock) Any interrupt SCK2 to SCK0= 0 SCK2 to SCK0 0 Medium-speed mode (main clock) SLEEP command SSBY = 1 Software standby mode External interrupt* : Transition after exception processing : Low power dissipation mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low. From any state, a transition to hardware standby mode occurs when STBY is driven low. * NMI and IRQ0 to IRQ5 Figure 21A.1 Mode Transition Diagram Rev. 5.00 Jan 10, 2006 page 701 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, and MSTPCR registers. Table 21A.2 summarizes these registers. Table 21A.2 Power-Down Mode Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'08 H'FDE4 System clock control register SCKCR R/W H'00 H'FDE6 Low power control register LPWRCR R/W H'00 H'FDEC Module stop control register A, B, C MSTPCRA R/W H'3F H'FDE8 MSTPCRB R/W H'FF H'FDE9 MSTPCRC R/W H'FF H'FDEA Note: * Lower 16 bits of the address. 21A.2 Register Descriptions 21A.2.1 Standby Control Register (SBYCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W — — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by executing the SLEEP instruction, the operating mode is determined in combination with other control bits. Note that the value of the SSBY bit does not change even when shifting between modes using interrupts. Rev. 5.00 Jan 10, 2006 page 702 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] Bit 7 SSBY Description 0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. (Initial value) 1 Shifts to software standby mode when the SLEEP instruction is executed in highspeed mode or medium-speed mode. Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode. With a quartz oscillator (table 21A.4), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, there are no specific wait requirements. Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 0 Standby time = 32768 states 1 Standby time = 65536 states 0 0 Standby time = 131072 states 1 Standby time = 262144 states 1 0 Reserved 1 Standby time = 16 states 1 1 (Initial value) Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the software standby mode. Bit 3 OPE Description 0 In software standby mode, address bus and bus control signals are high-impedance. 1 In software standby mode, the output state of the address bus and bus control signals is retained. (Initial value) Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to. Rev. 5.00 Jan 10, 2006 page 703 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.2.2 System Clock Control Register (SCKCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PSTOP — — — STCS SCK2 SCK1 SCK0 0 0 0 0 0 0 0 0 R/W — — — R/W R/W R/W R/W SCKCR is an 8-bit readable/writable register that performs φ clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ φ Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls φ output. See section 21A.8, φ Clock Output Disable Function, for details. Description Bit 7 PSTOP High-Speed Mode, Medium-Speed Mode Sleep Mode Software Standby Mode Hardware Standby Mode 0 φ output (initial value) φ output Fixed high High impedance 1 Fixed high Fixed high Fixed high High impedance Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified. Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS Description 0 Specified multiplication factor is valid after transition to software standby mode (Initial value) 1 Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, and medium-speed mode. Rev. 5.00 Jan 10, 2006 page 704 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master in high-speed mode 1 Medium-speed clock is φ/2 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 0 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 — — 1 1 0 1 (Initial value) 21A.2.3 Low-Power Control Register (LPWRCR) Bit : Initial value : R/W : 7 6 5 4 DTON LSON 0 0 0 0 R/W R/W R/W R/W 3 2 1 0 — STC1 STC0 0 0 0 0 R/W R/W R/W R/W NESEL SUBSTP RFCUT The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes. The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. The following describes bits 7 to 2. For details of other bits, see section 20.2.2, Low-Power Control Register (LPWRCR). Bits 7 to 4—Reserved: Bits DTON, LSON, NESEL, and SUBSTP must always be written with 0 in the H8S/2623 Group, as this version does not support subclock operation. Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the internal feedback resistance of the main clock oscillation circuit ON/OFF. Bit 3 RFCUT Description 0 When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. (Initial value) 1 Sets the feedback resistance OFF. Bit 2—Reserved: Only write 0 to this bit. Rev. 5.00 Jan 10, 2006 page 705 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.2.4 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MSTPCRB Bit : MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W : 7 6 5 4 3 2 1 0 MSTPCRC Bit MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control. MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode. They are not initialized in software standby mode. MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6): These bits specify module stop mode. See table 21A.3 for the method of selecting the on-chip peripheral functions. MSTPCRA/MSTPCRB/ MSTPCRC Bits 7 to 0 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0 Description 0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) 1 Module stop mode is set (initial value of MSTPA5–0, MSTPB7–0, MSTPC7–0) Rev. 5.00 Jan 10, 2006 page 706 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21A.2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 21A.2 Medium-Speed Mode Transition and Clearance Timing Rev. 5.00 Jan 10, 2006 page 707 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.4 Sleep Mode 21A.4.1 Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPUís internal registers are retained. Other supporting modules do not stop. 21A.4.2 Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins. Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the stipulated reset input duration, driving the RES pin High starts the CPU performing reset exception processing. Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made to hardware standby mode. 21A.5 Module Stop Mode 21A.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21A.3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter and HCAN are retained. After reset clearance, all modules other than DTC are in module stop mode. Rev. 5.00 Jan 10, 2006 page 708 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Table 21A.3 MSTP Bits and Corresponding On-Chip Supporting Modules Register Bit MSTPCRA MSTPA7* Module MSTPA6 Data transfer controller (DTC) MSTPA5 MSTPA4* 16-bit timer pulse unit (TPU) MSTPA3 MSTPA2* Programmable pulse generator (PPG) MSTPA1 A/D converter MSTPA0* MSTPCRB MSTPB7 Serial communication interface 0 (SCI0) MSTPB6 Serial communication interface 1 (SCI1) MSTPB5 MSTPB4* Serial communication interface 2 (SCI2) MSTPB3* MSTPB2* MSTPB1* MSTPB0* MSTPCRC MSTPC7* MSTPC6* MSTPC5* MSTPC4 PC break controller (PBC) MSTPC3 HCAN MSTPC2* MSTPC1* MSTPC0* Note: * MSTPA7 is a readable/writable bit with an initial value of 0. MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. Rev. 5.00 Jan 10, 2006 page 709 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.5.2 Usage Notes DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. 21A.6 Software Standby Mode 21A.6.1 Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SBYCR SSBY bit = 1. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, A/D converter, HCAN and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21A.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by means of the RES pin or STBY pin. • Clearing with an interrupt When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. Rev. 5.00 Jan 10, 2006 page 710 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] • Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. • Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. 21A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 21A.4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21A.4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 20 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz Unit 0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 1 65536 states 3.3 4.1 5.5 6.6 0 131072 states 6.6 1 262144 states 1 1 0 1 8.2 13.1 16.4 10.9 21.8 8.2 13.1 16.4 26.2 32.8 8.2 10.9 16.4 21.8 32.8 43.6 65.6 0 Reserved — — — — — — — 1 16 states* 0.8 1.0 1.3 1.6 2.0 1.7 4.0 µs : Recommended time setting Note: * Do not use this setting. Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore, the standby time should be set to a value of 2 ms or greater. Rev. 5.00 Jan 10, 2006 page 711 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.6.4 Software Standby Mode Application Example Figure 21A.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 21A.3 Software Standby Mode Application Example Rev. 5.00 Jan 10, 2006 page 712 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer Function, for details of the write data buffer function. 21A.7 Hardware Standby Mode 21A.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2623 Group is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Rev. 5.00 Jan 10, 2006 page 713 of 1042 REJ09B0275-0500 Section 21A Power-Down Modes [H8S/2623 Group] 21A.7.2 Hardware Standby Mode Timing Figure 21A.4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21A.4 Hardware Standby Mode Timing 21A.8 φ Clock Output Disabling Function Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set. Table 21A.5 shows the state of the φ pin in each processing state. Table 21A.5 φ Pin State in Each Processing State DDR 0 1 1 PSTOP — 0 1 Hardware standby mode High impedance High impedance High impedance Software standby High impedance Fixed high Fixed high Sleep mode High impedance φ output Fixed high High-speed mode, medium-speed mode High impedance φ output Fixed high Rev. 5.00 Jan 10, 2006 page 714 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Section 21B Power-Down Modes [H8S/2626 Group] 21B.1 Overview In addition to the normal program execution state, the H8S/2626 Group has nine power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2626 operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Subactive mode* (4) Sleep mode (5) Subsleep mode* (6) Watch mode* (7) Module stop mode (8) Software standby mode (9) Hardware standby mode (2) to (9) are power-down modes. Sleep mode and sub-sleep mode are CPU states, medium-speed mode is a CPU and bus master state, sub-active mode is a CPU and bus master and internal peripheral function state, and module stop mode is an internal peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop mode. Note: * Subclock functions are available in the H8S/2626 Group. See section 20.7, Subclock Oscillator (H8S/2626 Group Only), for the method of fixing pins OSC1 and OSC2 when not used. Table 21B.1 shows the internal state of the LSI in the respective modes. Table 21B.2 shows the conditions for shifting between the power-down modes. Figure 21B.1 is a mode transition diagram. Rev. 5.00 Jan 10, 2006 page 715 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Table 21B.1 LSI Internal States in Each Mode Function HighSpeed System clock pulse generator Function- Function- Function- Function- Halted ing ing ing ing Subclock pulse generator Function- Function- Function- Function- Function- Function- Function- Function- Halted ing ing ing ing ing ing ing ing CPU MediumSpeed Sleep Module Stop Watch Subactive Software Hardware Subsleep Standby Standby Halted Halted Halted Halted Instructions Function- Medium- Halted High/ Halted Subclock Halted Halted Halted Registers ing speed (retained) medium- (retained) operation (retained) (retained) (undefined) operation speed operation Function- Function- Function- Function- Function- Function- Function- Function- Halted External NMI ing ing ing ing ing ing ing ing interrupts IRQ0–IRQ5 Peripheral WDT1 functions Function- Function- Function-  ing ing ing Subclock Subclock Subclock Halted Halted operation operation operation (retained) (reset) WDT0 Function- Function- Function-  ing ing ing Halted Subclock Subclock Halted Halted (retained) operation operation (retained) (reset) DTC Function- Medium- Function- Halted Halted Halted Halted Halted Halted ing speed ing (retained) (retained) (retained) (retained) (retained) (reset) operation TPU Function- Function- Function- Halted Halted ing ing (PBC ing (retained) (retained) mediumspeed operation) Halted Halted Halted Halted (retained) (retained) (retained) (reset) (PBC subclock operation) Function- Function- Function- Halted ing ing ing (reset) Halted (reset) PBC PPG D/A2, 3 SCI0 SCI1 Halted (reset) Halted (reset) Halted (reset) Halted (reset) SCI2 PWM A/D RAM Function- Function- Function- Function- Retained ing ing ing (DTC) ing Function- Retained ing Retained Retained I/O Function- Function- Function- Function- Retained ing ing ing ing Function- Retained ing Retained High impedance HCAN Function- Function- Function- Halted ing ing* ing (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Halted (reset) Notes: “Halted (retained)” means that internal register values are retained. The internal state is “operation suspended.” “Halted (reset)” means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). * Note, however, that registers cannot be read or written to. Rev. 5.00 Jan 10, 2006 page 716 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Program-halted state STBY pin = Low Hardware standby mode Reset state STBY pin = High RES pin = Low RES pin = High Program execution state SSBY = 0, LSON = 0 Sleep mode (main clock) SLEEP command High-speed mode (main clock) Any interrupt SCK2 to SCK0= 0 SCK2 to SCK0 0 Medium-speed mode (main clock) SLEEP command SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 1 Clock switching exception processing SLEEP command SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SLEEP command Interrupt*1 LSON bit = 1 Sub-active mode (subclock) Software standby mode External interrupt*3 Interrupt*1 LSON bit = 0 SLEEP command SSBY = 1, PSS = 1 DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to 0), clock switching exception processing SSBY = 1, PSS = 0, LSON = 0 SLEEP command Interrupt*2 : Transition after exception processing SSBY = 0, PSS = 1, LSON = 1 Sub-sleep mode (subclock) : Power-down mode Notes: When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven Low. From any state, a transition to hardware standby mode occurs when STBY is driven low. Always select high-speed mode before making a transition to watch mode or sub-active mode. 1. NMI, IRQ0 to IRQ5, and WDT1 interrupts 2. NMI, IRQ0 to IRQ5, WDT0 interrupts, and WDT1 interrupt. 3. NMI and IRQ0 to IRQ5 Figure 21B.1 Mode Transition Diagram Rev. 5.00 Jan 10, 2006 page 717 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Table 21B.2 Power-Down Mode Transition Conditions State After Transition State After Transition Back from Power-Down Invoked by SLEEP Mode Invoked by LSON DTON Command Interrupt Status of Control Bit at Transition Pre-Transition State SSBY PSS High-speed/ 0 Medium-speed 0 * 0 * Sleep High-speed/Medium-speed * 1 * — — 1 0 0 * Software standby High-speed/Medium-speed 1 0 1 * — — 1 1 0 0 Watch High-speed 1 1 1 0 Watch Sub-active 1 1 0 1 — — 1 1 1 1 Sub-active — 0 0 * * — — 0 1 0 * — — 0 1 1 * Sub-sleep Sub-active 1 0 * * — — 1 1 0 0 Watch High-speed 1 1 1 0 Watch Sub-active 1 1 0 1 High-speed — 1 1 1 1 — — Sub-active Legend: —: Do not set. *: Don’t care Rev. 5.00 Jan 10, 2006 page 718 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and MSTPCR registers. Table 21B.3 summarizes these registers. Table 21B.3 Power-Down Mode Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'08 H'FDE4 System clock control register SCKCR R/W H'00 H'FDE6 Low-power control register LPWRCR R/W H'00 H'FDEC Timer control/status register TCSR R/W H'00 H'FFA2 Module stop control register A, B, C MSTPCRA R/W H'3F H'FDE8 MSTPCRB R/W H'FF H'FDE9 MSTPCRC R/W H'FF H'FDEA Note: * Lower 16 bits of the address. 21B.2 Register Descriptions 21B.2.1 Standby Control Register (SBYCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W — — — SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev. 5.00 Jan 10, 2006 page 719 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by executing the SLEEP instruction, the operating mode is determined in combination with other control bits. Note that the value of the SSBY bit does not change even when shifting between modes using interrupts. Bit 7 SSBY Description 0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to sub-sleep mode when the SLEEP instruction is executed in sub-active mode. 1 (Initial value) Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode. Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in sub-active mode. Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time for clock stabilization when shifting to high-speed mode or medium-speed mode by using a specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode. With a quartz oscillator (table 21B.5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, there are no specific wait requirements. Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 0 Standby time = 32768 states 1 Standby time = 65536 states 0 Standby time = 131072 states 1 Standby time = 262144 states 0 Reserved 1 Standby time = 16 states 1 1 0 1 Rev. 5.00 Jan 10, 2006 page 720 of 1042 REJ09B0275-0500 (Initial value) Section 21B Power-Down Modes [H8S/2626 Group] Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the software standby mode, watch mode, and when making a direct transition. Bit 3 OPE Description 0 In software standby mode, watch mode, and when making a direct transition, address bus and bus control signals are high-impedance. 1 In software standby mode, watch mode, and when making a direct transition, the output state of the address bus and bus control signals is retained. (Initial value) Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to. 21B.2.2 System Clock Control Register (SCKCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PSTOP — — — STCS SCK2 SCK1 SCK0 0 0 0 0 0 0 0 0 R/W — — — R/W R/W R/W R/W SCKCR is an 8-bit readable/writable register that performs φ clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—φ φ Clock Output Disable (PSTOP): In combination with the DDR of the applicable port, this bit controls φ output. See section 21B.12, φ Clock Output Disabling Function, for details. Description PSTOP High-Speed Mode, Medium-Speed Mode, Sleep Mode, Sub-Active Mode Sub-Sleep Mode Software Standby Mode, Watch Mode, Hardware Direct Transition Standby Mode 0 φ output (initial value) φ output Fixed high High impedance 1 Fixed high Fixed high Fixed high High impedance Bit 7 Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified. Rev. 5.00 Jan 10, 2006 page 721 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation when the PLL circuit frequency multiplication factor is changed. Bit 3 STCS Description 0 Specified multiplication factor is valid after transition to software standby mode, watch mode, or subactive mode (Initial value) 1 Specified multiplication factor is valid immediately after STC bits are rewritten Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in high-speed mode, medium-speed mode, and sub-active mode. Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode. Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master in high-speed mode 1 Medium-speed clock is φ/2 1 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 0 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 — — 1 0 1 (Initial value) 21B.2.3 Low-Power Control Register (LPWRCR) Bit : Initial value : R/W : 7 6 DTON LSON 5 4 3 NESEL SUBSTP RFCUT 2 1 0 — STC1 STC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes. The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. The following describes bits 7 to 2. For details of other bits, see section 20.2.2, Low-Power Control Register (LPWRCR). Rev. 5.00 Jan 10, 2006 page 722 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies whether or not to make a direct transition between high-speed mode or medium-speed mode and the sub-active modes. The selected operating mode after executing the SLEEP instruction is determined by the combination of other control bits. Bit 7 DTON Description 0 • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. • When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or watch mode. (Initial value) • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts directly to sub-active mode*, or shifts to sleep mode or software standby mode. • When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed mode, or shifts to sub-sleep mode. 1 Note: Always set high-speed mode when shifting to watch mode or sub-active mode. * Bit 6—Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing the SLEEP instruction, this bit specifies the operating mode, in combination with other control bits. This bit also controls whether to shift to high-speed mode or sub-active mode when watch mode is cancelled. Bit 6 LSON Description 0 • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. • When the SLEEP instruction is executed in sub-active mode, operation shifts to watch mode or shifts directly to high-speed mode. 1 Note: * • Operation shifts to high-speed mode when watch mode is cancelled. • When the SLEEP instruction is executed in high-speed mode, operation shifts to watch mode or sub-active mode. • When the SLEEP instruction is executed in sub-active mode, operation shifts to subsleep mode or watch mode. • Operation shifts to sub-active mode when watch mode is cancelled. (Initial value) Always set high-speed mode when shifting to watch mode or sub-active mode. Rev. 5.00 Jan 10, 2006 page 723 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling frequency of the subclock (φSUB) generated by the subclock oscillator is sampled by the clock (φ) generated by the system clock oscillator. Set this bit to 0 when φ=5MHz or more. Bit 5 NESEL Description 0 Sampling using 1/32 xφ 1 Sampling using 1/4 xφ (Initial value) Bit 4—Subclock enable (SUBSTP): This bit enables/disables subclock generation. Bit 4 SUBSTP Description 0 Enables subclock generation 1 Disables subclock generation (Initial value) Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the internal feedback resistance of the main clock oscillation circuit ON/OFF. Bit 3 RFCUT Description 0 When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. (Initial value) 1 Sets the feedback resistance OFF. Bit 2—Reserved: Only write 0 to this bit. Rev. 5.00 Jan 10, 2006 page 724 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.2.4 Timer Control/Status Register (TCSR) Bit : Initial value : R/W Note: : 7 6 5 4 3 2 1 0 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Only write 0 to clear the flag. * TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode. Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer Control/Status Register (TCSR). The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized in software standby mode. Bit 4—Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT. It also controls operation when shifting low power dissipation modes. The operating mode selected after the SLEEP instruction is executed is determined in combination with other control bits. For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register (TCSR), and this section. Bit 4 PSS Description 0 • TCNT counts the divided clock from the φ -based prescaler (PSM). • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode or software standby mode. (Initial value) • TCNT counts the divided clock from the φsubclock-based prescaler (PSS). • When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts to sleep mode, watch mode*, or sub-active mode*. When the SLEEP instruction is executed in sub-active mode*, operation shifts to sub-sleep mode*, watch mode*, or high-speed mode. 1 • Note: * Always set high-speed mode when shifting to watch mode or sub-active mode. Rev. 5.00 Jan 10, 2006 page 725 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.2.5 Module Stop Control Register (MSTPCR) MSTPCRA Bit : 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : R/W : 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MSTPCRB Bit : MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : R/W 1 1 1 1 1 1 1 1 : R/W R/W R/W R/W R/W R/W R/W R/W : 7 6 5 4 3 2 1 0 MSTPCRC Bit MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : R/W : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control. MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode. They are not initialized in software standby mode. MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0): These bits specify module stop mode. See table 21B.4 for the method of selecting the on-chip peripheral functions. MSTPCRA/MSTPCRB/ MSTPCRC Bits 7 to 0 MSTPA7 to MSTPA0, MSTPB7 to MSTPB0, MSTPC7 to MSTPC0 Description 0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) 1 Module stop mode is set (initial value of MSTPA5–0, MSTPB7–0, MSTPC7–0) Rev. 5.00 Jan 10, 2006 page 726 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.3 Medium-Speed Mode In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and LSON bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LPWRCR LSON bit = 0, and TCSR (WDT1) PSS bit = 0, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21B.2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 21B.2 Medium-Speed Mode Transition and Clearance Timing Rev. 5.00 Jan 10, 2006 page 727 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.4 Sleep Mode 21B.4.1 Sleep Mode When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. 21B.4.2 Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins. Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the stipulated reset input duration, driving the RES pin High starts the CPU performing reset exception processing. Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made to hardware standby mode. 21B.5 Module Stop Mode 21B.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21B.4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, A/D converter and HCAN are retained. After reset clearance, all modules other than DTC are in module stop mode. Rev. 5.00 Jan 10, 2006 page 728 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Table 21B.4 MSTP Bits and Corresponding On-Chip Supporting Modules Register Bit MSTPCRA MSTPA7* Module MSTPA6 Data transfer controller (DTC) MSTPA5 MSTPA4* 16-bit timer pulse unit (TPU) MSTPA3 MSTPA2* Programmable pulse generator (PPG) MSTPA1 A/D converter MSTPA0* MSTPCRB MSTPB7 Serial communication interface 0 (SCI0) MSTPB6 Serial communication interface 1 (SCI1) MSTPB5 MSTPB4* Serial communication interface 2 (SCI2) MSTPB3* MSTPB2* MSTPB1* MSTPB0* MSTPCRC MSTPC7* MSTPC6* MSTPC5 D/A converter (channels 2, 3) MSTPC4 PC break controller (PBC) MSTPC3 HCAN MSTPC2* MSTPC1* MSTPC0* Note: * MSTPA7 is a readable/writable bit with an initial value of 0. MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC4, and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. Rev. 5.00 Jan 10, 2006 page 729 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.5.2 Usage Notes DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6 bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 8, Data Transfer Controller (DTC). On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. 21B.6 Software Standby Mode 21B.6.1 Software Standby Mode A transition is made to software standby mode when the SLEEP instruction is executed when the SBYCR SSBY bit = 1 and the LPWRCR LSON bit = 0, and the TCSR (WDT1) PSS bit = 0. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI, A/D converter, HCAN and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21B.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by means of the RES pin or STBY pin. • Clearing with an interrupt When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 Rev. 5.00 Jan 10, 2006 page 730 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. • Clearing with the RES pin When the RES pin is driven Low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held Low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. • Clearing with the STBY pin When the STBY pin is driven Low, a transition is made to hardware standby mode. 21B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 21B.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21B.5 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 20 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz Unit 0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 1 65536 states 3.3 4.1 5.5 6.6 0 131072 states 6.6 1 262144 states 1 1 0 1 8.2 13.1 16.4 10.9 21.8 8.2 13.1 16.4 26.2 32.8 8.2 10.9 16.4 21.8 32.8 43.6 65.6 0 Reserved — — — — — — — 1 16 states* 0.8 1.0 1.3 1.6 2.0 1.7 4.0 µs : Recommended time setting Note: * Do not use this setting. Using an External Clock: It is necessary to allow time for the PLL circuit to stabilize. Therefore, the standby time should be set to a value of 2 ms or greater. Rev. 5.00 Jan 10, 2006 page 731 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.6.4 Software Standby Mode Application Example Figure 21B.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 21B.3 Software Standby Mode Application Example Rev. 5.00 Jan 10, 2006 page 732 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer Function, for details of the write data buffer function. 21B.7 Hardware Standby Mode 21B.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2626 Group is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Rev. 5.00 Jan 10, 2006 page 733 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.7.2 Hardware Standby Mode Timing Figure 21B.4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21B.4 Hardware Standby Mode Timing 21B.8 Watch Mode 21B.8.1 Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or sub-active mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR (WDT1) PSS = 1. In watch mode, the CPU is stopped and supporting modules other than WDT1 are also stopped. The contents of the CPU is internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, HCAN) and I/O ports are retained. Rev. 5.00 Jan 10, 2006 page 734 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.8.2 Exiting Watch Mode Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at the RES, or STBY pins. (1) Exiting Watch Mode by Interrupts When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed. In the case of IRQ0 to IRQ5 interrupts, no transition is made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. See section 21B.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode, for how to set the oscillation stabilization time when making a transition from watch mode to high-speed mode. (2) Exiting Watch Mode by RES pins For exiting watch mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2, Clearing Software Standby Mode. (3) Exiting Watch Mode by STBY pin When the STBY pin level is driven Low, a transition is made to hardware standby mode. 21B.8.3 Notes (1) I/O Port Status The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the address bus and bus control signals continue to be output. Therefore, when a High level is output, the current consumption is not diminished by the amount of current to support the High level output. (2) Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during stabilization of oscillation. Rev. 5.00 Jan 10, 2006 page 735 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.9 Sub-Sleep Mode 21B.9.1 Sub-Sleep Mode When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode. In sub-sleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are also stopped. The contents of the CPUís internal registers, the data in internal RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, HCAN) and I/O ports are retained. 21B.9.2 Exiting Sub-Sleep Mode Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or IRQ0 to IRQ5), or signals at the RES or STBY pins. (1) Exiting Sub-Sleep Mode by Interrupts When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts. In the case of IRQ0 to IRQ5 interrupts, sub-sleep mode is not cancelled if the corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting modules, the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU. (2) Exiting Sub-Sleep Mode by RES For exiting sub-sleep mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2, Clearing Software Standby Mode. (3) Exiting Sub-Sleep Mode by STBY Pin When the STBY pin level is driven Low, a transition is made to hardware standby mode. Rev. 5.00 Jan 10, 2006 page 736 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.10 Sub-Active Mode 21B.10.1 Sub-Active Mode When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a transition is made to sub-active mode. In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed step by step. Supporting modules other than WDT0, and WDT1 are also stopped. When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0. 21B.10.2 Exiting Sub-Active Mode Sub-active mode is exited by the SLEEP instruction or the RES or STBY pins. (1) Exiting Sub-Active Mode by SLEEP Instruction When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 0, and TCSR (WDT1) PSS bit = 1, the CPU exits sub-active mode and a transition is made to watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1, and TCSR (WDT1) PSS bit = 1, a transition is made to sub-sleep mode. Finally, when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT1) PSS bit = 1, a direct transition is made to high-speed mode (SCK0 to SCK2 all 0). See section 21B.11, Direct Transitions, for details of direct transitions. (2) Exiting Sub-Active Mode by RES Pins For exiting sub-active mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2, Clearing Software Standby Mode. (3) Exiting Sub-Active Mode by STBY Pin When the STBY pin level is driven Low, a transition is made to hardware standby mode. Rev. 5.00 Jan 10, 2006 page 737 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.11 Direct Transitions 21B.11.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution when shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. (1) Direct Transitions from High-Speed Mode to Sub-Active Mode Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 1, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a transition to subactive mode. (2) Direct Transitions from Sub-Active Mode to High-Speed Mode Execute the SLEEP instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 0, and DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed. 21B.12 φ Clock Output Disabling Function Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set. Table 21B.6 shows the state of the φ pin in each processing state. Table 21B.6 φ Pin State in Each Processing State DDR 0 1 1 PSTOP — 0 1 Hardware standby mode High impedance High impedance High impedance Software standby mode, watch mode, and direct transition High impedance Fixed high Fixed high Sleep mode and subsleep mode High impedance φ output Fixed high High-speed mode, medium-speed mode, and subactive mode High impedance φ output Fixed high Rev. 5.00 Jan 10, 2006 page 738 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] 21B.13 Usage Notes 1. When making a transition to sub-active mode or watch mode, set the DTC to enter module stop mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant bits in MSTPCR) until a transition from sub-active mode to high-speed mode or medium-speed mode has been performed. If a DTC activation source occurs in sub-active mode, the DTC will be activated only after module stop mode has been cleared and high-speed mode or medium-speed mode has been entered. 2. The on-chip peripheral modules (DTC and TPU) which halt operation in sub-active mode cannot clear an interrupt in sub-active mode. Therefore, if a transition is made to sub-active mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter sub-active mode or watch mode. Rev. 5.00 Jan 10, 2006 page 739 of 1042 REJ09B0275-0500 Section 21B Power-Down Modes [H8S/2626 Group] Rev. 5.00 Jan 10, 2006 page 740 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) Section 22 Electrical Characteristics (Preliminary) 22.1 Absolute Maximum Ratings Table 22.1 lists the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings — Preliminary — Item Symbol Value Unit Power supply voltage VCC –0.3 to +4.3 V PVCC1–4 –0.3 to +7.0 V Input voltage (XTAL, EXTAL, OSC1, OSC2) Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Input voltage (except ports 4 and 9) Vin –0.3 to PVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.3 V Analog power supply voltage AVCC –0.3 to +7.0 V Analog input voltage VAN –0.3 to AVCC +0.3 V Operating temperature Topr Regular specifications: –20 to +75 °C Wide-range specifications: –40 to +85 °C –55 to +125 °C PLLVCC Storage temperature Tstg Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Rev. 5.00 Jan 10, 2006 page 741 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) 22.2 DC Characteristics Table 22.2 lists the DC characteristics. Table 22.3 lists the permissible output currents. Table 22.2 DC Characteristics — Preliminary — Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Item Symbol Schmitt trigger input voltage IRQ0 to IRQ5 VT Input high voltage – + VT Output high Max Unit PVCC × 0.2 — — V — — RES, STBY, VIH NMI, MD2 to MD0, FWE PVCC × 0.9 PVCC + 0.3 V EXTAL, OSC1 VCC × 0.7 — VCC + 0.3 Ports 1, A to F, HRxD PVCC × 0.7 — PVCC + 0.3 V – — Test Conditions PVCC × 0.7 V — V V AVCC × 0.7 — AVCC + 0.3 V –0.3 — PVCC × 0.1 V EXTAL, OSC1 –0.3 — VCC × 0.2 Ports 1, A to F, HRxD –0.3 — PVCC × 0.2 V Ports 4 and 9 –0.3 — AVCC × 0.2 V All output pins VOH PVCC – 0.5 — — V IOH = –200 µA PVCC – 1.0 — — V IOH = –1 mA — — 0.4 V IOL = 1.6 mA — — 1.0 µA — — 1.0 µA Vin = 0.5 to PVCC – 0.5 V — — 1.0 µA RES, STBY, NMI, MD2 to MD0, FWE VIL voltage Output low voltage Typ PVCC × 0.05 — + VT – VT Port 4 and 9 Input low voltage Min All output pins VOL Input leakage RES | Iin | current STBY, NMI, HRxD, MD2 to MD0, FWE Ports 4 and 9 Rev. 5.00 Jan 10, 2006 page 742 of 1042 REJ09B0275-0500 V Vin = 0.5 to AVCC – 0.5 V Section 22 Electrical Characteristics (Preliminary) Item Three-state leakage current (off state) Symbol Typ Max Unit — — 1.0 µA Vin = 0.5 to PVCC – 0.5 V –IP 30 — 300 µA Vin = 0 V Cin — — 30 pF NMI — — 30 pF All input pins except RES and NMI — — 15 pF Vin = 0 V, f = 1 MHz, Ta = 25°C — 55 65 mA VCC = 3.3 V VCC = 3.6 V f = 20 MHz Sleep mode — 50 mA 40 VCC = 3.3 V VCC = 3.6 V f = 20 MHz All modules stopped — 40 — mA f = 20 MHz, VCC = 3.3 V (reference values) Mediumspeed mode (φ/32) — 30 — mA f = 20 MHz, VCC = 3.3 V (reference values) Subactive mode — 90 200 µA Using 32.768 kHz crystal resonator Subsleep mode — 120 µA Using 32.768 kHz crystal resonator Watch mode — 30 µA Using 32.768 kHz crystal resonator Ports 1, A to F ITSI MOS input Ports A to E pull-up current Input capacitance Current 2 dissipation* Test Conditions Min RES Normal operation 4 ICC* VCC = 3.3 V 60 VCC = 3.3 V 12 VCC = 3.3 V Standby 3 mode* — 2.0 5.0 µA Ta ≤ 50°C — — 20 µA 50°C < Ta Rev. 5.00 Jan 10, 2006 page 743 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) Item Port power supply current During operation Symbol Min Typ Max Unit PICC — 15 20 mA PVCC = 5.0 V PVCC = 5.5 V — 5.0 In standby 3 mode* Analog During A/D power supply and D/A current conversion — AlCC — — — 5.0 µA AlCC — 2.5 4.0 mA — — 5.0 µA VRAM 2.0 — — V Idle RAM standby voltage µA PVCC = 5.5 V Idle Reference During A/D power supply and D/A current conversion Test Conditions 1.0 2.0 mA AVCC = 5.0 V Vref = 5.0 V Notes: 1. If the A/D and D/A converter is not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to PVCC, for instance. Set Vref ≤ AVCC. 2. Current dissipation values are for VIH = VCC (EXTAL, OSC1), AVCC (ports 4 and 9), or PVCC (other), and VIL = 0 V, with all output pins unloaded and the on-chip MOS pull-up transistors in the off state. 3. The values are for VRAM ≤ PVCC < 3.0 V, VIH min = VCC – 0.1 V, and VIL max = 0.1 V. 4. ICC depends on VCC and f as follows: ICC max = 8.0 (mA) + 0.8 (mA/(MHz × V)) × VCC × f (normal operation) ICC max = 8.0 (mA) + 0.58 (mA/(MHz × V)) × VCC × f (sleep mode) 5. Applies to the mask ROM version only. Rev. 5.00 Jan 10, 2006 page 744 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) Table 22.3 Permissible Output Currents — Preliminary — Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins PVCC = 4.5 V to 5.5 V IOL — — 10 mA Permissible output low current (total) Total of all output pins PVCC = 4.5 V to 5.5 V ∑ IOL — — 100 mA Permissible output All output high current (per pin) pins PVCC = 4.5 V to 5.5 V –IOH — — 2.0 mA Permissible output high current (total) PVCC = 4.5 V to 5.5 V ∑ –IOH — — 30 mA Note: 22.3 * Total of all output pins To protect chip reliability, do not exceed the output current values in table 22.3. AC Characteristics Figure 22.1 show, the test conditions for the AC characteristics. 3V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement levels • Low level : 0.8 V • High level : 2.0 V Figure 22.1 Output Load Circuit Rev. 5.00 Jan 10, 2006 page 745 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) 22.3.1 Clock Timing Table 22.4 lists the clock timing Table 22.4 Clock Timing — Preliminary — Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 50 250 ns Figure 22.2 Clock high pulse width tCH 15 — ns Clock low pulse width tCL 15 — ns Clock rise time tCr — 5 ns Clock fall time tCf — 5 ns Oscillation stabilization time at reset (crystal) tOSC1 20 — ms Figure 22.3 Oscillation stabilization time in software standby (crystal) tOSC2 8 — ms Figure 21A.3, Figure 21B.3 External clock output stabilization delay time tDEXT 2 — ms Figure 22.3 32-kHz clock oscillation settling time tOSC3 — 2 s Sub clock oscillator frequency fSUB 32.768 — kHz Sub clock (φSUB) cycle time tSUB 30.5 — µs tcyc tCH tCf φ tCL tCr Figure 22.2 System Clock Timing Rev. 5.00 Jan 10, 2006 page 746 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 22.3 Oscillation Stabilization Timing 22.3.2 Control Signal Timing Table 22.5 lists the control signal timing. Table 22.5 Control Signal Timing Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 — ns Figure 22.4 RES pulse width tRESW 20 — tcyc NMI setup time tNMIS 150 — ns NMI hold time tNMIH 10 — NMI pulse width (exiting software standby mode) tNMIW 200 — ns IRQ setup time tIRQS 150 — ns IRQ hold time tIRQH 10 — ns IRQ pulse width (exiting software standby mode) tIRQW 200 — ns Figure 22.5 Rev. 5.00 Jan 10, 2006 page 747 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) φ tRESS tRESS RES tRESW Figure 22.4 Reset Input Timing φ tNMIH tNMIS NMI tNMIW IRQi (i = 0 to 2) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input Figure 22.5 Interrupt Input Timing Rev. 5.00 Jan 10, 2006 page 748 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) 22.3.3 Bus Timing Table 22.6 lists the bus timing. Table 22.6 Bus Timing — Preliminary — Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Address delay time tAD — 25 ns Address setup time tAS 0.5 × tcyc – 20 — ns Figure 22.6 to Figure 22.10 Address hold time tAH 0.5 × tcyc – 15 — ns AS delay time tASD — 20 ns RD delay time 1 tRSD1 — 20 ns RD delay time 2 tRSD2 — 20 ns Read data setup time tRDS 15 — ns Read data hold time tRDH 0 — ns Read data access time 1 tACC1 — 1.0 × tcyc – 35 ns Read data access time 2 tACC2 — 1.5 × tcyc – 25 ns Read data access time 3 tACC3 — 2.0 × tcyc – 35 ns Read data access time 4 tACC4 — 2.5 × tcyc – 25 ns Read data access time 5 tACC5 — 3.0 × tcyc – 35 ns WR delay time 1 tWRD1 — 20 ns WR delay time 2 tWRD2 — 20 ns WR pulse width 1 tWSW1 1.0 × tcyc – 20 — ns WR pulse width 2 tWSW2 1.5 × tcyc – 20 — ns Write data delay time tWDD — 30 ns Write data setup time tWDS 0.5 × tcyc – 20 — ns Write data hold time tWDH 0.5 × tcyc – 10 — ns WAIT setup time tWTS 30 — ns WAIT hold time tWTH 5 — ns Figure 22.8 Rev. 5.00 Jan 10, 2006 page 749 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) Item Symbol Min Max Unit Test Conditions BREQ setup time tBRQS 30 — ns Figure 22.11 BACK delay time tBACD — 15 ns Bus-floating time tBZD — 50 ns BREQO delay time tBRQOD — 25 ns T1 T2 φ tAD A23 to A0 tAS tAH tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 22.6 Basic Bus Timing (Two-State Access) Rev. 5.00 Jan 10, 2006 page 750 of 1042 REJ09B0275-0500 Figure 22.12 Section 22 Electrical Characteristics (Preliminary) T1 T2 T3 φ tAD A23 to A0 tAS tAH tASD tASD AS tRSD1 RD (read) tRSD2 tACC4 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 22.7 Basic Bus Timing (Three-State Access) Rev. 5.00 Jan 10, 2006 page 751 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) T1 T2 TW T3 φ A23 to A0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 22.8 Basic Bus Timing (Three-State Access with One Wait State) Rev. 5.00 Jan 10, 2006 page 752 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAS tASD tASD tAH AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 22.9 Burst ROM Access Timing (Two-State Access) Rev. 5.00 Jan 10, 2006 page 753 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) T1 T2 or T3 T1 φ tAD A23 to A0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 22.10 Burst ROM Access Timing (One-State Access) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD A23 to A0, AS, RD, HWR, LWR Figure 22.11 External Bus Release Timing Rev. 5.00 Jan 10, 2006 page 754 of 1042 REJ09B0275-0500 tBZD Section 22 Electrical Characteristics (Preliminary) φ tBRQOD tBRQOD BREQO Figure 22.12 External Bus Request Output Timing Rev. 5.00 Jan 10, 2006 page 755 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) 22.3.4 Timing of On-Chip Supporting Modules Table 22.7 lists the timing of on-chip supporting modules. Table 22.7 Timing of On-Chip Supporting Modules — Preliminary — Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 32.768 kHz, 4 to 20 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item I/O port TPU SCI Symbol Min Max Unit Test Conditions Output data delay time tPWD — 50 ns Figure 22.13 Input data setup time tPRS 30 — Input data hold time tPRH 30 — Timer output delay time tTOCD — 50 ns Figure 22.14 Timer input setup time tTICS 30 — Timer clock input setup time tTCKS 30 — ns Figure 22.15 Timer clock pulse width Single edge tTCKWH 1.5 — tcyc Both edges tTCKWL 2.5 — Input clock cycle Asynchronous tScyc 4 — 6 — Synchronous A/D converter HCAN* tcyc Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 tcyc Input clock fall time tSCKf — 1.5 Transmit data delay time tTXD — 50 Receive data setup time (synchronous) tRXS 50 — Receive data hold time (synchronous) tRXH 50 — Trigger input setup time tTRGS 30 Transmit data delay time tHTXD Transmit data setup time Transmit data hold time Figure 22.16 ns Figure 22.17 — ns Figure 22.18 — 100 ns Figure 22.19 tHRXS 100 — tHRXH 100 — Rev. 5.00 Jan 10, 2006 page 756 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) Item Symbol Min Max Unit Test Conditions tPOD — 50 ns Figure 22.20 PPG Pulse output delay time WDT0 Overflow output delay time tWOVD — 50 ns Figure 22.21 Buzz output delay time — 50 ns Figure 22.22 WDT1 Note: * tBUZD The HCAN input signal is asynchronous. However, its state is judged to have changed at the leading edge (two clock cycles) of the CK clock signal shown in figure 22.19. The HCAN output signal is also asynchronous. Its state changes based on the leading edge (two clock cycles) of the CK clock signal shown in figure 22.19. T1 T2 φ tPRS tPRH Ports 1, 4, 9 A to F (read) tPWD Ports 1, A to F (write) Figure 22.13 I/O Port Input/Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22.14 TPU Input/Output Timing Rev. 5.00 Jan 10, 2006 page 757 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 22.15 TPU Clock Input Timing tSCKW tSCKr tSCKf SCK0 to SCK3 tScyc Figure 22.16 SCK Clock Input Timing SCK0 to SCK3 tTXD TxD0 to TxD3 (transit data) tRXS tRXH RxD0 to RxD3 (receive data) Figure 22.17 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 22.18 A/D Converter External Trigger Input Timing Rev. 5.00 Jan 10, 2006 page 758 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) (Preliminary) VOL VOL CK tHTXD TX (transmit data ) tHRXS tHRXH RX (receive data) Figure 22.19 HCAN Input/Output Timing φ tPOD PO15 to 8 Figure 22.20 PPG Output Timing φ tWOVD tWOVD WDTOVF Figure 22.21 WDT0 Output Timing φ tBUZD tBUZD BUZZ Figure 22.22 WDT1 Output Timing Rev. 5.00 Jan 10, 2006 page 759 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) 22.4 A/D Conversion Characteristics Table 22.8 lists the A/D conversion characteristics. Table 22.8 A/D Conversion Characteristics — Preliminary — Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 4 to 20 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time — — — µs 10 — — Analog input capacitance — — 20 pF Permissible signal-source impedance — — 5 kΩ Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization — ±0.5 — LSB Absolute accuracy — — ±4.0 LSB 22.5 Test Conditions AVCC < 4.5 V AVCC ≥ 4.5 V D/A Conversion Characteristics Table 22.9 shows the D/A conversion characteristics. Table 22.9 D/A Conversion Characteristics Conditions: VCC = PLLVCC = 3.0 V to 3.6 V, PVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 4 to 20 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min Typ Max Unit Resolution 8 8 8 bits Conversion time — — 10 µs 20-pF capacitive load Absolute accuracy — ±1.5 ±2.0 LSB 2-MΩ resistive load — — ±1.5 LSB 4-MΩ resistive load Rev. 5.00 Jan 10, 2006 page 760 of 1042 REJ09B0275-0500 Test Conditions Section 22 Electrical Characteristics (Preliminary) 22.6 Flash Memory Characteristics Table 22.10 Flash Memory Characteristics Conditions: VCC = 3.0 to 3.6 V, AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Programming time*1 *2 *4 Erase time*1 *3 *5 tP — 10 200 ms/128 bytes tE — 100 1000 ms/block Number of rewrites NWEC — — 100 Times Wait time after SWE1 bit setting*1 Wait time after PSU1 bit setting*1 x0 1 — — µs y 50 — — µs Wait time after P1 bit setting*1 *4 z0 — — 30 µs z1 — — 10 µs z2 — — 200 µs Wait time after P1 bit clearing*1 α 5 — — µs Wait time after PSU1 bit clearing*1 Wait time after PV1 bit setting*1 β 5 — — µs γ 4 — — µs Wait time after H'FF dummy write*1 Wait time after PV1 bit clearing*1 ε 2 — — µs η 2 — — µs Maximum number of writes*1 *4 N1 — — 6 Times Programming Common Erasing N2 — — 994 Times Wait time after SWE1 bit clearing*1 Wait time after SWE1 bit setting*1 x1 100 — — µs x 1 — — µs Wait time after ESU1 bit setting*1 Wait time after E1 bit setting*1 *5 y 100 — — µs z — — 10 ms Wait time after E1 bit clearing*1 α 10 — — µs Wait time after ESU1 bit clearing*1 Wait time after EV1 bit setting*1 β 10 — — µs γ 6 — — µs Wait time after H'FF dummy write*1 Wait time after EV1 bit clearing*1 ε 2 — — µs η 4 — — µs Maximum number of erases*1 *5 Notes: N — — 100 Times 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P1 bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E1 bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time (tP(max) = Wait time after P1 bit setting (z) × maximum number of writes (N)) (z0 + z1) × 6 + z2 × 994 5. Maximum erase time (tE(max) = Wait time after E1 bit setting (z) × maximum number of erases (N)) Rev. 5.00 Jan 10, 2006 page 761 of 1042 REJ09B0275-0500 Section 22 Electrical Characteristics (Preliminary) 22.7 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. Therefore, if a system is evaluated using the F-ZTAT version, a similar evaluation should also be performed using the mask ROM version. Rev. 5.00 Jan 10, 2006 page 762 of 1042 REJ09B0275-0500 Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation Rs General register (destination)* General register (source)* Rn General register* Rd ERn General register (32-bit register) MAC Multiply-and-accumulate register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Add – Subtract × Multiply ÷ Divide ∧ Logical AND ∨ Logical OR ⊕ Logical exclusive OR → Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ¬ Logical NOT (logical complement) ( ) < > Contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 5.00 Jan 10, 2006 page 763 of 1042 REJ09B0275-0500 Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of instruction * Undetermined (no guaranteed value) 0 Always cleared to 0 1 Always set to 1 — Not affected by execution of the instruction Rev. 5.00 Jan 10, 2006 page 764 of 1042 REJ09B0275-0500 MOV B B B B W 4 W W MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd B MOV.B Rs,@(d:16,ERd) B B MOV.B Rs,@ERd MOV.B Rs,@(d:32,ERd) B MOV.B @aa:32,Rd B MOV.B @ERs+,Rd B B MOV.B @(d:32,ERs),Rd B B MOV.B @(d:16,ERs),Rd MOV.B @aa:16,Rd B MOV.B @ERs,Rd MOV.B @aa:8,Rd B MOV.B Rs,Rd Operand Size B 2 #xx MOV.B #xx:8,Rd Mnemonic Rn 2 2 @ERn 2 2 2 @(d,ERn) 8 4 8 4 @–ERn/@ERn+ 2 2 2 @aa @(d,PC) 6 4 2 6 4 — — — — — — — — #xx:16→Rd16 Rs16→Rd16 @ERs→Rd16 — — Rs8→@(d:16,ERd) Rs8→@aa:32 — — Rs8→@ERd — — — — @aa:32→Rd8 Rs8→@aa:16 — — @aa:16→Rd8 — — — — @aa:8→Rd8 — — — — @ERs→Rd8,ERs32+1→ERs32 ERd32-1→ERd32,Rs8→@ERd — — @(d:32,ERs)→Rd8 Rs8→@aa:8 — — @(d:16,ERs)→Rd8 — — — — @ERs→Rd8 Rs8→@(d:32,ERd) — — Rs8→Rd8 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 2 1 2 4 3 2 3 5 3 2 4 3 2 3 5 3 2 1 1 Advanced 0 — I H N Z V C — — Operation #xx:8→Rd8 No. of States*1 Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Table A.1 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Instruction Set (1) Data Transfer Instructions Rev. 5.00 Jan 10, 2006 page 765 of 1042 REJ09B0275-0500 MOV Rev. 5.00 Jan 10, 2006 page 766 of 1042 REJ09B0275-0500 L L MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd L L MOV.L ERs,ERd MOV.L @aa:32,ERd L 6 MOV.L #xx:32,ERd L W MOV.W Rs,@aa:32 MOV.L @aa:16,ERd W MOV.W Rs,@aa:16 L W MOV.W Rs,@-ERd L W MOV.W Rs,@(d:32,ERd) MOV.L @ERs+,ERd W MOV.W Rs,@(d:16,ERd) MOV.L @(d:32,ERs),ERd W W W MOV.W @aa:16,Rd MOV.W Rs,@ERd W MOV.W @ERs+,Rd MOV.W @aa:32,Rd W W MOV.W @(d:16,ERs),Rd Operand Size #xx MOV.W @(d:32,ERs),Rd Rn 2 @ERn 4 2 4 @(d,ERn) 10 6 8 4 8 @–ERn/@ERn+ 4 2 2 @aa 8 6 6 4 6 4 — — — — — — — — — — @aa:32→Rd16 Rs16→@ERd Rs16→@(d:16,ERd) Rs16→@(d:32,ERd) — — — — — — — — — — — — Rs16→@aa:32 #xx:32→ERd32 ERs32→ERd32 @ERs→ERd32 @(d:16,ERs)→ERd32 @(d:32,ERs)→ERd32 — — — — @aa:16→ERd32 @aa:32→ERd32 @ERs→ERd32,ERs32+4→ERs32 — — — — Rs16→@aa:16 ERd32-2→ERd32,Rs16→@ERd — — — — @aa:16→Rd16 @ERs→Rd16,ERs32+2→ERs32 — — — — @(d:32,ERs)→Rd16 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — I H N Z V C @(d:16,ERs)→Rd16 Operation ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @(d,PC) Addressing Mode/ Instruction Length (Bytes) 6 5 5 7 5 4 1 3 4 3 3 5 3 2 4 3 3 5 3 Advanced No. of States*1 Appendix A Instruction Set #xx — — — — — — — — — — — — — — @SP→Rn16,SP+2→SP @SP→ERn32,SP+4→SP SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) [2] [2] Cannot be used in the H8S/2626 Group or H8S/2623 Group Cannot be used in the H8S/2626 Group or H8S/2623 Group MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MOVFPE MOVTPE 4 Repeated for each register saved (SP-4→SP,ERn32→@SP) Repeated for each register restored L STM (ERm-ERn),@-SP — — — — — — 7/9/11 [1] 7/9/11 [1] 5 3 STM 4 0 — 0 — L 4 2 LDM @SP+,(ERm-ERn) 5 3 6 5 5 7 5 4 LDM 0 — 0 — 0 — — — ERs32→@aa:32 0 — — — ERs32→@aa:16 0 — 0 — 0 — 0 — L PUSH 4 2 — — ERs32→@(d:32,ERd) ERd32-4→ERd32,ERs32→@ERd — — — — PUSH.L ERn W POP.W Rn 8 6 — — ERs32→@(d:16,ERd) Advanced I H N Z V C ERs32→@ERd Operation L L MOV.L ERs,@aa:32 @–ERn/@ERn+ 4 @aa @(d,PC) W L MOV.L ERs,@aa:16 @@aa PUSH.W Rn L MOV.L ERs,@-ERd 10 Rn MOV.L ERs,@(d:32,ERd) L 4 @ERn 6 L @(d,ERn) MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@ERd — POP.L ERn POP MOV Operand Size Mnemonic No. of States*1 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 767 of 1042 REJ09B0275-0500 L B W W L ADDS #4,ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd W 4 L ADDS #2,ERd SUB.W #xx:16,Rd L ADDS #1,ERd B B ADDX Rs,Rd SUB.B Rs,Rd B 2 ADDX #xx:8,Rd SUB L ADD.L ERs,ERd L L 6 ADD.L #xx:32,ERd B W ADD.W Rs,Rd DAA Rd W 4 ADD.W #xx:16,Rd INC.L #2,ERd B 2 B ADD.B Rs,Rd Operand Size ADD.B #xx:8,Rd #xx DAA INC ADDS ADDX ADD Rn 2 2 2 2 2 2 2 2 2 2 2 2 2 2 I H N Z V C 1 1 1 1 1 1 1 1 1 —— — —— — — — — — —— — —— — — — —— — —— — — — [4] Rd8+#xx:8+C→Rd8 Rd8+Rs8+C→Rd8 ERd32+1→ERd32 ERd32+2→ERd32 ERd32+4→ERd32 1 —— —— —— —— —— — * — — [3] Rd8+1→Rd8 Rd16+1→Rd16 Rd16+2→Rd16 ERd32+1→ERd32 ERd32+2→ERd32 Rd8 decimal adjust→Rd8 Rd8-Rs8→Rd8 Rd16-#xx:16→Rd16 * 1 2 1 1 [5] [5] 3 1 2 1 — [4] — [3] — [3] Rd16+Rs16→Rd16 — Rd16+#xx:16→Rd16 — Rd8+#xx:8→Rd8 Rd8+Rs8→Rd8 ERd32+ERs32→ERd32 1 Advanced No. of States*1 ERd32+#xx:32→ERd32 Operation ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Rev. 5.00 Jan 10, 2006 page 768 of 1042 REJ09B0275-0500 ↔ ↔ ↔ ↔ — @@aa @aa @(d,PC) @–ERn/@ERn+ @(d,ERn) @ERn Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set (2) Arithmetic Instructions L L B B W B W DEC.L #2,ERd DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS.B Rs,Rd MULXS.W Rs,ERd DAS MULXU MULXS DEC DEC.L #1,ERd L SUBS #2,ERd W L SUBS #1,ERd DEC.W #2,Rd B SUBX Rs,Rd W B 2 SUBX #xx:8,Rd DEC.W #1,Rd L SUB.L ERs,ERd L L 6 SUB.L #xx:32,ERd B W SUB.W Rs,Rd DEC.B Rd Operand Size SUBS #4,ERd SUBS SUBX SUB Rn 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (signed multiplication) — — Rd16×Rs16→ERd32 — — — — 5 4 — — Rd8×Rs8→Rd16 (signed multiplication) (unsigned multiplication) Rd16×Rs16→ERd32 4 1 — — — — — — — — * Rd8 decimal adjust→Rd8 1 — 1 — — ERd32-2→ERd32 3 — — ERd32-1→ERd32 1 — 1 1 Rd8×Rs8→Rd16 (unsigned multiplication) — — — — — — — — Rd16-2→Rd16 — 1 1 * — — — — — — — — — ERd32-4→ERd32 Rd16-1→Rd16 1 — — — — — — ERd32-2→ERd32 [5] — — — — — — — ERd32-1→ERd32 — — 1 — Rd8-Rs8-C→Rd8 Rd8-1→Rd8 1 1 — Rd8-#xx:8-C→Rd8 [5] — [4] ERd32-ERs32→ERd32 3 — [4] 1 — [3] ERd32-#xx:32→ERd32 Advanced No. of States*1 Rd16-Rs16→Rd16 I H N Z V C ↔ ↔ ↔ Operation ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @aa @(d,PC) @–ERn/@ERn+ @(d,ERn) @ERn #xx Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 769 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 770 of 1042 REJ09B0275-0500 EXTU NEG CMP DIVXS DIVXU L W L EXTU.L ERd W NEG.W Rd EXTU.W Rd B NEG.B Rd NEG.L ERd L 6 L CMP.L ERs,ERd W CMP.W Rs,Rd CMP.L #xx:32,ERd W 4 CMP.W #xx:16,Rd W DIVXS.W Rs,ERd B 2 B divxs.B Rs,Rd B W DIVXU.W Rs,ERd CMP.B Rs,Rd B #xx CMP.B #xx:8,Rd Operand Size DIVXU.B Rs,Rd Rn 2 2 2 2 2 2 2 2 4 4 2 2 21 1 ERd32÷Rs16→ERd32 (Ed: remainder, — — [8] [7] — — — — — [3] — [3] — [4] — [4] — — — — — 0 — — 0 Rd8-#xx:8 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8→Rd8 0-Rd16→Rd16 0-ERd32→ERd32 0→( of Rd16) 0→( of ERd32) Rd: quotient) (signed division) 0 — 0 — 13 Rd16÷Rs8→Rd16 (RdH: remainder, — — [8] [7] — — RdL: quotient) (signed division) 1 1 1 1 1 1 3 1 2 1 20 Rd: quotient) (unsigned division) RdL: quotient) (unsigned division) ERd32÷Rs16→ERd32 (Ed: remainder, — — [6] [7] — — Advanced 12 I H N Z V C No. of States*1 Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — — Operation ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @(d,PC) @aa @–ERn/@ERn+ @ERn @(d,ERn) Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set STMAC L L STMAC MACL,ERd LDMAC STMAC MACH,ERd — CLRMAC CLRMAC L — MAC @ERn+,@ERm+ MAC L B TAS @ERd *3 TAS LDMAC ERs,MACL L EXTS.L ERd LDMAC ERs,MACH W EXTS.W Rd EXTS Operand Size Mnemonic Rn 2 2 2 2 2 2 @ERn 4 @–ERn/@ERn+ 4 — 2 1 0 — 0 — 2 [11] — — MACL→ERd — 1 [11] 2 [11] 1 [11] — — —— — — — — — ERs→MACL MACH→ERd 2 [11] — —— — — — — —— — — — 0→MACH,MACL [10] [10] [10] 4 4 1 0 — — —— — — — — — — — — — Advanced I H N Z V C ERs→MACH ERn+2→ERn,ERm+2→ERm (signed multiplication) @ERn×@ERm+MAC→MAC ( of @ERd) @ERd-0→CCR set, (1)→ ( of ERd32) ( of ERd32)→ ( of Rd16) ( of Rd16)→ Operation No. of States*1 ↔ ↔ ↔ ↔ Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ @@aa @aa @(d,PC) @(d,ERn) #xx Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 771 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 772 of 1042 REJ09B0275-0500 NOT XOR OR AND AND.L ERs,ERd L NOT.L ERd XOR.L ERs,ERd W L 6 L XOR.L #xx:32,ERd NOT.W Rd W XOR.W Rs,Rd B W 4 XOR.W #xx:16,Rd NOT.B Rd B OR.L ERs,ERd XOR.B Rs,Rd L OR.L #xx:32,ERd B 2 L 6 OR.W Rs,Rd XOR.B #xx:8,Rd W 4 W OR.W #xx:16,Rd B L 6 L AND.L #xx:32,ERd OR.B Rs,Rd W AND.W Rs,Rd B 2 W 4 AND.W #xx:16,Rd OR.B #xx:8,Rd B 2 B Operand Size AND.B Rs,Rd #xx AND.B #xx:8,Rd Mnemonic Rn 2 2 2 4 2 2 4 2 2 4 2 2 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Rd8∧Rs8→Rd8 Rd16∧#xx:16→Rd16 Rd16∧Rs16→Rd16 ERd32∧#xx:32→ERd32 ERd32∧ERs32→ERd32 Rd8∨#xx:8→Rd8 Rd8∨Rs8→Rd8 Rd16∨#xx:16→Rd16 Rd16∨Rs16→Rd16 ERd32∨#xx:32→ERd32 ERd32∨ERs32→ERd32 Rd8⊕#xx:8→Rd8 Rd8⊕Rs8→Rd8 Rd16⊕#xx:16→Rd16 Rd16⊕Rs16→Rd16 ERd32⊕#xx:32→ERd32 ERd32⊕ERs32→ERd32 ¬ Rd8→Rd8 ¬ Rd16→Rd16 ¬ ERd32→ERd32 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 0 — 1 1 1 2 3 1 2 1 1 2 3 1 2 1 1 2 3 1 2 1 1 Advanced I H N Z V C Rd8∧#xx:8→Rd8 Operation No. of States*1 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @aa @(d,PC) @–ERn/@ERn+ @(d,ERn) @ERn Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set (3) Logical Instructions SHLL SHAR SHAL W W L L SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd W W L L SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHAR.L #2,ERd B L SHAR.L ERd SHLL.B #2,Rd L SHAR.W #2,Rd B W SHAR.W Rd SHLL.B Rd B W SHAR.B #2,Rd B B SHAR.B Rd B SHAL.B #2,Rd Rn 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C C MSB MSB MSB LSB LSB LSB C 0 0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 I H N Z V C ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Operand Size SHAL.B Rd Operation ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @aa @(d,PC) @–ERn/@ERn+ @(d,ERn) @ERn #xx Addressing Mode/ Instruction Length (Bytes) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Advanced No. of States*1 Appendix A Instruction Set (4) Shift Instructions Rev. 5.00 Jan 10, 2006 page 773 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 774 of 1042 REJ09B0275-0500 ROTXR ROTXL SHLR B W W L L ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd L ROTXL.L #2,ERd B L ROTXL.L ERd ROTXR.B #2,Rd W ROTXR.B Rd W ROTXL.W #2,Rd L SHLR.L #2,ERd ROTXL.W Rd L SHLR.L ERd B W SHLR.W #2,Rd ROTXL.B #2,Rd W SHLR.W Rd B B ROTXL.B Rd B SHLR.B #2,Rd Operand Size SHLR.B Rd #xx Rn 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C LSB C — — — — — — MSB — — — — — C — — — LSB — — — — — — — — — — — — — — — — — — LSB — — — MSB — — 0 — — — — 0 — — — 0 — — 0 —0 MSB — — 0 — — — 0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I H N Z V C — Operation ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @(d,PC) @aa @–ERn/@ERn+ @(d,ERn) @ERn Addressing Mode/ Instruction Length (Bytes) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Advanced No. of States*1 Appendix A Instruction Set ROTR ROTL W W L L ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd L ROTL.L #2,ERd ROTR.W Rd L ROTL.L ERd B W ROTL.W #2,Rd ROTR.B #2,Rd W ROTL.W Rd B B ROTR.B Rd B ROTL.B #2,Rd Rn 2 2 2 2 2 2 2 2 2 2 2 2 MSB C — — — — — — — — 1 — — — — — — — — — — — LSB LSB — MSB C — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 I H N Z V C ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Operand Size ROTL.B Rd Operation ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @aa @(d,PC) @–ERn/@ERn+ @(d,ERn) @ERn #xx Addressing Mode/ Instruction Length (Bytes) 1 1 1 1 1 1 1 1 1 1 1 1 Advanced No. of States*1 Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 775 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 776 of 1042 REJ09B0275-0500 BCLR BSET B B B B B B B B B B B B B B BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 B BSET #xx:3,@aa:16 B B BSET #xx:3,@aa:8 BSET Rn,Rd B BSET #xx:3,@aa:32 B BSET #xx:3,@ERd Operand Size BSET #xx:3,Rd Mnemonic Rn 2 2 2 2 @ERn 4 4 4 4 @aa 6 4 8 6 4 8 6 4 8 6 4 — @@aa @(d,PC) @–ERn/@ERn+ @(d,ERn) #xx Addressing Mode/ Instruction Length (Bytes) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — (#xx:3 of Rd8)←1 (#xx:3 of @aa:8)←1 (#xx:3 of @aa:16)←1 (#xx:3 of @aa:32)←1 (Rn8 of Rd8)←1 (Rn8 of @ERd)←1 (Rn8 of @aa:8)←1 (Rn8 of @aa:16)←1 (Rn8 of @aa:32)←1 (#xx:3 of Rd8)←0 (#xx:3 of @ERd)←0 (#xx:3 of @aa:8)←0 (#xx:3 of @aa:16)←0 (#xx:3 of @aa:32)←0 (Rn8 of Rd8)←0 (Rn8 of @ERd)←0 (Rn8 of @aa:8)←0 (Rn8 of @aa:16)←0 I H N Z V C (#xx:3 of @ERd)←1 Operation Condition Code 5 4 4 1 6 5 4 4 1 6 5 4 4 1 6 5 4 4 1 Advanced No. of States*1 Appendix A Instruction Set (5) Bit-Manipulation Instructions BTST B B B BTST #xx:3,@aa:16 B BTST #xx:3,Rd BTST #xx:3,@aa:8 B BNOT Rn,@aa:32 BTST #xx:3,@ERd B B BNOT Rn,Rd BNOT Rn,@aa:16 B BNOT #xx:3,@aa:32 B B BNOT #xx:3,@aa:16 B B BNOT #xx:3,@aa:8 BNOT Rn,@aa:8 B BNOT #xx:3,@ERd BNOT Rn,@ERd B BNOT #xx:3,Rd B BCLR Rn,@aa:32 BNOT Operand Size BCLR Mnemonic #xx Rn 2 2 2 @ERn 4 4 4 @aa 6 4 8 6 4 8 6 4 8 6 — — — — — — — — — — — — — — — — — — ¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z ¬ (#xx:3 of @aa:8)→Z ¬ (#xx:3 of @aa:16)→Z [¬ (Rn8 of @aa:32)] (Rn8 of @aa:32)← [¬ (Rn8 of @aa:16)] — — — — — — 4 3 3 1 5 — — — — — — — — 4 (Rn8 of @aa:8)←[¬ (Rn8 of @aa:8)] — — — — — — (Rn8 of @aa:16)← 4 (Rn8 of @ERd)←[¬ (Rn8 of @ERd)] — — — — — — 6 5 1 — — — — — — — — — — — — — — — — — — — — — — — — (Rn8 of Rd8)←[¬ (Rn8 of Rd8)] [¬ (#xx:3 of @aa:32)] (#xx:3 of @aa:32)← [¬ (#xx:3 of @aa:16)] (#xx:3 of @aa:16)← [¬ (#xx:3 of @aa:8)] (#xx:3 of @aa:8)← 4 4 [¬ (#xx:3 of @ERd)] 1 (#xx:3 of @ERd)← — — — — — — 6 Advanced — — — — — — I H N Z V C No. of States*1 (#xx:3 of Rd8)←[¬ (#xx:3 of Rd8)] — — — — — — (Rn8 of @aa:32)←0 Operation Condition Code ↔ ↔ ↔ ↔ — @@aa @(d,PC) @–ERn/@ERn+ @(d,ERn) Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 777 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 778 of 1042 REJ09B0275-0500 BST BILD BLD BTST B BST #xx:3,@aa:8 B BILD #xx:3,@aa:16 B B BILD #xx:3,@aa:8 BST #xx:3,@ERd B BILD #xx:3,@ERd B B BILD #xx:3,Rd B B BLD #xx:3,@aa:32 BST #xx:3,Rd B BLD #xx:3,@aa:16 BILD #xx:3,@aa:32 B BLD #xx:3,@aa:8 B BTST Rn,@aa:32 B B BTST Rn,@aa:16 BLD #xx:3,@ERd B BTST Rn,@aa:8 B B BTST Rn,@ERd BLD #xx:3,Rd B B BTST Rn,Rd Operand Size BTST #xx:3,@aa:32 Rn 2 2 2 2 @ERn 4 4 4 4 @aa 4 8 6 4 8 6 4 8 6 4 8 — — — — — — — — — — — — C→(#xx:3 of @ERd24) — — — — — ¬ (#xx:3 of @aa:16)→C C→(#xx:3 of @aa:8) — — — — — ¬ (#xx:3 of @aa:8)→C — — — — — — — — — — ¬ (#xx:3 of @ERd)→C — — — — — — — — — — — ¬ (#xx:3 of @aa:32)→C — — — — — (#xx:3 of @aa:32)→C ¬ (#xx:3 of Rd8)→C C→(#xx:3 of Rd8) — — — — — — — — — — (#xx:3 of @aa:8)→C (#xx:3 of @aa:16)→C — — — — — (#xx:3 of @ERd)→C 4 4 1 5 4 3 3 1 5 4 3 3 1 5 — — — — — (#xx:3 of Rd8)→C 4 — — — — — — — — — — ¬ (Rn8 of @aa:16)→Z 3 ¬ (Rn8 of @aa:32)→Z 3 — — — — — ¬ (Rn8 of @aa:8)→Z 1 — — — — — ¬ (Rn8 of @ERd)→Z 5 — — — — — — — — ¬ (Rn8 of Rd8)→Z Advanced No. of States*1 — — I H N Z V C ¬ (#xx:3 of @aa:32)→Z Operation ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @(d,PC) @–ERn/@ERn+ @(d,ERn) #xx Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set BOR BIAND BAND BIST BST B B B B BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd B BAND #xx:3,@aa:16 B B BAND #xx:3,@aa:8 BIAND #xx:3,@aa:8 B BAND #xx:3,@ERd B B BAND #xx:3,Rd BIAND #xx:3,@ERd B BIST #xx:3,@aa:32 B B BIST #xx:3,@aa:16 B B BIST #xx:3,@aa:8 BIAND #xx:3,Rd B BIST #xx:3,@ERd BAND #xx:3,@aa:32 B B BIST #xx:3,Rd B BST #xx:3,@aa:32 Operand Size BST #xx:3,@aa:16 Mnemonic Rn 2 2 2 2 @ERn 4 4 4 4 @aa @(d,PC) 8 6 4 8 6 4 8 6 4 8 6 — — — — — — — — — — C∨(#xx:3 of Rd8)→C C∨(#xx:3 of @ERd24)→C — — — — — C∧[¬ (#xx:3 of @aa:8)]→C — — — — — — — — — — C∧[¬ (#xx:3 of @ERd24)]→C — — — — — — — — — — C∧[¬ (#xx:3 of Rd8)]→C C∧[¬ (#xx:3 of @aa:16)]→C — — — — — C∧(#xx:3 of @aa:32)→C C∧[¬ (#xx:3 of @aa:32)]→C — — — — — 1 C∧(#xx:3 of @aa:16)→C 6 — — — — — — ¬ C→(#xx:3 of @aa:32) 3 1 5 4 3 3 1 5 4 3 3 5 — — — — — — ¬ C→(#xx:3 of @aa:16) — — — — — 4 — — — — — — ¬ C→(#xx:3 of @aa:8) C∧(#xx:3 of @aa:8)→C 4 — — — — — — ¬ C→(#xx:3 of @ERd24) — — — — — 1 — — — — — — ¬ C→(#xx:3 of Rd8) — — — — — 6 — — — — — — C→(#xx:3 of @aa:32) C∧(#xx:3 of @ERd24)→C 5 — — — — — — C→(#xx:3 of @aa:16) C∧(#xx:3 of Rd8)→C Advanced I H N Z V C No. of States*1 Operation Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @–ERn/@ERn+ @(d,ERn) #xx Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 779 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 780 of 1042 REJ09B0275-0500 BIXOR BXOR BIOR BOR B B B B B B B B BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B BIOR #xx:3,@aa:32 B B BIOR #xx:3,@aa:16 B B BIOR #xx:3,@aa:8 BXOR #xx:3,@ERd B BIOR #xx:3,@ERd BXOR #xx:3,Rd B B BOR #xx:3,@aa:32 BIOR #xx:3,Rd B B BOR #xx:3,@aa:16 Operand Size #xx BOR #xx:3,@aa:8 Mnemonic Rn 2 2 2 @ERn 4 4 4 4 @aa 8 6 4 8 6 4 8 6 4 8 6 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — C⊕(#xx:3 of @aa:32)→C C⊕[¬ (#xx:3 of Rd8)]→C C⊕[¬ (#xx:3 of @ERd24)]→C C⊕[¬ (#xx:3 of @aa:8)]→C C⊕[¬ (#xx:3 of @aa:16)]→C C⊕[¬ (#xx:3 of @aa:32)]→C — — — — — C∨[¬ (#xx:3 of @aa:32)]→C — — — — — — — — — — C∨[¬ (#xx:3 of @aa:16)]→C C⊕(#xx:3 of @aa:16)→C — — — — — C∨[¬ (#xx:3 of @aa:8)]→C C⊕(#xx:3 of @aa:8)→C — — — — — C∨[¬ (#xx:3 of @ERd24)]→C — — — — — — — — — — C∨[¬ (#xx:3 of Rd8)]→C — — — — — — — — — — C∨(#xx:3 of @aa:32)→C C⊕(#xx:3 of @ERd24)→C — — — — — C⊕(#xx:3 of Rd8)→C — — — — — C∨(#xx:3 of @aa:16)→C I H N Z V C C∨(#xx:3 of @aa:8)→C Operation Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @(d,PC) @–ERn/@ERn+ @(d,ERn) Addressing Mode/ Instruction Length (Bytes) 5 4 3 3 1 5 4 3 3 1 5 4 3 3 1 5 4 3 Advanced No. of States*1 Appendix A Instruction Set Bcc — — — — — — — — — — — — — — — — — — BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 Operand Size BRA d:8(BT d:8) Mnemonic @aa @(d,PC) 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 — @@aa @–ERn/@ERn+ @(d,ERn) @ERn Rn #xx Addressing Mode/ Instruction Length (Bytes) Branching Condition else next; PC←PC+d V=0 Z=1 Z=0 C=1 C=0 C∨Z=1 C∨Z=0 Never if condition is true then Always Operation 3 — — — — — — 3 2 — — — — — — — — — — — — 3 2 — — — — — — — — — — — — 3 2 — — — — — — — — — — — — 3 2 — — — — — — — — — — — — 3 2 — — — — — — — — — — — — 3 2 — — — — — — — — — — — — 3 2 — — — — — — — — — — — — 2 — — — — — — 2 3 — — — — — — Advanced No. of States*1 — — — — — — I H N Z V C Condition Code Appendix A Instruction Set (6) Branch Instructions Rev. 5.00 Jan 10, 2006 page 781 of 1042 REJ09B0275-0500 Bcc Operand Size — — — — — — — — — — — — — — Mnemonic BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 @(d,PC) Rev. 5.00 Jan 10, 2006 page 782 of 1042 REJ09B0275-0500 4 2 4 2 4 2 4 2 4 2 4 2 4 2 — @@aa @aa @–ERn/@ERn+ @(d,ERn) @ERn #xx Rn Addressing Mode/ Instruction Length (Bytes) Operation 3 2 3 2 3 Z∨(N⊕V)=0 — — — — — — — — — — — — Z∨(N⊕V)=1 — — — — — — — — — — — — 2 3 — — — — — — 2 — — — — — — 3 — — — — — — — — — — — — 2 — — — — — — 3 — — — — — — N⊕V=1 N⊕V=0 N=1 2 — — — — — — 3 — — — — — — — — — — — — — — — — — — V=1 N=0 2 I H N Z V C Advanced No. of States*1 Branching Condition Condition Code Appendix A Instruction Set RTS JSR BSR JMP — — — — — — — — — JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS Operand Size JMP @ERn Mnemonic @ERn 2 2 4 4 2 @aa @(d,PC) 4 @@aa 2 2 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — PC←@aa:8 PC→@-SP,PC←PC+d:8 PC→@-SP,PC←PC+d:16 PC→@-SP,PC←ERn PC→@-SP,PC←aa:24 PC→@-SP,PC←@aa:8 — — — — — — — — — — — — PC←aa:24 I H N Z V C Condition Code PC←ERn Operation 2 PC←@SP+ — @–ERn/@ERn+ @(d,ERn) Rn #xx Addressing Mode/ Instruction Length (Bytes) 5 6 5 4 5 4 5 3 2 Advanced No. of States*1 Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 783 of 1042 REJ09B0275-0500 W W LDC @aa:32,CCR LDC @aa:32,EXR W LDC @ERs+,CCR W W LDC @(d:32,ERs),EXR LDC @aa:16,EXR W LDC @(d:32,ERs),CCR W W LDC @(d:16,ERs),EXR W W LDC @(d:16,ERs),CCR LDC @aa:16,CCR W LDC @ERs+,EXR W LDC @ERs,EXR B 4 LDC #xx:8,EXR LDC @ERs,CCR B 2 LDC #xx:8,CCR LDC B — SLEEP SLEEP B — RTE RTE LDC Rs,EXR — Mnemonic LDC Rs,CCR Operand Size #xx TRAPA #xx:2 2 Rn 2 @ERn 4 4 @(d,ERn) 10 10 6 6 4 8 8 6 6 @–ERn/@ERn+ @aa 4 Operation I H N Z V C 1 — — — — — 4 5 — — — — — — @ERs→CCR,ERs32+2→ERs32 @ERs→EXR,ERs32+2→ERs32 @aa:16→CCR @aa:16→EXR @aa:32→CCR 5 4 4 — — — — — — @(d:32,ERs)→EXR — — — — — — 6 4 — — — — — — @(d:32,ERs)→CCR @aa:32→EXR 4 6 — — — — — — @(d:16,ERs)→EXR 3 4 @(d:16,ERs)→CCR 3 @ERs→EXR — — — — — — @ERs→CCR 1 — — — — — — Rs8→EXR 2 1 — — — — — — Rs8→CCR #xx:8→EXR 2 1 — — — — — — 5 [13] 8 [13] Advanced No. of States*1 #xx:8→CCR Transition to power-down state PC←@SP+ EXR←@SP+,CCR←@SP+, EXR→@-SP,→PC PC→@-SP,CCR→@-SP, ↔ ↔ ↔ ↔ TRAPA Condition Code ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Rev. 5.00 Jan 10, 2006 page 784 of 1042 REJ09B0275-0500 ↔ ↔ ↔ ↔ ↔ ↔ — @@aa @(d,PC) Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set (7) System Control Instructions NOP XORC ORC ANDC B 4 — XORC #xx:8,EXR NOP B 2 B 4 ORC #xx:8,EXR XORC #xx:8,CCR B 2 ORC #xx:8,CCR B 4 W STC EXR,@aa:32 ANDC #xx:8,EXR W STC CCR,@aa:32 B 2 W STC EXR,@aa:16 2 2 #xx Rn ANDC #xx:8,CCR W W STC CCR,@(d:32,ERd) STC CCR,@aa:16 W STC EXR,@(d:16,ERd) W W STC CCR,@(d:16,ERd) STC EXR,@-ERd W STC EXR,@ERd W W STC CCR,@ERd W B STC CCR,@-ERd B STC EXR,Rd STC EXR,@(d:32,ERd) Operand Size STC CCR,Rd @ERn 4 4 @(d,ERn) 10 10 6 6 @–ERn/@ERn+ 4 4 @aa 8 8 6 6 6 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CCR→@ERd EXR→@ERd CCR→@(d:16,ERd) EXR→@(d:16,ERd) CCR→@(d:32,ERd) EXR→@(d:32,ERd) 1 — — — — — — — — — — — — — EXR⊕#xx:8→EXR 2 PC←PC+2 1 2 2 CCR⊕#xx:8→CCR 1 — — — — — — EXR∨#xx:8→EXR 2 5 — — — — — — EXR→@aa:32 — — — — — — 5 — — — — — — CCR→@aa:32 CCR∨#xx:8→CCR 4 — — — — — — EXR→@aa:16 EXR∧#xx:8→EXR 4 — — — — — — CCR→@aa:16 1 4 — — — — — — ERd32-2→ERd32,EXR→@ERd CCR∧#xx:8→CCR 4 ERd32-2→ERd32,CCR→@ERd — — — — — — 6 4 4 3 3 1 — — — — — — 1 — — — — — — EXR→Rd8 Advanced CCR→Rd8 I H N Z V C ↔ ↔ ↔ STC Operation No. of States*1 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Mnemonic Condition Code ↔ ↔ ↔ @@aa @(d,PC) Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 785 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 786 of 1042 REJ09B0275-0500 Notes: 1. 2. 3. [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] EEPMOV — — EEPMOV.B EEPMOV.W @@aa @aa @(d,PC) @–ERn/@ERn+ @(d,ERn) @ERn Rn #xx — — — — — — — — — — — — 4 if R4≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; I H N Z V C 4 if R4L≠0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; Operation Condition Code 4+2n*2 4+2n*2 Advanced No. of States*1 The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. n is the initial value of R4L or R4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. Cannot be used in the H8S/2626 Group or H8S/2623 Group. Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the divisor is negative; otherwise cleared to 0. Set to 1 when the divisor is zero; otherwise cleared to 0. Set to 1 when the quotient is negative; otherwise cleared to 0. One additional state is required for execution when EXR is valid. MAC instruction results are indicated in the flags when the STMAC instruction is executed. A maximum of three additional states are required for execution of one of these instructions within three states after execution of a MAC instruction. For example, if there is a one-state instruction (such as NOP) between a MAC instruction and one of these instructions, that instruction will be two states longer. Operand Size Mnemonic — Addressing Mode/ Instruction Length (Bytes) Appendix A Instruction Set (8) Block Transfer Instructions Appendix A Instruction Set A.2 Instruction Codes Table A.2 shows the instruction codes. Rev. 5.00 Jan 10, 2006 page 787 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 788 of 1042 REJ09B0275-0500 Bcc BAND ANDC AND ADDX 1 rs 1 0 8 9 9 9 A A B B B rd E rd 7 0 7 0 0 0 0 9 0 E W L L L L L B B B ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd 0 erd rd rd rd rs 6 F 4 0 IMM 0 erd 1 3 6 A 1 6 1 6 C E A A 0 8 1 8 6 7 0 0 0 7 7 7 6 6 4 5 4 5 W L L B B B B B B B — — — — AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) 1 0 6 9 7 rd rd rd rd disp disp abs 0 0 0 0 0 rd 1 0 0 erd IMM rs 6 1 B W AND.W #xx:16,Rd IMM AND.B Rs,Rd rs IMM 0 erd 0 erd 0 erd 1 ers 0 erd rs 8 0 B W ADD.W #xx:16,Rd IMM 2nd byte ADD.B Rs,Rd rd 8 1st byte B Size ADD.B #xx:8,Rd Mnemonic IMM IMM 0 IMM 6 disp disp abs 0 IMM 6 IMM 0 0 abs 0 ers 0 erd 7 6 6 IMM IMM 4th byte 7 0 6 3rd byte 7 6 0 IMM 0 6th byte Instruction Format 5th byte 7 6 7th byte 0 IMM 0 8th byte 9th byte 10th byte Table A.2 ADDS ADD Instruction Appendix A Instruction Set Instruction Codes Bcc Instruction — — — — — — — — — — — — — — — — — — — — — — — — — — — — BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 Size BHI d:8 Mnemonic 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 8 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 1st byte F E D C B A 9 8 7 6 5 4 3 2 disp disp disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2nd byte 3rd byte disp disp disp disp disp disp disp disp disp disp disp disp disp disp 4th byte 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 789 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 790 of 1042 REJ09B0275-0500 BIOR BILD BIAND BCLR Instruction 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 B B B B B B B B B B B B B B B B B B B B B B BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 0 erd D 0 erd C rd 0 1 IMM 0 erd 7 C 0 erd C 0 0 1 3 A 0 A abs 1 IMM 4 E 0 3 A rd 0 1 A abs 0 3 A E 0 1 0 A abs 1 IMM 6 E 8 3 A rd 8 1 A 0 rd rn 2 abs 8 3 A F 8 0 1 abs A F 0 erd 7 B BCLR #xx:3,@aa:8 D 7 B BCLR #xx:3,@ERd rd 0 IMM 2 7 2nd byte 1st byte B Size BCLR #xx:3,Rd Mnemonic 0 IMM 2 1 IMM 6 1 IMM 7 7 1 IMM 4 7 abs 1 IMM 4 7 abs 1 IMM 7 7 abs 1 IMM 6 7 0 0 0 0 0 0 0 rn 2 7 0 rn 2 6 0 0 6 abs abs 0 IMM 2 7 4th byte 7 3rd byte abs abs abs abs abs 7 7 7 6 7 4 7 6 2 2 1 IMM 1 IMM 1 IMM rn 0 IMM 0 0 0 0 0 6th byte Instruction Format 5th byte 7 7 7 6 7 4 7 6 2 2 7th byte 1 IMM 1 IMM 1 IMM rn 0 IMM 0 0 0 0 0 8th byte 9th byte 10th byte Appendix A Instruction Set BNOT BLD BIXOR BIST Instruction 8 8 0 0 0 0 8 8 rd 8 8 1 3 1 IMM 0 erd 1 3 0 IMM 0 erd 1 3 0 IMM 0 erd 1 3 rn 0 erd 1 3 A A 5 C E A A 7 C E A A 1 D F A A 1 D F A A 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 B B B B B B B B B B B B B B B B B B B B B B BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 abs abs abs abs 0 0 rd 0 rd 0 rd 0 F 7 B BIST #xx:3,@aa:8 abs 0 erd D 7 B BIST #xx:3,@ERd rd 1 IMM 7 6 2nd byte 1st byte B Size BIST #xx:3,Rd Mnemonic 1 IMM 7 1 IMM 5 7 0 IMM 7 7 0 IMM 1 7 rn rn 1 1 6 6 abs abs 0 IMM 1 7 abs 0 IMM 7 7 abs 1 IMM 5 7 abs 1 IMM 7 6 0 0 0 0 0 0 0 0 0 0 4th byte 6 3rd byte abs abs abs abs abs 6 7 7 7 6 1 1 7 5 7 rn 0 IMM 0 IMM 1 IMM 1 IMM 0 0 0 0 0 6th byte Instruction Format 5th byte 6 7 7 7 6 1 1 7 5 7 7th byte rn 0 IMM 0 IMM 1 IMM 1 IMM 0 0 0 0 0 8th byte 9th byte 10th byte Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 791 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 792 of 1042 REJ09B0275-0500 BTST BST BSR BSET BOR Instruction 0 0 8 8 rd 8 8 8 8 0 0 rd 1 3 0 IMM 0 erd 1 3 rn 0 erd 1 3 0 0 IMM 0 erd 1 3 0 IMM 0 erd 1 3 rn 0 erd A A 0 D F A A 0 D F A A 5 C 7 D F A A 3 C E A A 3 C 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 B B B B B B B B B B B B — — B B B B B B B B B B B B BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd abs abs disp abs abs 0 0 rd 0 rd 0 0 0 rd 0 E 7 B BOR #xx:3,@aa:8 abs 0 erd C 7 B BOR #xx:3,@ERd rd 0 IMM 4 7 2nd byte 1st byte B Size BOR #xx:3,Rd Mnemonic 0 IMM 4 0 IMM 0 7 0 IMM 7 6 6 3 rn 0 IMM 3 7 abs 0 IMM 3 7 abs 0 IMM 7 6 0 0 0 0 0 0 rn 0 disp 0 rn 0 6 0 0 0 0 6 abs abs 0 IMM 0 7 abs 0 IMM 4 7 4th byte 7 3rd byte abs abs abs abs abs 7 6 6 7 7 3 7 0 0 4 0 IMM 0 IMM rn 0 IMM 0 IMM 0 0 0 0 0 6th byte Instruction Format 5th byte 7 6 6 7 7 3 7 0 0 4 7th byte 0 IMM 0 IMM rn 0 IMM 0 IMM 0 0 0 0 0 8th byte 9th byte 10th byte Appendix A Instruction Set 6 6 7 7 7 6 6 0 A 1 7 1 7 1 0 1 B B B B B B B — B B W W L L B B BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd CMP 0 5 5 7 7 W B W — — DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W DEC.L #2,ERd DIVXU DIVXS DIVXS.W Rs,ERd DEC.L #1,ERd 0 DEC.W #2,Rd 1 1 L DEC.W #1,Rd L 1 W DEC.B Rd DEC B 1 W DAS Rd DAS DIVXS.B Rs,Rd 1 B DAA Rd DAA BXOR BTST B B 3 1 1 1 B B B B A F F F A D 9 C rd 1 A A E C 5 A A E 1st byte 7 Size B Mnemonic BTST Rn,@aa:8 Instruction 0 rd 0 3 0 IMM 0 erd 0 0 3 A rd rd 0 erd 2 rs 2 8 8 9 9 5 5 rd 0 erd C 4 5 D F F 0 rs rs 3 5 0 D rs rd 0 erd rs 1 5 0 erd F D IMM abs rd rd 5 IMM 0 0 0 erd rd 0 0 IMM 5 7 abs 0 IMM 5 7 abs 7 rd 0 abs 0 rn 3 6 4th byte 3rd byte D rd 0 1 ers 0 erd rd rs IMM 0 1 abs 0 1 abs 2nd byte 7 6 5 3 0 IMM rn 0 0 6th byte Instruction Format 5th byte 7 6 5 3 7th byte 0 IMM rn 0 0 8th byte 9th byte 10th byte Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 793 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 794 of 1042 REJ09B0275-0500 LDC JSR JMP INC EXTU EXTS Instruction rd rd 0 erd 0 erd 0 0 5 D 7 F 0 ern A B B B B 9 0 0 0 0 0 0 0 0 W W W W W W W W LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR 0 B LDC Rs,CCR 0 0 B LDC #xx:8,EXR W 0 B LDC #xx:8,CCR LDC @ERs,EXR 5 — JSR @@aa:8 0 5 — JSR @aa:24 0 5 — JSR @ERn B 5 — JMP @@aa:8 W 5 — JMP @aa:24 LDC @ERs,CCR 5 LDC Rs,EXR 0 L 0 L INC.L #1,ERd — 0 W INC.W #2,Rd JMP @ERn 0 INC.W #1,Rd INC.L #2,ERd 0 B W INC.B Rd 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 9 9 F F 8 8 D D B B 6 6 6 6 7 7 6 6 6 6 rs 0 1 0 1 0 1 0 1 0 1 1 4 4 4 4 4 4 4 4 4 4 1 1 1 1 1 1 1 1 1 IMM 1 7 3 0 1 rs 0 3 IMM B disp disp 0 B 0 0 0 6 0 disp 6 0 disp 0 2 2 0 0 6th byte Instruction Format 5th byte 0 0 0 4th byte 4 7 abs abs 3rd byte 1 abs 0 ern F E D B 0 rd 7 7 1 L EXTU.L ERd abs rd 0 erd 5 7 1 A 0 erd F 7 1 L W EXTU.W Rd EXTS.L ERd rd D 7 1 2nd byte 1st byte W Size EXTS.W Rd Mnemonic 7th byte 8th byte disp disp 9th byte 10th byte Appendix A Instruction Set F 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 B B B B B B B B B B B B B B B W W W W W MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd 0 B 0 L — LDMAC ERs,MACL MOV.B #xx:8,Rd 0 L LDMAC ERs,MACH MOV 0 L LDM.L @SP+, (ERn-ERn+3) MAC @ERn+,@ERm+ 0 L LDM.L @SP+, (ERn-ERn+2) 0 6 1 0 ers 0 ers E 8 C 1 erd 0 erd 1 erd E 8 C 0 ers 0 ers F 8 0 rd rd rd rs 0 ers rd 0 9 9 rs A A D rs 8 rs 0 rs A abs 1 erd 8 rs rd 2 A rs rd 0 rd 0 rd rd A abs 0 ers 8 rd rs 0 ers C rd 0 ers 3 3 6 6 6 B A A D 0 ers 2 3 6 6 0 3 1 IMM D 6 0 2 1 rd D 6 0 0 0 ern+3 0 ern+2 0 ern+1 disp IMM abs disp abs disp 2 A 2 rd rs rd abs abs 0 ern 0 erm 7 7 7 2 B D 6 1 1 1 0 L 4 1 0 W LDM.L @SP+, (ERn-ERn+1) LDC @aa:32,EXR 0 2 B 6 0 4 1 0 4th byte 3rd byte 2nd byte 1st byte W Size LDC @aa:32,CCR Mnemonic MAC LDMAC LDM LDC Instruction 6th byte Instruction Format 5th byte disp disp disp abs abs 7th byte 8th byte 9th byte 10th byte Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 795 of 1042 REJ09B0275-0500 0 ers 0 erd 0 ers 0 erd 0 ers 0 erd 0 erd 0 erd 0 ers 0 2 9 F 8 D B B 6 6 7 6 6 6 rs rs 0 erd 0 0 0 0 0 0 0 erd 1 erd 8 A 0 0 0 0 0 0 0 8 D B B A F 1 1 1 1 1 1 7 6 6 6 7 0 0 0 0 Rev. 5.00 Jan 10, 2006 page 796 of 1042 REJ09B0275-0500 0 0 0 1 erd 0 ers 1 erd 0 ers 0 ers 0 ers rd 0 erd 0 erd 8 A rs rs F 8 D B B 0 2 6 7 6 6 6 5 5 0 0 0 0 0 0 0 rd 0 erd 0 0 0 0 0 C C rs rs 1 1 1 1 1 1 1 0 2 0 0 0 0 0 0 0 5 5 W L L L L L L L L L L L B B B W B W MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd L MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 L L MOV.W Rs,@aa:32 MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS MULXU 1 erd 0 ers 9 6 0 0 1 0 W MOV.W Rs,@aa:16 0 IMM 6 6 B B abs disp abs disp A 2 disp abs 0 ers abs 0 erd 6th byte Instruction Format 5th byte Cannot be used in the H8S/2626 Group or H8S/2623 Group. 1 ers 0 erd 0 0 W MOV.W Rs,@-ERd rs abs W MOV.W Rs,@(d:32,ERd) rs 1 erd F 6 W MOV.W Rs,@(d:16,ERd) rs W MOV.W Rs,@ERd A rs 1 erd 9 6 W B rd 2 B 6 W MOV.W @aa:32,Rd 6 rd 0 B 6 abs rd 0 ers D 4th byte 6 3rd byte 2nd byte 1st byte MOV.W @aa:16,Rd Size W Mnemonic MOV.W @ERs+,Rd MOV Instruction 7th byte 8th byte disp disp 9th byte 10th byte Appendix A Instruction Set 6 7 0 0 0 6 W L L B B W OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn ROTL PUSH POP ORC 1 1 1 1 1 B W W L L ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 1 ROTL.B Rd ROTL.B #2, Rd 0 L B PUSH.L ERn 6 7 W OR.W #xx:16,Rd 0 1 B OR.B Rs,Rd L C B OR.B #xx:8,Rd W 1 L NOT.L ERd PUSH.W Rn 1 W NOT.W Rd POP.L ERn 1 B NOT.B Rd OR 0 — NOP 1 L NEG.L ERd NOT 1 W NEG.W Rd rd 0 erd 0 1 3 0 7 7 7 rd 0 erd 0 rs 4 F 4 A 1 0 rn 0 rd rd rd rd 0 erd 0 erd 0 F 0 8 C 9 D B F 1 1 2 2 2 2 2 2 7 D D 1 rn 4 1 IMM rd 4 9 4 rd rs 4 IMM 0 rd 0 7 rd rd 0 erd 9 B 7 rd 8 7 1 2nd byte 1st byte B Size NEG.B Rd Mnemonic NOP NEG Instruction 6 6 0 6 D D 4 4 3rd byte IMM F 7 0 ern 0 ern IMM 0 ers 0 erd IMM 4th byte 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 797 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 798 of 1042 REJ09B0275-0500 B W W L L SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd B SHAL.B Rd SHAL SHAL.W Rd — RTS RTS SHAL.B #2, Rd L L ROTXR.L ERd — W ROTXR.W #2, Rd RTE W ROTXR.W Rd ROTXR.L #2, ERd B ROTXR.B #2, Rd L ROTXL.L ERd L W ROTXL.W #2, Rd B W ROTXL.W Rd ROTXR.B Rd B ROTXL.B #2, Rd ROTXL.L #2, ERd L ROTR.L ERd B L ROTR.W #2, Rd ROTXL.B Rd W ROTR.W Rd ROTR.L #2, ERd B W ROTR.B #2, Rd B Size ROTR.B Rd Mnemonic RTE ROTXR ROTXL ROTR Instruction 2nd byte rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 C 9 D B F 1st byte 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3rd byte 4th byte 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte Appendix A Instruction Set 0 0 0 0 0 0 0 0 0 0 B W W STC.W EXR,@ERd STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W STC.W CCR,@ERd STC.W CCR,@(d:16,ERd) W W STC.B EXR,Rd STC.W CCR,@-ERd STC.W EXR,@-ERd 0 1 L — SHLR.L #2, ERd B 1 L SHLR.L ERd STC.B CCR,Rd 1 W SHLR.W #2, Rd STC 1 W SHLR.W Rd SLEEP 1 B SHLR.B #2, Rd SHLL.L #2, ERd 1 1 L SHLL.L ERd 1 1 W SHLL.W #2, Rd L 1 W SHLL.W Rd B 1 B SHLL.B #2, Rd SHLR.B Rd 1 SHAR.L #2, ERd 1 1 L SHAR.L ERd L 1 W SHAR.W #2, Rd B 1 SHAR.W Rd SHLL.B Rd 1 B W SHAR.B #2, Rd 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1st byte B Size SHAR.B Rd Mnemonic SLEEP SHLR SHLL SHAR Instruction 6 6 6 6 7 7 6 6 0 rd rd 0 1 0 1 0 1 0 1 0 1 4 4 4 4 4 4 4 4 0 erd 7 D D 8 8 F F 9 9 3rd byte 8 rd rd 1 0 erd rd 4 3 rd 0 5 0 erd 7 rd 1 rd rd 4 0 erd rd 0 3 0 erd F 5 rd 0 erd rd 9 B rd C D rd 8 2nd byte 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 1 erd 1 erd 6 0 0 0 6 B B disp disp A A 0 0 6th byte Instruction Format 5th byte 0 0 0 0 0 4th byte 7th byte 8th byte disp disp 9th byte 10th byte Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 799 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 800 of 1042 REJ09B0275-0500 rd rd rd 0 erd 0 erd 0 erd 0 erd rd 0 rd rd rd 0 erd 0 rs 3 rs 3 0 8 9 rs E 00 IMM rs 5 rs 5 F 9 9 A A B B B rd E 1 7 rd 5 9 5 A 1 7 1 7 1 1 1 1 B 1 0 5 D 1 7 6 7 0 W W L L L L L B B B — B B W W L L SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd*2 TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd SUBX TAS TRAPA XOR SUBS IMM IMM 0 1 ers 0 erd 0 ers 3 SUB 8 6 7 5 B 0 ers 2 2 0 L STMAC MACH,ERd 2 D 6 0 3 1 0 L STM.L (ERn-ERn+3), @-SP 1 D 6 0 2 1 0 L STM.L (ERn-ERn+2), @-SP 0 D 6 0 1 1 0 L STM.L(ERn-ERn+1), @-SP L B 6 1 4 1 0 W STC.W EXR,@aa:32 B B 6 0 4 1 0 W STC.W CCR,@aa:32 SUB.B Rs,Rd B 6 1 4 1 0 W STC.W EXR,@aa:16 IMM 8 C IMM IMM 0 ern 0 ern 0 ern 0 0 0 0 ers 0 erd IMM 0 erd F F F A A 0 8 B 6 0 4 1 4th byte 3rd byte 0 2nd byte 1st byte W Size STC.W CCR,@aa:16 Mnemonic STMAC MACL,ERd STMAC STM STC Instruction abs abs 6th byte Instruction Format 5th byte abs abs 7th byte 8th byte 9th byte 10th byte Appendix A Instruction Set B B XORC #xx:8,EXR Size XORC #xx:8,CCR Mnemonic 0 0 1 5 1st byte 4 IMM 1 2nd byte 0 5 3rd byte IMM 4th byte 7th byte 8th byte 9th byte 10th byte General Register ER0 ER1 • • • ER7 Register Field 000 001 • • • 111 Address Register 32-Bit Register 0000 0001 • • • 0111 1000 1001 • • • 1111 R0 R1 • • • R7 E0 E1 • • • E7 General Register 16-Bit Register Register Field 0000 0001 • • • 0111 1000 1001 • • • 1111 Register Field R0H R1H • • • R7H R0L R1L • • • R7L General Register 8-Bit Register Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) The register fields specify general registers as follows. Legend: IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: 6th byte Instruction Format 5th byte Notes: 1. Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. XORC Instruction Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 801 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 802 of 1042 REJ09B0275-0500 1 2 BH 3 BL XOR BSR BCS AND RTE BNE BST TRAPA BEQ SUB ADD MOV OR XOR AND MOV C D E F CMP SUBX B BVS 9 Table A.3(2) MOV Table A.3(2) A Note: * Cannot be used in the H8S/2626 Group or H8S/2623 Group. 8 BVC MOV.B Table A.3(2) LDC 7 BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND OR RTS BCC AND ANDC 6 ADDX BTST DIVXU BLS XOR XORC 5 9 BCLR MULXU BHI OR ORC 4 Table A.3(2) Table A.3(2) JMP BPL Table A.3(2) Table A.3(2) A EEPMOV BMI Table A.3(2) Table A.3(2) B Instruction when most significant bit of BH is 1. Instruction when most significant bit of BH is 0. ADD BNOT DIVXU BRN LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) AL 2nd byte 8 7 BSET MULXU 5 6 BRA 4 3 2 NOP Table A.3(2) 1 0 0 AL AH 1st byte BSR BGE C CMP BLT JSR BGT SUBX ADDX E Table A.3(3) MOV MOV D F BLE Table A.3(2) Table A.3(2) A.3 AH Instruction code Appendix A Instruction Set Operation Code Map Table A.3 shows the operation code map. Table A.3 Operation Code Map (1) ROTXR 13 DAS BRA MOV MOV MOV 1B 1F 58 6A 79 7A ADD CMP CMP MOV ADD BHI BRN 2 BH Table A.3(4) AL BCC ROTXR ROTXL SHLR SHLL STC 4 LDC SUB SUB OR OR Table A.3(4) MOVFPE BLS NOT STM 3 BL 2nd byte XOR XOR BCS DEC EXTU INC 5 Note: * Cannot be used in the H8S/2626 Group or H8S/2623 Group. DEC SUBS 1A NOT ROTXL 12 17 SHLL DAA 0F SHLR ADDS 0B 11 INC 1 LDM AH 1st byte 10 MOV 0 0A BH 01 AH AL Instruction code AND AND BNE MAC 6 * BEQ DEC EXTU ROTXR ROTXL SHLR SHLL INC 7 MOV BVC 9 BVS SUBS NEG ROTR ROTL SHAR SHAL ADDS SLEEP 8 MOV BPL * CLRMAC A BMI NEG B C BGE MOVTPE CMP SUB ROTR ROTL SHAR SHAL MOV ADD Table A.3(3) D BLT DEC EXTS INC Table A.3(3) BGT TAS E F BLE DEC EXTS ROTR ROTL SHAR SHAL INC Table A.3(3) Appendix A Instruction Set Table A.3 Operation Code Map (2) Rev. 5.00 Jan 10, 2006 page 803 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 804 of 1042 REJ09B0275-0500 BCLR MULXS 2 3 BSET 7Faa7 *2 BNOT BNOT BCLR BCLR Notes: 1. r is the register specification field. 2. aa is the absolute address specification. BSET 7Faa6 *2 7Eaa7 BTST BCLR BTST BNOT *2 BSET 7Dr07 *1 7Eaa6 *2 BSET 7Dr06 *1 7Cr07 XOR 5 DH AND 6 DL 4th byte 7 BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST OR 4 CL 3rd byte CH DIVXS BL BTST BNOT DIVXS 1 BH BTST MULXS 0 AL 2nd byte *1 CL AH 1st byte 7Cr06 *1 01F06 01D05 01C05 AH AL BH BL CH Instruction code 8 9 A B C D E F Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. Appendix A Instruction Set Table A.3 Operation Code Map (3) BSET 0 AH BNOT 1 AL 1st byte BNOT 1 0 BSET AL 1st byte AH BCLR 2 BH 3 6 7 EL 5th byte EH 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST 3 5 DL 4th byte DH BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 2nd byte BCLR 2 BL 2nd byte BH Note: * aa is the absolute address specification. 6A38aaaaaaaa7* 6A38aaaaaaaa6* 6A30aaaaaaaa7* 6A30aaaaaaaa6* AHALBHBL ... FHFLGH GL Instruction code 6A18aaaa7* 6A18aaaa6* 6A10aaaa7* 6A10aaaa6* AHALBHBLCHCLDHDLEH EL Instruction code 8 8 FH 9 FL 6th byte 9 FL 6th byte FH A B HH HL 8th byte C D E F B C D E F Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. GL 7th byte GH A Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. Appendix A Instruction Set Table A.3 Operation Code Map (4) Rev. 5.00 Jan 10, 2006 page 805 of 1042 REJ09B0275-0500 Appendix A Instruction Set A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A.5: I = L = 2, J = K = M = N = 0 From table A.4: SI = 4, SL = 2 Number of states required for execution = 2 × 4 + 2 × 2 = 12 2. JSR @@30 From table A.5: I = J = K = 2, L = M = N = 0 From table A.4: SI = SJ = SK = 4 Number of states required for execution = 2 × 4 + 2 × 4 + 2 × 4 = 24 Rev. 5.00 Jan 10, 2006 page 806 of 1042 REJ09B0275-0500 Appendix A Instruction Set Table A.4 Number of States per Cycle Access Conditions On-Chip Memory Cycle Instruction fetch SI 1 On-Chip Supporting Module External Device 8-Bit Bus 8-Bit Bus 16-Bit Bus 4 2 16-Bit Bus 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m 1 1 Branch address read SJ Stack operation SK Byte data access SL 2 2 3+m Word data access SM 4 4 6 + 2m Internal operation SN 1 1 1 1 1 Legend: m: Number of wait states inserted into external device access Rev. 5.00 Jan 10, 2006 page 807 of 1042 REJ09B0275-0500 Appendix A Instruction Set Table A.5 Number of Cycles in Instruction Execution Instruction Branch Stack Fetch Address Read Operation I J K Instruction Mnemonic ADD ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND AND.B #xx:8,Rd 1 AND.B Rs,Rd 1 AND.W #xx:16,Rd 2 AND.W Rs,Rd 1 AND.L #xx:32,ERd 3 Byte Data Access L AND.L ERs,ERd 2 ANDC ANDC #xx:8,CCR 1 ANDC #xx:8,EXR 2 BAND BAND #xx:3,Rd 1 BAND #xx:3,@ERd 2 BAND #xx:3,@aa:8 2 1 BAND #xx:3,@aa:16 3 1 BAND #xx:3,@aa:32 4 1 BRA d:8 (BT d:8) 2 BRN d:8 (BF d:8) Bcc BHI d:8 2 2 BLS d:8 2 BCC d:8 (BHS d:8) 2 BCS d:8 (BLO d:8) 2 BNE d:8 2 BEQ d:8 2 BVC d:8 2 BVS d:8 2 BPL d:8 2 BMI d:8 2 BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 2 Rev. 5.00 Jan 10, 2006 page 808 of 1042 REJ09B0275-0500 1 Word Data Access M Internal Operation N Appendix A Instruction Set Instruction Bcc Instruction Branch Stack Fetch Address Read Operation I J K Mnemonic BIAND BILD Word Data Access M Internal Operation N BRA d:16 (BT d:16) 2 1 BRN d:16 (BF d:16) 2 1 BHI d:16 2 1 BLS d:16 2 1 2 1 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BCLR Byte Data Access L 2 1 2 1 BEQ d:16 2 1 BVC d:16 2 1 BVS d:16 2 1 BPL d:16 2 1 BMI d:16 2 1 BGE d:16 2 1 BLT d:16 2 1 BGT d:16 2 1 BLE d:16 2 1 BCLR #xx:3,Rd 1 BCLR #xx:3,@ERd 2 2 BCLR #xx:3,@aa:8 2 2 BCLR #xx:3,@aa:16 3 2 BCLR #xx:3,@aa:32 4 2 BCLR Rn,Rd 1 BCLR Rn,@ERd 2 2 BCLR Rn,@aa:8 2 2 BCLR Rn,@aa:16 3 2 BCLR Rn,@aa:32 4 2 BIAND #xx:3,Rd 1 BIAND #xx:3,@ERd 2 BIAND #xx:3,@aa:8 2 1 BIAND #xx:3,@aa:16 3 1 BIAND #xx:3,@aa:32 4 1 BILD #xx:3,Rd 1 1 BILD #xx:3,@ERd 2 1 BILD #xx:3,@aa:8 2 1 BILD #xx:3,@aa:16 3 1 BILD #xx:3,@aa:32 4 1 Rev. 5.00 Jan 10, 2006 page 809 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction BIOR BIST BIXOR BLD BNOT BOR Mnemonic Instruction Branch Stack Fetch Address Read Operation I J K Byte Data Access L BIOR #xx:8,Rd 1 BIOR #xx:8,@ERd 2 1 BIOR #xx:8,@aa:8 2 1 BIOR #xx:8,@aa:16 3 1 BIOR #xx:8,@aa:32 4 1 BIST #xx:3,Rd 1 BIST #xx:3,@ERd 2 2 BIST #xx:3,@aa:8 2 2 BIST #xx:3,@aa:16 3 2 BIST #xx:3,@aa:32 4 2 BIXOR #xx:3,Rd 1 BIXOR #xx:3,@ERd 2 1 BIXOR #xx:3,@aa:8 2 1 BIXOR #xx:3,@aa:16 3 1 BIXOR #xx:3,@aa:32 4 1 BLD #xx:3,Rd 1 BLD #xx:3,@ERd 2 BLD #xx:3,@aa:8 2 1 BLD #xx:3,@aa:16 3 1 BLD #xx:3,@aa:32 4 1 BNOT #xx:3,Rd 1 1 BNOT #xx:3,@ERd 2 2 BNOT #xx:3,@aa:8 2 2 BNOT #xx:3,@aa:16 3 2 BNOT #xx:3,@aa:32 4 2 BNOT Rn,Rd 1 BNOT Rn,@ERd 2 BNOT Rn,@aa:8 2 2 BNOT Rn,@aa:16 3 2 BNOT Rn,@aa:32 4 2 BOR #xx:3,Rd 1 BOR #xx:3,@ERd 2 BOR #xx:3,@aa:8 2 1 BOR #xx:3,@aa:16 3 1 BOR #xx:3,@aa:32 4 1 Rev. 5.00 Jan 10, 2006 page 810 of 1042 REJ09B0275-0500 2 1 Word Data Access M Internal Operation N Appendix A Instruction Set Instruction BSET Mnemonic Instruction Branch Stack Fetch Address Read Operation I J K BSET #xx:3,Rd 1 Byte Data Access L BSET #xx:3,@ERd 2 2 BSET #xx:3,@aa:8 2 2 BSET #xx:3,@aa:16 3 2 BSET #xx:3,@aa:32 4 2 BSET Rn,Rd 1 BSET Rn,@ERd 2 2 BSET Rn,@aa:8 2 2 BSET Rn,@aa:16 3 2 BSET Rn,@aa:32 4 BSR BSR d:8 2 2 BSR d:16 2 2 BST BST #xx:3,Rd 1 BST #xx:3,@ERd 2 BST #xx:3,@aa:8 2 2 BST #xx:3,@aa:16 3 2 BST #xx:3,@aa:32 4 2 BTST #xx:3,Rd 1 BTST BXOR 1 2 2 1 BTST #xx:3,@aa:8 2 1 BTST #xx:3,@aa:16 3 1 BTST #xx:3,@aa:32 4 1 BTST Rn,Rd 1 BTST Rn,@ERd 2 1 BTST Rn,@aa:8 2 1 BTST Rn,@aa:16 3 1 BTST Rn,@aa:32 4 1 BXOR #xx:3,Rd 1 BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:3,@aa:16 3 1 BXOR #xx:3,@aa:32 4 1 CLRMAC CLRMAC 1 CMP CMP.B #xx:8,Rd 1 CMP.B Rs,Rd 1 DAA 2 CMP.W Rs,Rd 1 CMP.L #xx:32,ERd 3 CMP.L ERs,ERd 1 DAA Rd 1 Internal Operation N 2 BTST #xx:3,@ERd CMP.W #xx:16,Rd Word Data Access M 1*3 Rev. 5.00 Jan 10, 2006 page 811 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction Mnemonic Instruction Branch Stack Fetch Address Read Operation I J K DAS DAS Rd 1 DEC DEC.B Rd 1 DEC.W #1/2,Rd 1 Byte Data Access L Word Data Access M Internal Operation N DEC.L #1/2,ERd 1 DIVXS.B Rs,Rd 2 DIVXS.W Rs,ERd 2 19 DIVXU DIVXU.B Rs,Rd 1 11 DIVXU.W Rs,ERd 1 EEPMOV EEPMOV.B 2 EEPMOV.W 2 EXTS EXTS.W Rd 1 DIVXS EXTU INC JMP JSR LDC EXTS.L ERd 1 EXTU.W Rd 1 EXTU.L ERd 1 INC.B Rd 1 INC.W #1/2,Rd 1 INC.L #1/2,ERd 1 JMP @ERn 2 JMP @aa:24 2 JMP @@aa:8 2 JSR @ERn 2 JSR @aa:24 2 JSR @@aa:8 2 LDC #xx:8,CCR 1 LDC #xx:8,EXR 2 LDC Rs,CCR 1 11 19 2n + 2*2 2 2n + 2* 1 2 1 2 2 2 1 2 LDC Rs,EXR 1 LDC @ERs,CCR 2 LDC @ERs,EXR 2 1 LDC @(d:16,ERs),CCR 3 1 LDC @(d:16,ERs),EXR 3 1 LDC @(d:32,ERs),CCR 5 1 LDC @(d:32,ERs),EXR 5 1 LDC @ERs+,CCR 2 1 1 LDC @ERs+,EXR 2 1 1 LDC @aa:16,CCR 3 1 LDC @aa:16,EXR 3 1 LDC @aa:32,CCR 4 1 LDC @aa:32,EXR 4 1 Rev. 5.00 Jan 10, 2006 page 812 of 1042 REJ09B0275-0500 1 Appendix A Instruction Set Instruction LDM Mnemonic Instruction Branch Stack Fetch Address Read Operation I J K Byte Data Access L Word Data Access M Internal Operation N LDM.L @SP+, (ERn-ERn+1) 2 4 1 LDM.L @SP+, (ERn-ERn+2) 2 6 1 LDM.L @SP+, (ERn-ERn+3) 2 8 LDMAC ERs,MACH 1 1 1*3 LDMAC ERs,MACL 1 3 1* MAC MAC @ERn+,@ERm+ 2 MOV MOV.B #xx:8,Rd 1 MOV.B Rs,Rd 1 LDMAC 2 MOV.B @ERs,Rd 1 1 MOV.B @(d:16,ERs),Rd 2 1 MOV.B @(d:32,ERs),Rd 4 1 MOV.B @ERs+,Rd 1 1 MOV.B @aa:8,Rd 1 1 MOV.B @aa:16,Rd 2 1 MOV.B @aa:32,Rd 3 1 MOV.B Rs,@ERd 1 1 MOV.B Rs,@(d:16,ERd) 2 1 MOV.B Rs,@(d:32,ERd) 4 1 MOV.B Rs,@-ERd 1 1 MOV.B Rs,@aa:8 1 1 MOV.B Rs,@aa:16 2 1 MOV.B Rs,@aa:32 3 1 MOV.W #xx:16,Rd 2 MOV.W Rs,Rd 1 1 1 MOV.W @ERs,Rd 1 1 MOV.W @(d:16,ERs),Rd 2 1 MOV.W @(d:32,ERs),Rd 4 1 MOV.W @ERs+,Rd 1 1 MOV.W @aa:16,Rd 2 1 MOV.W @aa:32,Rd 3 1 MOV.W Rs,@ERd 1 1 MOV.W Rs,@(d:16,ERd) 2 1 MOV.W Rs,@(d:32,ERd) 4 1 MOV.W Rs,@-ERd 1 1 MOV.W Rs,@aa:16 2 1 MOV.W Rs,@aa:32 3 1 MOV.L #xx:32,ERd 3 MOV.L ERs,ERd 1 MOV.L @ERs,ERd 2 1 1 2 Rev. 5.00 Jan 10, 2006 page 813 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction MOV Mnemonic Instruction Branch Stack Fetch Address Read Operation I J K Byte Data Access L Word Data Access M MOV.L @(d:16,ERs),ERd 3 2 MOV.L @(d:32,ERs),ERd 5 2 MOV.L @ERs+,ERd 2 2 MOV.L @aa:16,ERd 3 2 MOV.L @aa:32,ERd 4 2 MOV.L ERs,@ERd 2 2 MOV.L ERs,@(d:16,ERd) 3 2 MOV.L ERs,@(d:32,ERd) 5 2 MOV.L ERs,@-ERd 2 2 MOV.L ERs,@aa:16 3 2 2 MOV.L ERs,@aa:32 4 MOVFPE MOVFPE @:aa:16,Rd Can not be used in the H8S/2626 Group or H8S/2623 Group. MOVTPE MOVTPE Rs,@:aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd 2 MULXU.B Rs,Rd 1 MULXU.W Rs,ERd 1 NEG NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP NOP 1 NOT NOT.B Rd 1 OR ORC POP PUSH NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8,Rd 1 OR.B Rs,Rd 1 OR.W #xx:16,Rd 2 OR.W Rs,Rd 1 OR.L #xx:32,ERd 3 OR.L ERs,ERd 2 1 1 2*3 3*3 2 MULXU Internal Operation N 2*3 3*3 ORC #xx:8,CCR 1 ORC #xx:8,EXR 2 POP.W Rn 1 1 1 POP.L ERn 2 2 1 PUSH.W Rn 1 1 1 PUSH.L ERn 2 2 1 Rev. 5.00 Jan 10, 2006 page 814 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction ROTL ROTR ROTXL ROTXR Mnemonic Instruction Branch Stack Fetch Address Read Operation I J K ROTL.B Rd 1 ROTL.B #2,Rd 1 ROTL.W Rd 1 ROTL.W #2,Rd 1 ROTL.L ERd 1 ROTL.L #2,ERd 1 ROTR.B Rd 1 ROTR.B #2,Rd 1 ROTR.W Rd 1 ROTR.W #2,Rd 1 ROTR.L ERd 1 ROTR.L #2,ERd 1 ROTXL.B Rd 1 ROTXL.B #2,Rd 1 ROTXL.W Rd 1 ROTXL.W #2,Rd 1 ROTXL.L ERd 1 ROTXL.L #2,ERd 1 ROTXR.B Rd 1 ROTXR.B #2,Rd 1 ROTXR.W Rd 1 ROTXR.W #2,Rd 1 Byte Data Access L Word Data Access M Internal Operation N ROTXR.L ERd 1 ROTXR.L #2,ERd 1 RTE RTE 2 2/3*1 1 RTS RTS 2 2 1 SHAL SHAL.B Rd 1 SHAL.B #2,Rd 1 SHAR SHAL.W Rd 1 SHAL.W #2,Rd 1 SHAL.L ERd 1 SHAL.L #2,ERd 1 SHAR.B Rd 1 SHAR.B #2,Rd 1 SHAR.W Rd 1 SHAR.W #2,Rd 1 SHAR.L ERd 1 SHAR.L #2,ERd 1 Rev. 5.00 Jan 10, 2006 page 815 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction SHLL SHLR Mnemonic Instruction Branch Stack Fetch Address Read Operation I J K SHLL.B Rd 1 SHLL.B #2,Rd 1 SHLL.W Rd 1 SHLL.W #2,Rd 1 SHLL.L ERd 1 SHLL.L #2,ERd 1 SHLR.B Rd 1 SHLR.B #2,Rd 1 SHLR.W Rd 1 SHLR.W #2,Rd 1 SHLR.L ERd 1 SHLR.L #2,ERd 1 SLEEP SLEEP 1 STC STC.B CCR,Rd 1 STC.B EXR,Rd 1 STM STMAC*3 SUB Byte Data Access L Word Data Access M Internal Operation N 1 STC.W CCR,@ERd 2 1 STC.W EXR,@ERd 2 1 STC.W CCR,@(d:16,ERd) 3 1 STC.W EXR,@(d:16,ERd) 3 1 STC.W CCR,@(d:32,ERd) 5 1 STC.W EXR,@(d:32,ERd) 5 1 STC.W CCR,@-ERd 2 1 1 STC.W EXR,@-ERd 2 1 1 STC.W CCR,@aa:16 3 1 STC.W EXR,@aa:16 3 1 STC.W CCR,@aa:32 4 1 STC.W EXR,@aa:32 4 1 STM.L (ERn-ERn+1),@-SP 2 4 1 STM.L (ERn-ERn+2),@-SP 2 6 1 STM.L (ERn-ERn+3),@-SP 2 8 STMAC MACH,ERd 1 1 *3 STMAC MACL,ERd 1 *3 SUB.B Rs,Rd 1 SUB.W #xx:16,Rd 2 SUB.W Rs,Rd 1 SUB.L #xx:32,ERd 3 SUB.L ERs,ERd 1 SUBS SUBS #1/2/4,ERd 1 SUBX SUBX #xx:8,Rd 1 SUBX Rs,Rd 1 Rev. 5.00 Jan 10, 2006 page 816 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction Branch Stack Fetch Address Read Operation I J K Byte Data Access L 2 2 Instruction Mnemonic TAS TAS TRAPA TRAPA #x:2 2 XOR XOR.B #xx:8,Rd 1 XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XORC @ERd * 4 XOR.W Rs,Rd 1 XOR.L #xx:32,ERd 3 XOR.L ERs,ERd 2 XORC #xx:8,CCR 1 XORC #xx:8,EXR 2 Word Data Access M 1 2/3* 2 Internal Operation N 2 Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. 5 for concatenated execution, 4 otherwise. 3. An internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation R:W EA 2 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Rev. 5.00 Jan 10, 2006 page 817 of 1042 REJ09B0275-0500 Appendix A Instruction Set Legend: R:B Byte-size read R:W Word-size read W:B Byte-size write W:W Word-size write :M Transfer of the bus is not performed immediately after this cycle 2nd Address of 2nd word (3rd and 4th bytes) 3rd Address of 3rd word (5th and 6th bytes) 4th Address of 4th word (7th and 8th bytes) 5th Address of 5th word (9th and 10th bytes) NEXT Address of next instruction EA Effective address VEC Vector address Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A.1 Address Bus, RD, RD HWR, HWR and LWR Timing (8-Bit Bus, Three-State Access, No Wait States) Rev. 5.00 Jan 10, 2006 page 818 of 1042 REJ09B0275-0500 Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W 3rd R:W NEXT R:W NEXT 4 5 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT R:W NEXT 3 6 7 8 9 Table A.6 R:W 3rd R:W NEXT 2 Appendix A Instruction Set Instruction Execution Cycles Rev. 5.00 Jan 10, 2006 page 819 of 1042 REJ09B0275-0500 1 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd Instruction BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 Rev. 5.00 Jan 10, 2006 page 820 of 1042 REJ09B0275-0500 R:B:M EA R:B:M EA R:W 3rd 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state 4 5 R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA 3 6 7 8 9 Appendix A Instruction Set Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 5 6 R:W:M NEXT W:B EA R:B:M EA R:B:M EA R:W 3rd R:W 3rd 4 R:B:M EA 3 R:W 4th 2 R:W 3rd 7 8 9 Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 821 of 1042 REJ09B0275-0500 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd Rev. 5.00 Jan 10, 2006 page 822 of 1042 REJ09B0275-0500 R:W:M NEXT R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W:M stack (H) R:W EA R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA Internal operation, 1 state R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:W stack (L) W:W:M stack (H) W:W stack (L) W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:B:M EA R:B:M EA R:W 3rd R:W 3rd 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd 7 8 9 Appendix A Instruction Set 1 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd Internal operation, 1 state R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 ← Repeated n times*2 → R:W 3rd R:W NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W NEXT 3 4 5 R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT 2 R:B EA R:W 3rd R:W 3rd R:W NEXT R:W NEXT 6 7 8 9 Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 823 of 1042 REJ09B0275-0500 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn–ERn+1) 3 4 5 R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W NEXT Rev. 5.00 Jan 10, 2006 page 824 of 1042 REJ09B0275-0500 R:W NEXT R:W NEXT R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W EA R:W EA R:W EA R:W 5th R:W 5th R:W EA Internal operation, R:W EA 1 state R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 2 R:W EA R:W EA R:W EA 6 7 8 9 Appendix A Instruction Set 1 R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT Instruction LDM.L @SP+,(ERn–ERn+2) LDM.L @SP+,(ERn–ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT R:W EA R:W NEXT R:W EA R:W 4th R:W EA W:B EA R:W NEXT W:B EA R:W 4th W:B EA R:B EA R:W NEXT R:B EA R:W 4th R:B EA R:B EA R:W NEXT W:B EA R:W NEXT R:B EA R:W NEXT R:W EA W:B EA R:B EA 3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Internal operation, ← Repeated n times*3 → 1 state Internal operation, 1 state R:W NEXT R:W EAn R:W EAm 2 R:W NEXT 6 7 8 9 Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 825 of 1042 REJ09B0275-0500 Rev. 5.00 Jan 10, 2006 page 826 of 1042 REJ09B0275-0500 R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd W:W EA R:W NEXT R:W NEXT 3 W:W EA R:E 4th W:W EA R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W:M 3rd R:W NEXT R:W:M 3rd R:W 4th R:W:M NEXT W:W:M EA R:W:M 3rd R:W NEXT R:W:M 3rd R:W:M 4th R:W:M NEXT Internal operation, 1 state R:W:M 3rd R:W NEXT R:W:M 3rd R:W 4th R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT 2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W:M EA R:W NEXT R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA R:W EA+2 R:W:M EA R:W 5th R:W:M EA W:W EA R:W NEXT 4 R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Internal operation, 2 states R:W NEXT Internal operation, 3 states Internal operation, 2 states Internal operation, 3 states Cannot be used in the H8S/2626 Group or H8S/2623 Group. 1 R:W 2nd R:W 2nd R:W NEXT Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@–ERd W:W EA+2 W:W:M EA W:W EA+2 R:W NEXT W:W EA+2 R:W EA+2 R:W:M EA R:W EA+2 R:W NEXT R:W EA+2 W:W EA 5 W:W EA+2 W:W:M EA R:W EA+2 R:W:M EA 6 W:W EA+2 R:W EA+2 7 8 9 Appendix A Instruction Set 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd R:W NEXT R:W 3rd R:W NEXT 4 R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state 3 2 R:W NEXT W:W EA+2 R:W EA+2 5 6 7 8 9 Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 827 of 1042 REJ09B0275-0500 1 R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd Instruction ROTXR.L #2,ERd RTE RTS SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) 3 Rev. 5.00 Jan 10, 2006 page 828 of 1042 REJ09B0275-0500 R:W NEXT R:W NEXT R:W 3rd Internal operation:M W:W EA W:W EA R:W NEXT R:W:M stack (H) R:W stack (L) R:W stack (EXR) R:W stack (H) 2 5 6 W:W EA R:W stack (L) Internal operation, R:W*4 1 state Internal operation, R:W*4 1 state 4 7 8 9 Appendix A Instruction Set 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@–ERd STC EXR,@–ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn–ERn+1),@–SP STM.L(ERn–ERn+2),@–SP STM.L(ERn–ERn+3),@–SP STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd *8 TRAPA #x:2 XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state R:W 3rd R:W NEXT 3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state R:W:M NEXT Internal operation, 1 state 2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W NEXT R:W NEXT 5 W:B EA W:W stack (H) W:W EA W:W EA 6 W:W stack (EXR) R:W:M VEC W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W EA 4 W:W EA R:W 5th R:W 5th W:W EA R:W VEC+2 7 9 Internal operation, R:W*7 1 state 8 Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 829 of 1042 REJ09B0275-0500 R:W*6 Interrupt exception 3 4 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state R:W NEXT R:W VEC+2 2 R:W NEXT W:W stack (EXR) 5 R:W:M VEC 6 R:W VEC+2 7 9 Internal operation, R:W*8 1 state 8 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. 3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. Start address after return. 5. Start address of the program. 6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. Start address of the interrupt-handling routine. 8. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Reset exception Appendix A Instruction Set Rev. 5.00 Jan 10, 2006 page 830 of 1042 REJ09B0275-0500 Appendix A Instruction Set A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m=      31 for longword operands 15 for word operands 7 for byte operands Si The i-th bit of the source operand Di The i-th bit of the destination operand Ri The i-th bit of the result Dn The specified bit in the destination operand — Not affected Modified according to the result of the instruction (see definition) 0 Always cleared to 0 1 Always set to 1 * Undetermined (no guaranteed value) Z' Z flag before instruction execution C' C flag before instruction execution Rev. 5.00 Jan 10, 2006 page 831 of 1042 REJ09B0275-0500 Appendix A Instruction Set Table A.7 Instruction Condition Code Modification H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADD N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADDX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ANDC Stores the corresponding bits of the result. No flags change when the operand is EXR. BAND — — — — Bcc — — — — — BCLR — — — — — BIAND — — — — C = C' · Dn BILD — — — — C = Dn BIOR — — — — C = C' + Dn BIST — — — — — BIXOR — — — — C = C' · Dn + C' · Dn BLD — — — — C = Dn BNOT — — — — — BOR — — — — BSET — — — — — BSR — — — — — BST — — — — — BTST — — BXOR — — — — — — C = C' · Dn C = C' + Dn Z = Dn C = C' · Dn + C' · Dn Rev. 5.00 Jan 10, 2006 page 832 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction H N Z V C CLRMAC — — — — — Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 CMP N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm DIVXS — — — N = Sm · Dm + Sm · Dm Z = Sm · Sm–1 · ...... · S0 DIVXU — — — N = Sm Z = Sm · Sm–1 · ...... · S0 EEPMOV — — — — — EXTS — EXTU — 0 INC — 0 0 — N = Rm — Z = Rm · Rm–1 · ...... · R0 Z = Rm · Rm–1 · ...... · R0 — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm JMP — — — — — JSR — — — — — LDC Stores the corresponding bits of the result. No flags change when the operand is EXR. LDM — — — — — LDMAC — — — — — MAC — — — — — Rev. 5.00 Jan 10, 2006 page 833 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction H MOV — N Z V C Definition 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 MOVFPE Can not be used in the H8S/2626 Group or H8S/2623 Group. MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ...... · R0 MULXU — — — — — NEG H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP — — — — — NOT — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 OR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ORC Stores the corresponding bits of the result. No flags change when the operand is EXR. POP — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 PUSH — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ROTL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) Rev. 5.00 Jan 10, 2006 page 834 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction H ROTXL — N Z V C 0 Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE Stores the corresponding bits of the result. RTS — — — — — SHAL — N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Dm–1 + Dm · Dm–1 (1-bit shift) V = Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2 (2-bit shift) C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHAR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) SHLR — 0 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP — — — — — STC — — — — — STM — — — — — STMAC — — N = 1 if MAC instruction resulted in negative value in MAC register Z = 1 if MAC instruction resulted in zero value in MAC register V = 1 if MAC instruction resulted in overflow Rev. 5.00 Jan 10, 2006 page 835 of 1042 REJ09B0275-0500 Appendix A Instruction Set Instruction H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUB N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUBX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 TRAPA — — — — — XOR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 XORC Stores the corresponding bits of the result. No flags change when the operand is EXR. Rev. 5.00 Jan 10, 2006 page 836 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Appendix B Internal I/O Register B.1 Address Register Address Name H'EBC0 to H'EFBF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width MRA SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz DTC MRB CHNE DISEL — — — — — — 16/32*1 bits SAR DAR CRA CRB H'F800 MCR MCR7 — MCR5 — — MCR2 MCR1 MCR0 H'F801 GSR — — — — GSR3 GSR2 GSR1 GSR0 8 H'F802 BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 8, 16 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 — H'F803 H'F804 MBCR H'F805 H'F806 TXPR H'F807 H'F808 TXCR H'F809 H'F80A TXACK H'F80B H'F80C ABACK H'F80D H'F80E RXPR H'F80F H'F810 RFPR H'F811 H'F812 H'F813 IRR MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 — TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 — TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 — TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 — ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 — — — IRR12 — — IRR9 IRR8 HCAN 8 16 Rev. 5.00 Jan 10, 2006 page 837 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name H'F814 MBIMR H'F815 H'F816 IMR H'F817 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width HCAN 8, 16 MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — — — — IMR12 — — IMR9 IMR8 H'F818 REC 8 H'F819 TEC 8 H'F81A UMSR H'F81B H'F81C LAFML H'F81D H'F81E LAFMH H'F81F UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 LAFMH7 LAFMH6 LAFMH5 — — — LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 H'F820 MC0[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F821 MC0[2] — — — — — — — — H'F822 MC0[3] — — — — — — — — H'F823 MC0[4] — — — — — — — — H'F824 MC0[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F825 MC0[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F826 MC0[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F827 MC0[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F828 MC1[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F829 MC1[2] — — — — — — — — H'F82A MC1[3] — — — — — — — — H'F82B MC1[4] — — — — — — — — H'F82C MC1[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F82D MC1[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F82E MC1[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F82F MC1[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F830 MC2[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F831 MC2[2] — — — — — — — — H'F832 MC2[3] — — — — — — — — H'F833 MC2[4] — — — — — — — — H'F834 MC2[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 EXD_ID6 EXD_ID6 H'F835 MC2[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F836 MC2[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F837 MC2[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F838 MC3[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F839 MC3[2] — — — — — — — — EXD_ID6 Rev. 5.00 Jan 10, 2006 page 838 of 1042 REJ09B0275-0500 8, 16 16 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width HCAN 8, 16 H'F83A MC3[3] — — — — — — — — H'F83B MC3[4] — — — — — — — — H'F83C MC3[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F83D MC3[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F83E MC3[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F83F MC3[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F840 MC4[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F841 MC4[2] — — — — — — — — H'F842 MC4[3] — — — — — — — — H'F843 MC4[4] — — — — — — — — H'F844 MC4[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F845 MC4[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F846 MC4[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F847 MC4[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F848 MC5[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F849 MC5[2] — — — — — — — — H'F84A MC5[3] — — — — — — — — H'F84B MC5[4] — — — — — — — — H'F84C MC5[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 EXD_ID6 EXD_ID6 H'F84D MC5[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F84E MC5[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F84F MC5[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F850 MC6[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F851 MC6[2] — — — — — — — — H'F852 MC6[3] — — — — — — — — H'F853 MC6[4] — — — — — — — — H'F854 MC6[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F855 MC6[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F856 MC6[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F857 MC6[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F858 MC7[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F859 MC7[2] — — — — — — — — H'F85A MC7[3] — — — — — — — — H'F85B MC7[4] — — — — — — — — H'F85C MC7[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 EXD_ID6 EXD_ID6 H'F85D MC7[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F85E MC7[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 EXD_ID6 Rev. 5.00 Jan 10, 2006 page 839 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width HCAN 8, 16 H'F85F MC7[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F860 MC8[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F861 MC8[2] — — — — — — — — H'F862 MC8[3] — — — — — — — — H'F863 MC8[4] — — — — — — — — H'F864 MC8[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F865 MC8[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F866 MC8[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F867 MC8[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F868 MC9[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F869 MC9[2] — — — — — — — — H'F86A MC9[3] — — — — — — — — H'F86B MC9[4] — — — — — — — — H'F86C MC9[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 EXD_ID6 H'F86D MC9[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F86E MC9[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F86F MC9[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F870 MC10[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F871 MC10[2] — — — — — — — — H'F872 MC10[3] — — — — — — — — H'F873 MC10[4] — — — — — — — — H'F874 MC10[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 EXD_ID6 H'F875 MC10[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F876 MC10[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F877 MC10[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F878 MC11[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F879 MC11[2] — — — — — — — — H'F87A MC11[3] — — — — — — — — H'F87B MC11[4] — — — — — — — — H'F87C MC11[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 EXD_ID6 H'F87D MC11[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F87E MC11[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F87F MC11[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F880 MC12[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F881 MC12[2] — — — — — — — — H'F882 MC12[3] — — — — — — — — H'F883 MC12[4] — — — — — — — — EXD_ID6 Rev. 5.00 Jan 10, 2006 page 840 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F884 MC12[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F885 MC12[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F886 MC12[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F887 MC12[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F888 MC13[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F889 MC13[2] — — — — — — — — H'F88A MC13[3] — — — — — — — — H'F88B MC13[4] — — — — — — — — H'F88C MC13[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F88D MC13[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F88E MC13[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F88F MC13[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F890 MC14[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F891 MC14[2] — — — — — — — — H'F892 MC14[3] — — — — — — — — H'F893 MC14[4] — — — — — — — — H'F894 MC14[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 EXD_ID6 EXD_ID6 H'F895 MC14[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F896 MC14[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F897 MC14[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F898 MC15[1] — — — — DLC3 DLC2 DLC1 DLC0 H'F899 MC15[2] — — — — — — — — H'F89A MC15[3] — — — — — — — — H'F89B MC15[4] — — — — — — — — H'F89C MC15[5] STD_ID2 STD_ID1 STD_ID0 RTR IDE — EXD_ID17 EXD_ID16 H'F89D MC15[6] STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H'F89E MC15[7] EXD_ID7 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H'F89F MC15[8] EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H'F8B0 MD0[1] H'F8B1 MD0[2] H'F8B2 MD0[3] H'F8B3 MD0[4] H'F8B4 MD0[5] H'F8B5 MD0[6] H'F8B6 MD0[7] H'F8B7 MD0[8] H'F8B8 MD1[1] EXD_ID6 EXD_ID6 Module Name Data Bus Width HCAN 8, 16 Rev. 5.00 Jan 10, 2006 page 841 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name H'F8B9 MD1[2] H'F8BA MD1[3] H'F8BB MD1[4] H'F8BC MD1[5] H'F8BD MD1[6] H'F8BE MD1[7] H'F8BF MD1[8] H'F8C0 MD2[1] H'F8C1 MD2[2] H'F8C2 MD2[3] H'F8C3 MD2[4] H'F8C4 MD2[5] H'F8C5 MD2[6] H'F8C6 MD2[7] H'F8C7 MD2[8] H'F8C8 MD3[1] H'F8C9 MD3[2] H'F8CA MD3[3] H'F8CB MD3[4] H'F8CC MD3[5] H'F8CD MD3[6] H'F8CE MD3[7] H'F8CF MD3[8] H'F8D0 MD4[1] H'F8D1 MD4[2] H'F8D2 MD4[3] H'F8D3 MD4[4] H'F8D4 MD4[5] H'F8D5 MD4[6] H'F8D6 MD4[7] H'F8D7 MD4[8] H'F8D8 MD5[1] H'F8D9 MD5[2] H'F8DA MD5[3] H'F8DB MD5[4] H'F8DC MD5[5] H'F8DD MD5[6] Bit 7 Bit 6 Bit 5 Bit 4 Rev. 5.00 Jan 10, 2006 page 842 of 1042 REJ09B0275-0500 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width HCAN 8, 16 Appendix B Internal I/O Register Register Address Name H'F8DE MD5[7] H'F8DF MD5[8] H'F8E0 MD6[1] H'F8E1 MD6[2] H'F8E2 MD6[3] H'F8E3 MD6[4] H'F8E4 MD6[5] H'F8E5 MD6[6] H'F8E6 MD6[7] H'F8E7 MD6[8] H'F8E8 MD7[1] H'F8E9 MD7[2] H'F8EA MD7[3] H'F8EB MD7[4] H'F8EC MD7[5] H'F8ED MD7[6] H'F8EE MD7[7] H'F8EF MD7[8] H'F8F0 MD8[1] H'F8F1 MD8[2] H'F8F2 MD8[3] H'F8F3 MD8[4] H'F8F4 MD8[5] H'F8F5 MD8[6] H'F8F6 MD8[7] H'F8F7 MD8[8] H'F8F8 MD9[1] H'F8F9 MD9[2] H'F8FA MD9[3] H'F8FB MD9[4] H'F8FC MD9[5] H'F8FD MD9[6] H'F8FE MD9[7] H'F8FF MD9[8] H'F900 MD10[1] H'F901 MD10[2] H'F902 MD10[3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width HCAN 8, 16 Rev. 5.00 Jan 10, 2006 page 843 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name H'F903 MD10[4] H'F904 MD10[5] H'F905 MD10[6] H'F906 MD10[7] H'F907 MD10[8] H'F908 MD11[1] H'F909 MD11[2] H'F90A MD11[3] H'F90B MD11[4] H'F90C MD11[5] H'F90D MD11[6] H'F90E MD11[7] H'F90F MD11[8] H'F910 MD12[1] H'F911 MD12[2] H'F912 MD12[3] H'F913 MD12[4] H'F914 MD12[5] H'F915 MD12[6] H'F916 MD12[7] H'F917 MD12[8] H'F918 MD13[1] H'F919 MD13[2] H'F91A MD13[3] H'F91B MD13[4] H'F91C MD13[5] H'F91D MD13[6] H'F91E MD13[7] H'F91F MD13[8] H'F920 MD14[1] H'F921 MD14[2] H'F922 MD14[3] H'F923 MD14[4] H'F924 MD14[5] H'F925 MD14[6] H'F926 MD14[7] H'F927 MD14[8] H'F928 MD15[1] Bit 7 Bit 6 Bit 5 Bit 4 Rev. 5.00 Jan 10, 2006 page 844 of 1042 REJ09B0275-0500 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width HCAN 8, 16 Appendix B Internal I/O Register Register Address Name H'F929 MD15[2] H'F92A MD15[3] H'F92B MD15[4] H'F92C MD15[5] H'F92D MD15[6] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F92E MD15[7] H'F92F MD15[8] H'FDAC DADR2*6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FDAD DADR3*6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FDAE DACR23*6 DAOE1 DAOE0 DAE — — — — — Module Name Data Bus Width HCAN 8, 16 D/A converter 8 8 H'FDB4 SCRX — — — — FLSHE — — — ROM H'FDE4 SBYCR SSBY STS2 STS1 STS0 OPE — — — 8 Powerdown state H'FDE5 SYSCR MACS — INTM1 INTM0 NMIEG — — RAME MCU, RAM interrupt controller H'FDE6 SCKCR PSTOP — — — STCS SCK2 SCK1 SCK0 8 Clock pulse generator, powerdown state H'FDE7 MDCR — — — — — MDS2 MDS1 MDS0 MCU H'FDE8 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 H'FDE9 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Power8 down state H'FDEA MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 H'FDEB PFCR — — BUZZE*4 — AE3 AE2 AE1 AE0 MCU, bus controller 8 H'FDEC LPWRCR DTON*4 LSON*4 NESEL*4 SUBSTP*4 RFCUT — STC1 STC0 Clock pulse generator 8 H'FE00 BARA — — — — — — — — BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 PC break controller 8 BAA23 H'FE04 BARB BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 — — — — — — — — BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA8 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 H'FE08 BCRA CMFA CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA H'FE09 BCRB CMFB CDB BAMRB2 BAMRB1 BAMRA0 CSELB1 CSELB0 BIEB 8 8 Rev. 5.00 Jan 10, 2006 page 845 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FE12 ISCRH — — — — IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA H'FE13 ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA H'FE14 IER — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E H'FE15 ISR — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F H'FE16 DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 H'FE17 DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 H'FE18 DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 H'FE19 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 H'FE1A DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 H'FE1B DTCERF DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 H'FE1C DTCERG DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG3 DTCEG2 DTCEG1 DTCEG0 H'FE1F DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 H'FE26 PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 H'FE27 PMR G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV H'FE28 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 H'FE29 NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 H'FE2A PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 H'FE2B PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 H'FE2C NDRH*2 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 H'FE2D NDRL*2 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 H'FE2E NDRH*2 — — — — NDR11 NDR10 NDR9 NDR8 H'FE2F NDRL*2 — — — — NDR3 NDR2 NDR1 NDR0 H'FE30 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR H'FE39 PADDR — — PA5DDR*5 PA4DDR*5 PA3DDR PA2DDR PA1DDR PA0DDR H'FE3A PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR H'FE3B PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR H'FE3C PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR H'FE3D PEDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR H'FE3E PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR H'FE40 PAPCR — — PA5PCR*5 PA4PCR*5 PA3PCR PA2PCR PA1PCR PA0PCR H'FE41 PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR H'FE42 PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR H'FE43 PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR H'FE44 PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR H'FE47 PAODR — — PA5ODR*5 PA4ODR*5 PA3ODR PA2ODR PA1ODR PA0ODR H'FE48 PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR H'FE49 PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Rev. 5.00 Jan 10, 2006 page 846 of 1042 REJ09B0275-0500 Module Name Data Bus Width Interrupt controller 8 DTC 8 PPG 8 I/O port 8 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Data Bus Width H'FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3 16 H'FE81 TMDR3 — — BFB BFA MD3 MD2 MD1 MD0 IOA0 TPU4 16 TPU5 16 H'FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 H'FE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H'FE84 TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA H'FE85 TSR3 — — — TCFV TGFD TGFC TGFB TGFA H'FE86 TCNT3 H'FE87 H'FE88 TGR3A H'FE89 H'FE8A TGR3B H'FE8B H'FE8C TGR3C H'FE8D H'FE8E TGR3D H'FE8F H'FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FE91 TMDR4 — — — — MD3 MD2 MD1 MD0 H'FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FE94 TIER4 TTGE — TCIEU TCIEV — — TGIEB TGIEA H'FE95 TSR4 TCFD — TCFU TCFV — — TGFB TGFA H'FE96 TCNT4 H'FE97 H'FE98 TGR4A H'FE99 H'FE9A TGR4B H'FE9B H'FEA0 TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FEA1 TMDR5 — — — — MD3 MD2 MD1 MD0 H'FEA2 TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FEA4 TIER5 TTGE — TCIEU TCIEV — — TGIEB TGIEA H'FEA5 TSR5 TCFD — TCFU TCFV — — TGFB TGFA H'FEA6 TCNT5 H'FEA7 H'FEA8 TGR5A H'FEA9 H'FEAA TGR5B H'FEAB Rev. 5.00 Jan 10, 2006 page 847 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FEB0 TSTR — — CST5 CST4 CST3 CST2 CST1 CST0 H'FEB1 TSYR — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 H'FEC0 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC1 IPRB — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC2 IPRC — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC3 IPRD — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC4 IPRE — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC5 IPRF — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC6 IPRG — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC7 IPRH — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC8 IPRI — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC9 IPRJ — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FECA IPRK — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FECC IPRM — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FED0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 H'FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 H'FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40 H'FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00 H'FED4 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — — Module Name Data Bus Width TPU All 16 Interrupt controller 8 Bus controller 8 H'FED5 BCRL BRLE BREQOE — — — — WDBE WAITE H'FEDB RAMER*3 — — — — RAMS RAM2 RAM1 RAM0 ROM H'FF00 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR I/O port 8 H'FF09 PADR — — PA5DR*5 PA4DR*5 PA3DR PA2DR PA1DR PA0DR TPU0 16 H'FF0A PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR H'FF0B PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR H'FF0C PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR H'FF0D PEDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR H'FF0E PFDR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR H'FF10 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FF11 TMDR0 — — BFB BFA MD3 MD2 MD1 MD0 H'FF12 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FF13 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H'FF14 TIER0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA H'FF15 TSR0 — — — TCFV TGFD TGFC TGFB TGFA H'FF16 TCNT0 H'FF17 Rev. 5.00 Jan 10, 2006 page 848 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name H'FF18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGR0A Module Name Data Bus Width TPU0 16 TPU1 16 TPU2 16 WDT0 16 H'FF19 H'FF1A TGR0B H'FF1B H'FF1C TGR0C H'FF1D H'FF1E TGR0D H'FF1F H'FF20 TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FF21 TMDR1 — — — — MD3 MD2 MD1 MD0 H'FF22 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FF24 TIER1 TTGE — TCIEU TCIEV — — TGIEB TGIEA H'FF25 TSR1 TCFD — TCFU TCFV — — TGFB TGFA H'FF26 TCNT1 H'FF27 H'FF28 TGR1A H'FF29 H'FF2A TGR1B H'FF2B H'FF30 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 H'FF31 TMDR2 — — — — MD3 MD2 MD1 MD0 H'FF32 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FF34 TIER2 TTGE — TCIEU TCIEV — — TGIEB TGIEA H'FF35 TSR2 TCFD — TCFU TCFV — — TGFB TGFA H'FF36 TCNT2 OVF WT/IT TME — — CKS2 CKS1 CKS0 H'FF37 H'FF38 TGR2A H'FF39 H'FF3A TGR2B H'FF3B H'FF74 TCSR0 (Write) TCNT0 H'FF75 (Read) TCNT0 H'FF76 (Write) RSTCSR WOVF RSTE RSTS — — — — — H'FF77 (Read) RSTCSR WOVF RSTE RSTS — — — — — Rev. 5.00 Jan 10, 2006 page 849 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register Register Address Name Bit 7 H'FF78 SMR0 H'FF79 BRR0 H'FF7A SCR0 H'FF7B TDR0 H'FF7C SSR0 Bit 4 Bit 3 Bit 2 Bit 1 Module Name Data Bus Width CKS0 SCI0 8 CKS0 Smart card interface 0 Bit 6 Bit 5 Bit 0 C/A CHR PE O/E STOP MP CKS1 GM BLK PE O/E BCP1 BCP0 CKS1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI0, smart card interface 0 TDRE RDRF ORER FER PER TEND MPB MPBT SCI0 TDRE RDRF ORER ERS PER TEND MPB MPBT Smart card interface 0 — SDIR SINV — SMIF H'FF7D RDR0 H'FF7E SCMR0 — — — H'FF80 SMR1 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI1 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Smart card interface 1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCI0, smart card interface 0 SCI1, smart card interface 1 H'FF81 BRR1 H'FF82 SCR1 H'FF83 TDR1 H'FF84 SSR1 TDRE RDRF ORER FER PER TEND MPB MPBT SCI1 SSR1 TDRE RDRF ORER ERS PER TEND MPB MPBT Smart card interface 1 — SDIR SINV — SMIF H'FF85 RDR1 H'FF86 SCMR1 — — — H'FF88 SMR2 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI2 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Smart card interface 2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'FF89 BRR2 H'FF8A SCR2 H'FF8B TDR2 H'FF8C SCI1, smart card interface 1 SCI2, smart card interface 2 SSR2 TDRE RDRF ORER FER PER TEND MPB MPBT SCI2 SSR2 TDRE RDRF ORER ERS PER TEND MPB MPBT Smart card interface 2 — — — — SDIR SINV — SMIF H'FF8D RDR2 H'FF8E SCMR2 Rev. 5.00 Jan 10, 2006 page 850 of 1042 REJ09B0275-0500 8 SCI2, smart card interface 2 8 Appendix B Internal I/O Register Register Address Name Bit 7 H'FF90 ADDRA H'FF91 H'FF92 ADDRB H'FF93 H'FF94 ADDRC H'FF95 H'FF96 ADDRD H'FF97 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Module Name Data Bus Width A/D converter 16 H'FF98 ADCSR ADF ADIE ADST SCAN CH3 CH2 CH1 CH0 H'FF99 ADCR TRGS1 TRGS0 — — CKS1 CKS0 — — H'FFA2 TCSR1*6 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 WDT1 16 (Write) TCNT1*6 H'FFA3 (Read) TCNT1*6 H'FFA8 FLMCR1*3 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 ROM 8 H'FFA9 FLMCR2*3 FLER — — — — — — — H'FFAA EBR1*3 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H'FFAB EBR2*3 — — — — EB11 EB10 EB9 EB8 H'FFAC FLPWCR PDWND — — — — — — — H'FFB0 PORT1 P17 P16 P15 P14 P13 P12 P11 P10 I/O port 8 H'FFB3 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 H'FFB8 PORT9 P97 P96 P95 P94 P93 P92 P91 P90 H'FFB9 PORTA — — PA5 PA4 PA3 PA2 PA1 PA0 H'FFBA PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 H'FFBB PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 H'FFBC PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 H'FFBD PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 H'FFBE PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 2. The address depends on the output trigger setting. 3. These registers are present in the F-ZTAT version, but not in the mask ROM version. An undefined value will be returned if these registers are read in the mask ROM version. 4. Valid only in the H8S/2626 Group; reserved bits in the H8S/2623 Group. For the handling of these bits in register writes, see the individual register descriptions the respective sections. 5. Valid only in the H8S/2623 Group; reserved bits in the H8S/2626 Group. For the handling of these bits in register writes, see the individual register descriptions the respective sections. 6. These registers are not available, and must not be accessed, in the H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 851 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register B.2 Functions Register acronym Register name Address to which the register is mapped SBYCR—Standby Control Register H'FDE4 Name of on-chip supporting module Power-Down Modes Bit numbers Bit Initial bit values : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — Initial value : 0 0 0 0 1 0 0 0 Read/Write : R/W R/W R/W R/W R/W — — R/W Names of the bits. Dashes (—) indicate reserved bits. Output port enable 0 In software standby mode, address bus and bus control signals are high-impedance Possible types of access R Read only W Write only 1 In software standby mode, address bus and bus control signals retain their output state Full name of bit Standby timer select R/W Read and write 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 1 0 Standby time = 32768 states 1 Standby time = 65536 states 1 0 0 Standby time = 131072 states 1 Standby time = 262144 states 1 0 Reserved 1 Standby time = 16 states Software standby 0 Transition to sleep mode after execution of SLEEP instruction 1 Transition to software standby mode after execution of SLEEP instruction Rev. 5.00 Jan 10, 2006 page 852 of 1042 REJ09B0275-0500 Descriptions of bit settings Appendix B Internal I/O Register MRA—DTC Mode Register A Bit : Initial value : Read/Write : H'EBC0–H'EFBF DTC 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — — — DTC data transfer size 0 Byte-size transfer 1 Word-size transfer DTC transfer mode select 0 Destination side is repeat area or block area 1 Source side is repeat area or block area DTC mode 0 0 Normal mode 1 Repeat mode 1 0 Block transfer mode 1 — Destination address mode 0 — DAR is fixed 1 0 DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Source address mode 0 — SAR is fixed 1 0 SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 1 SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) Rev. 5.00 Jan 10, 2006 page 853 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MRB—DTC Mode Register B Bit DTC 7 6 5 4 3 2 1 0 CHNE DISEL — — — — — — : Initial value : H'EBC0–H'EFBF Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined — Read/Write : — — — — — — — DTC interrupt select 0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After a data transfer ends, the CPU interrupt is enabled DTC chain transfer enable 0 End of DTC data transfer 1 DTC chain transfer SAR—DTC Source Address Register Bit : 23 22 21 20 19 H'EBC0–H'EFBF --- 4 DTC 3 2 1 0 --Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — ----- Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — Specifies DTC transfer data source address DAR—DTC Destination Address Register Bit : 23 22 21 20 19 H'EBC0–H'EFBF --- 4 DTC 3 2 1 0 --Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — ----- Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — Specifies DTC transfer data destination address Rev. 5.00 Jan 10, 2006 page 854 of 1042 REJ09B0275-0500 — — — Appendix B Internal I/O Register CRA—DTC Transfer Count Register A Bit : Initial value : Read/Write : 15 14 13 12 11 H'EBC0–H'EFBF 10 9 8 7 6 5 DTC 4 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — CRAH — — — — CRAL Specifies the number of DTC data transfers CRB—DTC Transfer Count Register B Bit : Initial value : Read/Write : 15 14 13 12 11 H'EBC0–H'EFBF 10 9 8 7 6 5 4 DTC 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — — — — — — Specifies the number of DTC block data transfers Rev. 5.00 Jan 10, 2006 page 855 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MCR—Master Control Register H'F800 HCAN MCR Bit : 7 6 5 4 3 2 1 0 MCR7 — MCR5 — — MCR2 MCR1 MCR0 Initial value : 0 0 0 0 0 0 0 1 Read/Write : R/W R R/W R R R/W R/W R/W Reset request 0 Normal operating mode (MCR0 = 0 and GSR3 = 0) [Setting condition] When 0 is written after an HCAN reset 1 HCAN reset mode transition request Halt request 0 HCAN normal operating mode 1 HCAN halt mode transition request Message transmission method 0 Transmission order determined by message identifier priority 1 Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) HCAN sleep mode 0 HCAN sleep mode released 1 Transition to HCAN sleep mode enabled HCAN sleep mode release 0 HCAN sleep mode release by CAN bus operation disabled 1 HCAN sleep mode release by CAN bus operation enabled Rev. 5.00 Jan 10, 2006 page 856 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register GSR—General Status Register H'F801 HCAN GSR Bit : 7 6 5 4 3 2 1 0 — — — — GSR3 GSR2 GSR1 GSR0 Initial value : 0 0 0 0 1 1 0 0 Read/Write : R R R R R R R R Bus off flag 0 [Reset condition] Recovery from bus off state 1 When TEC ≥ 256 (bus off state) Transmit/receive warning flag 0 [Reset condition] When TEC < 96 and REC < 96 or TEC ≥ 256 1 When TEC ≥ 96 or REC ≥ 96 Message transmission status flag 0 Message transmission period 1 [Reset condition] Idle period Reset status bit 0 Normal operating state [Setting condition] After an HCAN internal reset 1 Configuration mode [Reset condition] MCR0 reset mode and sleep mode Rev. 5.00 Jan 10, 2006 page 857 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BCR—Bit Configuration Register H'F802 HCAN BCR Bit : 15 14 13 12 11 10 9 8 BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Baud rate prescale 0 0 0 0 0 0 2 × system clock 0 0 0 0 0 1 4 × system clock 0 0 0 0 1 0 6 × system clock : : : : : : 1 1 1 1 1 1 : 128 × system clock Resynchronization jump width 0 0 Max. bit synchronization width = 1 time quantum 1 Max. bit synchronization width = 2 time quanta 1 0 Max. bit synchronization width = 3 time quanta 1 Max. bit synchronization width = 4 time quanta Rev. 5.00 Jan 10, 2006 page 858 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BCR Bit : 7 6 5 4 3 2 1 0 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Time segment 1 0 0 0 0 Setting prohibited 0 0 0 1 Setting prohibited 0 0 1 0 Setting prohibited 0 0 1 1 TSEG1 = 4 time quanta 0 1 0 0 TSEG1 = 5 time quanta : : : : 1 1 1 1 TSEG1 = 16 time quanta : Time segment 2 0 0 0 Setting prohibited 1 TSEG2 = 2 time quanta 1 0 TSEG2 = 3 time quanta 1 TSEG2 = 4 time quanta 1 0 0 TSEG2 = 5 time quanta 1 TSEG2 = 6 time quanta 1 0 TSEG2 = 7 time quanta 1 TSEG2 = 8 time quanta Bit sample point 0 Bit sampling at one point (end of time segment 1 (TSEG1)) 1 Bit sampling at three points (end of time segment 1 (TSEG1), and 1 time quantum before and after) Note: For details, see section 15.2.3, Bit Configuration Register (BCR). Rev. 5.00 Jan 10, 2006 page 859 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MBCR—Mailbox Configuration Register H'F804 HCAN MBCR Bit 15 14 13 12 11 10 9 8 MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 — Initial value : 0 0 0 0 0 0 0 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 Bit : : MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Mailbox setting register 0 Corresponding mailbox is set for transmission 1 Corresponding mailbox is set for reception Rev. 5.00 Jan 10, 2006 page 860 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TXPR—Transmit Wait Register H'F806 HCAN TXPR Bit 15 14 13 12 11 10 9 8 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 Bit : : TXPR9 TXPR8 Initial value : TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Transmit wait register 0 Transmit message idle state in corresponding mailbox [Clearing condition] Message transmission completion and cancellation completion 1 Transmit wait for transmit message in corresponding mailbox (CAN bus arbitration) Rev. 5.00 Jan 10, 2006 page 861 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TXCR—Transmit Wait Cancel Register H'F808 HCAN TXCR Bit 15 14 13 12 11 10 9 8 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 TXCR9 TXCR8 Bit : : TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Transmit wait cancel register 0 Transmit message cancellation idle state in corresponding mailbox [Clearing condition] Completion of TXPR clearing (when transmit message is canceled normally) 1 TXPR cleared for corresponding mailbox (transmit message cancellation) Rev. 5.00 Jan 10, 2006 page 862 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TXACK—Transmit Acknowledge Register H'F80A HCAN TXACK Bit : 15 14 13 12 11 10 9 TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 8 — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R 7 6 5 4 3 2 1 0 Bit : TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Transmit acknowledge register 0 [Clearing condition] Writing 1 1 Completion of message transmission for corresponding mailbox Note: * Can only be written with 1 for flag clearing. Rev. 5.00 Jan 10, 2006 page 863 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register ABACK—Abort Acknowledge Register H'F80C HCAN ABACK Bit : 15 14 13 12 11 10 9 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 8 — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R 7 6 5 4 3 2 1 0 Bit : ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Abort acknowledge register 0 [Clearing condition] Writing 1 1 Completion of transmit message cancellation for corresponding mailbox Note: * Can only be written with 1 for flag clearing. Rev. 5.00 Jan 10, 2006 page 864 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register RXPR—Receive Complete Register H'F80E HCAN RXPR Bit 15 14 13 12 11 10 9 8 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 Bit : : RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Receive complete register 0 [Clearing condition] Writing 1 1 Completion of message (data frame or remote frame) reception in corresponding mailbox Note: * Can only be written with 1 for flag clearing. Rev. 5.00 Jan 10, 2006 page 865 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register RFPR—Remote Request Register H'F810 HCAN RFPR Bit 15 14 13 12 11 10 9 8 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 Bit : : RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Remote request wait register 0 [Clearing condition] Writing 1 1 Completion of remote frame reception in corresponding mailbox Note: * Can only be written with 1 for flag clearing. Rev. 5.00 Jan 10, 2006 page 866 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register IRR—Interrupt Register H'F812 HCAN IRR Bit : 15 14 13 12 11 10 9 8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/(W)* Reset interrupt flag 0 [Clearing condition] Writing 1 1 Hardware reset (HCAN module stop, software standby) [Setting condition] When reset processing is completed after a hardware reset (HCAN module stop, software standby) Receive message interrupt flag 0 [Clearing condition] Clearing of all bits in RXPR (receive complete register) of mailbox for which receive interrupt requests are enabled MBIMR 1 Remote frame request interrupt flag 0 [Clearing condition] Clearing of all bits in RFPR (remote request wait register) of mailbox for which receive interrupt requests are enabled MBIMR 1 Remote frame received and stored in mailbox [Setting conditions] When remote frame reception is completed When corresponding MBIMR = 0 Bus off interrupt flag 0 [Clearing condition] Writing 1 1 Transmit overload warning interrupt flag 0 [Clearing condition] Writing 1 Bus off state caused by transmit error [Setting condition] When TEC ≥ 256 1 Overload frame transmission or recovery from bus off state [Setting conditions] • Error active/passive state — When overload frame is transmitted • Bus off state — When 11 recessive bits are received 128 times (REC ≥ 128) Error warning state caused by transmit error [Setting condition] When TEC ≥ 96 Receive overload warning interrupt flag 0 [Clearing condition] Writing 1 Overload frame/bus off recovery interrupt flag 0 [Clearing condition] Writing 1 1 Data frame or remote frame received and stored in mailbox [Setting conditions] When data frame or remote frame reception is completed When corresponding MBIMR = 0 1 Error warning state caused by receive error [Setting condition] When REC ≥ 96 Error passive interrupt flag 0 [Clearing condition] Writing 1 1 Error passive state caused by transmit/receive error [Setting condition] When TEC ≥ 128 or REC ≥ 128 Note: * Can only be written with 1 for flag clearing. Rev. 5.00 Jan 10, 2006 page 867 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register IRR Bit : 7 6 5 4 3 2 1 0 — — — IRR12 — — IRR9 IRR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — R/(W)* — — R R/(W)* Mailbox empty interrupt flag 0 [Clearing condition] Writing 1 1 Transmit message has been transmitted or aborted, and new message can be stored [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort Unread interrupt flag 0 [Clearing condition] Clearing of all bits in UMSR (unread message status register) 1 Unread message overwrite [Setting condition] When UMSR (unread message status register) is set Bus operation interrupt flag 0 CAN bus idle state [Clearing condition] Writing 1 1 CAN bus operation in HCAN sleep mode [Setting condition] Bus operation (dominant bit detection) in HCAN sleep mode Note: * Can only be written with 1 for flag clearing. Rev. 5.00 Jan 10, 2006 page 868 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MBIMR—Mailbox Interrupt Mask Register H'F814 HCAN MBIMR Bit : 15 14 13 12 11 10 9 8 MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit : MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Mailbox interrupt mask 0 [Transmitting] Interrupt request to CPU due to TXPR clearing [Receiving] Interrupt request to CPU due to RXPR setting 1 Interrupt requests to CPU disabled Rev. 5.00 Jan 10, 2006 page 869 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register IMR—Interrupt Mask Register H'F816 HCAN IMR Bit : 15 14 13 12 11 10 9 8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 — Initial value : 1 1 1 1 1 1 1 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R Receive message interrupt mask 0 Message reception interrupt request (RM1) to CPU by IRR1 enabled 1 Message reception interrupt request (RM1) to CPU by IRR1 disabled Remote frame request interrupt mask 0 Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled 1 Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled Transmit overload warning interrupt mask 0 TEC error warning interrupt request (OVR0) to CPU by IRR3 enabled 1 TEC error warning interrupt request (OVR0) to CPU by IRR3 disabled Receive overload warning interrupt mask 0 REC error warning interrupt request (OVR0) to CPU by IRR4 enabled 1 REC error warning interrupt request (OVR0) to CPU by IRR4 disabled Error passive interrupt mask 0 Error passive interrupt request to (ERS0) CPU by IRR5 enabled 1 Error passive interrupt request to (ERS0) CPU by IRR5 disabled Bus off interrupt mask 0 Bus off interrupt request (ERS0) to CPU by IRR6 enabled 1 Bus off interrupt request (ERS0) to CPU by IRR6 disabled Overload frame/bus off recovery interrupt mask 0 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 enabled 1 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7 disabled Rev. 5.00 Jan 10, 2006 page 870 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register IMR Bit : 7 6 5 4 3 2 1 0 — — — IMR12 — — IMR9 IMR8 Initial value : 1 1 1 1 1 1 1 1 Read/Write : — — — R/W — — R/W R/W Mailbox empty interrupt mask 0 Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled 1 Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled Unread interrupt mask 0 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 enabled 1 Unread message overwrite interrupt request (OVR0) to CPU by IRR9 disabled Bus operation interrupt mask 0 Bus operation interrupt request (OVR0) to CPU by IRR12 enabled 1 Bus operation interrupt request (OVR0) to CPU by IRR12 disabled Rev. 5.00 Jan 10, 2006 page 871 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register REC—Receive Error Counter H'F818 HCAN REC Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R TEC—Transmit Error Counter H'F819 HCAN TEC Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R UMSR—Unread Message Status Register H'F81A HCAN UMSR Bit 15 14 13 12 11 10 9 8 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 Bit : : UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Unread message status flags 0 [Clearing condition] Writing 1 1 Unread receive message is overwritten by a new message [Setting condition] When a new message is received before RXPR is cleared Note: * Can only be written with 1 for flag clearing. Rev. 5.00 Jan 10, 2006 page 872 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register LAFML—Local Acceptance Filter Mask LAFMH—Local Acceptance Filter Mask H'F81C H'F81E HCAN HCAN LAFML Bit : 15 14 13 12 11 10 9 8 LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit : LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 — — — LAFMH Bit : LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R R R R/W R/W 7 6 5 4 3 2 1 0 Bit : LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W LAFMH Bits 7 to 0 and 15 to 13—11-bit identifier filter 0 Stored in MC0, MD0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Care) 1 Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (Don’t Care) LAFMH bits 9 and 8, LAFML Bits 15 to 0—18-bit identifier filter 0 Stored in MC0 (receive-only mailbox) depending on bit match between MC0 message identifier and receive message identifier (Care) 1 Stored in MC0 (receive-only mailbox) regardless of bit match between MC0 message identifier and receive message identifier (Don’t Care) Rev. 5.00 Jan 10, 2006 page 873 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC0—Message Control H'F820 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=0 Rev. 5.00 Jan 10, 2006 page 874 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC1—Message Control H'F828 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=1 Rev. 5.00 Jan 10, 2006 page 875 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC2—Message Control H'F830 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=2 Rev. 5.00 Jan 10, 2006 page 876 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC3—Message Control H'F838 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=3 Rev. 5.00 Jan 10, 2006 page 877 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC4—Message Control H'F840 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=4 Rev. 5.00 Jan 10, 2006 page 878 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC5—Message Control H'F848 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=5 Rev. 5.00 Jan 10, 2006 page 879 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC6—Message Control H'F850 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=6 Rev. 5.00 Jan 10, 2006 page 880 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC7—Message Control H'F858 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=7 Rev. 5.00 Jan 10, 2006 page 881 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC8—Message Control H'F860 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=8 Rev. 5.00 Jan 10, 2006 page 882 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC9—Message Control H'F868 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x=9 Rev. 5.00 Jan 10, 2006 page 883 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC10—Message Control H'F870 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 10 Rev. 5.00 Jan 10, 2006 page 884 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC11—Message Control H'F878 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 11 Rev. 5.00 Jan 10, 2006 page 885 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC12—Message Control H'F880 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 12 Rev. 5.00 Jan 10, 2006 page 886 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC13—Message Control H'F888 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 13 Rev. 5.00 Jan 10, 2006 page 887 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC14—Message Control H'F890 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 14 Rev. 5.00 Jan 10, 2006 page 888 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MC15—Message Control H'F898 HCAN MCx[1] Bit : 7 — 6 — 5 — 4 — 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Data length code 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0/1 0/1 0/1 Data length = 0 bytes Data length = 1 byte Data length = 2 bytes Data length = 3 bytes Data length = 4 bytes Data length = 5 bytes Data length = 6 bytes Data length = 7 bytes Data length = 8 bytes MCx[2] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[3] Bit : 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 — Initial value : Read/Write : Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W MCx[4] Bit : 7 — Undefined R/W 6 — Undefined R/W 5 — Undefined R/W 4 — Undefined R/W 3 — Undefined R/W 2 — Undefined R/W 1 — Undefined R/W 0 — Undefined R/W 7 STD_ID2 Undefined R/W 6 STD_ID1 Undefined R/W 5 STD_ID0 Undefined R/W 4 RTR Undefined R/W 3 IDE Undefined R/W 2 — Undefined R/W 1 EXD_ID17 Undefined R/W 0 EXD_ID16 Undefined R/W Initial value : Read/Write : MCx[5] Bit : Initial value : Read/Write : Identifier extension 0 Standard format 1 Extended format Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[6] Bit : Initial value : Read/Write : 7 STD_ID10 Undefined R/W 6 STD_ID9 Undefined R/W Remote transmission request 0 Data frame 1 Remote frame 5 STD_ID8 Undefined R/W 4 STD_ID7 Undefined R/W 3 STD_ID6 Undefined R/W 2 STD_ID5 Undefined R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames 1 STD_ID4 Undefined R/W 0 STD_ID3 Undefined R/W Standard identifier These bits set the identifier (standard identifier) of data frames and remote frames MCx[7] Bit : 7 EXD_ID7 6 EXD_ID6 5 EXD_ID5 4 EXD_ID4 3 EXD_ID3 2 EXD_ID2 1 EXD_ID1 0 EXD_ID0 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit : 7 EXD_ID15 6 EXD_ID14 5 EXD_ID13 4 EXD_ID12 3 EXD_ID11 2 EXD_ID10 1 EXD_ID9 0 EXD_ID8 Initial value : Read/Write : Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Extended identifier These bits set the identifier (extended identifier) of data frames and remote frames x = 15 Rev. 5.00 Jan 10, 2006 page 889 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MD0—Message Data MD1—Message Data MD2—Message Data MD3—Message Data MD4—Message Data MD5—Message Data MD6—Message Data MD7—Message Data MD8—Message Data MD9—Message Data MD10—Message Data MD11—Message Data MD12—Message Data MD13—Message Data MD14—Message Data MD15—Message Data H'F8B0 H'F8B8 H'F8C0 H'F8C8 H'F8D0 H'F8D8 H'F8E0 H'F8E8 H'F8F0 H'F8F8 H'F900 H'F908 H'F910 H'F918 H'F920 H'F928 HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN HCAN MDx [1] Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MDx [2] Bit: Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W MDx [3] Rev. 5.00 Jan 10, 2006 page 890 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MDx [4] Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MDx [5] MDx [6] Bit: Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: * * * * * * * * Read/Write: R/W R/W R/W R/W R/W R/W R/W MDx [7] MDx [8] R/W *: Undefined x = 0 to 15 Rev. 5.00 Jan 10, 2006 page 891 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register DADR2—D/A Data Register 2 DADR3—D/A Data Register 3 Bit H'FDAC H'FDAD D/A2 D/A3 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W DACR23—D/A Control Register 23 Bit : H'FDAE D/A2, 3 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value : 0 0 0 1 1 1 1 1 Read/Write : R/W R/W R/W — — — — — D/A enable DAOE1 DAOE0 0 DAE Description 0 * Disables channel 2, 3 D/A conversion 1 0 Enables channel 2 D/A conversion Disables channel 3 D/A conversion 1 0 1 Enables channel 2, 3 D/A conversion 0 Disables channel 2 D/A conversion Enables channel 3 D/A conversion 1 1 Enables channel 2, 3 D/A conversion * Enables channel 2, 3 D/A conversion *: Don’t care D/A output enable 0 0 Disables analog output DA2 1 Enables channel 2 D/A conversion. Also enables analog output DA2 D/A output enable 1 0 Disables analog output DA3 1 Enables channel 3 D/A conversion. Also enables analog output DA3 Rev. 5.00 Jan 10, 2006 page 892 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCRX—Serial Control Register X Bit : H'FDB4 ROM 7 6 5 4 3 2 1 0 — — — — FLSHE — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Flash memory control register enable 0 Area H'FFFFA8 to H'FFFFAC flash control registers are not selected 1 Area H'FFFFA8 to H'FFFFAC flash control registers are selected Rev. 5.00 Jan 10, 2006 page 893 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SBYCR—Standby Control Register Bit : H'FDE4 Power-Down Modes 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — — Initial value : 0 0 0 0 1 0 0 0 Read/Write : R/W R/W R/W R/W R/W — — — Output port enable 0 In software standby mode, address bus and bus control signals are high-impedance 1 In software standby mode, address bus and bus control signals retain their output state Standby timer select 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 1 0 Standby time = 32768 states 1 Standby time = 65536 states 1 0 0 Standby time = 131072 states 1 Standby time = 262144 states 1 0 Reserved 1 Standby time = 16 states Software standby 0 Transition to sleep mode after execution of SLEEP instruction 1 Transition to software standby mode after execution of SLEEP instruction Rev. 5.00 Jan 10, 2006 page 894 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SYSCR—System Control Register Bit : H'FDE5 MCU 7 6 5 4 3 2 1 0 MACS — INTM1 INTM0 NMIEG — — RAME Initial value : 0 0 0 0 0 0 0 1 Read/Write : R/W — R/W R/W R/W R/W — R/W RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled Note: When the DTC is used, the RAME bit must be set to 1. NMI interrupt input edge select 0 Falling edge 1 Rising edge Interrupt control mode select 0 0 Interrupt control mode 0 1 Setting prohibited 1 0 Interrupt control mode 2 1 Setting prohibited Note: For details, see section 5.4.1 Interrupt Control Modes and Interrupt Operation. Mac saturation 0 Non-saturating calculation for MAC instruction 1 Saturating calculation for MAC instruction Rev. 5.00 Jan 10, 2006 page 895 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCKCR—System Clock Control Register Bit : H'FDE6 Clock Pulse Generator, Power-Down 7 6 5 4 3 2 1 0 PSTOP — — — STCS SCK2 SCK1 SCK0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W — — — R/W R/W R/W R/W Bus master clock select 0 0 0 Bus master is in high-speed mode 1 Medium-speed clock is φ/2 1 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 1 0 1 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 1 — — Frequency multiplication factor switching mode select 0 Specified multiplication factor is valid after transition to software standby mode 1 Specified multiplication factor is valid immediately after STC bits are rewritten φ clock output control High-Speed Mode, Sleep Mode, PSTOP Medium-Speed Mode, Sub-Sleep Mode* Sub-Active Mode* Software Standby Mode, Watch Mode*, Direct Transition* Hardware Standby Mode 0 φ output φ output Fixed high High impedance 1 Fixed high Fixed high Fixed high High impedance Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) and direct transition are not available in the H8S/2623 Group, but are available in the H8S/2626 Group. Rev. 5.00 Jan 10, 2006 page 896 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MDCR—Mode Control Register Bit : H'FDE7 MCU 7 6 5 4 3 2 1 0 — — — — — MDS2 MDS1 MDS0 Initial value : 1 0 0 0 0 —* —* —* Read/Write : R/W — — — — R R R Current mode pin operating mode Note: * Determined by pins MD2 to MD0. Rev. 5.00 Jan 10, 2006 page 897 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register MSTPCRA—Module Stop Control Register MSTPCRB—Module Stop Control Register MSTPCRC—Module Stop Control Register H'FDE8 H'FDE9 H'FDEA Power-Down Modes Power-Down Modes Power-Down Modes MSTPCRA Bit : 7 4 5 6 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : 0 0 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MSTPCRB Bit : MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MSTPCRC Bit : MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Module stop mode specification 0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6) 1 Module stop mode is set (initial value of MSTPA5–0, MSTPB7–0, and MSTPC7–0) MSTP bits and corresponding on-chip supporting modules Register Bit MSTPCRA MSTPA7* — MSTPA6 Data transfer controller (DTC) MSTPCRB MSTPCRC Module MSTPA5 16-bit timer pulse unit (TPU) MSTPA4* — MSTPA3 Programmable pulse generator (PPG) MSTPA2* — MSTPA1 A/D converter MSTPA0* — MSTPB7 Serial communication interface 0 (SCI0) MSTPB6 Serial communication interface 1 (SCI1) MSTPB5 Serial communication interface 2 (SCI2) MSTPB4* — MSTPB3* — MSTPB2* — MSTPB1* — MSTPB0* — MSTPC7* — MSTPC6* — MSTPC5 D/A converter (channels 2, 3) MSTPC4 PC break controller (PBC) MSTPC3 HCAN MSTPC2* — MSTPC1* — MSTPC0* — Notes: * MSTPA7 is a readable/writable bit with an initial value of 0. MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC4, and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. Rev. 5.00 Jan 10, 2006 page 898 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PFCR—Pin Function Control Register Bit : H'FDEB 7 6 5 4 3 MCU, Bus Controller 2 1 0 — — BUZZE — AE3 AE2 AE1 AE0 Initial value : 0 0 0*2 0 1/0*1 1/0*1 0 1/0*1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Address output enable 0 0 0 0 A8–A23 address output disabled 1 A8 address output enabled; A9–A23 address output disabled 1 0 A8, A9 address output enabled; A10–A23 address output disabled 1 A8–A10 address output enabled; A11–A23 address output disabled 1 0 0 A8–A11 address output enabled; A12–A23 address output disabled 1 A8–A12 address output enabled; A13–A23 address output disabled 1 0 A8–A13 address output enabled; A14–A23 address output disabled 1 A8–A14 address output enabled; A15–A23 address output disabled 1 0 0 0 A8–A15 address output enabled; A16–A23 address output disabled 1 A8–A16 address output enabled; A17–A23 address output disabled 1 0 A8–A17 address output enabled; A18–A23 address output disabled 1 A8–A18 address output enabled; A19–A23 address output disabled 1 0 0 A8–A19 address output enabled; A20–A23 address output disabled 1 A8–A20 address output enabled; A21–A23 address output disabled 1 0 A8–A21 address output enabled; A22, A23 address output disabled 1 A8–A23 address output enabled BUZZ output enable 0 Functions as PF1 I/O pin 1 Functions as BUZZ output pin Notes: 1. In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000. In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101. Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1. 2. This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be written to this bit. Rev. 5.00 Jan 10, 2006 page 899 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register LPWRCR—Low-Power Control Register Bit : 7 6 5 H'FDEC 4 Clock Pulse Generator 3 2 1 0 DTON LSON — STC1 STC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W NESEL SUBSTP RFCUT Frequency multiplier STC1 0 1 STC0 0 × 1 (initial value) 1 ×2 0 ×4 1 Do not set Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should not exceed the maximum operating frequency defined in section 22, Electrical Characteristics. Oscillator circuit feedback resistor control bit 0 Feedback resistor ON when main clock operating; OFF when not operation 1 Feedback resistor OFF Subclock enable 0 Subclock generation enabled 1 Subclock generation disabled Note: This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be written to this bit. Noise elimination sampling frequency select 0 Sampling uses φ/32 clock 1 Sampling uses φ/4 clock Low-speed ON flag Note: This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be written to this bit. 0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode* • When the SLEEP command is executed in sub-active mode, operation transfers to watch mode, or directly to high-speed mode • Operation transfers to high-speed mode after watch mode is canceled 1 • When the SLEEP command is executed in high-speed mode, operation transfers to watch mode or sub-active mode • When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode • Operation transfers to sub-active mode immediately watch mode is canceled Notes: This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be written to this bit. * Always select high-speed mode when transferring to watch mode or sub-active mode. Direct transfer ON flag 0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep mode, software standby mode, or watch mode* • When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode 1 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers directly to sub-active mode, or transfers to sleep mode or software standby mode • When the SLEEP command is executed in sub-active mode, operation transfers directly to highspeed mode or transfers to sub-sleep mode Notes: This bit is valid only in the H8S/2626 Group; in the H8S/2623 Group, 0 must be written to this bit. * Always select high-speed mode when transferring to watch mode or sub-active mode. Rev. 5.00 Jan 10, 2006 page 900 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BARA—Break Address Register A BARB—Break Address Register B Bit : 31 ... 24 — ... BAA BAA BAA BAA BAA BAA BAA BAA — 23 22 21 20 19 18 17 16 23 Initial value : Unde- ... Unde- 0 fined fined Read/Write : H'FE00 H'FE04 — ... 22 0 21 0 20 0 19 0 18 0 17 0 16 0 — R/W R/W R/W R/W R/W R/W R/W R/W ... ... ... ... PBC PBC 7 6 5 4 3 2 1 0 BAA BAA BAA BAA BAA BAA BAA BAA 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Break address specification Rev. 5.00 Jan 10, 2006 page 901 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BCRA—Break Control Register A BCRB—Break Control Register B Bit : H'FE08 H'FE09 PBC PBC 7 6 CMFA CDA Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/W R/W R/W R/W R/W R/W R/W 5 4 3 2 1 BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 0 BIEA Break interrupt enable 0 PC break interrupts are disabled 1 PC break interrupts are enabled Break condition select 0 0 Instruction fetch is used as break condition 1 0 Data write cycle is used as break condition 1 Data read cycle is used as break condition 1 Data read/write cycle is used as break condition Break address mask register 0 0 0 All BARA bits are unmasked and included in break conditions 1 BAA0 (lowest bit) is masked, and not included in break conditions 1 0 BAA1–0 (lower 2 bits) are masked, and not included in break conditions 1 BAA2–0 (lower 3 bits) are masked, and not included in break conditions 1 0 0 BAA3–0 (lower 4 bits) are masked, and not included in break conditions 1 BAA7–0 (lower 8 bits) are masked, and not included in break conditions 1 0 BAA11–0 (lower 12 bits) are masked, and not included in break conditions 1 BAA15–0 (lower 16 bits) are masked, and not included in break conditions CPU cycle/DTC cycle select A 0 PC break is performed when CPU is bus master 1 PC break is performed when CPU or DTC is bus master Condition match flag 0 [Clearing condition] When 0 is written to CMFA after reading CMFA = 1 1 [Setting condition] When a condition set for channel A is satisfied Notes: The bit configuration of BCRB is the same as that of BCRA, except that BCRB performs break control for channel B. * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 902 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register ISCRH—IRQ Sense Control Register H ISCRL—IRQ Sense Control Register L H'FE12 H'FE13 Interrupt Controller Interrupt Controller ISCRH Bit : 15 14 13 12 10 11 9 8 IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA — — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W IRQ5 and IRQ4 sense control ISCRL Bit : 7 6 5 4 3 2 1 0 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W IRQ3 to IRQ0 sense control IRQnSCB IRQnSCA 0 1 Interrupt Request Generation 0 Low level of IRQn input 1 Falling edge of IRQn input 0 Rising edge of IRQn input 1 Rising and falling edges of IRQn input (n = 5 to 0) Rev. 5.00 Jan 10, 2006 page 903 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register IER—IRQ Enable Register Bit : H'FE14 Interrupt Controller 7 6 5 4 3 2 1 0 — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W IRQn enable 0 IRQn interrupt is disabled 1 IRQn interrupt is enabled (n = 5 to 0) Rev. 5.00 Jan 10, 2006 page 904 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register ISR—IRQ Status Register Bit : H'FE15 Interrupt Controller 7 6 5 4 3 2 1 0 — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* IRQ5 to IRQ0 interrupt request status indication 0 [Clearing conditions] • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high • When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) • When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 1 [Setting conditions] • When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) • When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) • When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) • When a falling or rising edge occurs in IRQn input when bothedge detection is set (IRQnSCB = IRQnSCA = 1) (n = 5 to 0) Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 905 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register DTCER—DTC Enable Register Bit : H'FE16 to H'FE1C DTC 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W DTC activation enable 0 DTC activation by interrupt is disabled [Clearing conditions] • When data transfer ends while the DISEL bit is 1 • When the specified number of transfers are completed 1 DTC activation by interrupt is enabled [Maintenance condition] When the DISEL bit is 0 and the specified number of transfers have not been completed Interrupt Sources and DTCER Bits Register Bit 7 6 5 4 3 2 1 0 DTCERA IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 — — DTCERB — ADI TGI0A TGI0B TGI0C TGI0D TGI1A TGI1B TGI2B TGI3A TGI3B TGI3C TGI3D TGI4A TGI4B DTCERD — — TGI5A TGI5B — — — — DTCERE — — — — RXI0 TXI0 RXI1 TXI1 DTCERF RXI2 TXI2 — — — — — — DTCERG — — RM0 — — — — — DTCERC TGI2A Rev. 5.00 Jan 10, 2006 page 906 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register DTVECR—DTC Vector Register Bit : 7 6 H'FE1F 5 4 3 DTC 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)*1 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 Sets vector number for DTC software activation DTC software activation enable 0 DTC software activation is disabled [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not been completed • When 0 is written after a software-activated data transfer interrupt (SWDTEND) request has been sent to the CPU 1 DTC software activation is enabled [Maintenance conditions] • When data transfer ends while the DISEL bit is 1 • When the specified number of transfers are completed • During data transfer activated by software Notes: 1. Only 1 can be written to the SWDTE bit. 2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. Rev. 5.00 Jan 10, 2006 page 907 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PCR—PPG Output Control Register Bit : 7 6 H'FE26 5 4 3 PPG 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Group 0 compare match select 0 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 1 compare match select 0 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 2 compare match select 0 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Group 3 compare match select 0 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Rev. 5.00 Jan 10, 2006 page 908 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PMR—PPG Output Mode Register Bit : H'FE27 PPG 7 6 5 4 3 2 1 0 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value : 1 1 1 1 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Group 0 non-overlap 0 Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 0 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 1 non-overlap 0 Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 1 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 2 non-overlap 0 Normal operation in pulse output group 2 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 2 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 3 non-overlap 0 Normal operation in pulse output group 3 (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group 3 (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel) Group 0 invert 0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL) 1 Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL) Group 1 invert 0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) 1 Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) Group 2 invert 0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) 1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) Group 3 invert 0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH) 1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH) Rev. 5.00 Jan 10, 2006 page 909 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register NDERH—Next Data Enable Register H Bit : 7 6 5 H'FE28 4 3 PPG 2 1 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 0 NDER8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Next data enable 0 Pulse outputs PO15 to PO8 are disabled (transfer from NDR15–NDR8 to POD15–POD8 is disabled) 1 Pulse outputs PO15 to PO8 are enabled (transfer from NDR15–NDR8 to POD15–POD8 is enabled) NDERL—Next Data Enable Register L Bit : H'FE29 PPG 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Next data enable 0 Pulse outputs PO7 to PO0 are disabled (transfer from NDR7–NDR0 to POD7–POD0 is disabled) 1 Pulse outputs PO7 to PO0 are enabled (transfer from NDR7–NDR0 to POD7–POD0 is enabled) Rev. 5.00 Jan 10, 2006 page 910 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PODRH—Output Data Register H Bit : H'FE2A PPG 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only. PODRL—Output Data Register L Bit : H'FE2B PPG 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * A bit that has been set for pulse output by NDER is read-only. Rev. 5.00 Jan 10, 2006 page 911 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register NDRH—Next Data Register H NDRH—Next Data Register H H'FE2C H'FE2E PPG PPG When pulse output group output triggers are the same H'FE2C Bit : 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — — — — — — — H'FE2E Bit : Initial value : 1 1 1 1 1 1 1 1 Read/Write : — — — — — — — — When pulse output group output triggers are different H'FE2C Bit : 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 — — — — Initial value : 0 0 0 0 1 1 1 1 Read/Write : R/W R/W R/W R/W — — — — 7 6 5 4 3 2 1 0 — — — — NDR11 NDR10 NDR9 NDR8 Initial value : 1 1 1 1 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W H'FE2E Bit : Note: For details see section 11.2.4, Notes on NDR Access. Rev. 5.00 Jan 10, 2006 page 912 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register NDRL—Next Data Register L NDRL—Next Data Register L H'FE2D H'FE2F PPG PPG When pulse output group output triggers are the same H'FE2D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — — — — — — — H'FE2F Bit : Initial value : 1 1 1 1 1 1 1 1 Read/Write : — — — — — — — — When pulse output group output triggers are different H'FE2D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 — — — — Initial value : 0 0 0 0 1 1 1 1 Read/Write : R/W R/W R/W R/W — — — — 7 6 5 4 3 2 1 0 — — — — NDR3 NDR2 NDR1 NDR0 Initial value : 1 1 1 1 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W H'FE2F Bit : Note: For details see section 11.2.4, Notes on NDR Access. Rev. 5.00 Jan 10, 2006 page 913 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register P1DDR—Port 1 Data Direction Register Bit : 7 6 H'FE30 5 4 3 PPG 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Bit-by-bit specification of input or output for port 1 pins PADDR—Port A Data Direction Register Bit : Initial value : Read/Write : 7 6 — — — Port A 5 4 3 2 1 0 * * PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Undefined Undefined — H'FE39 0 0 0 0 0 0 W W W W W W Specification of input or output for port A pins Note: * Reserved bits in the H8S/2626 Group. PBDDR—Port B Data Direction Register Bit : 7 6 5 H'FE3A 4 3 Port B 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specification of input or output for port B pins Rev. 5.00 Jan 10, 2006 page 914 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PCDDR—Port C Data Direction Register Bit : 7 6 5 H'FE3B 4 3 Port C 2 1 0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specification of input or output for port C pins PDDDR—Port D Data Direction Register Bit : 7 6 5 H'FE3C 4 3 Port D 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specification of input or output for port D pins PEDDR—Port E Data Direction Register Bit : 7 6 5 H'FE3D 4 3 Port E 2 1 0 PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specification of input or output for port E pins Rev. 5.00 Jan 10, 2006 page 915 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PFDDR—Port F Data Direction Register Bit : 7 6 5 H'FE3E 4 3 Port F 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 Initial value : 1 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Mode 7 Specification of input or output for port F pins PAPCR—Port A MOS Pull-Up Control Register Bit : Initial value : Read/Write : 7 6 — — — Port A 5 4 3 2 1 0 * * PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Undefined Undefined — H'FE40 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Bit-by-bit control of port A MOS input pull-ups Note: * Reserved bits in the H8S/2626 Group. PBPCR—Port B MOS Pull-Up Control Register Bit : 7 6 5 4 H'FE41 3 Port B 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit-by-bit control of port B MOS input pull-ups Rev. 5.00 Jan 10, 2006 page 916 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PCPCR—Port C MOS Pull-Up Control Register Bit : 7 6 5 4 H'FE42 3 Port C 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit-by-bit control of port C MOS input pull-ups PDPCR—Port D MOS Pull-Up Control Register Bit : 7 6 5 4 H'FE43 3 Port D 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit-by-bit control of port D MOS input pull-ups PEPCR—Port E MOS Pull-Up Control Register Bit : 7 6 5 4 H'FE44 3 Port E 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit-by-bit control of port E MOS input pull-ups Rev. 5.00 Jan 10, 2006 page 917 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PAODR—Port A Open Drain Control Register Bit : Initial value : Read/Write : 7 6 — — Port A 5 4 3 2 1 0 * * PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Undefined Undefined — H'FE47 — 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W PMOS on/off control for port A pins (PA5 to PA0) Note: * Reserved bits in the H8S/2626 Group. PBODR—Port B Open Drain Control Register Bit : 7 6 5 H'FE48 4 3 Port B 2 1 0 PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W PMOS on/off control for port B pins (PB7 to PB0) PCODR—Port C Open Drain Control Register Bit : 7 6 5 H'FE49 4 3 Port C 2 1 0 PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W PMOS on/off control for port C pins (PC7 to PC0) Rev. 5.00 Jan 10, 2006 page 918 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCR3—Timer Control Register 3 Bit : H'FE80 TPU3 7 6 5 4 3 2 1 0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Timer prescaler 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 1 0 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on φ/1024 1 0 Internal clock: counts on φ/256 1 Internal clock: counts on φ/4096 Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Counter clear 0 0 Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if is φ/1 is selected as the input clock. 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 1 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 1 0 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input capture*2 1 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev. 5.00 Jan 10, 2006 page 919 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TMDR3—Timer Mode Register 3 Bit : H'FE81 TPU3 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Mode 0 0 0 0 Normal operation 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 * * * — *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 3. In this case, 0 should always be written to MD2. Buffer operation setting A 0 TGRA operates normally 1 TGRA and TGRC used together for buffer operation Buffer operation setting B 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation Rev. 5.00 Jan 10, 2006 page 920 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR3H—Timer I/O Control Register 3H Bit : H'FE82 TPU3 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR3A I/O control 0 0 0 1 0 TGR3A is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCA3 pin 1 0 TGR3A is input 1 capture * register Input capture at rising edge * * Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock Input capture at falling edge Input capture at both edges *: Don’t care TGR3B I/O control 0 0 0 1 0 TGR3B is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCB3 pin 1 0 TGR3B is input 1 capture * register Input capture at rising edge * * Capture input Input capture at TCNT4 count-up/ source is channel count-down*1 4/count clock Input capture at falling edge Input capture at both edges *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. Rev. 5.00 Jan 10, 2006 page 921 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR3L—Timer I/O Control Register 3L Bit : H'FE83 TPU3 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TRG3C I/O control 0 0 0 1 0 TGR3C is output 1 compare 0 register Output disabled 0 0 Output disabled 1 1 0 Initial output is 1 output Initial output is 0 output 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCC3 pin 1 0 TGR3C is input 1 capture * register Input capture at rising edge * * Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock Input capture at falling edge Input capture at both edges *: Don’t care TGR3D I/O control 0 0 0 1 0 TGR3D is output 1 compare *2 0 register Output disabled Initial output is 0 output 0 0 Output disabled 1 1 0 Initial output is 1 output 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCD3 pin 1 0 TGR3D is input 1 capture *2 * register Input capture at rising edge * * Capture input Input capture at TCNT4 count-up/ source is channel count-down*1 4/count clock Input capture at falling edge Input capture at both edges *: Don’t care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 5.00 Jan 10, 2006 page 922 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIER3—Timer Interrupt Enable Register 3 Bit : H'FE84 TPU3 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — — R/W R/W R/W R/W R/W TGR interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled TGR interrupt enable C 0 Interrupt requests (TGIC) by TGFC bit disabled 1 Interrupt requests (TGIC) by TGFC bit enabled TGR interrupt enable D 0 Interrupt requests (TGID) by TGFD bit disabled 1 Interrupt requests (TGID) by TGFD bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled Rev. 5.00 Jan 10, 2006 page 923 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TSR3—Timer Status Register 3 Bit : H'FE85 TPU3 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* TGR input capture/output compare flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGR input capture/output compare flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register TGR input capture/output compare flag C 0 [Clearing conditions] • When DTC is activated by TGIC interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFC after reading TGFC = 1 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register TGR input capture/output compare flag D 0 [Clearing conditions] • When DTC is activated by TGID interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 924 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT3—Timer Counter 3 Bit H'FE86 TPU3 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D Bit : Initial value : Read/Write : H'FE88 H'FE8A H'FE8C H'FE8E TPU3 TPU3 TPU3 TPU3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 925 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCR4—Timer Control Register 4 Bit : H'FE90 TPU4 7 6 5 4 3 2 1 0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W Time prescaler 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 1 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 1 0 Internal clock: counts on φ/1024 1 Counts on TCNT5 overflow/underflow Note: This setting is invalid when channel 4 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Note: This setting is invalid when channel 4 is in phase counting mode. This setting is ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected. Counter clear 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 1 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 5.00 Jan 10, 2006 page 926 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TMDR4—Timer Mode Register 4 Bit : H'FE91 TPU4 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 0 Normal operation 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 * * * — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 5.00 Jan 10, 2006 page 927 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR4—Timer I/O Control Register 4 Bit : H'FE92 TPU4 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR4A I/O control 0 0 0 1 0 TGR4A is output 1 compare 0 register Output disabled Initial output is 0 output 0 0 Output disabled 1 1 0 Initial output is 1 output 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCA4 pin 1 0 TGR4A is input 1 capture * register Input capture at rising edge * * Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture Input capture at falling edge Input capture at both edges *: Don’t care TGR4B I/O control 0 0 0 1 0 TGR4B is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCB4 pin 1 0 TGR4B is input 1 capture * register Input capture at rising edge * * Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture Input capture at falling edge Input capture at both edges *: Don’t care Rev. 5.00 Jan 10, 2006 page 928 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIER4—Timer Interrupt Enable Register 4 Bit : H'FE94 TPU4 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGI interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGI interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled Rev. 5.00 Jan 10, 2006 page 929 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TSR4—Timer Status Register 4 Bit : H'FE95 TPU4 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* TGR input capture/output compare flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGR input capture/output compare flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 930 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT4—Timer Counter 4 Bit H'FE96 TPU4 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR4A—Timer General Register 4A TGR4B—Timer General Register 4B Bit H'FE98 H'FE9A TPU4 TPU4 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 931 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCR5—Timer Control Register 5 Bit : H'FEA0 TPU5 7 6 5 4 3 2 1 0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W Time prescaler 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 1 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin input 1 0 Internal clock: counts on φ/256 1 External clock: counts on TCLKD pin input Note: This setting is invalid when channel 5 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Note: This setting is invalid when channel 5 is in phase counting mode, and also when φ/1 is selected as the input clock. Counter clear 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 1 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 5.00 Jan 10, 2006 page 932 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TMDR5—Timer Mode Register 5 Bit : H'FEA1 TPU5 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 0 Normal operation 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 * * * — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 5.00 Jan 10, 2006 page 933 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR5—Timer I/O Control Register 5 Bit : H'FEA2 TPU5 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR5A I/O control 0 0 0 1 0 TGR5A is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 * 0 1 0 TGR5A is input 1 capture * register 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCA5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care TGR5B I/O control 0 0 0 1 0 TGR5B is output 1 compare 0 register Output disabled Initial output is 0 output 0 0 Output disabled 1 1 0 Initial output is 1 output * 0 1 0 TGR5B is input 1 capture * register 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCB5 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care Rev. 5.00 Jan 10, 2006 page 934 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIER5—Timer Interrupt Enable Register 5 Bit : H'FEA4 TPU5 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGI interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGI interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled Rev. 5.00 Jan 10, 2006 page 935 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TSR5—Timer Status Register 5 Bit : H'FEA5 TPU5 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* TGR input capture/output compare flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGR input capture/output compare flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 936 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT5—Timer Counter 5 Bit H'FEA6 TPU5 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR5A—Timer General Register 5A TGR5B—Timer General Register 5B Bit H'FEA8 H'FEAA TPU5 TPU5 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TSTR—Timer Start Register Bit : H'FEB0 TPU 7 6 5 4 3 2 1 0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Counter start 0 TCNTn count operation is stopped 1 TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. Rev. 5.00 Jan 10, 2006 page 937 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TSYR—Timer Sync Register Bit : H'FEB1 TPU 7 6 5 4 3 2 1 0 — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Timer synchronization 0 TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) 1 TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. Rev. 5.00 Jan 10, 2006 page 938 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register IPRA—Interrupt Priority Register A IPRB—Interrupt Priority Register B IPRC—Interrupt Priority Register C IPRD—Interrupt Priority Register D IPRE—Interrupt Priority Register E IPRF—Interrupt Priority Register F IPRG—Interrupt Priority Register G IPRH—Interrupt Priority Register H IPRI—Interrupt Priority Register I IPRJ—Interrupt Priority Register J IPRK—Interrupt Priority Register K IPRM—Interrupt Priority Register M Bit : H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECC Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller 7 6 5 4 3 2 1 0 — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : 0 1 1 1 0 1 1 1 Read/Write : — R/W R/W R/W — R/W R/W R/W Interrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ2 IRQ4 IRQ3 IRQ5 IPRC —*1 DTC IPRD WDT0 —*1 IPRE PC break A/D converter, WDT1*2 IPRF TPU channel 0 TPU channel 1 IPRG TPU channel 2 TPU channel 3 IPRH TPU channel 4 TPU channel 5 IPRI —*1 —*1 IPRJ —*1 SCI channel 0 IPRK SCI channel 1 SCI channel 2 IPRM HCAN —*1 Notes: 1. These bits are reserved. They are always read as 1 and cannot be modified. 2. Valid only in the H8S/2626 Group. Rev. 5.00 Jan 10, 2006 page 939 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register ABWCR—Bus Width Control Register Bit : H'FED0 Bus Controller 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Modes 5 to 7 Mode 4 Area 7 to 0 bus width control 0 Area n is designated for 16-bit access 1 Area n is designated for 8-bit access (n = 7 to 0) ASTCR—Access State Control Register Bit : H'FED1 Bus Controller 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 access state control 0 Area n is designated for 2-state access Wait state insertion in area n external space access is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space access is enabled (n = 7 to 0) Rev. 5.00 Jan 10, 2006 page 940 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register WCRH—Wait Control Register H Bit : H'FED2 Bus Controller 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Area 4 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Area 5 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Area 6 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Area 7 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Rev. 5.00 Jan 10, 2006 page 941 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register WCRL—Wait Control Register L Bit : H'FED3 Bus Controller 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Area 0 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Area 1 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Area 2 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Area 3 wait control 0 0 Program wait not inserted 1 1 program wait state inserted 1 0 2 program wait states inserted 1 3 program wait states inserted Rev. 5.00 Jan 10, 2006 page 942 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BCRH—Bus Control Register H Bit : H'FED4 7 6 ICIS1 ICIS0 Initial value : 1 1 0 1 Read/Write : R/W R/W R/W R/W 5 4 3 Bus Controller 2 1 0 — — — 0 0 0 0 R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 Burst cycle select 0 0 Max. 4 words in burst access 1 Max. 8 words in burst access Burst cycle select 1 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states Area 0 burst ROM enable 0 Basic bus interface 1 Burst ROM interface Idle cycle insert 0 0 Idle cycle not inserted in case of successive external read and external write cycles 1 Idle cycle inserted in case of successive external read and external write cycles Idle cycle insert 1 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas Rev. 5.00 Jan 10, 2006 page 943 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BCRL—Bus Control Register L Bit : H'FED5 Bus Controller 7 6 5 4 3 2 1 0 BRLE BREQOE — — — — WDBE WAITE Initial value : 0 0 0 0 1 0 0 0 Read/Write : R/W R/W — R/W R/W R/W R/W R/W WAIT pin enable 0 Wait input by WAIT pin disabled 1 Wait input by WAIT pin enabled Write data buffer enable 0 Write data buffer function not used 1 Write data buffer function used BREQO pin enable 0 BREQO output disabled 1 BREQO output enabled Bus release enable 0 External bus release disabled 1 External bus release enabled Rev. 5.00 Jan 10, 2006 page 944 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register RAMER—RAM Emulation Register* Bit : 1 H'FEDB ROM 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R/W R/W R/W R/W R/W R/W Flash memory area select RAM select 0 Emulation not selected Program/erase-protection of all flash memory blocks is disabled 1 Emulation selected Program/erase-protection of all flash memory blocks is enabled Flash memory area divisions Addresses Block Name RAMS RAM2 RAM1 RAM0 H'FFD000–H'FFDFFF RAM area 4 kbytes 0 * * * H'000000–H'000FFF EB0 (4 kbytes) 1 0 0 0 H'001000–H'001FFF EB1 (4 kbytes) 1 0 0 1 H'002000–H'002FFF EB2 (4 kbytes) 1 0 1 0 H'003000–H'003FFF EB3 (4 kbytes) 1 0 1 1 H'004000–H'004FFF EB4 (4 kbytes) 1 1 0 0 H'005000–H'005FFF EB5 (4 kbytes) 1 1 0 1 H'006000–H'006FFF EB6 (4 kbytes) 1 1 1 0 H'007000–H'007FFF EB7 (4 kbytes) 1 1 1 1 *: Don't care Note: 1. This register is present only in the F-ZTAT version; it is not provided in the mask ROM version. Rev. 5.00 Jan 10, 2006 page 945 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register P1DR—Port 1 Data Register Bit : H'FF00 Port 1 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port 1 pins (P17 to P10) PADR—Port A Data Register Bit : Initial value : Read/Write : 7 6 — — H'FF09 5 4 3 * * PA5DR PA4DR PA3DR Undefined Undefined — — Port A 2 1 0 PA2DR PA1DR PA0DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Stores output data for port A pins (PA5 to PA0) Note: * Reserved bits in the H8S/2626 Group. PBDR—Port B Data Register Bit : H'FF0A Port B 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port B pins (PB7 to PB0) Rev. 5.00 Jan 10, 2006 page 946 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PCDR—Port C Data Register Bit : H'FF0B Port C 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port C pins (PC7 to PC0) PDDR—Port D Data Register Bit : H'FF0C Port D 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port D pins (PD7 to PD0) PEDR—Port E Data Register Bit : H'FF0D Port E 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port E pins (PE7 to PE0) PFDR—Port F Data Register Bit : H'FF0E Port F 7 6 5 4 3 2 1 0 — PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port F pins (PF6 to PF0) Rev. 5.00 Jan 10, 2006 page 947 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCR0—Timer Control Register 0 Bit : H'FF10 TPU0 7 6 5 4 3 2 1 0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Time prescaler 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 1 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is ignored if is φ/1 is selected as the input clock. Counter clear 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 1 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 1 0 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input capture*2 1 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Rev. 5.00 Jan 10, 2006 page 948 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TMDR0—Timer Mode Register 0 Bit : H'FF11 TPU0 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Mode 0 0 0 0 Normal operation 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 * * * — *: Don’t care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2. Buffer operation setting A 0 TGRA operates normally 1 TGRA and TGRC used together for buffer operation Buffer operation setting B 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation Rev. 5.00 Jan 10, 2006 page 949 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR0H—Timer I/O Control Register 0H Bit : H'FF12 TPU0 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR0A I/O control 0 0 0 1 0 TGR0A is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCA0 pin 1 0 TGR0A is input 1 capture * register Input capture at rising edge * * Capture input Input capture at TCNT1count-up/ source is channel count-down 1/count clock Input capture at falling edge Input capture at both edges *: Don’t care TGR0B I/O control 0 0 0 1 0 TGR0B is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCB0 pin 1 0 TGR0B is input 1 capture * register Input capture at rising edge * * Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock Input capture at falling edge Input capture at both edges *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Rev. 5.00 Jan 10, 2006 page 950 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR0L—Timer I/O Control Register 0L Bit : H'FF13 TPU0 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR0C I/O control 0 0 0 1 0 TGR0C is output 1 compare 0 register Output disabled Initial output is 0 output 0 0 Output disabled 1 1 0 Initial output is 1 output 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCC0 pin 1 0 TGR0C is input 1 capture * register Input capture at rising edge * * Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock Input capture at falling edge Input capture at both edges *: Don’t care TGR0D I/O control 0 0 0 1 0 TGR0D is output 1 compare 0 register Output disabled 0 0 Output disabled 1 1 0 Initial output is 1 output Initial output is 0 output 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCD0 pin 1 0 TGR0D is input 1 capture * register Input capture at rising edge * * Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock Input capture at falling edge Input capture at both edges *: Don’t care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Note: When TGR0C or TGR0D is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Rev. 5.00 Jan 10, 2006 page 951 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIER0—Timer Interrupt Enable Register 0 Bit : H'FF14 TPU0 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — — R/W R/W R/W R/W R/W TGR interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled TGR interrupt enable C 0 Interrupt requests (TGIC) by TGFC bit disabled 1 Interrupt requests (TGIC) by TGFC bit enabled TGR interrupt enable D 0 Interrupt requests (TGID) by TGFD bit disabled 1 Interrupt requests (TGID) by TGFD bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled Rev. 5.00 Jan 10, 2006 page 952 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TSR0—Timer Status Register 0 Bit : H'FF15 TPU0 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* TGRA input capture/output compare flag 0 [Clearing conditions] • When DTC is activated by TGIA interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGRB input capture/output compare flag 0 [Clearing conditions] • When DTC is activated by TGIB interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register TGRC input capture/output compare flag 0 [Clearing conditions] • When DTC is activated by TGIC interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFC after reading TGFC = 1 1 [Setting conditions] • When TCNT = TGRC while TGRC is functioning as output compare register • When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register TGRD input capture/output compare flag 0 [Clearing conditions] • When DTC is activated by TGID interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFD after reading TGFD = 1 1 [Setting conditions] • When TCNT = TGRD while TGRD is functioning as output compare register • When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 953 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT0—Timer Counter 0 Bit H'FF16 TPU0 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A—Timer General Register 0A TGR0B—Timer General Register 0B TGR0C—Timer General Register 0C TGR0D—Timer General Register 0D Bit H'FF18 H'FF1A H'FF1C H'FF1E TPU0 TPU0 TPU0 TPU0 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 954 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCR1—Timer Control Register 1 Bit : H'FF20 TPU1 7 6 5 4 3 2 1 0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W Time prescaler 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 1 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 0 Internal clock: counts on φ/256 1 Counts on TCNT2 overflow/underflow Note: This setting is invalid when channel 1 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Note: This setting is invalid when channel 1 is in phase counting mode, and also when φ/1 or overflow/underflow of another channel is selected as the input clock. Counter clear 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 1 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 5.00 Jan 10, 2006 page 955 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TMDR1—Timer Mode Register 1 Bit : H'FF21 TPU1 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 0 Normal operation 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 * * * — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 5.00 Jan 10, 2006 page 956 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR1—Timer I/O Control Register 1 Bit : H'FF22 TPU1 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR1A I/O control 0 0 0 1 0 TGR1A is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCA1 pin 1 0 TGR1A is input 1 capture * register Input capture at rising edge * * Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture Input capture at falling edge Input capture at both edges *: Don’t care TGR1B I/O control 0 0 0 1 0 TGR1B is output 1 compare 0 register Output disabled Initial output is 0 output 0 1 0 Output disabled 1 Initial output is 1 output 0 0 1 0 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCB1 pin 1 0 TGR1B is input 1 capture * register Input capture at rising edge * * Capture input Input capture at generation of source is TGR0C TGR0C compare match/input compare match/ capture input capture Input capture at falling edge Input capture at both edges *: Don’t care Rev. 5.00 Jan 10, 2006 page 957 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIER1—Timer Interrupt Enable Register 1 Bit : H'FF24 TPU1 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGI interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGI interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled Rev. 5.00 Jan 10, 2006 page 958 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TSR1—Timer Status Register 1 Bit : H'FF25 TPU1 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* TGR input capture/output compare flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGR input capture/output compare flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 959 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT1—Timer Counter 1 Bit H'FF26 TPU1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A—Timer General Register 1A TGR1B—Timer General Register 1B Bit H'FF28 H'FF2A TPU1 TPU1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 960 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCR2—Timer Control Register 2 Bit : H'FF30 TPU2 7 6 5 4 3 2 1 0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W Time prescaler 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 1 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on φ/1024 Note: This setting is invalid when channel 2 is in phase counting mode. Input clock edge select 0 0 Count at rising edge 1 Count at falling edge 1 — Count at both edges Note: This setting is invalid when channel 2 is in phase counting mode, and also when φ/1 is selected as the input clock. Counter clear 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 1 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. Rev. 5.00 Jan 10, 2006 page 961 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TMDR2—Timer Mode Register 2 Bit : H'FF31 TPU2 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 0 Normal operation 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 * * * — *: Don’t care Note: MD3 is a reserved bit. In a write, it should always be written with 0. Rev. 5.00 Jan 10, 2006 page 962 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIOR2—Timer I/O Control Register 2 Bit : H'FF32 TPU2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR2A I/O control 0 0 0 1 0 TGR2A is output 1 compare 0 register Output disabled Initial output is 0 output 0 0 Output disabled 1 1 0 Initial output is 1 output * 0 1 0 TGR2A is input 1 capture * register 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCA2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care TGR2B I/O control 0 0 0 1 0 TGR2B is output 1 compare 0 register Output disabled Initial output is 0 output 0 0 Output disabled 1 1 0 Initial output is 1 output * 0 1 0 TGR2B is input 1 capture * register 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Capture input source is TIOCB2 pin Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don’t care Rev. 5.00 Jan 10, 2006 page 963 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TIER2—Timer Interrupt Enable Register 2 Bit : H'FF34 TPU2 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGI interrupt enable A 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGI interrupt enable B 0 Interrupt requests (TGIB) by TGFB bit disabled 1 Interrupt requests (TGIB) by TGFB bit enabled Overflow interrupt enable 0 Interrupt requests (TCIV) by TCFV disabled 1 Interrupt requests (TCIV) by TCFV enabled Underflow interrupt enable 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled A/D conversion start request enable 0 A/D conversion start request generation disabled 1 A/D conversion start request generation enabled Rev. 5.00 Jan 10, 2006 page 964 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TSR2—Timer Status Register 2 Bit : H'FF35 TPU2 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* TGR input capture/output compare flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFA after reading TGFA = 1 1 [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register • When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register TGR input capture/output compare flag B 0 [Clearing conditions] • When DTC is activated by TGIB interrupt, and DISEL bit in DTC’s MRB is 0 • When 0 is written to TGFB after reading TGFB = 1 1 [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register • When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow flag 0 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) Underflow flag 0 [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) Counter direction flag 0 TCNT counts down 1 TCNT counts up Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 965 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT2—Timer Counter 2 Bit H'FF36 TPU2 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A—Timer General Register 2A TGR2B—Timer General Register 2B Bit H'FF38 H'FF3A TPU2 TPU2 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Jan 10, 2006 page 966 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCSR0—Timer Control/Status Register 0 Bit : H'FF74 (W), H'FF74 (R) WDT0 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 Initial value : 0 0 0 1 1 0 0 0 Read/Write : R/(W)* R/W R/W — — R/W R/W R/W Clock select Clock CKS2 CKS2 CKS2 0 0 1 1 0 1 Overflow Period* (when ø = 20 MHz) 0 φ/2 (Initial value) 25.6 µs 1 φ/64 819.2 µs 0 φ/128 1.6 ms 1 φ/512 6.6 ms 0 φ/2048 26.2 ms 1 φ/8192 104.9 ms 0 φ/32768 419.4 ms 1 φ/131072 1.68 s Note: * The overflow period is the time from when TCNT starts counting up until overflow occurs. Timer enable 0 TCNT is initialized to H'00 and halted 1 TCNT counts Timer mode select 0 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows 1 Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows* Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 12.2.3, Reset Control/Status Register (RSTCSR). Overflow flag 0 [Clearing conditions] When 0 is written to OVF after reading TCSR when OVF = 1 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on register access. * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 967 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT0—Timer Counter 0 Bit H'FF74 (W), H'FF75 (R) WDT : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Note: TCNT is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. RSTCSR—Reset Control/Status Register Bit : H'FF76 (W), H'FF77 (R) WDT 7 6 5 4 3 2 1 0 WOVF RSTE RSTS — — — — — Initial value : 0 0 0 1 1 1 1 1 Read/Write : R/(W)* R/W R/W — — — — — Reset select 0 Power-on reset 1 Setting prohibited Reset enable 0 Internal reset is not performed when TCNT overflows* 1 Internal reset is performed when TCNT overflows Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset. Watchdog overflow flag 0 [Clearing condition] When 0 is written to WOVF after reading TCSR when WOVF = 1 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) in watchdog timer mode Notes: RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 968 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SMR0—Serial Mode Register 0 Bit : H'FF78 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 φ clock 1 φ/4 clock 1 0 φ/16 clock 1 φ/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 1 stop bit Parity mode 1 2 stop bits 0 Even parity*1 1 Odd parity*2 Parity enable Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous mode/synchronous mode select 0 Asynchronous mode 1 Synchronous mode Rev. 5.00 Jan 10, 2006 page 969 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SMR0—Serial Mode Register 0 Bit : H'FF78 Smart Card Interface 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 φ clock 1 φ/4 clock 1 0 φ/16 clock 1 φ/64 clock Basic clock pulse 0 0 32 clock periods 1 64 clock periods 1 Parity mode 0 372 clock periods 1 256 clock periods 0 Even parity*1 1 Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Note: When the smart card interface is used, be sure to make the 1 setting. Block transfer mode 0 Normal smart card interface mode operation • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) 1 Block transfer mode operation • Error signal transmission/detection and automatic data retransmission not performed • TXI interrupt generated by TDRE flag • TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) GSM mode 0 Normal smart card interface mode operation • TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output on/off control only 1 GSM mode smart card interface mode operation • TEND flag generation 11.0 etu after beginning of start bit • High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 5.00 Jan 10, 2006 page 970 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BRR0—Bit Rate Register 0 Bit H'FF79 SCI0, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). Rev. 5.00 Jan 10, 2006 page 971 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCR0—Serial Control Register 0 Bit : H'FF7A SCI0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock enable 0 0 Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output 1 Asynchronous Internal clock/SCK pin functions as mode clock output*1 Synchronous Internal clock/SCK pin functions as mode serial clock output 1 0 Asynchronous External clock/SCK pin functions as clock input*2 mode Synchronous External clock/SCK pin functions as mode serial clock input 1 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). Rev. 5.00 Jan 10, 2006 page 972 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCR0—Serial Control Register 0 Bit : H'FF7A Smart Card Interface 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock enable SCMR SMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 See the SCI specification 0 1 0 0 0 Operates as port I/O pin 1 Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin 0 1 1 1 0 1 Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). Rev. 5.00 Jan 10, 2006 page 973 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TDR0—Transmit Data Register 0 Bit H'FF7B SCI0, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev. 5.00 Jan 10, 2006 page 974 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SSR0—Serial Status Register 0 Bit : H'FF7C SCI0 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 13.2.7, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 975 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SSR0—Serial Status Register 0 Bit : H'FF7C Smart Card Interface 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • Upon reset, and in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is also 0 • When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 • When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 • When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 • When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error signal status 0 [Clearing conditions] • Upon reset, and in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 1 [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 14.2.2, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 976 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register RDR0—Receive Data Register 0 Bit H'FF7D SCI0, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR0—Smart Card Mode Register 0 Bit : H'FF7E SCI0, Smart Card Interface 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev. 5.00 Jan 10, 2006 page 977 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SMR1—Serial Mode Register 1 Bit : H'FF80 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 φ clock 1 φ/4 clock 1 0 φ/16 clock 1 φ/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 1 stop bit Parity mode 1 2 stop bits 0 Even parity*1 1 Odd parity*2 Parity enable Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous mode/synchronous mode select 0 Asynchronous mode 1 Synchronous mode Rev. 5.00 Jan 10, 2006 page 978 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SMR1—Serial Mode Register 1 Bit : H'FF80 Smart Card Interface 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 φ clock 1 φ/4 clock 1 0 φ/16 clock 1 φ/64 clock Basic clock pulse 0 0 32 clock periods 1 64 clock periods 1 0 372 clock periods 1 256 clock periods Parity mode 0 Even parity*1 1 Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Note: When the smart card interface is used, be sure to make the 1 setting. Block transfer mode 0 Normal smart card interface mode operation • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) 1 Block transfer mode operation • Error signal transmission/detection and automatic data retransmission not performed • TXI interrupt generated by TDRE flag • TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) GSM mode 0 Normal smart card interface mode operation • TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output on/off control only 1 GSM mode smart card interface mode operation • TEND flag generation 11.0 etu after beginning of start bit • High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 5.00 Jan 10, 2006 page 979 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BRR1—Bit Rate Register 1 Bit H'FF81 SCI1, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). Rev. 5.00 Jan 10, 2006 page 980 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCR1—Serial Control Register 1 Bit : H'FF82 SCI1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock enable 0 0 Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output 1 Asynchronous Internal clock/SCK pin functions as mode clock output*1 Synchronous Internal clock/SCK pin functions as mode serial clock output 1 0 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input 1 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). Rev. 5.00 Jan 10, 2006 page 981 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCR1—Serial Control Register 1 Bit : H'FF82 Smart Card Interface 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock enable SCMR SMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 See the SCI specification 0 1 0 0 0 Operates as port I/O pin 1 Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin 0 1 1 1 0 1 Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). Rev. 5.00 Jan 10, 2006 page 982 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TDR1—Transmit Data Register 1 Bit H'FF83 SCI1, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev. 5.00 Jan 10, 2006 page 983 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SSR1—Serial Status Register 1 Bit : H'FF84 SCI 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 13.2.7, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 984 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SSR1—Serial Status Register 1 Bit : H'FF84 Smart Card Interface 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • Upon reset, and in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is also 0 • When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 • When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 • When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 • When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error signal status 0 [Clearing conditions] • Upon reset, and in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 1 [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 14.2.2, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 985 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register RDR1—Receive Data Register 1 Bit H'FF85 SCI, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR1—Smart Card Mode Register 1 Bit : H'FF86 SCI, Smart Card Interface 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev. 5.00 Jan 10, 2006 page 986 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SMR2—Serial Mode Register 2 Bit : H'FF88 SCI 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 φ clock 1 φ/4 clock 1 0 φ/16 clock 1 φ/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 1 stop bit Parity mode 1 2 stop bits 0 Even parity*1 1 Odd parity*2 Parity enable Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 8-bit data 1 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous mode/synchronous mode select 0 Asynchronous mode 1 Synchronous mode Rev. 5.00 Jan 10, 2006 page 987 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SMR2—Serial Mode Register 2 Bit : H'FF88 Smart Card Interface 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock select 0 0 φ clock 1 0 φ/16 clock 1 φ/4 clock 1 φ/64 clock Basic clock pulse 0 0 32 clock periods 1 64 clock periods 1 Parity mode 0 Even 0 372 clock periods 1 256 clock periods parity*1 1 Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Note: When the smart card interface is used, be sure to make the 1 setting. Block transfer mode 0 Normal smart card interface mode operation • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode) 1 Block transfer mode operation • Error signal transmission/detection and automatic data retransmission not performed • TXI interrupt generated by TDRE flag • TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode) GSM mode 0 Normal smart card interface mode operation • TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output on/off control only 1 GSM mode smart card interface mode operation • TEND flag generation 11.0 etu after beginning of start bit • High/low fixing control possible in addition to clock output on/off control (set by SCR) Note: etu: Elementary Time Unit (time for transfer of 1 bit) Rev. 5.00 Jan 10, 2006 page 988 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register BRR2—Bit Rate Register 2 Bit H'FF89 SCI, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transmit/receive bit rate Note: For details see section 13.2.8, Bit Rate Register (BRR). Rev. 5.00 Jan 10, 2006 page 989 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCR2—Serial Control Register 2 Bit : H'FF8A SCI 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock enable 0 0 Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output 1 Asynchronous Internal clock/SCK pin functions as mode clock output*1 Synchronous Internal clock/SCK pin functions as mode serial clock output 1 0 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input 1 Asynchronous External clock/SCK pin functions as mode clock input*2 Synchronous External clock/SCK pin functions as mode serial clock input Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). Rev. 5.00 Jan 10, 2006 page 990 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SCR2—Serial Control Register 2 Bit : H'FF8A Smart Card Interface 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock enable SCMR SMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 See the SCI specification 0 1 0 0 1 0 Operates as port I/O pin 1 Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin 0 1 1 0 1 Transmit end interrupt enable 0 Transmit end interrupt (TEI) request disabled 1 Transmit end interrupt (TEI) request enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts disabled [Clearing conditions] • When the MPIE bit is cleared to 0 • When data with MPB = 1 is received 1 Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Receive enable 0 Reception disabled 1 Reception enabled Transmit enable 0 Transmission disabled 1 Transmission enabled Receive interrupt enable 0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit interrupt enable 0 Transmit data empty interrupt (TXI) request disabled 1 Transmit data empty interrupt (TXI) request enabled Note: For details of how to clear interrupt requests, see section 13.2.6, Serial Control Register (SCR). Rev. 5.00 Jan 10, 2006 page 991 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TDR2—Transmit Data Register 2 Bit H'FF8B SCI, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev. 5.00 Jan 10, 2006 page 992 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SSR2—Serial Status Register 2 Bit : H'FF8C SCI 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing error 0 [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 13.2.7, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 993 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register SSR2—Serial Status Register 2 Bit : H'FF8C Smart Card Interface 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When data with a 1 multiprocessor bit is received Transmit end 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • Upon reset, and in standby mode or module stop mode • When the TE bit in SCR is 0 and the ERS bit is also 0 • When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 0 • When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 • When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 • When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) Parity error 0 [Clearing condition] When 0 is written to PER after reading PER = 1 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error signal status 0 [Clearing conditions] • Upon reset, and in standby mode or module stop mode • When 0 is written to ERS after reading ERS = 1 1 [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Overrun error 0 [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive data register full 0 [Clearing conditions] • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Transmit data register empty 0 [Clearing conditions] • When 0 is written to TDRE after reading TDRE = 1 • When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR and data can be written to TDR Notes: For details, see section 14.2.2, Serial Status Register (SSR). * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 994 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register RDR2—Receive Data Register 2 Bit H'FF8D SCI, Smart Card Interface : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR2—Smart Card Mode Register 2 Bit : H'FF8E SCI, Smart Card Interface 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev. 5.00 Jan 10, 2006 page 995 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register ADDRA—A/D Data Register A ADDRB—A/D Data Register B ADDRC—A/D Data Register C ADDRD—A/D Data Register D Bit : 15 14 13 12 H'FF90 H'FF92 H'FF94 H'FF96 11 10 9 8 7 A/D Converter A/D Converter A/D Converter A/D Converter 6 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 5 4 3 2 1 0 — — — — — — Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R R R R R R R R R Analog input channels and corresponding ADDR registers Analog Input Channel Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1) A/D Data Register Group 0 Group 1 Group 0 Group 1 AN0 AN4 AN8 AN12 AN1 AN5 AN9 AN13 ADDRB AN2 AN6 AN10 AN14 ADDRC AN3 AN7 AN11 AN15 ADDRD ADDRA Note: The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details see section 16.3, Interface to Bus Master. Rev. 5.00 Jan 10, 2006 page 996 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register ADCSR—A/D Control/Status Register Bit : H'FF98 A/D Converter 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CH3 CH2 CH1 CH0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W* R/W R/W R/W R/W R/W R/W R/W Channel select CH3 CH2 CH1 CH0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single Mode (SCAN = 0) AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 AN8 AN8, AN9 AN8 to AN10 AN8 to AN11 AN12 AN12, AN13 AN12 to AN14 AN12 to AN15 Channel select 0 AN8 to AN11 are group 0 analog input pins, AN12 to AN15 are group 1 analog input pins 1 AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins Scan mode 0 Single mode 1 Scan mode A/D start 0 A/D conversion stopped 1 • Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends • Scan mode: A/D conversion is started. Conversion continues consecutively on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode A/D interrupt enable 0 A/D conversion end interrupt (ADI) request disabled 1 A/D conversion end interrupt (ADI) request enabled A/D end flag 0 [Clearing conditions] • When 0 is written to ADF after reading ADF = 1 • When the DTC is activated by an ADI interrupt and ADDR is read 1 [Setting conditions] • Single mode: When A/D conversion ends • Scan mode: When A/D conversion ends on all specified channels Note: * Can only be written with 0 for flag clearing. Rev. 5.00 Jan 10, 2006 page 997 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register ADCR—A/D Control Register Bit : H'FF99 A/D Converter 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — CKS1 CKS0 — — Initial value : 0 0 1 1 0 0 1 1 Read/Write : R/W R/W — — R/W R/W — — Clock select 0 0 Conversion time = 530 states (max.) 1 Conversion time = 266 states (max.) 1 0 Conversion time = 134 states (max.) 1 Conversion time = 68 states (max.) Timer trigger select 0 0 A/D conversion start by software is enabled 1 A/D conversion start by TPU conversion start trigger is enabled 1 0 Setting prohibited 1 A/D conversion start by external trigger pin (ADTRG) is enabled Rev. 5.00 Jan 10, 2006 page 998 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCSR1—Timer Control/Status Register 1* Bit 2 H'FFA2 WDT1 7 6 5 4 3 2 1 0 OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)*1 R/W R/W R/W R/W R/W R/W R/W Clock select 2 to 0 PSS CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Overflow cycle* (when φ = 20 MHz) (when φSUB = 32.768 kHz) 0 φ/2 25.6 µs 1 φ/64 819.2 µs 0 φ/128 1.6 ms 1 φ/512 6.6 ms 0 φ/2048 26.2 ms 1 φ/8192 104.9 ms 0 φ/32768 419.4 ms 1 φ/131072 1.68 s 0 φSUB/2 15.6 ms 1 φSUB/4 31.3 ms 0 φSUB/8 62.5 ms 1 φSUB/16 125 ms 0 φSUB/32 250 ms 1 φSUB/64 500 ms 0 φSUB/128 1s 1 φSUB/256 2s Note: * The overflow cycle starts when TCNT starts counting from H'00 and ends when an overflow occurs. Reset or NMI 0 NMI interrupt request 1 Internal reset request Prescaler select 0 TCNT counts the divided clock output by the ø-based prescaler 1 TCNT counts the divided clock output by the øSUB-based prescaler (PSS) Timer enable 0 Initializes TCNT to H’00 and disables the counting operation 1 TCNT performs counting operation Timer mode select 0 Interval timer mode: Interval timer interrupt (WOVI) request sent to CPU when overflow occurs at TCNT 1 Watchdog timer mode: Reset or NMI interrupt request sent to CPU when overflow occurs at TCNT Overflow flag 0 [Clearing] (1) When 0 is written to TME bit; (2) When 0 is written to OVF bit after reading TCSR when OVF=1. 1 [Setting] When TCNT overflows (H'FF→ H'00). When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Notes: TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. 1. Only 0 can be written to these bits (to clear these flags). 2. This register is not available, and must not be accessed, in the H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 999 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register TCNT1—Timer Counter 1* Bit H'FFA2 (W), H'FFA3 (R) WDT1 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Notes: TCNT1 is write-protected by a password to prevent accidental overwriting. For details see section 12.2.5, Notes on Register Access. * This register is not available, and must not be accessed, in the H8S/2623 Group. Rev. 5.00 Jan 10, 2006 page 1000 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register FLMCR1—Flash Memory Control Register 1 Bit : H'FFA8 ROM 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 Initial value : —* 0 0 0 0 0 0 0 Read/Write : R R/W R/W R/W R/W R/W R/W R/W Program 1 0 Program mode cleared 1 Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 Erase 1 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1 Program-verify 1 0 Program-verify mode cleared 1 Transition to program-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 Erase-verify 1 0 Erase-verify mode cleared 1 Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE1 = 1 Program setup bit 1 0 Program setup cleared 1 Program setup [Setting condition] When FWE = 1 and SWE1 = 1 Erase setup bit 1 0 Erase setup cleared 1 Erase setup [Setting condition] When FWE = 1 and SWE1 = 1 Software write enable bit 1 0 Writes disabled 1 Writes enabled [Setting condition] When FWE = 1 Flash write enable bit 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin Notes: 1. This register is not present in the mask ROM version, and an attempt to read it will return an undefined value. 2. To access this register, set the FLSHE bit to 1 in serial control register X (SCRX). Even if FLSHE = 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes to this register are also invalid when the FWE bit in FLMCR1 is not set to 1. Note: * Determined by the state of the FWE pin. Rev. 5.00 Jan 10, 2006 page 1001 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register FLMCR2—Flash Memory Control Register 2 Bit : H'FFA9 ROM 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R — — — — — — — Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 19.8.3, Error Protection Notes: 1. This register is not present in the mask ROM version, and an attempt to read it will return an undefined value. 2. To access this register, set the FLSHE bit to 1 in serial control register X (SCRX). Even if FLSHE = 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes to this register are also invalid when the FWE bit in FLMCR1 is not set to 1. EBR1—Erase Block Register 1 Bit : H'FFAA ROM 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets flash memory erase area block by block Rev. 5.00 Jan 10, 2006 page 1002 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register EBR2—Erase Block Register 2 Bit : H'FFAB ROM 7 6 5 4 3 2 1 0 — — — — EB11 EB10 EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets flash memory erase area block by block Flash memory erase blocks Block (Size) Addresses EB0 (4 kbytes) H'000000–H'000FFF EB1 (4 kbytes) H'001000–H'001FFF EB2 (4 kbytes) H'002000–H'002FFF EB3 (4 kbytes) H'003000–H'003FFF EB4 (4 kbytes) H'004000–H'004FFF EB5 (4 kbytes) H'005000–H'005FFF EB6 (4 kbytes) H'006000–H'006FFF EB7 (4 kbytes) H'007000–H'007FFF EB8 (32 kbytes) H'008000–H'00FFFF EB9 (64 kbytes) H'010000–H'01FFFF EB10 (64 kbytes) H'020000–H'02FFFF EB11 (64 kbytes) H'030000–H'03FFFF Notes: 1. This register is not present in the mask ROM version, and an attempt to read it will return an undefined value. 2. To access this register, set the FLSHE bit to 1 in serial control register X (SCRX). Even if FLSHE = 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return H'00 and writes are invalid. Writes to this register are also invalid when the FWE bit in FLMCR1 is not set to 1. Rev. 5.00 Jan 10, 2006 page 1003 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register FLPWCR—Flash Memory Power Control Register Bit : H'FFAC ROM 7 6 5 4 3 2 1 0 PDWND — — — — — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R R R R R R R Power-down disable 0 Transition to flash memory power-down mode enabled 1 Transition to flash memory power-down mode disabled PORT1—Port 1 Register Bit : H'FFB0 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port 1 pins Note: * Determined by the state of pins P17 to P10. PORT4—Port 4 Register Bit : H'FFB3 Port 4 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port 4 pins Note: * Determined by the state of pins P47 to P40. Rev. 5.00 Jan 10, 2006 page 1004 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PORT9—Port 9 Register Bit : H'FFB8 Port 9 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port 9 pins Note: * Determined by the state of pins P97 to P90. PORTA—Port A Register Bit : 7 — Initial value : Read/Write : H'FFB9 6 5 4 3 2 1 0 — PA5*2 PA4*2 PA3 PA2 PA1 PA0 —*1 —*1 —*1 —*1 —*1 —*1 R R R R R R Undefined Undefined — Port A — State of port A pins Notes: 1. Determined by the state of pins PA5 to PA0. 2. Reserved bits in the H8S/2626 Group. PORTB—Port B Register Bit : H'FFBA Port B 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port B pins Note: * Determined by the state of pins PB7 to PB0. Rev. 5.00 Jan 10, 2006 page 1005 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PORTC—Port C Register Bit : H'FFBB Port C 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port C pins Note: * Determined by the state of pins PC7 to PC0. PORTD—Port D Register Bit : H'FFBC Port D 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port D pins Note: * Determined by the state of pins PD7 to PD0. PORTE—Port E Register Bit : H'FFBD Port E 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port E pins Note: * Determined by the state of pins PE7 to PE0. Rev. 5.00 Jan 10, 2006 page 1006 of 1042 REJ09B0275-0500 Appendix B Internal I/O Register PORTF—Port F Register Bit : H'FFBE Port F 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port F pins Note: * Determined by the state of pins PF7 to PF0. Rev. 5.00 Jan 10, 2006 page 1007 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagrams WDDR1 Reset R Q D P1nDR C P1n * WDR1 Internal address bus R Q D P1nDDR C Internal data bus Reset System controller Address output enable PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: n = 0 or 1 * Priority order: address output > output compare output/PWM output > pulse output > DR output Figure C.1 (a) Port 1 Block Diagram (Pins P10 and P11) Rev. 5.00 Jan 10, 2006 page 1008 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams WDDR1 Reset R Q D P1nDR C P1n * WDR1 From internal address bus Internal address bus R Q D P1nDDR C Internal data bus Reset System controller Address output enable PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Notes: n = 2 or 3 * Priority order: address output > output compare output/PWM output > pulse output > DR output Figure C.1 (b) Port 1 Block Diagram (Pins P12 and P13) Rev. 5.00 Jan 10, 2006 page 1009 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D P14DDR C WDDR1 Reset P14 * R Q D P14DR C WDR1 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Interrupt controller IRQ0 interrupt input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C.1 (c) Port 1 Block Diagram (Pin P14) Rev. 5.00 Jan 10, 2006 page 1010 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D P15DDR C WDDR1 Reset Internal data bus Reset R Q D P15DR C P15 * WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C.1 (d) Port 1 Block Diagram (Pin P15) Rev. 5.00 Jan 10, 2006 page 1011 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D P16DDR C WDDR1 Reset Internal data bus Reset R Q D P16DR C P16 * WDR1 PPG module Pulse output enable Pulse output RDR1 TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input Interrupt controller IRQ1 interrupt input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C.1 (e) Port 1 Block Diagram (Pin P16) Rev. 5.00 Jan 10, 2006 page 1012 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D P17DDR C WDDR1 Reset Internal data bus Reset R Q D P17DR C P17 * WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: * Priority order: output compare output/PWM output > pulse output > DR output Figure C.1 (f) Port 1 Block Diagram (Pin P17) Rev. 5.00 Jan 10, 2006 page 1013 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams Port 4 Block Diagram RPOR4 P4n Internal data bus C.2 A/D converter module Analog input Legend: RPOR4: Read port 4 Note: n = 0 to 7 Figure C.2 Port 4 Block Diagram (Pins P40 to P47) Port 9 Block Diagram RPOR9 P9n Internal data bus C.3 A/D converter module Analog input Legend: RPOR9: Read port 9 Note: n = 0 to 7 Figure C.3 Port 9 Block Diagram (Pins P90 to P97) Rev. 5.00 Jan 10, 2006 page 1014 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams Port A Block Diagrams R Q D PA0PCR C WPCRA RPCRA Internal address bus Reset Internal data bus C.4 Reset R Q D PA0DDR C WDDRA *1 Reset PA0 Modes 4 to 6 Address enable *2 R Q D PA0DR C WDRA Reset R Q D PA0ODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C.4 (a) Port A Block Diagram (Pin PA0) Rev. 5.00 Jan 10, 2006 page 1015 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams WPCRA RPCRA Smart card mode signal TxD output TxD output enable Reset R Q D PA1DDR C WDDRA *1 Reset PA1 Modes 4 to 6 Address enable R Q D PA1DR C WDRA Reset *2 R Q D PA1ODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: 1. Output enable signal 2. Open drain control signal Figure C.4 (b) Port A Block Diagram (Pin PA1) Rev. 5.00 Jan 10, 2006 page 1016 of 1042 REJ09B0275-0500 Internal address bus R Q D PA1PCR C Internal data bus Reset Appendix C I/O Port Block Diagrams WPCRA RPCRA Internal address bus R Q D PA2PCR C Internal data bus Reset RxD input enable SCK output SCK output enable Reset R Q D PA2DDR C WDDRA *1 Reset PA2 Modes 4 to 6 Address enable R Q D PA2DR C WDRA Reset *2 R Q D PA2ODR C WODRA RODRA RDRA RxD input Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR RPORA Notes: 1. Output enable signal 2. Open drain control signal Figure C.4 (c) Port A Block Diagram (Pin PA2) Rev. 5.00 Jan 10, 2006 page 1017 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams WPCRA RPCRA SCK input enable SCK output SCK output enable Reset R Q D PA3DDR C WDDRA *1 Reset PA3 Modes 4 to 6 Address enable R Q D PA3DR C WDRA Reset *2 R Q D PA3ODR C WODRA RODRA RDRA SCK input Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR RPORA Notes: 1. Output enable signal 2. Open drain control signal Figure C.4 (d) Port A Block Diagram (Pin PA3) Rev. 5.00 Jan 10, 2006 page 1018 of 1042 REJ09B0275-0500 Internal address bus R Q D PA3PCR C Internal data bus Reset Appendix C I/O Port Block Diagrams R Q D PAnPCR C WPCRA RPCRA Internal data bus Reset Reset R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C PAn WDRA Reset *2 R Q D PAnODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: n = 4 or 5 In the H8S/2626 Group, PA5 and PA4 are OSC2 and OSC1, respectively. 1. Output enable signal 2. Open drain control signal Figure C.4 (e) Port A Block Diagram (Pins PA4 and PA5) Rev. 5.00 Jan 10, 2006 page 1019 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams C.5 Port B Block Diagram WPCRB RPCRB (Output compare) TPU output TPU output enable Reset R Q D PBnDDR C WDDRB *1 Reset PBn Modes 4 to 6 Address enable R Q D PBnDR C WDRB Reset *2 R Q D PBnODR C WODRB RODRB RDRB TPU input (input capture) Legend: WDDRB: WDRB: WODRB: WPCRB: RDRB: RPORB: RODRB: RPCRB: Write to PBDDR Write to PBDR Write to PBODR Write to PBPCR Read PBDR Read port B Read PBODR Read PBPCR RPORB Notes: n = 0 to 7 1. Output enable signal 2. Open drain control signal Figure C.5 Port B Block Diagram (Pins PB0 to PB7) Rev. 5.00 Jan 10, 2006 page 1020 of 1042 REJ09B0275-0500 Internal address bus R Q D PBnPCR C Internal data bus Reset Appendix C I/O Port Block Diagrams Port C Block Diagrams R Q D PCnPCR C WPCRC RPCRC Internal address bus Reset Internal data bus C.6 Smart card mode signal TxD output TxD output enable Reset R Q D PCnDDR C WDDRC *1 Reset PCn Modes 4 to 6 Address enable R Q D PCnDR C WDRC Reset *2 R Q D PCnODR C WODRC RODRC RDRC RPORC Legend: WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR Notes: n = 0 or 3 1. Output enable signal 2. Open drain control signal Figure C.6 (a) Port C Block Diagram (Pins PC0 and PC3) Rev. 5.00 Jan 10, 2006 page 1021 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams WPCRC RPCRC RxD input enable Reset R Q D PCnDDR C WDDRC *1 Reset PCn Modes 4 to 6 Address enable R Q D PCnDR C WDRA Reset *2 R Q D PCnODR C WODRC RODRC RDRC RxD input Legend: WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR RPORC Notes: n = 1 or 4 1. Output enable signal 2. Open drain control signal Figure C.6 (b) Port C Block Diagram (Pins PC1 and PC4) Rev. 5.00 Jan 10, 2006 page 1022 of 1042 REJ09B0275-0500 Internal address bus R Q D PCnPCR C Internal data bus Reset Appendix C I/O Port Block Diagrams WPCRC RPCRC SCK input enable Internal address bus R Q D PCnPCR C Internal data bus Reset SCK output SCK output enable Reset R Q D PCnDDR C WDDRC *1 Reset PCn Modes 4 to 6 Address enable R Q D PCnDR C WDRC Reset *2 R Q D PCnODR C WODRC RODRC RDRC IRQ interrupt input SCK input Legend: WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR RPORC Notes: n = 2 or 5 1. Output enable signal 2. Open drain control signal Figure C.6 (c) Port C Block Diagram (Pins PC2 and PC5) Rev. 5.00 Jan 10, 2006 page 1023 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams WPCRC RPCRC PWM output PWM output enable Reset R Q D PCnDDR C WDDRA *1 Reset Modes 4 to 6 PCn Mode 6 R Q D PCnDR C WDRA Reset *2 R Q D PCnODR C WODRC RODRC RDRC RPORC Legend: WDDRC: WDRC: WODRC: WPCRC: RDRC: RPORC: RODRC: RPCRC: Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port C Read PCODR Read PCPCR Notes: n = 6 or 7 1. Output enable signal 2. Open drain control signal Figure C.6 (d) Port C Block Diagram (Pins PC6 and PC7) Rev. 5.00 Jan 10, 2006 page 1024 of 1042 REJ09B0275-0500 Internal address bus R Q D PCnPCR C Internal data bus Reset Appendix C I/O Port Block Diagrams Port D Block Diagram Reset R Q D PDnPCR C WPCRD RPCRD Internal upper data bus C.7 Reset R Q D PDnDDR C External address write WDDRD Reset R Q D PDnDR C Mode 7 Modes 4 to 6 PDn WDRD External address upper write RDRD RPORD External address upper read Legend: WDDRD: WDRD: WPCRD: RDRD: RPORD: RPCRD: Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR Note: n = 0 to 7 Figure C.7 Port D Block Diagram (Pins PD0 to PD7) Rev. 5.00 Jan 10, 2006 page 1025 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams C.8 Port E Block Diagram WPCRE RPCRE Reset External address write R Q D PEnDDR C WDDRE Reset Mode 7 Modes 4 to 6 PEn R Q D PEnDR C WDRE RDRE RPORE External address lower read Legend: WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Note: n = 0 to 7 Figure C.8 Port E Block Diagram (Pins PE0 to PE7) Rev. 5.00 Jan 10, 2006 page 1026 of 1042 REJ09B0275-0500 Internal lower data bus R Q D PEnPCR C Internal upper data bus Reset Appendix C I/O Port Block Diagrams Port F Block Diagrams Reset R Q D PF0DDR C Internal data bus C.9 WDDRF Bus controller Modes 4 to 6 BRLE bit Reset R Q D PF0DR C PF0 WDRF RDRF RPORF Bus request input Legend: WDDRF: WDRF: RDRF: RPORF: IRQ interrupt input Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (a) Port F Block Diagram (Pin PF0) Rev. 5.00 Jan 10, 2006 page 1027 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D PF1DDR C WDDRF Reset Internal data bus Reset R Q D PF1DR C PF1 WDRF Modes 4 to 6 Bus controller BRLE output Bus request input acknowledge output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (b) Port F Block Diagram in the H8S/2623 Group (Pin PF1) Rev. 5.00 Jan 10, 2006 page 1028 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams BUZZ output BUZZ output enable R Q D PF1DDR C WDDRF Reset Internal data bus Reset R Q D PF1DR C PF1 WDRF Modes 4 to 6 Bus controller BRLE output Bus request input acknowledge output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (c) Port F Block Diagram in the H8S/2626 Group (Pin PF1) Rev. 5.00 Jan 10, 2006 page 1029 of 1042 REJ09B0275-0500 Reset R Q D PF2DDR C WDDRF Reset Modes 4 to 6 PF2 Modes 4 to 6 Internal data bus Appendix C I/O Port Block Diagrams Bus controller Wait enable R Q D PF2DR C WDRF Modes 4 to 6 Bus request output enable Bus request output RDRF RPORF Wait input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (d) Port F Block Diagram (Pin PF2) Rev. 5.00 Jan 10, 2006 page 1030 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D PF3DDR C WDDRF Reset PF3 Modes 4 to 6 Internal data bus Reset R Q D PF3DR C WDRF Bus controller LWR output RDRF RPORF ADTRG input Legend: WDDRF: WDRF: RDRF: RPORF: IRQ interrupt input Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (e) Port F Block Diagram (Pin PF3) Rev. 5.00 Jan 10, 2006 page 1031 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D PF4DDR C WDDRF Reset PF4 Modes 4 to 6 Internal data bus Reset R Q D PF4DR C WDRF Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (f) Port F Block Diagram (Pin PF4) Rev. 5.00 Jan 10, 2006 page 1032 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D PF5DDR C WDDRF Reset PF5 Modes 4 to 6 R Q D PF5DR C Internal data bus Reset WDRF Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (g) Port F Block Diagram (Pin PF5) Rev. 5.00 Jan 10, 2006 page 1033 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams R Q D PF6DDR C WDDRF Reset PF6 Modes 4 to 6 R Q D PF6DR C Internal data bus Reset WDRF Bus controller AS output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.9 (h) Port F Block Diagram (Pin PF6) Rev. 5.00 Jan 10, 2006 page 1034 of 1042 REJ09B0275-0500 Appendix C I/O Port Block Diagrams Modes 4 to 6 Reset R Q D D PF7DDR C WDDRF Internal data bus S* PF7 φ RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Note: * Set priority Figure C.9 (i) Port F Block Diagram (Pin PF7) Rev. 5.00 Jan 10, 2006 page 1035 of 1042 REJ09B0275-0500 Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Table D.1 I/O Port States in Each Processing State Port Name Pin Name MCU Operating Mode PowerOn Reset Hardware Standby Mode Port 1 4, 5 L T 6 T Software Standby Mode Bus Release State Program Execution State Sleep Mode [Address output, OPE = 0] T [Address output] T [Address output] A23 to A20 [Address output, OPE = 1] kept [Otherwise] kept [Otherwise] I/O port [Otherwise] kept 7 T T kept kept I/O port Port 4 4 to 7 T T T T Input port Port 9 4 to 7 T T T T Input port PA5 4 to 7 T T kept kept I/O port 4, 5 L T [Address output, OPE = 0] T [Address output] T [Address output] A19 to A17 6 T [Address output, OPE = 1] kept [Otherwise] kept [Otherwise] I/O port PA4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 [Otherwise] kept Port B 7 T T kept kept I/O port 4, 5 L T [Address output, OPE = 0] T [Address output] T [Address output] A15 to A8 6 T [Address output, OPE = 1] kept [Otherwise] kept [Otherwise] I/O port kept I/O port [Otherwise] kept 7 T T Rev. 5.00 Jan 10, 2006 page 1036 of 1042 REJ09B0275-0500 kept Appendix D Pin States Port Name Pin Name MCU Operating Mode PowerOn Reset Port C 4, 5 L Hardware Standby Mode T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0] T T A7 to A0 T [DDR = 1] A7 to A0 [OPE = 1] kept 6 T T [DDR = 1, OPE = 0] T [DDR = 0] I/O port [DDR = 1, OPE = 1] kept [DDR = 0] kept 7 T T kept kept I/O port Port D 4 to 6 T T T T Data bus 7 T T kept kept I/O port Port E 4 to 6 8-bit bus T T kept kept I/O port 16-bit T bus T T T Data bus 7 T T kept kept I/O port 4 to 6 Clock output T [DDR = 0] T kept [DDR = 0] T 7 T 4 to 6 H PF7/φ PF6/AS [DDR = 1] H T [OPE = 0] T [DDR = 1] Clock output T AS [OPE = 1] H PF5/RD 7 T T kept kept I/O port 4 to 6 H T [OPE = 0] T T RD, HWR, LWR kept I/O port PF4/HWR PF3/LWR/ ADTRG/ IRQ3 [OPE = 1] H 7 T T kept Rev. 5.00 Jan 10, 2006 page 1037 of 1042 REJ09B0275-0500 Appendix D Pin States Port Name Pin Name PF2/WAIT/ BREQO PF1/BACK PF0/BREQ/ IRQ2 MCU Operating Mode PowerOn Reset 4 to 6 T 7 T 4 to 6 T Hardware Standby Mode T T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0] T [BREQOE = 1] BREQO [BREQOE = 1] BREQO [OPE = 1] kept [WAITE = 1] T [WAITE = 1] WAIT kept kept I/O port [BRLE = 0] I/O port [BRLE = 0] I/O port [BRLE = 0] I/O port [BRLE = 1] H [BRLE = 1] L [BRLE = 1] BACK 7 T T kept kept I/O port 4 to 6 T T [BRLE = 0] kept T [BRLE = 0] I/O port [BRLE = 1] T [BRLE = 1] BREQ 7 T T kept kept I/O port HTxD 4 to 7 H T H H Output HRxD 4 to 7 Input T T Input Input Legend: H L T kept DDR OPE WAITE BRLE BREQOE : High level : Low level : High impedance : Input port becomes high-impedance, output port retains state : Data direction register : Output port enable : Wait input enable : Bus release enable : BREQO pin enable Rev. 5.00 Jan 10, 2006 page 1038 of 1042 REJ09B0275-0500 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY t1 ≥ 10tcyc t2 ≥ 0ns RES Figure E.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t ≥ 100ns RES tOSC tNMIRH NMI Figure E.2 Timing of Recovery from Hardware Standby Mode Rev. 5.00 Jan 10, 2006 page 1039 of 1042 REJ09B0275-0500 Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.1 H8S/2626 Group and H8S/2623 Group Product Code Lineup Product Type Product Code Mark Code Package (Package Code) H8S/2626 F-ZTAT version HD64F2626 HD64F2626FA 100-pin QFP (FP-100B) Mask ROM version HD6432626 HD6432626FA 100-pin QFP (FP-100B) H8S/2625 HD6432625 HD6432625FA 100-pin QFP (FP-100B) H8S/2624 HD6432624 HD6432624FA 100-pin QFP (FP-100B) F-ZTAT version HD64F2623 HD64F2623FA 100-pin QFP (FP-100B) Mask ROM version H8S/2623 HD6432623 HD6432623FA 100-pin QFP (FP-100B) H8S/2622 HD6432622 HD6432622FA 100-pin QFP (FP-100B) H8S/2621 HD6432621 HD6432621FA 100-pin QFP (FP-100B) Rev. 5.00 Jan 10, 2006 page 1040 of 1042 REJ09B0275-0500 Appendix G Package Dimensions Appendix G Package Dimensions Figure G.1 shows the FP-100B package dimensions of the H8S/2626 Group and H8S/2623 Group. JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g HD *1 D 75 51 76 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 50 bp c c1 HE *2 E b1 ZE Terminal cross section 26 100 1 25 c F A2 A ZD θ A1 L L1 Detail F e *3 y bp x M Reference Dimension in Millimeters Symbol Min D E A2 HD HE A A1 bp b1 c c1 θ e x y ZD ZE L L1 Nom Max 14 14 2.70 15.7 16.0 16.3 15.7 16.0 16.3 3.05 0.00 0.12 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0° 8° 0.5 0.08 0.10 1.0 1.0 0.3 0.5 0.7 1.0 Figure G.1 FP-100B Package Dimensions Rev. 5.00 Jan 10, 2006 page 1041 of 1042 REJ09B0275-0500 Appendix G Package Dimensions Rev. 5.00 Jan 10, 2006 page 1042 of 1042 REJ09B0275-0500 Renesas 16Bit Single-Chip Microcomputer Hardware Manual H8S/2626 Group, H8S/2623 Group, H8S/2626F-ZTAT , H8S/2623F-ZTAT  Publication Date: 1st Edition, December 1998 Rev.5.00, January 10, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. 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