DATASHEET
EL4585
FN7175
Rev 4.00
September 3, 2009
Horizontal Genlock, 8FSC
The EL4585 is a PLL (Phase Lock Loop) sub-system,
designed for video applications and also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS-compatible pixel clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 sync separator. An
input signal to “coast” is provided for applications where
periodic disturbances are present in the reference video
timing such as VTR head switching. The lock detector output
indicates correct lock.
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards by external
selection of three control pins. These four ratios have been
selected for common video applications including 8FSC,
6FSC, 27MHz (CCIR 601 format) and square picture
elements used in some workstation graphics. To generate
4FSC, 3FSC, 13.5MHz (CCIR 601 format) etc., use the
EL4584, which does not have the additional divide-by-two
stage of the EL4585.
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
6FSC
(Note 1)
Divisor (Note 4)
PAL FOSC (MHz)
Divisor (Note 4)
NTSC FOSC (MHz)
CCIR 601 SQUARE
(Note 2) (Note 3)
• 36MHz, general purpose PLL
• 8FSC timing (use the EL4584 for 4FSC)
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
• User-controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed popular TV scan rate clock divisors
• Single 5V, low current operation
• Pb-Free Available (RoHS Compliant)
Applications
• Pixel clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing
Ordering Information
PART
NUMBER
FREQUENCIES AND DIVISORS
FUNCTION
Features
8FSC
PART
MARKING
PKG.
DWG. #
PACKAGE
EL4585CN
EL4585CN
16 Ld PDIP
E16.3
EL4585CS
EL4585CS
16 Ld SOIC
MDP0027
1702
1728
1888
2270
EL4585CS-T7*
EL4585CS
16 Ld SOIC
MDP0027
26.602
27.0
29.5
35.468
EL4585CS-T13*
EL4585CS
16 Ld SOIC
MDP0027
EL4585CSZ
(Note 5)
EL4585CSZ
16 Ld SOIC
(Pb-free)
MDP0027
EL4585CSZ-T7*
(Note 5)
EL4585CSZ
16 Ld SOIC
(Pb-free)
MDP0027
EL4585CSZ-T13*
(Note 5)
EL4585CSZ
16 Ld SOIC
(Pb-free)
MDP0027
1364
1716
1560
1820
21.476
27.0
24.546
28.636
NOTES:
1. 6FSC frequencies do not yield integer divisors.
2. CCIR 601 divisors yield 1440 pixels in the active portion of each
line for NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL.
4. Divisor does not include ÷ 2 block.
*Please refer to TB347 for details on reel specifications.
NOTES:
5. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet
or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. For 3FSC and 4FSC clock frequency operation, see EL4584
datasheet.
Demo Board
A demo PCB is available for this product.
FN7175 Rev 4.00
September 3, 2009
Page 1 of 15
EL4585
Pinout
EL4585
(16 LD SOIC, PDIP)
TOP VIEW
PROG B 1
16 PROG A
PROG C 2
15 CLK OUT
OSC/VCO OUT 3
14 VSS (D)
VDD (A) 4
13 EXT DIV
OSC/VCO IN 5
VSS (A) 6
CHARGE PUMP OUT 7
DIV SELECT 8
FN7175 Rev 4.00
September 3, 2009
12 LOCK DET
11 VDD (D)
10 HSYNC IN
9 COAST
Page 2 of 15
EL4585
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V
Thermal Resistance (Typical, Note 7)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
JA (°C/W)
16 Lead PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36MHz
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
VDD = 5V, TA = +25°C unless otherwise noted.
PARAMETER
IDD
CONDITIONS
MIN
VDD = 5V (Note 8)
TYP
MAX
UNIT
2
4
mA
1.5
V
VIL Input Low Voltage
VIH Input High Voltage
3.5
V
-100
nA
IIL Input Low Current
All inputs except COAST, VIN = 1.5V
IIH Input High Current
All inputs except COAST, VIN = 3.5V
IIL Input Low Current
COAST pin, VIN = 1.5V
IIH Input High Current
COAST pin, VIN = 3.5V
VOL Output Low Voltage
Lock Det, IOL = 1.6mA
VOH Output High Voltage
Lock Det, IOH = -1.6mA
VOL Output Low Voltage
CLK, IOL = 3.2mA
VOH Output High Voltage
CLK, IOH = -3.2mA
VOL Output Low Voltage
OSC Out, IOL = 200µA
VOH Output High Voltage
OSC Out, IOH = -200µA
2.4
IOL Output Low Current
Filter Out, VOUT = 2.5V
200
IOH Output High Current
Filter Out, VOUT = 2.5V
IOL/IOH Current Ratio
Filter Out, VOUT = 2.5V
ILEAK Filter Out
Coast Mode, VDD > VOUT > 0V
100
-100
-60
60
nA
µA
100
µA
0.4
V
2.4
V
0.4
2.4
V
V
0.4
V
V
300
µA
-300
-200
µA
1.05
1.0
0.95
-100
±1
100
nA
MIN
TYP
MAX
UNIT
NOTE:
8. All inputs to 0V, COAST floating.
AC Electrical Specifications
VDD = 5V, TA = +25°C unless otherwise noted
PARAMETER
CONDITIONS
VCO Gain @ 20MHz
Test circuit 1
15.5
HSYNC S/N Ratio
VDD = 5V (Note 9)
Jitter
VCXO oscillator
1
ns
Jitter
LC oscillator (Typ)
10
ns
35
dB
dB
NOTE:
9. Noisy video signal input to EL4583, HSYNC input to EL4585. Test for positive signal lock.
FN7175 Rev 4.00
September 3, 2009
Page 3 of 15
EL4585
Pin Descriptions
Pin NUMBER
PIN NAME
FUNCTION
1, 2, 16
PROG B, C, A
3
OSC/VCO OUT
4
VDD (A)
5
OSC/VCO IN
6
VSS (A)
7
CHARGE PUMP
OUT
Connect to loop filter. If the HSYNC phase is leading or HSYNC frequency > CLK ÷ 2N, current is pumped
into the filter capacitor to increase VCO frequency. If HSYNC phase is lagging or frequency < CLK ÷ 2N,
current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when
locked, charge pump goes to a high impedance state.
8
DIV SELECT
Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting
CLK ÷ 2N. When low, the internal divider is disabled and EXT DIV is an input from an external ÷N.
9
COAST
10
HSYNC IN
11
VDD (D)
12
LOCK DET
13
EXT DIV
External divide input when DIV SEL is low, internal ÷ 2N output when DIV SEL is high.
14
VSS (D)
Ground for digital, I/O circuits.
15
CLK OUT
Digital inputs to select ÷ N value for internal counter. See Table 1 for values.
Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
Analog positive supply for oscillator, PLL circuits.
Input from external VCO.
Analog ground for oscillator, PLL circuits.
Three-state logic input. Low (< 1/3*VCC) = normal mode, Hi Z (or 1/3 to 2/3*VCC) = fast lock mode,
High (> 2/3*VCC) = coast mode.
Horizontal sync pulse (CMOS level) input.
Positive supply for digital, I/O circuits.
Lock detect output. Low level when PLL is locked. Pulses high when out of lock.
Buffered output of the VCO.
TABLE 1. VCO DIVISORS
PROG A (PIN 16)
PROG B (PIN 1)
PROG C (PIN 2)
DIV VALUE (N)
0
0
0
1702
0
0
1
1728
0
1
0
1888
0
1
1
2270
1
0
0
1364
1
0
1
1716
1
1
0
1560
1
1
1
1820
FN7175 Rev 4.00
September 3, 2009
Page 4 of 15
EL4585
Timing Diagrams
~200ns ± 50ns
H-SYNC
(INPUT)
EXT. DIV.
(INPUT OR
OUTPUT)
PLL LOCKED CONDITION (PHASE ERROR = 0)
~200ns
HSYNC
tH
t0
EXT. DIV
-
E = ttH 360°
tH = HSYNC PERIOD
t = PHASE ERROR PERIOD
+
+
CHARGE
PUMP
-OFF
OFF
OUT OF LOCK CONDITION
Test Circuit
+
VOUT
300k
3
VIN
0.1µF
5
10mVRMS
TEST CIRCUIT 1
FN7175 Rev 4.00
September 3, 2009
Page 5 of 15
EL4585
Typical Performance Curves
FIGURE 1. IDDvs FOSC
FIGURE 2. OSC GAIN @ 20MHz vs TEMP
FIGURE 3. TYPICAL VARACTOR
FIGURE 4. OSC GAIN vs FOSC
FIGURE 5. CHARGE PUMP DUTY CYCLE vs E
FN7175 Rev 4.00
September 3, 2009
Page 6 of 15
EL4585
Typical Performance Curves (Continued)
1.8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
2.0
1.8
1.4
POWER DISSIPATION (W)
1.6
POWER DISSIPATION (W)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.23W
1.2
PDIP16
JA = +81°C/W
1.0 0.91W
0.8
0.6
SO16 (0.150”)
JA = +110°C/W
0.4
0.2
1.6
1.43W
1.4
1.25W
1.2
PDIP16
JA = +70°C/W
1.0
0.8
SO16 (0.150”)
JA = +80°C/W
0.6
0.4
0.2
0
0
0
25
50
75 85 100
125
150
0
AMBIENT TEMPERATURE (°C)
FIGURE 6. POWER DISSIPATION vs AMBIENT
TEMPERATURE
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 7. POWER DISSIPATION vs AMBIENT
TEMPERATURE
EL4585 Block Diagram
Description Of Operation
The horizontal sync signal (CMOS level, falling leading edge)
is input to HSYNC input (pin 10). This signal is delayed about
200ns, the falling edge of which becomes the reference to
which the clock output will be locked (See “Timing Diagrams”
on page 5). The clock is generated by the signal on pin 5,
OSC IN. There are 2 general types of VCO that can be used
with the EL4585, LC and crystal controlled. Additionally,
each type can be either built up using discrete components,
including a varactor as the frequency controlling element, or
complete, self contained modules can be purchased with
everything inside a metal can. These modules are very
forgiving of PCB layout, but cost more than discrete
solutions. The VCO or VCXO is used to regulate the clock.
An LC tank resonator has greater “pull” than a crystal
controlled circuit, but will also be more likely to drift over
time, and thus will generate more jitter. The “pullability” of the
circuit refers to the ability to pull the frequency of oscillation
away from its center frequency by modulating the voltage on
the control pin of the VCO module or varactor, and is a
function of the slope and range of the capacitance-voltage
curve of the varactor or VCO module used. The VCO signal
FN7175 Rev 4.00
September 3, 2009
is sent to the CLK out pin, divided by two, then sent to the
divide by N counter. The divisor N is determined by the state
of pins 1, 2, and 16 and is described in Table 1. The divided
signal is sent, along with the delayed HSYNC input, to the
phase/frequency detector, which compares the two signals
for phase and frequency differences. Any phase difference is
converted to a current at the charge pump output, (pin 7). A
VCO with a positive frequency deviation with control voltage
must be used. Varactors have negative capacitance slope
with voltage, resulting in positive frequency deviation with
increasing control voltage for the oscillators in Figures 10
and 11.
VCO
The VCO should be tuned so that its frequency of oscillation
is very close to the required clock output frequency when the
voltage on the varactor is 2.5V. VCXO and VCO modules are
already tuned to the desired frequency, so this step is not
necessary if using one of these units. The output range of
the charge pump output (pin 7) is 0V to 5V, and it can source
or sink a maximum of about 300µA, so all frequency control
must be accomplished with variable capacitance from the
Page 7 of 15
EL4585
varactor within this range. Crystal oscillators are more stable
than LC oscillators, which translates into lower jitter, but LC
oscillators can be pulled from their mid-point values further,
resulting in a greater capture and locking range. If the
incoming horizontal sync signal is known to be very stable,
then a crystal oscillator circuit can be used. If the HSYNC
signal experiences frequency variations of greater than
about 300ppm, an LC oscillator should be considered, as
crystal oscillators are very difficult to pull this far. When
HSYNC input frequency is greater than CLK frequency ÷ 2N,
charge pump output (pin 7) sources current into the filter
capacitor, increasing the voltage across the varactor, thus
tending to increase VCO frequency. Conversely, charge
pump output pulls current from the filter capacitor when
HSYNC frequency is less than CLK ÷ 2N, forcing the VCO
frequency lower.
Loop Filter
The loop filter controls how fast the VCO will respond to a
change in phase comparator output stimulus. Its
components should be chosen so that fast lock can be
achieved, yet with a minimum of VCO “hunting”, preferably in
one to two oscillations of charge pump output, assuming the
VCO frequency starts within capture range. If the filter is
under-damped, the VCO will over and under-shoot the
desired operating point many times before a stable lock
takes place. It is possible to under-damp the filter so much
that the loop itself oscillates, and VCO lock is never
achieved. If the filter is over-damped, the VCO response
time will be excessive and many cycles will be required for a
lock condition. Over-damping is also characterized by an
easily unlocked system because the filter can’t respond fast
enough to perturbations in VCO frequency. A severely over
damped system will seem to endlessly oscillate, like a very
large mass at the end of a long pendulum. Due to parasitic
effects of PCB traces and component variables, it will take
some trial and error experimentation to determine the best
values to use for any given situation. Use the component
tables as a starting point, but be aware that deviations from
these values are not out of the ordinary.
External Divide
DIV SEL (pin 8) controls the use of the internal divider. When
high, the internal divider is enabled and EXT DIV (pin 13)
outputs the CLK out divided by 2N. This is the signal to
which the horizontal sync input will lock. When divide select
is low, the internal divider output is disabled, and external
divide becomes an input from an external divider, so that a
divisor other than one of the 8 pre-programmed internal
divisors can be used.
Normal Mode
Normal mode is enabled by pulling COAST (pin 9) low
(below 1/3*VCC). If HSYNC and CLK ÷ 2N have any phase or
frequency difference, an error signal is generated and sent
to the charge pump. The charge pump will either force
current into or out of the filter capacitor in an attempt to
FN7175 Rev 4.00
September 3, 2009
modulate the VCO frequency. Modulation will continue until
the phase and frequency of CLK ÷ 2N exactly match the
HSYNC input. When the phase and frequency match (with
some offset in phase that is a function of the VCO
characteristics), the error signal goes to zero, lock detect no
longer pulses high, and the charge pump enters a high
impedance state. The clock is now locked to the HSYNC
input. As long as phase and frequency differences remain
small, the PLL can adjust the VCO to remain locked and lock
detect remains low.
Fast Lock Mode
Fast Lock mode is enabled by either allowing coast to float,
or pulling it to mid supply (between 1/3 and 2/3*VCC). In this
mode, lock is achieved much faster than in normal mode, but
the clock divisor is modified on the fly to achieve this. If the
phase detector detects an error of enough magnitude, the
clock is either inhibited or reset to attempt a “fast lock” of the
signals. Forcing the clock to be synchronized to the HSYNC
input this way allows a lock in approximately 2 H-cycles, but
the clock spacing will not be regular during this time. Once
the near lock condition is attained, charge pump output
should be very close to its lock-on value, and placing the
device into normal mode should result in a normal lock very
quickly. Fast lock mode is intended to be used where HSYNC
becomes irregular, until a stable signal is again obtained.
Coast Mode
Coast mode is enabled by pulling COAST (pin 9) high
(above 2/3*VCC). In coast mode the internal phase detector
is disabled and filter out remains in high impedance mode to
keep filter out voltage and VCO frequency as constant as
possible. VCO frequency will drift as charge leaks from the
filter capacitor, and the voltage changes the VCO operating
point. Coast mode is intended to be used when noise or
signal degradation result in loss of horizontal sync for many
cycles. The phase detector will not attempt to adjust to the
resultant loss of signal so that when horizontal sync returns,
sync lock can be re-established quickly. However, if much
VCO drift has occurred, it may take as long to re-lock as
when restarting.
Lock Detect
Lock detect (pin 12) will go low when lock is established. Any
DC current path from charge pump out will skew EXT DIV
relative to HSYNC in, tending to offset or add to the 200ns
internal delay, depending on which way the extra current is
flowing. This offset is called static phase error, and is always
present in any PLL system. If, when the part stabilizes in a
locked mode, lock detect is not low, adding or subtracting
from the loop filter series resistor R2 will change this static
phase error to allow LDET to go low while in lock. The goal is
to put the rising edge of EXT DIV in sync with the falling
edge of HSYNC + 200ns (see “Timing Diagrams” on
page 5). Increasing R2 decreases phase error, while
decreasing R2 increases phase error. (Phase error is
Page 8 of 15
EL4585
positive when EXT DIV lags HSYNC.) The resistance needed
will depend on VCO design or VCXO module selection.
Applications Information
Choosing External Components
1. To choose LC VCO components, first pick the desired
operating frequency. For our example we will use
28.636MHz, with an HSYNC frequency of 15.734kHz.
2. Choose a reasonable inductor value (1µ to 5µH works
well). We choose 3.3µH.
3. Calculate CT needed to produce FOSC.
FIGURE 9. TYPICAL XTAL VCO
1
F OSC = ----------------------2 LC T
(EQ. 1)
1
1
C T = --------------------- = ----------------------------------------------------------------------- = 9.4pF
2 2
2
2
4 28.636e6 3.3e – 6
4 F L
Typical Application
4. From the varactor data sheet find CV @ 2.5V, the desired
lock voltage. CV=23pF for our SMV1204-12 for example.
5. C2 should be about 10CV, so we choose C2=220pF for
our example.
6. Calculate C1. Since:
C1 C2 CV
C T = ------------------------------------------------------------------------- C1 C2 + C1 CV + C2 CV
(EQ. 2)
then:
C2 CT CV
C 1 = ------------------------------------------------------------------------- C2 CV – C2 CT – CT CV
(EQ. 3)
Horizontal genlock provides clock for an analog-to-digital
converter, digitizing analog video.
XTAL VCO COMPONENT VALUES (APPROXIMATE)
For our example, C1=17pF. (A trim capacitor may be used
for fine tuning.) Examples for each frequency using the
internal divider is shown in Figure 8.
FIGURE 8. TYPICAL LC VCO
LC VCO COMPONENT VALUES (APPROXIMATE) (Note)
FREQUENCY
(MHz)
L1
(µH)
C1
(pF)
C2
(pF)
26.602
3.3
22
220
27.0
3.3
21
220
29.5
2.7
22
220
35.468
2.2
16
220
21.476
4.7
26
220
24.546
3.9
22
220
28.636
3.3
17
220
FREQUENCY
(MHz)
R1
(k)
C1
(pF)
C2
(µF)
26.602
300
15
0.001
27.0
300
15
0.001
29.5
300
15
0.001
35.468
300
15
0.001
21.476
300
15
0.001
24.546
300
15
0.001
28.636
300
15
0.001
The oscillators are arranged as Colpitts oscillators
(see Figure 8), and the structure is redrawn here to emphasize
the split capacitance used in a Colpitts oscillator. It should be
noted that this oscillator configuration is just one of literally
hundreds possible, and the configuration shown here does not
necessarily represent the best solution for all applications.
Crystal manufacturers are very informative sources on the
design and use of oscillators in a wide variety of applications,
and the reader is encouraged to become familiar with them.
NOTE: Use shielded inductors for optimum performance.
FN7175 Rev 4.00
September 3, 2009
Page 9 of 15
EL4585
probably is not) linear about the lock point (2.5V). Its
value depends on the VCO configuration and the varactor
transfer function CV = F(VC), where VC is the reverse
bias control voltage, and CV is varactor capacitance.
Since F(VC) is nonlinear, it is probably best to build the
VCO and measure KVCO about 2.5V. The results of one
such measurement are shown below. The slope of the
curve is determined by linear regression techniques and
equals KVCO. For our example, KVCO = 9.06 Mrad/s/V.
FIGURE 10. COLPITTS OSCILLATOR
C1 is to adjust the center frequency, C2 DC isolates the
control from the oscillator, and V1 is the primary control
device. C2 should be much larger than CV so that V1 has
maximum modulation capability. The frequency of oscillation
is given by Equation 4:
1
F = ----------------------2 LC T
(EQ. 4)
C1 C2 Cv
C T = ------------------------------------------------------------------------- C1 C2 + C1 CV + C1 CV
FIGURE 11. FOSC vs VC, LC VCO
Choosing Loop Filter Components
5. Now we can solve for C3, C4, and R3 in Equation 7:
The PLL, VCO, and loop filter can be described as:
K d K VCO
4.77e – 5 9.06e6
C 3 = ------------------------ = ------------------------------------------------------ = 0.01F
2
2
1820 5000
N n
C3
C 4 = ------- = 0.001F
10
2N 2
2 1820 1 5000
R 3 = ------------------------ = ------------------------------------------------------ = 42.1k
4.77e – 5 9.06e6
K d K VCO
Where:
Kd = phase detector gain in A/rad
We choose R3 = 43k for convenience.
F(s) = loop filter impedance in V/A
KVCO = VCO gain in rad/s/V
N = Total internal or external divisor (see 3 below)
It can be shown that for the loop filter shown in Equation 5:
K d K VCO
C3
2Nn
C 3 = ------------------------ C 4 = ------- R 3 = -----------------------2
10
K d K VCO
N n
(EQ. 5)
Where n = loop filter bandwidth, and = loop filter damping
factor.
1. Kd = 300µA/2rad = 4.77e-5A/rad for the EL4585.
2. The loop bandwidth should be about HSYNC
frequency/20, and the damping ratio should be 1 for
optimum performance. For our example,
n = 15.734kHz/20=787 Hz5000 rad/S.
3. N = 910x2 = 1820 from Table 1.
F VCO
28.636M
N = -------------------- = ---------------------------- = 1820 = 910x2
15.73426k
F Hsync
(EQ. 7)
(EQ. 6)
6. Notice R2 has little effect on the loop filter design. R2
should be large, around 100k, and can be adjusted to
compensate for any static phase error T at lock, but if
made too large, will slow loop response. If R2 is made
smaller, T (see “Timing Diagrams” on page 5) increases,
and if R2 increases, T decreases. For LDET to be low at
lock, |T| < 50ns. C4 is used mainly to attenuate high
frequency noise from the charge pump. The effect these
components have on-time to lock is illustrated in
Figure 12.
Lock Time
Let T = R3C3. As T increases, damping increases, but so
does lock time. Decreasing T decreases damping and
speeds up loop response, but increases overshoot and thus
increases the number of hunting oscillations before lock.
Critical damping (=1) occurs at minimum lock time.
Because decreased damping also decreases loop stability, it
is sometimes desirable to design slightly overdamped (>1),
trading lock time for increased stability.
4. KVCO represents how much the VCO frequency changes
for each volt applied at the control pin. It is assumed (but
FN7175 Rev 4.00
September 3, 2009
Page 10 of 15
EL4585
XTAL LOOP FILTER COMPONENTS (APPROXIMATE)
.
FIGURE 12. TYPICAL LOOP FILTER
LC LOOP FILTER COMPONENTS (APPROXIMATE)
FREQUENCY
(MHz)
R2
(k)
R3
(k)
C3
(µF)
C4
(µF)
26.602
100
39
0.01
0.001
27.0
100
39
0.01
0.001
29.5
100
43
0.01
0.001
35.468
100
51
0.01
0.001
21.476
100
30
0.01
0.001
24.546
100
36
0.01
0.001
28.636
100
43
0.01
0.001
FN7175 Rev 4.00
September 3, 2009
FREQUENCY
(MHz)
R2
(k)
R3
(M)
C3
(pF)
C4
(pF)
26.602
100
4.3
68
6.8
27.0
100
4.3
68
6.8
29.5
100
4.3
68
6.8
35.468
100
4.3
68
6.8
21.476
100
4.3
68
6.8
24.546
100
4.3
68
6.8
28.636
100
4.3
68
6.8
PCB Layout Considerations
It is highly recommended that power and ground planes be
used in layout. The oscillator and filter sections constitute a
feedback loop and thus care must be taken to avoid any
feedback signal influencing the oscillator except at the
control input. The entire oscillator/filter section should be
surrounded by copper ground to prevent unwanted
influences from nearby signals. Use separate paths for
analog and digital supplies, keeping the analog (oscillator
section) as short and free from spurious signals as possible.
Careful attention must be paid to correct bypassing. Keep
lead lengths short and place bypass caps as close to the
supply pins as possible. If laying out a PCB to use discrete
components for the VCO section, care must be taken to
avoid parasitic capacitance at the OSC pins 3 and 5, and
FILTER out (pin 7). Remove ground and power plane copper
above and below these traces to avoid making a capacitive
connection to them. It is also recommended to enclose the
oscillator section within a shielded cage to reduce external
influences on the VCO, as they tend to be very sensitive to
“hand waving” influences, the LC variety being more
sensitive than crystal controlled oscillators. In general, the
higher the operating frequency, the more important these
considerations are. Self contained VCXO or VCO modules
are already mounted in a shielding cage and therefore do
not require as much consideration in layout. Many crystal
manufacturers publish informative literature regarding use
and layout of oscillators which should be helpful.
Page 11 of 15
EL4585
EL4585/4 Demo Board
+5V
+5V
The VCO and loop filter section of the EL4583/4/5 Demo Board can be implemented in the following configurations:
FIGURE 13. VCXO
FIGURE 14. XTAL
FN7175 Rev 4.00
September 3, 2009
FIGURE 15. LC TANK
Page 12 of 15
EL4585
Component Sources
Inductors
• Dale Electronics
E. Highway 50
PO Box 180
Yankton, SD 57078-0180
(605) 665-9301
Crystals, VCXO, VCO Modules
• Connor-Winfield
2111 Comprehensive Drive
Aurora, IL 60606
(708) 851-4722
• Piezo Systems
100 K Street
PO Box 619
Carlisle, PA 17013
(717) 249-2151
• Reeves-Hoffman
400 West North Street
Carlisle, PA 17013
(717) 243-5929
• SaRonix
151 Laura Lane
Palo Alto, CA 94043
(415) 856-6900
• Standard Crystal
9940 Baldwin Place
El Monte, CA 91731
(818) 443-2121
Varactors
• Sky Works Solutions Inc.
20 Sylvan Road
Woburn, MA 01801
(781) 376-3000
www.skyworksinc.com
• Motorola Semiconductor Products
2100 E. Elliot
Tempe, AZ 85284
(602) 244-6900
Note: These sources are provided for information purposes
only. No endorsement of these companies is implied by this
listing.
FN7175 Rev 4.00
September 3, 2009
Page 13 of 15
EL4585
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
NOTES:
Rev. M 2/07
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN7175 Rev 4.00
September 3, 2009
Page 14 of 15
EL4585
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.204
0.355
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
L
0.115
N
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
16
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
16
6
10.92
7
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
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FN7175 Rev 4.00
September 3, 2009
Page 15 of 15
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